1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU104 RevA";
20 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_can1_default>;
59 phy-mode = "rgmii-id";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_gem3_default>;
64 ti,rx-internal-delay = <0x8>;
65 ti,tx-internal-delay = <0xa>;
66 ti,fifo-depth = <0x1>;
67 ti,rxctrl-strap-worka;
81 clock-frequency = <400000>;
82 pinctrl-names = "default", "gpio";
83 pinctrl-0 = <&pinctrl_i2c1_default>;
84 pinctrl-1 = <&pinctrl_i2c1_gpio>;
85 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
86 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
88 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
89 i2c-mux@74 { /* u34 */
90 compatible = "nxp,pca9548";
99 * IIC_EEPROM 1kB memory which uses 256B blocks
100 * where every block has different address.
101 * 0 - 256B address 0x54
102 * 256B - 512B address 0x55
103 * 512B - 768B address 0x56
104 * 768B - 1024B address 0x57
106 eeprom@54 { /* u23 */
107 compatible = "atmel,24c08";
109 #address-cells = <1>;
115 #address-cells = <1>;
118 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
119 compatible = "idt,8t49n287";
125 #address-cells = <1>;
128 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
130 compatible = "infineon,irps5401";
133 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
135 compatible = "infineon,irps5401";
141 #address-cells = <1>;
144 tca6416_u97: gpio@21 {
145 compatible = "ti,tca6416";
152 * 0 - IRPS5401_ALERT_B
153 * 1 - HDMI_8T49N241_INT_ALM
155 * 3 - MAX6643_FANFAIL_B
156 * 5 - IIC_MUX_RESET_B
157 * 6 - GEM3_EXP_RESET_B
158 * 7 - FMC_LPC_PRSNT_M2C_B
159 * 4, 10 - 17 - not connected
165 #address-cells = <1>;
171 #address-cells = <1>;
176 /* 3, 6 not connected */
183 pinctrl_can1_default: can1-default {
186 groups = "can1_6_grp";
190 groups = "can1_6_grp";
191 slew-rate = <SLEW_RATE_SLOW>;
192 io-standard = <IO_STANDARD_LVCMOS18>;
193 drive-strength = <12>;
207 pinctrl_i2c1_default: i2c1-default {
209 groups = "i2c1_4_grp";
214 groups = "i2c1_4_grp";
216 slew-rate = <SLEW_RATE_SLOW>;
217 io-standard = <IO_STANDARD_LVCMOS18>;
218 drive-strength = <12>;
222 pinctrl_i2c1_gpio: i2c1-gpio {
224 groups = "gpio0_16_grp", "gpio0_17_grp";
229 groups = "gpio0_16_grp", "gpio0_17_grp";
230 slew-rate = <SLEW_RATE_SLOW>;
231 io-standard = <IO_STANDARD_LVCMOS18>;
232 drive-strength = <12>;
236 pinctrl_gem3_default: gem3-default {
238 function = "ethernet3";
239 groups = "ethernet3_0_grp";
243 groups = "ethernet3_0_grp";
244 slew-rate = <SLEW_RATE_SLOW>;
245 io-standard = <IO_STANDARD_LVCMOS18>;
246 drive-strength = <12>;
250 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
257 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
265 groups = "mdio3_0_grp";
269 groups = "mdio3_0_grp";
270 slew-rate = <SLEW_RATE_SLOW>;
271 io-standard = <IO_STANDARD_LVCMOS18>;
276 pinctrl_sdhci1_default: sdhci1-default {
278 groups = "sdio1_0_grp";
283 groups = "sdio1_0_grp";
284 slew-rate = <SLEW_RATE_SLOW>;
285 io-standard = <IO_STANDARD_LVCMOS18>;
287 drive-strength = <12>;
291 groups = "sdio1_cd_0_grp";
292 function = "sdio1_cd";
296 groups = "sdio1_cd_0_grp";
299 slew-rate = <SLEW_RATE_SLOW>;
300 io-standard = <IO_STANDARD_LVCMOS18>;
304 pinctrl_uart0_default: uart0-default {
306 groups = "uart0_4_grp";
311 groups = "uart0_4_grp";
312 slew-rate = <SLEW_RATE_SLOW>;
313 io-standard = <IO_STANDARD_LVCMOS18>;
314 drive-strength = <12>;
328 pinctrl_uart1_default: uart1-default {
330 groups = "uart1_5_grp";
335 groups = "uart1_5_grp";
336 slew-rate = <SLEW_RATE_SLOW>;
337 io-standard = <IO_STANDARD_LVCMOS18>;
338 drive-strength = <12>;
352 pinctrl_usb0_default: usb0-default {
354 groups = "usb0_0_grp";
359 groups = "usb0_0_grp";
360 slew-rate = <SLEW_RATE_SLOW>;
361 io-standard = <IO_STANDARD_LVCMOS18>;
362 drive-strength = <12>;
366 pins = "MIO52", "MIO53", "MIO55";
371 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
372 "MIO60", "MIO61", "MIO62", "MIO63";
381 compatible = "m25p80"; /* n25q512a 128MiB */
382 #address-cells = <1>;
385 spi-tx-bus-width = <1>;
386 spi-rx-bus-width = <4>;
387 spi-max-frequency = <108000000>; /* Based on DC1 spec */
388 partition@qspi-fsbl-uboot { /* for testing purpose */
389 label = "qspi-fsbl-uboot";
390 reg = <0x0 0x100000>;
392 partition@qspi-linux { /* for testing purpose */
393 label = "qspi-linux";
394 reg = <0x100000 0x500000>;
396 partition@qspi-device-tree { /* for testing purpose */
397 label = "qspi-device-tree";
398 reg = <0x600000 0x20000>;
400 partition@qspi-rootfs { /* for testing purpose */
401 label = "qspi-rootfs";
402 reg = <0x620000 0x5E0000>;
413 /* SATA OOB timing settings */
414 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
415 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
416 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
417 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
418 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
419 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
420 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
421 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
422 phy-names = "sata-phy";
423 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
426 /* SD1 with level shifter */
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_sdhci1_default>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_uart0_default>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_uart1_default>;
452 /* ULPI SMSC USB3320 */
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_usb0_default>;
462 snps,usb3_lpm_capable;
463 phy-names = "usb3-phy";
464 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
465 maximum-speed = "super-speed";
486 phy-names = "dp-phy0", "dp-phy1";
487 phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>;
490 &zynqmp_dp_snd_pcm0 {
494 &zynqmp_dp_snd_pcm1 {
498 &zynqmp_dp_snd_card0 {
502 &zynqmp_dp_snd_codec0 {