drivers/usb/dwc3/dwc3-of-simple.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * dwc3-of-simple.c - OF glue layer for simple integrations
   4  *
   5  * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Author: Felipe Balbi <balbi@ti.com>
   8  *
   9  * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
  10  * <iivanov@mm-sol.com> and the original patch adding support for Xilinx' SoC
  11  * by Subbaraya Sundeep Bhatta <subbaraya.sundeep.bhatta@xilinx.com>
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/clk.h>
  20 #include <linux/of.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/reset.h>
  24 #include <linux/soc/xilinx/zynqmp/fw.h>
  25 #include <linux/slab.h>
  26
  27 #include <linux/phy/phy-zynqmp.h>
  28 #include <linux/of_address.h>
  29
  30 #include "core.h"
  31
  32 /* Xilinx USB 3.0 IP Register */
  33 #define XLNX_USB_COHERENCY              0x005C
  34 #define XLNX_USB_COHERENCY_ENABLE       0x1
  35
  36 /* ULPI control registers */
  37 #define ULPI_OTG_CTRL_SET               0xB
  38 #define ULPI_OTG_CTRL_CLEAR             0XC
  39 #define OTG_CTRL_DRVVBUS_OFFSET         5
  40
  41 #define XLNX_USB_CUR_PWR_STATE          0x0000
  42 #define XLNX_CUR_PWR_STATE_D0           0x00
  43 #define XLNX_CUR_PWR_STATE_D3           0x0F
  44 #define XLNX_CUR_PWR_STATE_BITMASK      0x0F
  45
  46 #define XLNX_USB_PME_ENABLE             0x0034
  47 #define XLNX_PME_ENABLE_SIG_GEN         0x01
  48
  49 #define XLNX_USB_REQ_PWR_STATE          0x003c
  50 #define XLNX_REQ_PWR_STATE_D0           0x00
  51 #define XLNX_REQ_PWR_STATE_D3           0x03
  52
  53 /* Number of retries for USB operations */
  54 #define DWC3_PWR_STATE_RETRIES          1000
  55 #define DWC3_PWR_TIMEOUT                100
  56
  57 #define DWC3_OF_ADDRESS(ADDR)           ((ADDR) - DWC3_GLOBALS_REGS_START)
  58
  59 struct dwc3_of_simple {
  60         struct device           *dev;
  61         struct clk              **clks;
  62         int                     num_clocks;
  63         void __iomem            *regs;
  64         struct dwc3             *dwc;
  65         struct phy              *phy;
  66         bool                    wakeup_capable;
  67         bool                    dis_u3_susphy_quirk;
  68         bool                    enable_d3_suspend;
  69         char                    soc_rev;
  70         struct reset_control    *resets;
  71         bool                    pulse_resets;
  72         bool                    need_reset;
  73 };
  74
  75 int dwc3_enable_hw_coherency(struct device *dev)
  76 {
  77         struct device_node *node = of_get_parent(dev->of_node);
  78
  79         if (of_device_is_compatible(node, "xlnx,zynqmp-dwc3")) {
  80                 struct platform_device *pdev_parent;
  81                 struct dwc3_of_simple *simple;
  82                 void __iomem *regs;
  83                 u32 reg;
  84
  85                 pdev_parent = of_find_device_by_node(node);
  86                 simple = platform_get_drvdata(pdev_parent);
  87                 regs = simple->regs;
  88
  89                 reg = readl(regs + XLNX_USB_COHERENCY);
  90                 reg |= XLNX_USB_COHERENCY_ENABLE;
  91                 writel(reg, regs + XLNX_USB_COHERENCY);
  92         }
  93
  94         return 0;
  95 }
  96 EXPORT_SYMBOL(dwc3_enable_hw_coherency);
  97
  98 void dwc3_set_simple_data(struct dwc3 *dwc)
  99 {
 100         struct device_node *node = of_get_parent(dwc->dev->of_node);
 101
 102         if (node && of_device_is_compatible(node, "xlnx,zynqmp-dwc3")) {
 103                 struct platform_device *pdev_parent;
 104                 struct dwc3_of_simple   *simple;
 105
 106                 pdev_parent = of_find_device_by_node(node);
 107                 simple = platform_get_drvdata(pdev_parent);
 108
 109                 /* Set (struct dwc3 *) to simple->dwc for future use */
 110                 simple->dwc =  dwc;
 111         }
 112 }
 113 EXPORT_SYMBOL(dwc3_set_simple_data);
 114
 115 void dwc3_simple_check_quirks(struct dwc3 *dwc)
 116 {
 117         struct device_node *node = of_get_parent(dwc->dev->of_node);
 118
 119         if (node && of_device_is_compatible(node, "xlnx,zynqmp-dwc3")) {
 120                 struct platform_device *pdev_parent;
 121                 struct dwc3_of_simple   *simple;
 122
 123                 pdev_parent = of_find_device_by_node(node);
 124                 simple = platform_get_drvdata(pdev_parent);
 125
 126                 /* Add snps,dis_u3_susphy_quirk */
 127                 dwc->dis_u3_susphy_quirk = simple->dis_u3_susphy_quirk;
 128         }
 129 }
 130 EXPORT_SYMBOL(dwc3_simple_check_quirks);
 131
 132 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup)
 133 {
 134         struct device_node *node = of_node_get(dev->parent->of_node);
 135
 136         /* check for valid parent node */
 137         while (node) {
 138                 if (!of_device_is_compatible(node, "xlnx,zynqmp-dwc3"))
 139                         node = of_get_next_parent(node);
 140                 else
 141                         break;
 142         }
 143
 144         if (node)  {
 145                 struct platform_device *pdev_parent;
 146                 struct dwc3_of_simple   *simple;
 147
 148                 pdev_parent = of_find_device_by_node(node);
 149                 simple = platform_get_drvdata(pdev_parent);
 150
 151                 /* Set wakeup capable as true or false */
 152                 simple->wakeup_capable = wakeup;
 153
 154                 /* Allow D3 state if wakeup capable only */
 155                 simple->enable_d3_suspend = wakeup;
 156         }
 157 }
 158 EXPORT_SYMBOL(dwc3_simple_wakeup_capable);
 159
 160 static int dwc3_simple_set_phydata(struct dwc3_of_simple *simple)
 161 {
 162         struct device           *dev = simple->dev;
 163         struct device_node      *np = dev->of_node;
 164         struct phy              *phy;
 165
 166         np = of_get_next_child(np, NULL);
 167
 168         if (np) {
 169                 phy = of_phy_get(np, "usb3-phy");
 170                 if (IS_ERR(phy)) {
 171                         dev_err(dev, "%s: Can't find usb3-phy\n", __func__);
 172                         return PTR_ERR(phy);
 173                 }
 174
 175                 /* Store phy for future usage */
 176                 simple->phy = phy;
 177
 178                 /* assign USB vendor regs addr to phy platform_data */
 179                 phy->dev.platform_data = simple->regs;
 180
 181                 phy_put(phy);
 182         } else {
 183                 dev_err(dev, "%s: Can't find child node\n", __func__);
 184                 return -EINVAL;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
 191 {
 192         struct device           *dev = simple->dev;
 193         struct device_node      *np = dev->of_node;
 194         int                     i;
 195
 196         simple->num_clocks = count;
 197
 198         if (!count)
 199                 return 0;
 200
 201         simple->clks = devm_kcalloc(dev, simple->num_clocks,
 202                         sizeof(struct clk *), GFP_KERNEL);
 203         if (!simple->clks)
 204                 return -ENOMEM;
 205
 206         for (i = 0; i < simple->num_clocks; i++) {
 207                 struct clk      *clk;
 208                 int             ret;
 209
 210                 clk = of_clk_get(np, i);
 211                 if (IS_ERR(clk)) {
 212                         while (--i >= 0) {
 213                                 clk_disable_unprepare(simple->clks[i]);
 214                                 clk_put(simple->clks[i]);
 215                         }
 216                         return PTR_ERR(clk);
 217                 }
 218
 219                 ret = clk_prepare_enable(clk);
 220                 if (ret < 0) {
 221                         while (--i >= 0) {
 222                                 clk_disable_unprepare(simple->clks[i]);
 223                                 clk_put(simple->clks[i]);
 224                         }
 225                         clk_put(clk);
 226
 227                         return ret;
 228                 }
 229
 230                 simple->clks[i] = clk;
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int dwc3_of_simple_probe(struct platform_device *pdev)
 237 {
 238         struct dwc3_of_simple   *simple;
 239         struct device           *dev = &pdev->dev;
 240         struct device_node      *np = dev->of_node;
 241
 242         int                     ret;
 243         int                     i;
 244         bool                    shared_resets = false;
 245
 246         simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
 247         if (!simple)
 248                 return -ENOMEM;
 249
 250         platform_set_drvdata(pdev, simple);
 251         simple->dev = dev;
 252
 253         if (of_device_is_compatible(pdev->dev.of_node,
 254                                     "xlnx,zynqmp-dwc3")) {
 255
 256                 char                    *soc_rev;
 257                 struct resource         *res;
 258                 void __iomem            *regs;
 259
 260                 res = platform_get_resource(pdev,
 261                                             IORESOURCE_MEM, 0);
 262
 263                 regs = devm_ioremap_resource(&pdev->dev, res);
 264                 if (IS_ERR(regs))
 265                         return PTR_ERR(regs);
 266
 267                 /* Store the usb control regs into simple for further usage */
 268                 simple->regs = regs;
 269
 270                 /* read Silicon version using nvmem driver */
 271                 soc_rev = zynqmp_nvmem_get_silicon_version(&pdev->dev,
 272                                                    "soc_revision");
 273
 274                 if (PTR_ERR(soc_rev) == -EPROBE_DEFER) {
 275                         /* Do a deferred probe */
 276                         return -EPROBE_DEFER;
 277
 278                 } else if (!IS_ERR(soc_rev) &&
 279                                         (*soc_rev < ZYNQMP_SILICON_V4)) {
 280                         /* Add snps,dis_u3_susphy_quirk
 281                          * for SOC revison less than v4
 282                          */
 283                         simple->dis_u3_susphy_quirk = true;
 284                 }
 285
 286                 /* Update soc_rev to simple for future use */
 287                 simple->soc_rev = *soc_rev;
 288
 289                 /* Clean soc_rev if got a valid pointer from nvmem driver
 290                  * else we may end up in kernel panic
 291                  */
 292                 if (!IS_ERR(soc_rev))
 293                         kfree(soc_rev);
 294         }
 295
 296         /* Set phy data for future use */
 297         dwc3_simple_set_phydata(simple);
 298
 299         /*
 300          * Some controllers need to toggle the usb3-otg reset before trying to
 301          * initialize the PHY, otherwise the PHY times out.
 302          */
 303         if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
 304                 simple->need_reset = true;
 305
 306         if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
 307             of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
 308                 shared_resets = true;
 309                 simple->pulse_resets = true;
 310         }
 311
 312         simple->resets = of_reset_control_array_get(np, shared_resets, true);
 313         if (IS_ERR(simple->resets)) {
 314                 ret = PTR_ERR(simple->resets);
 315                 dev_err(dev, "failed to get device resets, err=%d\n", ret);
 316                 return ret;
 317         }
 318
 319         if (simple->pulse_resets) {
 320                 ret = reset_control_reset(simple->resets);
 321                 if (ret)
 322                         goto err_resetc_put;
 323         } else {
 324                 ret = reset_control_deassert(simple->resets);
 325                 if (ret)
 326                         goto err_resetc_put;
 327         }
 328
 329         ret = dwc3_of_simple_clk_init(simple, of_count_phandle_with_args(np,
 330                                                 "clocks", "#clock-cells"));
 331         if (ret)
 332                 goto err_resetc_assert;
 333
 334         ret = of_platform_populate(np, NULL, NULL, dev);
 335         if (ret) {
 336                 for (i = 0; i < simple->num_clocks; i++) {
 337                         clk_disable_unprepare(simple->clks[i]);
 338                         clk_put(simple->clks[i]);
 339                 }
 340
 341                 goto err_resetc_assert;
 342         }
 343
 344         platform_set_drvdata(pdev, simple);
 345
 346         pm_runtime_set_active(dev);
 347         pm_runtime_enable(dev);
 348         pm_runtime_get_sync(dev);
 349
 350         return 0;
 351
 352 err_resetc_assert:
 353         if (!simple->pulse_resets)
 354                 reset_control_assert(simple->resets);
 355
 356 err_resetc_put:
 357         reset_control_put(simple->resets);
 358         return ret;
 359 }
 360
 361 static int dwc3_of_simple_remove(struct platform_device *pdev)
 362 {
 363         struct dwc3_of_simple   *simple = platform_get_drvdata(pdev);
 364         struct device           *dev = &pdev->dev;
 365         int                     i;
 366
 367         of_platform_depopulate(dev);
 368
 369         for (i = 0; i < simple->num_clocks; i++) {
 370                 clk_disable_unprepare(simple->clks[i]);
 371                 clk_put(simple->clks[i]);
 372         }
 373         simple->num_clocks = 0;
 374
 375         if (!simple->pulse_resets)
 376                 reset_control_assert(simple->resets);
 377
 378         reset_control_put(simple->resets);
 379
 380         pm_runtime_disable(dev);
 381         pm_runtime_put_noidle(dev);
 382         pm_runtime_set_suspended(dev);
 383
 384         return 0;
 385 }
 386
 387 static void dwc3_simple_vbus(struct dwc3 *dwc, bool vbus_off)
 388 {
 389         u32 reg, addr;
 390         u8  val;
 391
 392         if (vbus_off)
 393                 addr = ULPI_OTG_CTRL_CLEAR;
 394         else
 395                 addr = ULPI_OTG_CTRL_SET;
 396
 397         val = (1 << OTG_CTRL_DRVVBUS_OFFSET);
 398
 399         reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_GUSB2PHYACC_ADDR(addr);
 400         reg |= DWC3_GUSB2PHYACC_WRITE | val;
 401
 402         addr = DWC3_OF_ADDRESS(DWC3_GUSB2PHYACC(0));
 403         writel(reg, dwc->regs + addr);
 404 }
 405
 406 void dwc3_usb2phycfg(struct dwc3 *dwc, bool suspend)
 407 {
 408         u32 addr, reg;
 409
 410         addr = DWC3_OF_ADDRESS(DWC3_GUSB2PHYCFG(0));
 411
 412         if (suspend) {
 413                 reg = readl(dwc->regs + addr);
 414                 if (!(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 415                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 416                         writel(reg, (dwc->regs + addr));
 417                 }
 418         } else {
 419                 reg = readl(dwc->regs + addr);
 420                 if ((reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 421                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 422                         writel(reg, (dwc->regs + addr));
 423                 }
 424         }
 425 }
 426
 427 int dwc3_set_usb_core_power(struct dwc3 *dwc, bool on)
 428 {
 429         u32 reg, retries;
 430         void __iomem *reg_base;
 431         struct platform_device *pdev_parent;
 432         struct dwc3_of_simple *simple;
 433         struct device_node *node = of_get_parent(dwc->dev->of_node);
 434
 435         /* this is for Xilinx devices only */
 436         if (!of_device_is_compatible(node, "xlnx,zynqmp-dwc3"))
 437                 return 0;
 438
 439         pdev_parent = of_find_device_by_node(node);
 440         simple = platform_get_drvdata(pdev_parent);
 441         reg_base = simple->regs;
 442
 443         /* Check if entering into D3 state is allowed during suspend */
 444         if ((simple->soc_rev < ZYNQMP_SILICON_V4) || !simple->enable_d3_suspend)
 445                 return 0;
 446
 447         if (!simple->phy)
 448                 return 0;
 449
 450         if (on) {
 451                 dev_dbg(dwc->dev, "trying to set power state to D0....\n");
 452
 453                 /* Release USB core reset , which was assert during D3 entry */
 454                 xpsgtr_usb_crst_release(simple->phy);
 455
 456                 /* change power state to D0 */
 457                 writel(XLNX_REQ_PWR_STATE_D0,
 458                        reg_base + XLNX_USB_REQ_PWR_STATE);
 459
 460                 /* wait till current state is changed to D0 */
 461                 retries = DWC3_PWR_STATE_RETRIES;
 462                 do {
 463                         reg = readl(reg_base + XLNX_USB_CUR_PWR_STATE);
 464                         if ((reg & XLNX_CUR_PWR_STATE_BITMASK) ==
 465                              XLNX_CUR_PWR_STATE_D0)
 466                                 break;
 467
 468                         udelay(DWC3_PWR_TIMEOUT);
 469                 } while (--retries);
 470
 471                 if (!retries) {
 472                         dev_err(dwc->dev, "Failed to set power state to D0\n");
 473                         return -EIO;
 474                 }
 475
 476                 dwc->is_d3 = false;
 477
 478                 /* Clear Suspend PHY bit if dis_u2_susphy_quirk is set */
 479                 if (dwc->dis_u2_susphy_quirk)
 480                         dwc3_usb2phycfg(dwc, false);
 481         } else {
 482                 dev_dbg(dwc->dev, "Trying to set power state to D3...\n");
 483
 484                 /*
 485                  * Set Suspend PHY bit before entering D3 if
 486                  * dis_u2_susphy_quirk is set
 487                  */
 488                 if (dwc->dis_u2_susphy_quirk)
 489                         dwc3_usb2phycfg(dwc, true);
 490
 491                 /* enable PME to wakeup from hibernation */
 492                 writel(XLNX_PME_ENABLE_SIG_GEN, reg_base + XLNX_USB_PME_ENABLE);
 493
 494                 /* change power state to D3 */
 495                 writel(XLNX_REQ_PWR_STATE_D3,
 496                        reg_base + XLNX_USB_REQ_PWR_STATE);
 497
 498                 /* wait till current state is changed to D3 */
 499                 retries = DWC3_PWR_STATE_RETRIES;
 500                 do {
 501                         reg = readl(reg_base + XLNX_USB_CUR_PWR_STATE);
 502                         if ((reg & XLNX_CUR_PWR_STATE_BITMASK) ==
 503                                         XLNX_CUR_PWR_STATE_D3)
 504                                 break;
 505
 506                         udelay(DWC3_PWR_TIMEOUT);
 507                 } while (--retries);
 508
 509                 if (!retries) {
 510                         dev_err(dwc->dev, "Failed to set power state to D3\n");
 511                         return -EIO;
 512                 }
 513
 514                 /* Assert USB core reset after entering D3 state */
 515                 xpsgtr_usb_crst_assert(simple->phy);
 516
 517                 dwc->is_d3 = true;
 518         }
 519
 520         return 0;
 521 }
 522 EXPORT_SYMBOL(dwc3_set_usb_core_power);
 523
 524 static int __maybe_unused dwc3_of_simple_runtime_suspend(struct device *dev)
 525 {
 526         struct dwc3_of_simple   *simple = dev_get_drvdata(dev);
 527         int                     i;
 528
 529         for (i = 0; i < simple->num_clocks; i++)
 530                 clk_disable(simple->clks[i]);
 531
 532         return 0;
 533 }
 534
 535 static int __maybe_unused dwc3_of_simple_runtime_resume(struct device *dev)
 536 {
 537         struct dwc3_of_simple   *simple = dev_get_drvdata(dev);
 538         int                     ret;
 539         int                     i;
 540
 541         for (i = 0; i < simple->num_clocks; i++) {
 542                 ret = clk_enable(simple->clks[i]);
 543                 if (ret < 0) {
 544                         while (--i >= 0)
 545                                 clk_disable(simple->clks[i]);
 546                         return ret;
 547                 }
 548
 549                 /* Ask ULPI to turn ON Vbus */
 550                 dwc3_simple_vbus(simple->dwc, false);
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int __maybe_unused dwc3_of_simple_suspend(struct device *dev)
 557 {
 558         struct dwc3_of_simple *simple = dev_get_drvdata(dev);
 559         int                     i;
 560
 561         if (!simple->wakeup_capable && !simple->dwc->is_d3) {
 562                 /* Ask ULPI to turn OFF Vbus */
 563                 dwc3_simple_vbus(simple->dwc, true);
 564
 565                 /* Disable the clocks */
 566                 for (i = 0; i < simple->num_clocks; i++)
 567                         clk_disable(simple->clks[i]);
 568         }
 569
 570         if (simple->need_reset)
 571                 reset_control_assert(simple->resets);
 572
 573         return 0;
 574 }
 575
 576 static int __maybe_unused dwc3_of_simple_resume(struct device *dev)
 577 {
 578         struct dwc3_of_simple *simple = dev_get_drvdata(dev);
 579         int                     ret;
 580         int                     i;
 581
 582         if (simple->wakeup_capable || simple->dwc->is_d3)
 583                 return 0;
 584
 585         for (i = 0; i < simple->num_clocks; i++) {
 586                 ret = clk_enable(simple->clks[i]);
 587                 if (ret < 0) {
 588                         while (--i >= 0)
 589                                 clk_disable(simple->clks[i]);
 590                         return ret;
 591                 }
 592         }
 593
 594         if (simple->need_reset)
 595                 reset_control_deassert(simple->resets);
 596
 597         return 0;
 598 }
 599
 600 static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 601         SET_SYSTEM_SLEEP_PM_OPS(dwc3_of_simple_suspend, dwc3_of_simple_resume)
 602         SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend,
 603                         dwc3_of_simple_runtime_resume, NULL)
 604 };
 605
 606 static const struct of_device_id of_dwc3_simple_match[] = {
 607         { .compatible = "rockchip,rk3399-dwc3" },
 608         { .compatible = "xlnx,zynqmp-dwc3" },
 609         { .compatible = "xlnx,versal-dwc3" },
 610         { .compatible = "cavium,octeon-7130-usb-uctl" },
 611         { .compatible = "sprd,sc9860-dwc3" },
 612         { .compatible = "amlogic,meson-axg-dwc3" },
 613         { .compatible = "amlogic,meson-gxl-dwc3" },
 614         { .compatible = "allwinner,sun50i-h6-dwc3" },
 615         { /* Sentinel */ }
 616 };
 617 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
 618
 619 static struct platform_driver dwc3_of_simple_driver = {
 620         .probe          = dwc3_of_simple_probe,
 621         .remove         = dwc3_of_simple_remove,
 622         .driver         = {
 623                 .name   = "dwc3-of-simple",
 624                 .of_match_table = of_dwc3_simple_match,
 625                 .pm     = &dwc3_of_simple_dev_pm_ops,
 626         },
 627 };
 628
 629 module_platform_driver(dwc3_of_simple_driver);
 630 MODULE_LICENSE("GPL v2");
 631 MODULE_DESCRIPTION("DesignWare USB3 OF Simple Glue Layer");
 632 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");