]> rtime.felk.cvut.cz Git - zynq/linux-build.git/commit
Create empty file if no FPGA bitstream is provided
authorMichal Sojka <michal.sojka@cvut.cz>
Fri, 1 Jun 2018 13:17:36 +0000 (15:17 +0200)
committerMichal Sojka <michal.sojka@cvut.cz>
Fri, 1 Jun 2018 14:11:59 +0000 (16:11 +0200)
commit3e27b548ae201bbde34e6fe9e89552da773ca177
tree78e07a06afdda6c5a526477b26d1098bbffd9551
parenta4948a98ffa915cd5db13a4e7a4595fc0cfba4da
Create empty file if no FPGA bitstream is provided
build/xlnx_4.9/Makefile