1 Xilinx ARM-Microblaze remoteproc driver
3 This driver requires specific Zynq hardware design where Microblaze is added
4 to the programmable logic.
5 Microblaze is connected with PS block via axi bus connected to PS HP port
6 to ensure access to PS DDR.
7 Communication channels are done via soft GPIO IP connected to PS block
8 and to Microblaze. There are also 2 gpio control signals reset and debug
9 which are used for reseting Microblaze.
12 - compatible : Should be "xlnx,mb_remoteproc"
13 - reg : Address and length of the ddr address space
14 - bram: Phandle to bram controller which can access Microblaze BRAM
15 - bram-firmware : Microblaze BRAM bootloader name
16 - firmware : Default firmware name which can be override by
17 "firmware" module parameter
18 - reset : Gpio phandle which reset Microblaze remoteproc
19 - debug : Gpio phandle which setup Microblaze to debug state
20 - ipino : Gpio phandle for Microblaze to ARM communication
21 - vring0 : Gpio phandle for ARM to Microblaze communication vring 0
22 - vring1 : Gpio phandle for ARM to Microblaze communication vring 1
24 Microblaze SoC can be also connected to the PS block via a axi bus.
25 That's why there is the option to allocate interrupts for Microblaze use only.
26 The driver will allocate interrupts to itself and Microblaze sw has to ensure
27 that interrupts are properly enabled and handled by Microblaze interrupt
31 - interrupts : Interrupt mapping for remoteproc
32 - interrupt-parent : Phandle for the interrupt controller
35 test_mb: mb_remoteproc-test@800000 {
36 compatible = "xlnx,mb_remoteproc";
37 reg = < 0x8000000 0x8000000 >;
38 bram = <&axi_bram_ctrl_0>;
39 bram-firmware = "mb.bin";
40 firmware = "image.elf";
41 reset = <&zynq_gpio_reset 1 0>;
42 debug = <&zynq_gpio_reset 0 0>;
43 ipino = <&zynq_gpio_vring 0 0>;
44 vring0 = <&zynq_gpio_vring 1 0>;
45 vring1 = <&zynq_gpio_vring 2 0>;