arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts

   1 /*
   2  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "zynqmp.dtsi"
  17 #include "zynqmp-clk-ccf.dtsi"
  18 #include <dt-bindings/gpio/gpio.h>
  19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  20
  21 / {
  22         model = "ZynqMP zc1751-xm016-dc2 RevA";
  23         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  24
  25         aliases {
  26                 can0 = &can0;
  27                 can1 = &can1;
  28                 ethernet0 = &gem2;
  29                 gpio0 = &gpio;
  30                 i2c0 = &i2c0;
  31                 rtc0 = &rtc;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 spi0 = &spi0;
  35                 spi1 = &spi1;
  36                 usb0 = &usb1;
  37         };
  38
  39         chosen {
  40                 bootargs = "earlycon";
  41                 stdout-path = "serial0:115200n8";
  42         };
  43
  44         memory@0 {
  45                 device_type = "memory";
  46                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  47         };
  48 };
  49
  50 &can0 {
  51         status = "okay";
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_can0_default>;
  54 };
  55
  56 &can1 {
  57         status = "okay";
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_can1_default>;
  60 };
  61
  62 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  63 &fpd_dma_chan1 {
  64         status = "okay";
  65         xlnx,include-sg; /* for testing purpose */
  66         xlnx,overfetch; /* for testing purpose */
  67         xlnx,ratectrl = <0>; /* for testing purpose */
  68         xlnx,src-issue = <31>;
  69 };
  70
  71 &fpd_dma_chan2 {
  72         status = "okay";
  73         xlnx,ratectrl = <100>; /* for testing purpose */
  74         xlnx,src-issue = <4>; /* for testing purpose */
  75 };
  76
  77 &fpd_dma_chan3 {
  78         status = "okay";
  79 };
  80
  81 &fpd_dma_chan4 {
  82         status = "okay";
  83         xlnx,include-sg; /* for testing purpose */
  84 };
  85
  86 &fpd_dma_chan5 {
  87         status = "okay";
  88 };
  89
  90 &fpd_dma_chan6 {
  91         status = "okay";
  92         xlnx,include-sg; /* for testing purpose */
  93 };
  94
  95 &fpd_dma_chan7 {
  96         status = "okay";
  97 };
  98
  99 &fpd_dma_chan8 {
 100         status = "okay";
 101         xlnx,include-sg; /* for testing purpose */
 102 };
 103
 104 &gem2 {
 105         status = "okay";
 106         phy-handle = <&phy0>;
 107         phy-mode = "rgmii-id";
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_gem2_default>;
 110         phy0: phy@5 {
 111                 reg = <5>;
 112                 ti,rx-internal-delay = <0x8>;
 113                 ti,tx-internal-delay = <0xa>;
 114                 ti,fifo-depth = <0x1>;
 115                 ti,rxctrl-strap-worka;
 116         };
 117 };
 118
 119 &gpio {
 120         status = "okay";
 121 };
 122
 123 &i2c0 {
 124         status = "okay";
 125         clock-frequency = <400000>;
 126         pinctrl-names = "default", "gpio";
 127         pinctrl-0 = <&pinctrl_i2c0_default>;
 128         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 129         scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
 130         sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
 131
 132         tca6416_u26: gpio@20 {
 133                 compatible = "ti,tca6416";
 134                 reg = <0x20>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137                 /* IRQ not connected */
 138         };
 139
 140         rtc@68 {
 141                 compatible = "dallas,ds1339";
 142                 reg = <0x68>;
 143         };
 144 };
 145
 146 &nand0 {
 147         status = "okay";
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_nand0_default>;
 150         arasan,has-mdma;
 151
 152         nand@0 {
 153                 reg = <0x0>;
 154                 #address-cells = <0x2>;
 155                 #size-cells = <0x1>;
 156
 157                 partition@0 {   /* for testing purpose */
 158                         label = "nand-fsbl-uboot";
 159                         reg = <0x0 0x0 0x400000>;
 160                 };
 161                 partition@1 {   /* for testing purpose */
 162                         label = "nand-linux";
 163                         reg = <0x0 0x400000 0x1400000>;
 164                 };
 165                 partition@2 {   /* for testing purpose */
 166                         label = "nand-device-tree";
 167                         reg = <0x0 0x1800000 0x400000>;
 168                 };
 169                 partition@3 {   /* for testing purpose */
 170                         label = "nand-rootfs";
 171                         reg = <0x0 0x1c00000 0x1400000>;
 172                 };
 173                 partition@4 {   /* for testing purpose */
 174                         label = "nand-bitstream";
 175                         reg = <0x0 0x3000000 0x400000>;
 176                 };
 177                 partition@5 {   /* for testing purpose */
 178                         label = "nand-misc";
 179                         reg = <0x0 0x3400000 0xfcc00000>;
 180                 };
 181         };
 182         nand@1 {
 183                 reg = <0x1>;
 184                 #address-cells = <0x2>;
 185                 #size-cells = <0x1>;
 186
 187                 partition@0 {   /* for testing purpose */
 188                         label = "nand1-fsbl-uboot";
 189                         reg = <0x0 0x0 0x400000>;
 190                 };
 191                 partition@1 {   /* for testing purpose */
 192                         label = "nand1-linux";
 193                         reg = <0x0 0x400000 0x1400000>;
 194                 };
 195                 partition@2 {   /* for testing purpose */
 196                         label = "nand1-device-tree";
 197                         reg = <0x0 0x1800000 0x400000>;
 198                 };
 199                 partition@3 {   /* for testing purpose */
 200                         label = "nand1-rootfs";
 201                         reg = <0x0 0x1c00000 0x1400000>;
 202                 };
 203                 partition@4 {   /* for testing purpose */
 204                         label = "nand1-bitstream";
 205                         reg = <0x0 0x3000000 0x400000>;
 206                 };
 207                 partition@5 {   /* for testing purpose */
 208                         label = "nand1-misc";
 209                         reg = <0x0 0x3400000 0xfcc00000>;
 210                 };
 211         };
 212 };
 213
 214 &rtc {
 215         status = "okay";
 216 };
 217
 218 &spi0 {
 219         status = "okay";
 220         num-cs = <1>;
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_spi0_default>;
 223
 224         spi0_flash0: spi0_flash0@0 {
 225                 compatible = "m25p80";
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228                 spi-max-frequency = <50000000>;
 229                 reg = <0>;
 230
 231                 spi0_flash0@0 {
 232                         label = "spi0_flash0";
 233                         reg = <0x0 0x100000>;
 234                 };
 235         };
 236 };
 237
 238 &spi1 {
 239         status = "okay";
 240         num-cs = <1>;
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_spi1_default>;
 243
 244         spi1_flash0: spi1_flash0@0 {
 245                 compatible = "mtd_dataflash";
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 spi-max-frequency = <20000000>;
 249                 reg = <0>;
 250
 251                 spi1_flash0@0 {
 252                         label = "spi1_flash0";
 253                         reg = <0x0 0x84000>;
 254                 };
 255         };
 256 };
 257
 258 /* ULPI SMSC USB3320 */
 259 &usb1 {
 260         status = "okay";
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_usb1_default>;
 263 };
 264
 265 &dwc3_1 {
 266         status = "okay";
 267         dr_mode = "host";
 268 };
 269
 270 &uart0 {
 271         status = "okay";
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_uart0_default>;
 274 };
 275
 276 &uart1 {
 277         status = "okay";
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_uart1_default>;
 280 };
 281
 282 &pinctrl0 {
 283         status = "okay";
 284         pinctrl_can0_default: can0-default {
 285                 mux {
 286                         function = "can0";
 287                         groups = "can0_9_grp";
 288                 };
 289
 290                 conf {
 291                         groups = "can0_9_grp";
 292                         slew-rate = <SLEW_RATE_SLOW>;
 293                         io-standard = <IO_STANDARD_LVCMOS18>;
 294                 };
 295
 296                 conf-rx {
 297                         pins = "MIO38";
 298                         bias-high-impedance;
 299                 };
 300
 301                 conf-tx {
 302                         pins = "MIO39";
 303                         bias-disable;
 304                 };
 305         };
 306
 307         pinctrl_can1_default: can1-default {
 308                 mux {
 309                         function = "can1";
 310                         groups = "can1_8_grp";
 311                 };
 312
 313                 conf {
 314                         groups = "can1_8_grp";
 315                         slew-rate = <SLEW_RATE_SLOW>;
 316                         io-standard = <IO_STANDARD_LVCMOS18>;
 317                 };
 318
 319                 conf-rx {
 320                         pins = "MIO33";
 321                         bias-high-impedance;
 322                 };
 323
 324                 conf-tx {
 325                         pins = "MIO32";
 326                         bias-disable;
 327                 };
 328         };
 329
 330         pinctrl_i2c0_default: i2c0-default {
 331                 mux {
 332                         groups = "i2c0_1_grp";
 333                         function = "i2c0";
 334                 };
 335
 336                 conf {
 337                         groups = "i2c0_1_grp";
 338                         bias-pull-up;
 339                         slew-rate = <SLEW_RATE_SLOW>;
 340                         io-standard = <IO_STANDARD_LVCMOS18>;
 341                 };
 342         };
 343
 344         pinctrl_i2c0_gpio: i2c0-gpio {
 345                 mux {
 346                         groups = "gpio0_6_grp", "gpio0_7_grp";
 347                         function = "gpio0";
 348                 };
 349
 350                 conf {
 351                         groups = "gpio0_6_grp", "gpio0_7_grp";
 352                         slew-rate = <SLEW_RATE_SLOW>;
 353                         io-standard = <IO_STANDARD_LVCMOS18>;
 354                 };
 355         };
 356
 357         pinctrl_uart0_default: uart0-default {
 358                 mux {
 359                         groups = "uart0_10_grp";
 360                         function = "uart0";
 361                 };
 362
 363                 conf {
 364                         groups = "uart0_10_grp";
 365                         slew-rate = <SLEW_RATE_SLOW>;
 366                         io-standard = <IO_STANDARD_LVCMOS18>;
 367                 };
 368
 369                 conf-rx {
 370                         pins = "MIO42";
 371                         bias-high-impedance;
 372                 };
 373
 374                 conf-tx {
 375                         pins = "MIO43";
 376                         bias-disable;
 377                 };
 378         };
 379
 380         pinctrl_uart1_default: uart1-default {
 381                 mux {
 382                         groups = "uart1_10_grp";
 383                         function = "uart1";
 384                 };
 385
 386                 conf {
 387                         groups = "uart1_10_grp";
 388                         slew-rate = <SLEW_RATE_SLOW>;
 389                         io-standard = <IO_STANDARD_LVCMOS18>;
 390                 };
 391
 392                 conf-rx {
 393                         pins = "MIO41";
 394                         bias-high-impedance;
 395                 };
 396
 397                 conf-tx {
 398                         pins = "MIO40";
 399                         bias-disable;
 400                 };
 401         };
 402
 403         pinctrl_usb1_default: usb1-default {
 404                 mux {
 405                         groups = "usb1_0_grp";
 406                         function = "usb1";
 407                 };
 408
 409                 conf {
 410                         groups = "usb1_0_grp";
 411                         slew-rate = <SLEW_RATE_SLOW>;
 412                         io-standard = <IO_STANDARD_LVCMOS18>;
 413                 };
 414
 415                 conf-rx {
 416                         pins = "MIO64", "MIO65", "MIO67";
 417                         bias-high-impedance;
 418                 };
 419
 420                 conf-tx {
 421                         pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 422                                "MIO72", "MIO73", "MIO74", "MIO75";
 423                         bias-disable;
 424                 };
 425         };
 426
 427         pinctrl_gem2_default: gem2-default {
 428                 mux {
 429                         function = "ethernet2";
 430                         groups = "ethernet2_0_grp";
 431                 };
 432
 433                 conf {
 434                         groups = "ethernet2_0_grp";
 435                         slew-rate = <SLEW_RATE_SLOW>;
 436                         io-standard = <IO_STANDARD_LVCMOS18>;
 437                 };
 438
 439                 conf-rx {
 440                         pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
 441                                                                         "MIO63";
 442                         bias-high-impedance;
 443                         low-power-disable;
 444                 };
 445
 446                 conf-tx {
 447                         pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
 448                                                                         "MIO57";
 449                         bias-disable;
 450                         low-power-enable;
 451                 };
 452
 453                 mux-mdio {
 454                         function = "mdio2";
 455                         groups = "mdio2_0_grp";
 456                 };
 457
 458                 conf-mdio {
 459                         groups = "mdio2_0_grp";
 460                         slew-rate = <SLEW_RATE_SLOW>;
 461                         io-standard = <IO_STANDARD_LVCMOS18>;
 462                         bias-disable;
 463                 };
 464         };
 465
 466         pinctrl_nand0_default: nand0-default {
 467                 mux {
 468                         groups = "nand0_0_grp";
 469                         function = "nand0";
 470                 };
 471
 472                 conf {
 473                         groups = "nand0_0_grp";
 474                         bias-pull-up;
 475                 };
 476
 477                 mux-ce {
 478                         groups = "nand0_0_ce_grp";
 479                         function = "nand0_ce";
 480                 };
 481
 482                 conf-ce {
 483                         groups = "nand0_0_ce_grp";
 484                         bias-pull-up;
 485                 };
 486
 487                 mux-rb {
 488                         groups = "nand0_0_rb_grp";
 489                         function = "nand0_rb";
 490                 };
 491
 492                 conf-rb {
 493                         groups = "nand0_0_rb_grp";
 494                         bias-pull-up;
 495                 };
 496
 497                 mux-dqs {
 498                         groups = "nand0_0_dqs_grp";
 499                         function = "nand0_dqs";
 500                 };
 501
 502                 conf-dqs {
 503                         groups = "nand0_0_dqs_grp";
 504                         bias-pull-up;
 505                 };
 506         };
 507
 508         pinctrl_spi0_default: spi0-default {
 509                 mux {
 510                         groups = "spi0_0_grp";
 511                         function = "spi0";
 512                 };
 513
 514                 conf {
 515                         groups = "spi0_0_grp";
 516                         bias-disable;
 517                         slew-rate = <SLEW_RATE_SLOW>;
 518                         io-standard = <IO_STANDARD_LVCMOS18>;
 519                 };
 520
 521                 mux-cs {
 522                         groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp",
 523                                                         "spi0_0_ss2_grp";
 524                         function = "spi0_ss";
 525                 };
 526
 527                 conf-cs {
 528                         groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp",
 529                                                         "spi0_0_ss2_grp";
 530                         bias-disable;
 531                 };
 532         };
 533
 534         pinctrl_spi1_default: spi1-default {
 535                 mux {
 536                         groups = "spi1_3_grp";
 537                         function = "spi1";
 538                 };
 539
 540                 conf {
 541                         groups = "spi1_3_grp";
 542                         bias-disable;
 543                         slew-rate = <SLEW_RATE_SLOW>;
 544                         io-standard = <IO_STANDARD_LVCMOS18>;
 545                 };
 546
 547                 mux-cs {
 548                         groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp",
 549                                                         "spi1_3_ss2_grp";
 550                         function = "spi1_ss";
 551                 };
 552
 553                 conf-cs {
 554                         groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp",
 555                                                         "spi1_3_ss2_grp";
 556                         bias-disable;
 557                 };
 558         };
 559 };