drivers/mtd/spi-nor/spi-nor.c

   1 /*
   2  * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
   3  * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
   4  *
   5  * Copyright (C) 2005, Intec Automation Inc.
   6  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   7  *
   8  * This code is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/errno.h>
  15 #include <linux/module.h>
  16 #include <linux/device.h>
  17 #include <linux/mutex.h>
  18 #include <linux/math64.h>
  19 #include <linux/sizes.h>
  20
  21 #include <linux/mtd/mtd.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/spi/flash.h>
  24 #include <linux/mtd/spi-nor.h>
  25 #include <linux/spi/spi.h>
  26
  27 /* Define max times to check status register before we give up. */
  28
  29 /*
  30  * For everything but full-chip erase; probably could be much smaller, but kept
  31  * around for safety for now
  32  */
  33 #define DEFAULT_READY_WAIT_JIFFIES              (40UL * HZ)
  34
  35 /*
  36  * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
  37  * for larger flash
  38  */
  39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES       (40UL * HZ)
  40
  41 #define SPI_NOR_MAX_ID_LEN      6
  42 #define SPI_NOR_MAX_ADDR_WIDTH  4
  43
  44 struct flash_info {
  45         char            *name;
  46
  47         /*
  48          * This array stores the ID bytes.
  49          * The first three bytes are the JEDIC ID.
  50          * JEDEC ID zero means "no ID" (mostly older chips).
  51          */
  52         u8              id[SPI_NOR_MAX_ID_LEN];
  53         u8              id_len;
  54
  55         /* The size listed here is what works with SPINOR_OP_SE, which isn't
  56          * necessarily called a "sector" by the vendor.
  57          */
  58         unsigned        sector_size;
  59         u16             n_sectors;
  60
  61         u16             page_size;
  62         u16             addr_width;
  63
  64         u16             flags;
  65 #define SECT_4K                 BIT(0)  /* SPINOR_OP_BE_4K works uniformly */
  66 #define SPI_NOR_NO_ERASE        BIT(1)  /* No erase command needed */
  67 #define SST_WRITE               BIT(2)  /* use SST byte programming */
  68 #define SPI_NOR_NO_FR           BIT(3)  /* Can't do fastread */
  69 #define SECT_4K_PMC             BIT(4)  /* SPINOR_OP_BE_4K_PMC works uniformly */
  70 #define SPI_NOR_DUAL_READ       BIT(5)  /* Flash supports Dual Read */
  71 #define SPI_NOR_QUAD_READ       BIT(6)  /* Flash supports Quad Read */
  72 #define USE_FSR                 BIT(7)  /* use flag status register */
  73 #define SPI_NOR_HAS_LOCK        BIT(8)  /* Flash supports lock/unlock via SR */
  74 #define SPI_NOR_HAS_TB          BIT(9)  /*
  75                                          * Flash SR has Top/Bottom (TB) protect
  76                                          * bit. Must be used with
  77                                          * SPI_NOR_HAS_LOCK.
  78                                                 */
  79 #define SST_GLOBAL_PROT_UNLK    BIT(10) /* Unlock the Global protection for
  80                                          * sst flashes
  81                                          */
  82
  83 };
  84
  85 #define JEDEC_MFR(info) ((info)->id[0])
  86
  87 static const struct flash_info *spi_nor_match_id(const char *name);
  88
  89 /*
  90  * Read the status register, returning its value in the location
  91  * Return the status register value.
  92  * Returns negative if error occurred.
  93  */
  94 static int read_sr(struct spi_nor *nor)
  95 {
  96         int ret;
  97         u8 val[2];
  98
  99         if (nor->isparallel) {
 100                 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val[0], 2);
 101                 if (ret < 0) {
 102                         pr_err("error %d reading SR\n", (int) ret);
 103                         return ret;
 104                 }
 105                 val[0] |= val[1];
 106         } else {
 107                 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val[0], 1);
 108                 if (ret < 0) {
 109                         pr_err("error %d reading SR\n", (int) ret);
 110                         return ret;
 111                 }
 112         }
 113
 114         return val[0];
 115 }
 116
 117 /*
 118  * Read the flag status register, returning its value in the location
 119  * Return the status register value.
 120  * Returns negative if error occurred.
 121  */
 122 static int read_fsr(struct spi_nor *nor)
 123 {
 124         int ret;
 125         u8 val[2];
 126
 127         if (nor->isparallel) {
 128                 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val[0], 2);
 129                 if (ret < 0) {
 130                         pr_err("error %d reading FSR\n", ret);
 131                         return ret;
 132                 }
 133                 val[0] &= val[1];
 134         } else {
 135                 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val[0], 1);
 136                 if (ret < 0) {
 137                         pr_err("error %d reading FSR\n", ret);
 138                         return ret;
 139                 }
 140         }
 141
 142         return val[0];
 143 }
 144
 145 /*
 146  * Read configuration register, returning its value in the
 147  * location. Return the configuration register value.
 148  * Returns negative if error occured.
 149  */
 150 static int read_cr(struct spi_nor *nor)
 151 {
 152         int ret;
 153         u8 val;
 154
 155         ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
 156         if (ret < 0) {
 157                 dev_err(nor->dev, "error %d reading CR\n", ret);
 158                 return ret;
 159         }
 160
 161         return val;
 162 }
 163
 164 /*
 165  * Dummy Cycle calculation for different type of read.
 166  * It can be used to support more commands with
 167  * different dummy cycle requirements.
 168  */
 169 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
 170 {
 171         switch (nor->flash_read) {
 172         case SPI_NOR_FAST:
 173         case SPI_NOR_DUAL:
 174         case SPI_NOR_QUAD:
 175                 return 8;
 176         case SPI_NOR_NORMAL:
 177                 return 0;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * Write status register 1 byte
 184  * Returns negative if error occurred.
 185  */
 186 static inline int write_sr(struct spi_nor *nor, u8 val)
 187 {
 188         nor->cmd_buf[0] = val;
 189         return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
 190 }
 191
 192 /*
 193  * Write status Register and configuration register with 2 bytes
 194  * The first byte will be written to the status register, while the
 195  * second byte will be written to the configuration register.
 196  * Return negative if error occured.
 197  */
 198 static int write_sr_cr(struct spi_nor *nor, u16 val)
 199 {
 200         nor->cmd_buf[0] = val & 0xff;
 201         nor->cmd_buf[1] = (val >> 8);
 202
 203         return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
 204 }
 205
 206 /*
 207  * Set write enable latch with Write Enable command.
 208  * Returns negative if error occurred.
 209  */
 210 static inline int write_enable(struct spi_nor *nor)
 211 {
 212         return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 213 }
 214
 215 /*
 216  * Send write disble instruction to the chip.
 217  */
 218 static inline int write_disable(struct spi_nor *nor)
 219 {
 220         return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
 221 }
 222
 223 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
 224 {
 225         return mtd->priv;
 226 }
 227
 228 /* Enable/disable 4-byte addressing mode. */
 229 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
 230                             int enable)
 231 {
 232         int status;
 233         bool need_wren = false;
 234         u8 cmd;
 235
 236         switch (JEDEC_MFR(info)) {
 237         case SNOR_MFR_MICRON:
 238                 /* Some Micron need WREN command; all will accept it */
 239                 need_wren = true;
 240         case SNOR_MFR_MACRONIX:
 241         case SNOR_MFR_WINBOND:
 242                 if (need_wren)
 243                         write_enable(nor);
 244
 245                 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
 246                 status = nor->write_reg(nor, cmd, NULL, 0);
 247                 if (need_wren)
 248                         write_disable(nor);
 249
 250                 return status;
 251         default:
 252                 /* Spansion style */
 253                 nor->cmd_buf[0] = enable << 7;
 254                 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
 255         }
 256 }
 257
 258 /**
 259  * read_ear - Get the extended/bank address register value
 260  * @nor:        Pointer to the flash control structure
 261  *
 262  * This routine reads the Extended/bank address register value
 263  *
 264  * Return:      Negative if error occured.
 265  */
 266 static int read_ear(struct spi_nor *nor, struct flash_info *info)
 267 {
 268         int ret;
 269         u8 val;
 270         u8 code;
 271
 272         /* This is actually Spansion */
 273         if (JEDEC_MFR(info) == CFI_MFR_AMD)
 274                 code = SPINOR_OP_BRRD;
 275         /* This is actually Micron */
 276         else if (JEDEC_MFR(info) == CFI_MFR_ST)
 277                 code = SPINOR_OP_RDEAR;
 278         else
 279                 return -EINVAL;
 280
 281         ret = nor->read_reg(nor, code, &val, 1);
 282         if (ret < 0)
 283                 return ret;
 284
 285         return val;
 286 }
 287
 288
 289 static inline int spi_nor_sr_ready(struct spi_nor *nor)
 290 {
 291         int sr = read_sr(nor);
 292         if (sr < 0)
 293                 return sr;
 294         else
 295                 return !(sr & SR_WIP);
 296 }
 297
 298 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
 299 {
 300         int fsr = read_fsr(nor);
 301         if (fsr < 0)
 302                 return fsr;
 303         else
 304                 return fsr & FSR_READY;
 305 }
 306
 307 static int spi_nor_ready(struct spi_nor *nor)
 308 {
 309         int sr, fsr;
 310         sr = spi_nor_sr_ready(nor);
 311         if (sr < 0)
 312                 return sr;
 313         fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
 314         if (fsr < 0)
 315                 return fsr;
 316         return sr && fsr;
 317 }
 318
 319 /*
 320  * Service routine to read status register until ready, or timeout occurs.
 321  * Returns non-zero if error.
 322  */
 323 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
 324                                                 unsigned long timeout_jiffies)
 325 {
 326         unsigned long deadline;
 327         int timeout = 0, ret;
 328
 329         deadline = jiffies + timeout_jiffies;
 330
 331         while (!timeout) {
 332                 if (time_after_eq(jiffies, deadline))
 333                         timeout = 1;
 334
 335                 ret = spi_nor_ready(nor);
 336                 if (ret < 0)
 337                         return ret;
 338                 if (ret)
 339                         return 0;
 340
 341                 cond_resched();
 342         }
 343
 344         dev_err(nor->dev, "flash operation timed out\n");
 345
 346         return -ETIMEDOUT;
 347 }
 348
 349 static int spi_nor_wait_till_ready(struct spi_nor *nor)
 350 {
 351         return spi_nor_wait_till_ready_with_timeout(nor,
 352                                                     DEFAULT_READY_WAIT_JIFFIES);
 353 }
 354
 355 /*
 356  * Update Extended Address/bank selection Register.
 357  * Call with flash->lock locked.
 358  */
 359 static int write_ear(struct spi_nor *nor, u32 addr)
 360 {
 361         u8 code;
 362         u8 ear;
 363         int ret;
 364         struct mtd_info *mtd = &nor->mtd;
 365
 366         /* Wait until finished previous write command. */
 367         if (spi_nor_wait_till_ready(nor))
 368                 return 1;
 369
 370         if (mtd->size <= (0x1000000) << nor->shift)
 371                 return 0;
 372
 373         addr = addr % (u32) mtd->size;
 374         ear = addr >> 24;
 375
 376         if ((!nor->isstacked) && (ear == nor->curbank))
 377                 return 0;
 378
 379         if (nor->isstacked && (mtd->size <= 0x2000000))
 380                 return 0;
 381
 382         if (nor->jedec_id == CFI_MFR_AMD)
 383                 code = SPINOR_OP_BRWR;
 384         if (nor->jedec_id == CFI_MFR_ST) {
 385                 write_enable(nor);
 386                 code = SPINOR_OP_WREAR;
 387         }
 388         nor->cmd_buf[0] = ear;
 389
 390         ret = nor->write_reg(nor, code, nor->cmd_buf, 1);
 391         if (ret < 0)
 392                 return ret;
 393
 394         nor->curbank = ear;
 395
 396         return 0;
 397 }
 398
 399 /*
 400  * Erase the whole flash memory
 401  *
 402  * Returns 0 if successful, non-zero otherwise.
 403  */
 404 static int erase_chip(struct spi_nor *nor)
 405 {
 406         u32 ret;
 407
 408         dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
 409
 410         if (nor->isstacked)
 411                 nor->spi->master->flags &= ~SPI_MASTER_U_PAGE;
 412
 413         ret = nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
 414         if (ret)
 415                 return ret;
 416
 417         if (nor->isstacked) {
 418                 /* Wait until previous write command finished */
 419                 ret = spi_nor_wait_till_ready(nor);
 420                 if (ret)
 421                         return ret;
 422
 423                 nor->spi->master->flags |= SPI_MASTER_U_PAGE;
 424
 425                 ret = nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
 426         }
 427         return ret;
 428
 429 }
 430
 431 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 432 {
 433         int ret = 0;
 434
 435         mutex_lock(&nor->lock);
 436
 437         if (nor->prepare) {
 438                 ret = nor->prepare(nor, ops);
 439                 if (ret) {
 440                         dev_err(nor->dev, "failed in the preparation.\n");
 441                         mutex_unlock(&nor->lock);
 442                         return ret;
 443                 }
 444         }
 445         return ret;
 446 }
 447
 448 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 449 {
 450         if (nor->unprepare)
 451                 nor->unprepare(nor, ops);
 452         mutex_unlock(&nor->lock);
 453 }
 454
 455 /*
 456  * Initiate the erasure of a single sector
 457  */
 458 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
 459 {
 460         u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
 461         int i;
 462
 463         if (nor->erase)
 464                 return nor->erase(nor, addr);
 465
 466         /*
 467          * Default implementation, if driver doesn't have a specialized HW
 468          * control
 469          */
 470         for (i = nor->addr_width - 1; i >= 0; i--) {
 471                 buf[i] = addr & 0xff;
 472                 addr >>= 8;
 473         }
 474
 475         return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
 476 }
 477
 478 /*
 479  * Erase an address range on the nor chip.  The address range may extend
 480  * one or more erase sectors.  Return an error is there is a problem erasing.
 481  */
 482 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
 483 {
 484         struct spi_nor *nor = mtd_to_spi_nor(mtd);
 485         u32 addr, len, offset;
 486         uint32_t rem;
 487         int ret;
 488
 489         dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
 490                         (long long)instr->len);
 491
 492         div_u64_rem(instr->len, mtd->erasesize, &rem);
 493         if (rem)
 494                 return -EINVAL;
 495
 496         addr = instr->addr;
 497         len = instr->len;
 498
 499         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
 500         if (ret)
 501                 return ret;
 502
 503         /* whole-chip erase? */
 504         if (len == mtd->size) {
 505                 unsigned long timeout;
 506
 507                 write_enable(nor);
 508
 509                 if (erase_chip(nor)) {
 510                         ret = -EIO;
 511                         goto erase_err;
 512                 }
 513
 514                 /*
 515                  * Scale the timeout linearly with the size of the flash, with
 516                  * a minimum calibrated to an old 2MB flash. We could try to
 517                  * pull these from CFI/SFDP, but these values should be good
 518                  * enough for now.
 519                  */
 520                 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
 521                               CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
 522                               (unsigned long)(mtd->size / SZ_2M));
 523                 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
 524                 if (ret)
 525                         goto erase_err;
 526
 527         /* REVISIT in some cases we could speed up erasing large regions
 528          * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K.  We may have set up
 529          * to use "small sector erase", but that's not always optimal.
 530          */
 531
 532         /* "sector"-at-a-time erase */
 533         } else {
 534                 while (len) {
 535
 536                         write_enable(nor);
 537                         offset = addr;
 538                         if (nor->isparallel == 1)
 539                                 offset /= 2;
 540
 541                         if (nor->isstacked == 1) {
 542                                 if (offset >= (mtd->size / 2)) {
 543                                         offset = offset - (mtd->size / 2);
 544                                         nor->spi->master->flags |=
 545                                                 SPI_MASTER_U_PAGE;
 546                                 } else {
 547                                         nor->spi->master->flags &=
 548                                                 ~SPI_MASTER_U_PAGE;
 549                                 }
 550                         }
 551                         if (nor->addr_width == 3) {
 552                                 /* Update Extended Address Register */
 553                                 ret = write_ear(nor, offset);
 554                                 if (ret)
 555                                         goto erase_err;
 556                         }
 557                         ret = spi_nor_wait_till_ready(nor);
 558                         if (ret)
 559                                 goto erase_err;
 560                         ret = spi_nor_erase_sector(nor, offset);
 561                         if (ret)
 562                                 goto erase_err;
 563
 564                         addr += mtd->erasesize;
 565                         len -= mtd->erasesize;
 566
 567                         ret = spi_nor_wait_till_ready(nor);
 568                         if (ret)
 569                                 goto erase_err;
 570                 }
 571         }
 572
 573         write_disable(nor);
 574
 575 erase_err:
 576         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
 577
 578         instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
 579         mtd_erase_callback(instr);
 580
 581         return ret;
 582 }
 583
 584 static inline uint16_t min_lockable_sectors(struct spi_nor *nor,
 585                                             uint16_t n_sectors)
 586 {
 587         uint16_t lock_granularity;
 588
 589         /*
 590          * Revisit - SST (not used by us) has the same JEDEC ID as micron but
 591          * protected area table is similar to that of spansion.
 592          */
 593         lock_granularity = max(1, n_sectors/M25P_MAX_LOCKABLE_SECTORS);
 594         if (nor->jedec_id == CFI_MFR_ST)        /* Micron */
 595                 lock_granularity = 1;
 596
 597         return lock_granularity;
 598 }
 599
 600 static inline uint32_t get_protected_area_start(struct spi_nor *nor,
 601                                                 uint8_t lock_bits)
 602 {
 603         u16 n_sectors;
 604         u32 sector_size;
 605         uint64_t mtd_size;
 606         struct mtd_info *mtd = &nor->mtd;
 607
 608         n_sectors = nor->n_sectors;
 609         sector_size = nor->sector_size;
 610         mtd_size = mtd->size;
 611
 612         if (nor->isparallel) {
 613                 sector_size = (nor->sector_size >> 1);
 614                 mtd_size = (mtd->size >> 1);
 615         }
 616         if (nor->isstacked) {
 617                 n_sectors = (nor->n_sectors >> 1);
 618                 mtd_size = (mtd->size >> 1);
 619         }
 620
 621         return mtd_size - (1<<(lock_bits-1)) *
 622                 min_lockable_sectors(nor, n_sectors) * sector_size;
 623 }
 624
 625 static uint8_t min_protected_area_including_offset(struct spi_nor *nor,
 626                                                    uint32_t offset)
 627 {
 628         uint8_t lock_bits, lockbits_limit;
 629
 630         /*
 631          * Revisit - SST (not used by us) has the same JEDEC ID as micron but
 632          * protected area table is similar to that of spansion.
 633          * Mircon has 4 block protect bits.
 634          */
 635         lockbits_limit = 7;
 636         if (nor->jedec_id == CFI_MFR_ST)        /* Micron */
 637                 lockbits_limit = 15;
 638
 639         for (lock_bits = 1; lock_bits < lockbits_limit; lock_bits++) {
 640                 if (offset >= get_protected_area_start(nor, lock_bits))
 641                         break;
 642         }
 643         return lock_bits;
 644 }
 645
 646 static int write_sr_modify_protection(struct spi_nor *nor, uint8_t status,
 647                                       uint8_t lock_bits)
 648 {
 649         uint8_t status_new, bp_mask;
 650         u16 val;
 651
 652         status_new = status & ~SR_BP_BIT_MASK;
 653         bp_mask = (lock_bits << SR_BP_BIT_OFFSET) & SR_BP_BIT_MASK;
 654
 655         /* Micron */
 656         if (nor->jedec_id == CFI_MFR_ST) {
 657                 /* To support chips with more than 896 sectors (56MB) */
 658                 status_new &= ~SR_BP3;
 659
 660                 /* Protected area starts from top */
 661                 status_new &= ~SR_BP_TB;
 662
 663                 if (lock_bits > 7)
 664                         bp_mask |= SR_BP3;
 665         }
 666
 667         status_new |= bp_mask;
 668
 669         write_enable(nor);
 670
 671         /* For spansion flashes */
 672         if (nor->jedec_id == CFI_MFR_AMD) {
 673                 val = read_cr(nor) << 8;
 674                 val |= status_new;
 675                 if (write_sr_cr(nor, val) < 0)
 676                         return 1;
 677         } else {
 678                 if (write_sr(nor, status_new) < 0)
 679                         return 1;
 680         }
 681         return 0;
 682 }
 683
 684 static uint8_t bp_bits_from_sr(struct spi_nor *nor, uint8_t status)
 685 {
 686         uint8_t ret;
 687
 688         ret = (((status) & SR_BP_BIT_MASK) >> SR_BP_BIT_OFFSET);
 689         if (nor->jedec_id == 0x20)
 690                 ret |= ((status & SR_BP3) >> (SR_BP_BIT_OFFSET + 1));
 691
 692         return ret;
 693 }
 694
 695
 696 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
 697                                  uint64_t *len)
 698 {
 699         struct mtd_info *mtd = &nor->mtd;
 700         u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 701         int shift = ffs(mask) - 1;
 702         int pow;
 703
 704         if (!(sr & mask)) {
 705                 /* No protection */
 706                 *ofs = 0;
 707                 *len = 0;
 708         } else {
 709                 pow = ((sr & mask) ^ mask) >> shift;
 710                 *len = mtd->size >> pow;
 711                 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
 712                         *ofs = 0;
 713                 else
 714                         *ofs = mtd->size - *len;
 715         }
 716 }
 717
 718 /*
 719  * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
 720  * @locked is false); 0 otherwise
 721  */
 722 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
 723                                     u8 sr, bool locked)
 724 {
 725         loff_t lock_offs;
 726         uint64_t lock_len;
 727
 728         if (!len)
 729                 return 1;
 730
 731         stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
 732
 733         if (locked)
 734                 /* Requested range is a sub-range of locked range */
 735                 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
 736         else
 737                 /* Requested range does not overlap with locked range */
 738                 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
 739 }
 740
 741 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
 742                             u8 sr)
 743 {
 744         return stm_check_lock_status_sr(nor, ofs, len, sr, true);
 745 }
 746
 747 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
 748                               u8 sr)
 749 {
 750         return stm_check_lock_status_sr(nor, ofs, len, sr, false);
 751 }
 752
 753 /*
 754  * Lock a region of the flash. Compatible with ST Micro and similar flash.
 755  * Supports the block protection bits BP{0,1,2} in the status register
 756  * (SR). Does not support these features found in newer SR bitfields:
 757  *   - SEC: sector/block protect - only handle SEC=0 (block protect)
 758  *   - CMP: complement protect - only support CMP=0 (range is not complemented)
 759  *
 760  * Support for the following is provided conditionally for some flash:
 761  *   - TB: top/bottom protect
 762  *
 763  * Sample table portion for 8MB flash (Winbond w25q64fw):
 764  *
 765  *   SEC  |  TB   |  BP2  |  BP1  |  BP0  |  Prot Length  | Protected Portion
 766  *  --------------------------------------------------------------------------
 767  *    X   |   X   |   0   |   0   |   0   |  NONE         | NONE
 768  *    0   |   0   |   0   |   0   |   1   |  128 KB       | Upper 1/64
 769  *    0   |   0   |   0   |   1   |   0   |  256 KB       | Upper 1/32
 770  *    0   |   0   |   0   |   1   |   1   |  512 KB       | Upper 1/16
 771  *    0   |   0   |   1   |   0   |   0   |  1 MB         | Upper 1/8
 772  *    0   |   0   |   1   |   0   |   1   |  2 MB         | Upper 1/4
 773  *    0   |   0   |   1   |   1   |   0   |  4 MB         | Upper 1/2
 774  *    X   |   X   |   1   |   1   |   1   |  8 MB         | ALL
 775  *  ------|-------|-------|-------|-------|---------------|-------------------
 776  *    0   |   1   |   0   |   0   |   1   |  128 KB       | Lower 1/64
 777  *    0   |   1   |   0   |   1   |   0   |  256 KB       | Lower 1/32
 778  *    0   |   1   |   0   |   1   |   1   |  512 KB       | Lower 1/16
 779  *    0   |   1   |   1   |   0   |   0   |  1 MB         | Lower 1/8
 780  *    0   |   1   |   1   |   0   |   1   |  2 MB         | Lower 1/4
 781  *    0   |   1   |   1   |   1   |   0   |  4 MB         | Lower 1/2
 782  *
 783  * Returns negative on errors, 0 on success.
 784  */
 785 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 786 {
 787         struct mtd_info *mtd = &nor->mtd;
 788         int status_old, status_new;
 789         u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 790         u8 shift = ffs(mask) - 1, pow, val;
 791         loff_t lock_len;
 792         bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
 793         bool use_top;
 794         int ret;
 795
 796         ofs = ofs >> nor->shift;
 797
 798         status_old = read_sr(nor);
 799         if (status_old < 0)
 800                 return status_old;
 801
 802         /* If nothing in our range is unlocked, we don't need to do anything */
 803         if (stm_is_locked_sr(nor, ofs, len, status_old))
 804                 return 0;
 805
 806         /* If anything below us is unlocked, we can't use 'bottom' protection */
 807         if (!stm_is_locked_sr(nor, 0, ofs, status_old))
 808                 can_be_bottom = false;
 809
 810         /* If anything above us is unlocked, we can't use 'top' protection */
 811         if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
 812                                 status_old))
 813                 can_be_top = false;
 814
 815         if (!can_be_bottom && !can_be_top)
 816                 return -EINVAL;
 817
 818         /* Prefer top, if both are valid */
 819         use_top = can_be_top;
 820
 821         /* lock_len: length of region that should end up locked */
 822         if (use_top)
 823                 lock_len = mtd->size - ofs;
 824         else
 825                 lock_len = ofs + len;
 826
 827         /*
 828          * Need smallest pow such that:
 829          *
 830          *   1 / (2^pow) <= (len / size)
 831          *
 832          * so (assuming power-of-2 size) we do:
 833          *
 834          *   pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
 835          */
 836         pow = ilog2(mtd->size) - ilog2(lock_len);
 837         val = mask - (pow << shift);
 838         if (val & ~mask)
 839                 return -EINVAL;
 840         /* Don't "lock" with no region! */
 841         if (!(val & mask))
 842                 return -EINVAL;
 843
 844         status_new = (status_old & ~mask & ~SR_TB) | val;
 845
 846         /* Disallow further writes if WP pin is asserted */
 847         status_new |= SR_SRWD;
 848
 849         if (!use_top)
 850                 status_new |= SR_TB;
 851
 852         /* Don't bother if they're the same */
 853         if (status_new == status_old)
 854                 return 0;
 855
 856         /* Only modify protection if it will not unlock other areas */
 857         if ((status_new & mask) < (status_old & mask))
 858                 return -EINVAL;
 859
 860         write_enable(nor);
 861         ret = write_sr(nor, status_new);
 862         if (ret)
 863                 return ret;
 864         return spi_nor_wait_till_ready(nor);
 865 }
 866
 867 /*
 868  * Unlock a region of the flash. See stm_lock() for more info
 869  *
 870  * Returns negative on errors, 0 on success.
 871  */
 872 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 873 {
 874         struct mtd_info *mtd = &nor->mtd;
 875         int status_old, status_new;
 876         u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 877         u8 shift = ffs(mask) - 1, pow, val;
 878         loff_t lock_len;
 879         bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
 880         bool use_top;
 881         int ret;
 882
 883         ofs = ofs >> nor->shift;
 884
 885         status_old = read_sr(nor);
 886         if (status_old < 0)
 887                 return status_old;
 888
 889         /* If nothing in our range is locked, we don't need to do anything */
 890         if (stm_is_unlocked_sr(nor, ofs, len, status_old))
 891                 return 0;
 892
 893         /* If anything below us is locked, we can't use 'top' protection */
 894         if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
 895                 can_be_top = false;
 896
 897         /* If anything above us is locked, we can't use 'bottom' protection */
 898         if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
 899                                 status_old))
 900                 can_be_bottom = false;
 901
 902         if (!can_be_bottom && !can_be_top)
 903                 return -EINVAL;
 904
 905         /* Prefer top, if both are valid */
 906         use_top = can_be_top;
 907
 908         /* lock_len: length of region that should remain locked */
 909         if (use_top)
 910                 lock_len = mtd->size - (ofs + len);
 911         else
 912                 lock_len = ofs;
 913
 914         /*
 915          * Need largest pow such that:
 916          *
 917          *   1 / (2^pow) >= (len / size)
 918          *
 919          * so (assuming power-of-2 size) we do:
 920          *
 921          *   pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
 922          */
 923         pow = ilog2(mtd->size) - order_base_2(lock_len);
 924         if (lock_len == 0) {
 925                 val = 0; /* fully unlocked */
 926         } else {
 927                 val = mask - (pow << shift);
 928                 /* Some power-of-two sizes are not supported */
 929                 if (val & ~mask)
 930                         return -EINVAL;
 931         }
 932
 933         status_new = (status_old & ~mask & ~SR_TB) | val;
 934
 935         /* Don't protect status register if we're fully unlocked */
 936         if (lock_len == 0)
 937                 status_new &= ~SR_SRWD;
 938
 939         if (!use_top)
 940                 status_new |= SR_TB;
 941
 942         /* Don't bother if they're the same */
 943         if (status_new == status_old)
 944                 return 0;
 945
 946         /* Only modify protection if it will not lock other areas */
 947         if ((status_new & mask) > (status_old & mask))
 948                 return -EINVAL;
 949
 950         write_enable(nor);
 951         ret = write_sr(nor, status_new);
 952         if (ret)
 953                 return ret;
 954         return spi_nor_wait_till_ready(nor);
 955 }
 956
 957 /*
 958  * Check if a region of the flash is (completely) locked. See stm_lock() for
 959  * more info.
 960  *
 961  * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
 962  * negative on errors.
 963  */
 964 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
 965 {
 966         int status;
 967
 968         status = read_sr(nor);
 969         if (status < 0)
 970                 return status;
 971
 972         return stm_is_locked_sr(nor, ofs, len, status);
 973 }
 974
 975 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 976 {
 977         struct spi_nor *nor = mtd_to_spi_nor(mtd);
 978         int ret;
 979         uint8_t status;
 980         uint8_t lock_bits;
 981
 982         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
 983         if (ret)
 984                 return ret;
 985
 986         if (nor->isparallel == 1)
 987                 ofs = ofs >> nor->shift;
 988
 989         if (nor->isstacked == 1) {
 990                 if (ofs >= (mtd->size / 2)) {
 991                         ofs = ofs - (mtd->size / 2);
 992                         nor->spi->master->flags |= SPI_MASTER_U_PAGE;
 993                 } else
 994                         nor->spi->master->flags &= ~SPI_MASTER_U_PAGE;
 995         }
 996
 997         ret = nor->flash_lock(nor, ofs, len);
 998         /* Wait until finished previous command */
 999         ret = spi_nor_wait_till_ready(nor);
1000         if (ret)
1001                 goto err;
1002
1003         status = read_sr(nor);
1004
1005         lock_bits = min_protected_area_including_offset(nor, ofs);
1006
1007         /* Only modify protection if it will not unlock other areas */
1008         if (lock_bits > bp_bits_from_sr(nor, status))
1009                 ret = write_sr_modify_protection(nor, status, lock_bits);
1010         else
1011                 dev_err(nor->dev, "trying to unlock already locked area\n");
1012 err:
1013         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1014         return ret;
1015 }
1016
1017 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1018 {
1019         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1020         int ret;
1021         uint8_t status;
1022         uint8_t lock_bits;
1023
1024         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1025         if (ret)
1026                 return ret;
1027
1028         if (nor->isparallel == 1)
1029                 ofs = ofs >> nor->shift;
1030
1031         if (nor->isstacked == 1) {
1032                 if (ofs >= (mtd->size / 2)) {
1033                         ofs = ofs - (mtd->size / 2);
1034                         nor->spi->master->flags |= SPI_MASTER_U_PAGE;
1035                 } else
1036                         nor->spi->master->flags &= ~SPI_MASTER_U_PAGE;
1037         }
1038
1039         ret = nor->flash_unlock(nor, ofs, len);
1040         /* Wait until finished previous command */
1041         ret = spi_nor_wait_till_ready(nor);
1042         if (ret)
1043                 goto err;
1044
1045         status = read_sr(nor);
1046
1047         lock_bits = min_protected_area_including_offset(nor, ofs+len) - 1;
1048
1049         /* Only modify protection if it will not lock other areas */
1050         if (lock_bits < bp_bits_from_sr(nor, status))
1051                 ret = write_sr_modify_protection(nor, status, lock_bits);
1052         else
1053                 dev_err(nor->dev, "trying to lock already unlocked area\n");
1054 err:
1055         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1056         return ret;
1057 }
1058
1059 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1060 {
1061         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1062         int ret;
1063
1064         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1065         if (ret)
1066                 return ret;
1067
1068         ret = nor->flash_is_locked(nor, ofs, len);
1069
1070         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1071         return ret;
1072 }
1073
1074 /* Used when the "_ext_id" is two bytes at most */
1075 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)      \
1076                 .id = {                                                 \
1077                         ((_jedec_id) >> 16) & 0xff,                     \
1078                         ((_jedec_id) >> 8) & 0xff,                      \
1079                         (_jedec_id) & 0xff,                             \
1080                         ((_ext_id) >> 8) & 0xff,                        \
1081                         (_ext_id) & 0xff,                               \
1082                         },                                              \
1083                 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),       \
1084                 .sector_size = (_sector_size),                          \
1085                 .n_sectors = (_n_sectors),                              \
1086                 .page_size = 256,                                       \
1087                 .flags = (_flags),
1088
1089 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)     \
1090                 .id = {                                                 \
1091                         ((_jedec_id) >> 16) & 0xff,                     \
1092                         ((_jedec_id) >> 8) & 0xff,                      \
1093                         (_jedec_id) & 0xff,                             \
1094                         ((_ext_id) >> 16) & 0xff,                       \
1095                         ((_ext_id) >> 8) & 0xff,                        \
1096                         (_ext_id) & 0xff,                               \
1097                         },                                              \
1098                 .id_len = 6,                                            \
1099                 .sector_size = (_sector_size),                          \
1100                 .n_sectors = (_n_sectors),                              \
1101                 .page_size = 256,                                       \
1102                 .flags = (_flags),
1103
1104 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags)   \
1105                 .sector_size = (_sector_size),                          \
1106                 .n_sectors = (_n_sectors),                              \
1107                 .page_size = (_page_size),                              \
1108                 .addr_width = (_addr_width),                            \
1109                 .flags = (_flags),
1110
1111 /* NOTE: double check command sets and memory organization when you add
1112  * more nor chips.  This current list focusses on newer chips, which
1113  * have been converging on command sets which including JEDEC ID.
1114  *
1115  * All newly added entries should describe *hardware* and should use SECT_4K
1116  * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
1117  * scenarios excluding small sectors there is config option that can be
1118  * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
1119  * For historical (and compatibility) reasons (before we got above config) some
1120  * old entries may be missing 4K flag.
1121  */
1122 static const struct flash_info spi_nor_ids[] = {
1123         /* Atmel -- some are (confusingly) marketed as "DataFlash" */
1124         { "at25fs010",  INFO(0x1f6601, 0, 32 * 1024,   4, SECT_4K) },
1125         { "at25fs040",  INFO(0x1f6604, 0, 64 * 1024,   8, SECT_4K) },
1126
1127         { "at25df041a", INFO(0x1f4401, 0, 64 * 1024,   8, SECT_4K) },
1128         { "at25df321a", INFO(0x1f4701, 0, 64 * 1024,  64, SECT_4K) },
1129         { "at25df641",  INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
1130
1131         { "at26f004",   INFO(0x1f0400, 0, 64 * 1024,  8, SECT_4K) },
1132         { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
1133         { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
1134         { "at26df321",  INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1135
1136         { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
1137
1138         /* EON -- en25xxx */
1139         { "en25f32",    INFO(0x1c3116, 0, 64 * 1024,   64, SECT_4K) },
1140         { "en25p32",    INFO(0x1c2016, 0, 64 * 1024,   64, 0) },
1141         { "en25q32b",   INFO(0x1c3016, 0, 64 * 1024,   64, 0) },
1142         { "en25p64",    INFO(0x1c2017, 0, 64 * 1024,  128, 0) },
1143         { "en25q64",    INFO(0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
1144         { "en25qh128",  INFO(0x1c7018, 0, 64 * 1024,  256, 0) },
1145         { "en25qh256",  INFO(0x1c7019, 0, 64 * 1024,  512, 0) },
1146         { "en25s64",    INFO(0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
1147
1148         /* ESMT */
1149         { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
1150
1151         /* Everspin */
1152         { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1153         { "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1154
1155         /* Fujitsu */
1156         { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
1157
1158         /* GigaDevice */
1159         {
1160                 "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,
1161                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1162                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1163         },
1164         {
1165                 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
1166                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1167                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1168         },
1169         {
1170                 "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
1171                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1172                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1173         },
1174         {
1175                 "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
1176                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1177                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1178         },
1179
1180         /* Intel/Numonyx -- xxxs33b */
1181         { "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },
1182         { "320s33b",  INFO(0x898912, 0, 64 * 1024,  64, 0) },
1183         { "640s33b",  INFO(0x898913, 0, 64 * 1024, 128, 0) },
1184
1185         /* ISSI */
1186         { "is25lp256d", INFO(0x9d6019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR | SPI_NOR_HAS_LOCK) },
1187         { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },
1188
1189         /* Macronix */
1190         { "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },
1191         { "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
1192         { "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
1193         { "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
1194         { "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
1195         { "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
1196         { "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
1197         { "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
1198         { "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
1199         { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1200         { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1201         { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
1202         { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1203         { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
1204         { "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1205
1206         /* Micron */
1207         { "n25q032",     INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
1208         { "n25q032a",    INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
1209         { "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
1210         { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
1211         { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR | SPI_NOR_HAS_LOCK) },
1212         { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR | SPI_NOR_HAS_LOCK) },
1213         { "n25q256a",    INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR| SPI_NOR_HAS_LOCK) },
1214         { "n25q256a13",  INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR | SPI_NOR_HAS_LOCK) },
1215         { "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1216         { "n25q512a13",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR | SPI_NOR_HAS_LOCK) },
1217         { "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1218         { "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1219         { "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1220
1221         /* PMC */
1222         { "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
1223         { "pm25lv010",   INFO(0,        0, 32 * 1024,    4, SECT_4K_PMC) },
1224         { "pm25lq032",   INFO(0x7f9d46, 0, 64 * 1024,   64, SECT_4K) },
1225
1226         /* Spansion -- single (large) sector size only, at least
1227          * for the chips listed here (without boot sectors).
1228          */
1229         { "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1230         { "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1231         { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1232         { "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1233         { "s25fl512s",  INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1234         { "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1235         { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, SPI_NOR_HAS_LOCK) },
1236         { "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, SPI_NOR_HAS_LOCK) },
1237         { "s25fl128s",  INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
1238         { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1239         { "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
1240         { "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
1241         { "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
1242         { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
1243         { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
1244         { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
1245         { "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1246         { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1247         { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1248         { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },
1249         { "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1250         { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },
1251         { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
1252         { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ) },
1253         { "sst26wf016B", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K | SST_GLOBAL_PROT_UNLK) },
1254
1255         /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1256         { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
1257         { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1258         { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1259         { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1260         { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1261         { "sst25wf512",  INFO(0xbf2501, 0, 64 * 1024,  1, SECT_4K | SST_WRITE) },
1262         { "sst25wf010",  INFO(0xbf2502, 0, 64 * 1024,  2, SECT_4K | SST_WRITE) },
1263         { "sst25wf020",  INFO(0xbf2503, 0, 64 * 1024,  4, SECT_4K | SST_WRITE) },
1264         { "sst25wf020a", INFO(0x621612, 0, 64 * 1024,  4, SECT_4K) },
1265         { "sst25wf040b", INFO(0x621613, 0, 64 * 1024,  8, SECT_4K) },
1266         { "sst25wf040",  INFO(0xbf2504, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
1267         { "sst25wf080",  INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1268
1269         /* ST Microelectronics -- newer production may have feature updates */
1270         { "m25p05",  INFO(0x202010,  0,  32 * 1024,   2, 0) },
1271         { "m25p10",  INFO(0x202011,  0,  32 * 1024,   4, 0) },
1272         { "m25p20",  INFO(0x202012,  0,  64 * 1024,   4, 0) },
1273         { "m25p40",  INFO(0x202013,  0,  64 * 1024,   8, 0) },
1274         { "m25p80",  INFO(0x202014,  0,  64 * 1024,  16, 0) },
1275         { "m25p16",  INFO(0x202015,  0,  64 * 1024,  32, 0) },
1276         { "m25p32",  INFO(0x202016,  0,  64 * 1024,  64, 0) },
1277         { "m25p64",  INFO(0x202017,  0,  64 * 1024, 128, 0) },
1278         { "m25p128", INFO(0x202018,  0, 256 * 1024,  64, 0) },
1279
1280         { "m25p05-nonjedec",  INFO(0, 0,  32 * 1024,   2, 0) },
1281         { "m25p10-nonjedec",  INFO(0, 0,  32 * 1024,   4, 0) },
1282         { "m25p20-nonjedec",  INFO(0, 0,  64 * 1024,   4, 0) },
1283         { "m25p40-nonjedec",  INFO(0, 0,  64 * 1024,   8, 0) },
1284         { "m25p80-nonjedec",  INFO(0, 0,  64 * 1024,  16, 0) },
1285         { "m25p16-nonjedec",  INFO(0, 0,  64 * 1024,  32, 0) },
1286         { "m25p32-nonjedec",  INFO(0, 0,  64 * 1024,  64, 0) },
1287         { "m25p64-nonjedec",  INFO(0, 0,  64 * 1024, 128, 0) },
1288         { "m25p128-nonjedec", INFO(0, 0, 256 * 1024,  64, 0) },
1289
1290         { "m45pe10", INFO(0x204011,  0, 64 * 1024,    2, 0) },
1291         { "m45pe80", INFO(0x204014,  0, 64 * 1024,   16, 0) },
1292         { "m45pe16", INFO(0x204015,  0, 64 * 1024,   32, 0) },
1293
1294         { "m25pe20", INFO(0x208012,  0, 64 * 1024,  4,       0) },
1295         { "m25pe80", INFO(0x208014,  0, 64 * 1024, 16,       0) },
1296         { "m25pe16", INFO(0x208015,  0, 64 * 1024, 32, SECT_4K) },
1297
1298         { "m25px16",    INFO(0x207115,  0, 64 * 1024, 32, SECT_4K) },
1299         { "m25px32",    INFO(0x207116,  0, 64 * 1024, 64, SECT_4K) },
1300         { "m25px32-s0", INFO(0x207316,  0, 64 * 1024, 64, SECT_4K) },
1301         { "m25px32-s1", INFO(0x206316,  0, 64 * 1024, 64, SECT_4K) },
1302         { "m25px64",    INFO(0x207117,  0, 64 * 1024, 128, 0) },
1303         { "m25px80",    INFO(0x207114,  0, 64 * 1024, 16, 0) },
1304
1305         /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1306         { "w25x05", INFO(0xef3010, 0, 64 * 1024,  1,  SECT_4K) },
1307         { "w25x10", INFO(0xef3011, 0, 64 * 1024,  2,  SECT_4K) },
1308         { "w25x20", INFO(0xef3012, 0, 64 * 1024,  4,  SECT_4K) },
1309         { "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
1310         { "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
1311         { "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
1312         { "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
1313         { "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
1314         {
1315                 "w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
1316                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1317                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1318         },
1319         { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1320         { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1321         {
1322                 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
1323                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1324                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1325         },
1326         {
1327                 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
1328                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
1329                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
1330         },
1331         { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
1332         { "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
1333         { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K| SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1334         { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K| SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1335
1336         /* Catalyst / On Semiconductor -- non-JEDEC */
1337         { "cat25c11", CAT25_INFO(  16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1338         { "cat25c03", CAT25_INFO(  32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1339         { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1340         { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1341         { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1342         { },
1343 };
1344
1345 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
1346 {
1347         int                     tmp;
1348         u8                      id[SPI_NOR_MAX_ID_LEN];
1349         const struct flash_info *info;
1350
1351         tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
1352         if (tmp < 0) {
1353                 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
1354                 return ERR_PTR(tmp);
1355         }
1356
1357         for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1358                 info = &spi_nor_ids[tmp];
1359                 if (info->id_len) {
1360                         if (!memcmp(info->id, id, info->id_len))
1361                                 return &spi_nor_ids[tmp];
1362                 }
1363         }
1364         dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
1365                 id[0], id[1], id[2]);
1366         return ERR_PTR(-ENODEV);
1367 }
1368
1369 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1370                         size_t *retlen, u_char *buf)
1371 {
1372         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1373         int ret;
1374         u32 offset = from;
1375         u32 stack_shift = 0;
1376         u32 read_len = 0;
1377         u32 rem_bank_len = 0;
1378         u8 bank;
1379         u8 is_ofst_odd = 0;
1380
1381 #define OFFSET_16_MB 0x1000000
1382
1383         dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1384
1385         if ((nor->isparallel) && (offset & 1)) {
1386                 /* We can hit this case when we use file system like ubifs */
1387                 from = (loff_t)(from - 1);
1388                 len = (size_t)(len + 1);
1389                 is_ofst_odd = 1;
1390         }
1391
1392         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1393         if (ret)
1394                 return ret;
1395
1396         while (len) {
1397
1398                 if (nor->addr_width == 3) {
1399                         bank = (u32)from / (OFFSET_16_MB << nor->shift);
1400                         rem_bank_len = ((OFFSET_16_MB << nor->shift) *
1401                                                         (bank + 1)) - from;
1402                 }
1403                 offset = from;
1404
1405                 if (nor->isparallel == 1)
1406                         offset /= 2;
1407
1408                 if (nor->isstacked == 1) {
1409                         stack_shift = 1;
1410                         if (offset >= (mtd->size / 2)) {
1411                                 offset = offset - (mtd->size / 2);
1412                                 nor->spi->master->flags |= SPI_MASTER_U_PAGE;
1413                         } else {
1414                                 nor->spi->master->flags &= ~SPI_MASTER_U_PAGE;
1415                         }
1416                 }
1417
1418                 /* Die cross over issue is not handled */
1419                 if (nor->addr_width == 4) {
1420                         rem_bank_len = (mtd->size >> stack_shift) -
1421                                         (offset << nor->shift);
1422                 }
1423                 if (nor->addr_width == 3)
1424                         write_ear(nor, offset);
1425                 if (len < rem_bank_len)
1426                         read_len = len;
1427                 else
1428                         read_len = rem_bank_len;
1429
1430                 /* Wait till previous write/erase is done. */
1431                 ret = spi_nor_wait_till_ready(nor);
1432                 if (ret)
1433                         goto read_err;
1434
1435                 ret = nor->read(nor, offset, read_len, buf);
1436                 if (ret == 0) {
1437                         /* We shouldn't see 0-length reads */
1438                         ret = -EIO;
1439                         goto read_err;
1440                 }
1441                 if (ret < 0)
1442                         goto read_err;
1443
1444                 WARN_ON(ret > len);
1445                 if (is_ofst_odd == 1) {
1446                         memcpy(buf, (buf + 1), (len - 1));
1447                         *retlen += (ret - 1);
1448                 } else {
1449                         *retlen += ret;
1450                 }
1451                 buf += ret;
1452                 from += ret;
1453                 len -= ret;
1454         }
1455         ret = 0;
1456
1457 read_err:
1458         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1459         return ret;
1460 }
1461
1462 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1463                 size_t *retlen, const u_char *buf)
1464 {
1465         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1466         size_t actual;
1467         int ret;
1468
1469         dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1470
1471         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1472         if (ret)
1473                 return ret;
1474
1475         write_enable(nor);
1476
1477         nor->sst_write_second = false;
1478
1479         actual = to % 2;
1480         /* Start write from odd address. */
1481         if (actual) {
1482                 nor->program_opcode = SPINOR_OP_BP;
1483
1484                 /* write one byte. */
1485                 ret = nor->write(nor, to, 1, buf);
1486                 if (ret < 0)
1487                         goto sst_write_err;
1488                 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1489                      (int)ret);
1490                 ret = spi_nor_wait_till_ready(nor);
1491                 if (ret)
1492                         goto sst_write_err;
1493         }
1494         to += actual;
1495
1496         /* Write out most of the data here. */
1497         for (; actual < len - 1; actual += 2) {
1498                 nor->program_opcode = SPINOR_OP_AAI_WP;
1499
1500                 /* write two bytes. */
1501                 ret = nor->write(nor, to, 2, buf + actual);
1502                 if (ret < 0)
1503                         goto sst_write_err;
1504                 WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
1505                      (int)ret);
1506                 ret = spi_nor_wait_till_ready(nor);
1507                 if (ret)
1508                         goto sst_write_err;
1509                 to += 2;
1510                 nor->sst_write_second = true;
1511         }
1512         nor->sst_write_second = false;
1513
1514         write_disable(nor);
1515         ret = spi_nor_wait_till_ready(nor);
1516         if (ret)
1517                 goto sst_write_err;
1518
1519         /* Write out trailing byte if it exists. */
1520         if (actual != len) {
1521                 write_enable(nor);
1522
1523                 nor->program_opcode = SPINOR_OP_BP;
1524                 ret = nor->write(nor, to, 1, buf + actual);
1525                 if (ret < 0)
1526                         goto sst_write_err;
1527                 WARN(ret != 1, "While writing 1 byte written %i bytes\n",
1528                      (int)ret);
1529                 ret = spi_nor_wait_till_ready(nor);
1530                 if (ret)
1531                         goto sst_write_err;
1532                 write_disable(nor);
1533                 actual += 1;
1534         }
1535 sst_write_err:
1536         *retlen += actual;
1537         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1538         return ret;
1539 }
1540
1541 /*
1542  * Write an address range to the nor chip.  Data must be written in
1543  * FLASH_PAGESIZE chunks.  The address range may be any size provided
1544  * it is within the physical boundaries.
1545  */
1546 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1547         size_t *retlen, const u_char *buf)
1548 {
1549         struct spi_nor *nor = mtd_to_spi_nor(mtd);
1550         size_t page_offset, page_remain, i;
1551         ssize_t ret;
1552         u32 offset, stack_shift=0;
1553         u8 bank = 0;
1554         u32 rem_bank_len = 0;
1555
1556 #define OFFSET_16_MB 0x1000000
1557
1558         dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1559         ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1560         if (ret)
1561                 return ret;
1562         for (i = 0; i < len; ) {
1563                 ssize_t written;
1564
1565                 if (nor->addr_width == 3) {
1566                         bank = (u32)to / (OFFSET_16_MB << nor->shift);
1567                         rem_bank_len = ((OFFSET_16_MB << nor->shift) *
1568                                                         (bank + 1)) - to;
1569                 }
1570
1571                 page_offset = ((to + i)) & (nor->page_size - 1);
1572
1573                 offset = (to + i);
1574
1575                 if (nor->isparallel == 1)
1576                         offset /= 2;
1577
1578                 if (nor->isstacked == 1) {
1579                         stack_shift = 1;
1580                         if (offset >= (mtd->size / 2)) {
1581                                 offset = offset - (mtd->size / 2);
1582                                 nor->spi->master->flags |= SPI_MASTER_U_PAGE;
1583                         } else {
1584                                 nor->spi->master->flags &= ~SPI_MASTER_U_PAGE;
1585                         }
1586                 }
1587
1588                 /* Die cross over issue is not handled */
1589                 if (nor->addr_width == 4)
1590                         rem_bank_len = (mtd->size >> stack_shift) - offset;
1591                 if (nor->addr_width == 3)
1592                         write_ear(nor, (offset >> nor->shift));
1593                 if (len < rem_bank_len) {
1594                         page_remain = min_t(size_t,
1595                                     nor->page_size - page_offset, len - i);
1596
1597                 }
1598                 else {
1599                 /* the size of data remaining on the first page */
1600                         page_remain = rem_bank_len;
1601                 }
1602                 ret = spi_nor_wait_till_ready(nor);
1603                 if (ret)
1604                         goto write_err;
1605
1606                 write_enable(nor);
1607
1608                 ret = nor->write(nor, (offset), page_remain, buf + i);
1609                 if (ret < 0)
1610                         goto write_err;
1611                 written = ret;
1612
1613                 ret = spi_nor_wait_till_ready(nor);
1614                 if (ret)
1615                         goto write_err;
1616                 *retlen += written;
1617                 i += written;
1618                 if (written != page_remain) {
1619                         dev_err(nor->dev,
1620                                 "While writing %zu bytes written %zd bytes\n",
1621                                 page_remain, written);
1622                         ret = -EIO;
1623                         goto write_err;
1624                 }
1625         }
1626
1627 write_err:
1628         spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1629         return ret;
1630 }
1631
1632 static int macronix_quad_enable(struct spi_nor *nor)
1633 {
1634         int ret, val;
1635
1636         val = read_sr(nor);
1637         if (val < 0)
1638                 return val;
1639         write_enable(nor);
1640
1641         write_sr(nor, val | SR_QUAD_EN_MX);
1642
1643         if (spi_nor_wait_till_ready(nor))
1644                 return 1;
1645
1646         ret = read_sr(nor);
1647         if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1648                 dev_err(nor->dev, "Macronix Quad bit not set\n");
1649                 return -EINVAL;
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int spansion_quad_enable(struct spi_nor *nor)
1656 {
1657         int ret;
1658         int quad_en = CR_QUAD_EN_SPAN << 8;
1659
1660         quad_en |= read_sr(nor);
1661         quad_en |= (read_cr(nor) << 8);
1662
1663         write_enable(nor);
1664
1665         ret = write_sr_cr(nor, quad_en);
1666         if (ret < 0) {
1667                 dev_err(nor->dev,
1668                         "error while writing configuration register\n");
1669                 return -EINVAL;
1670         }
1671
1672         /* read back and check it */
1673         ret = read_cr(nor);
1674         if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1675                 dev_err(nor->dev, "Spansion Quad bit not set\n");
1676                 return -EINVAL;
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1683 {
1684         int status;
1685
1686         switch (JEDEC_MFR(info)) {
1687         case SNOR_MFR_MACRONIX:
1688         case SNOR_MFR_ISSI:
1689                 status = macronix_quad_enable(nor);
1690                 if (status) {
1691                         dev_err(nor->dev, "Macronix quad-read not enabled\n");
1692                         return -EINVAL;
1693                 }
1694                 return status;
1695         case SNOR_MFR_MICRON:
1696                 return 0;
1697         default:
1698                 status = spansion_quad_enable(nor);
1699                 if (status) {
1700                         dev_err(nor->dev, "Spansion quad-read not enabled\n");
1701                         return -EINVAL;
1702                 }
1703                 return status;
1704         }
1705 }
1706
1707 static int spi_nor_check(struct spi_nor *nor)
1708 {
1709         if (!nor->dev || !nor->read || !nor->write ||
1710                 !nor->read_reg || !nor->write_reg) {
1711                 pr_err("spi-nor: please fill all the necessary fields!\n");
1712                 return -EINVAL;
1713         }
1714
1715         return 0;
1716 }
1717
1718 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1719 {
1720         struct flash_info *info = NULL;
1721         struct device *dev = nor->dev;
1722         struct mtd_info *mtd = &nor->mtd;
1723         struct device_node *np = spi_nor_get_flash_node(nor);
1724         struct device_node *np_spi ;
1725         int ret;
1726         int i;
1727         u32 is_dual;
1728
1729         ret = spi_nor_check(nor);
1730         if (ret)
1731                 return ret;
1732
1733         if (name)
1734                 info = (struct flash_info *)spi_nor_match_id(name);
1735         /* Try to auto-detect if chip name wasn't specified or not found */
1736         if (!info)
1737                 info = (struct flash_info *)spi_nor_read_id(nor);
1738         if (IS_ERR_OR_NULL(info))
1739                 return -ENOENT;
1740
1741         /*
1742          * If caller has specified name of flash model that can normally be
1743          * detected using JEDEC, let's verify it.
1744          */
1745         if (name && info->id_len) {
1746                 const struct flash_info *jinfo;
1747
1748                 jinfo = spi_nor_read_id(nor);
1749                 if (IS_ERR(jinfo)) {
1750                         return PTR_ERR(jinfo);
1751                 } else if (jinfo != info) {
1752                         /*
1753                          * JEDEC knows better, so overwrite platform ID. We
1754                          * can't trust partitions any longer, but we'll let
1755                          * mtd apply them anyway, since some partitions may be
1756                          * marked read-only, and we don't want to lose that
1757                          * information, even if it's not 100% accurate.
1758                          */
1759                         dev_warn(dev, "found %s, expected %s\n",
1760                                  jinfo->name, info->name);
1761                         info = (struct flash_info *)jinfo;
1762                 }
1763         }
1764
1765         mutex_init(&nor->lock);
1766
1767         /*
1768          * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1769          * with the software protection bits set
1770          */
1771
1772         if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1773             JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1774             JEDEC_MFR(info) == SNOR_MFR_SST ||
1775             info->flags & SPI_NOR_HAS_LOCK) {
1776                 write_enable(nor);
1777                 write_sr(nor, 0);
1778                 if (info->flags & SST_GLOBAL_PROT_UNLK) {
1779                         write_enable(nor);
1780                         /* Unlock global write protection bits */
1781                         nor->write_reg(nor, GLOBAL_BLKPROT_UNLK, NULL, 0);
1782                 }
1783                 spi_nor_wait_till_ready(nor);
1784         }
1785
1786         if (!mtd->name)
1787                 mtd->name = dev_name(dev);
1788         mtd->priv = nor;
1789         mtd->type = MTD_NORFLASH;
1790         mtd->writesize = 1;
1791         mtd->flags = MTD_CAP_NORFLASH;
1792         mtd->size = info->sector_size * info->n_sectors;
1793         mtd->_erase = spi_nor_erase;
1794         mtd->_read = spi_nor_read;
1795 #ifdef CONFIG_OF
1796         np_spi = of_get_next_parent(np);
1797         if ((of_property_match_string(np_spi, "compatible",
1798                     "xlnx,zynq-qspi-1.0") >= 0) ||
1799                         (of_property_match_string(np_spi, "compatible",
1800                                         "xlnx,zynqmp-qspi-1.0") >= 0)) {
1801                         if (of_property_read_u32(np_spi, "is-dual",
1802                                                  &is_dual) < 0) {
1803                                 /* Default to single if prop not defined */
1804                                 nor->shift = 0;
1805                                 nor->isstacked = 0;
1806                                 nor->isparallel = 0;
1807                         } else {
1808                                 if (is_dual == 1) {
1809                                         /* dual parallel */
1810                                         nor->shift = 1;
1811                                         info->sector_size <<= nor->shift;
1812                                         info->page_size <<= nor->shift;
1813                                         mtd->size <<= nor->shift;
1814                                         nor->isparallel = 1;
1815                                         nor->isstacked = 0;
1816                                         nor->spi->master->flags |=
1817                                                         (SPI_MASTER_DATA_STRIPE
1818                                                         | SPI_MASTER_BOTH_CS);
1819                                 } else {
1820 #ifdef CONFIG_SPI_ZYNQ_QSPI_DUAL_STACKED
1821                                         /* dual stacked */
1822                                         nor->shift = 0;
1823                                         mtd->size <<= 1;
1824                                         info->n_sectors <<= 1;
1825                                         nor->isstacked = 1;
1826                                         nor->isparallel = 0;
1827 #else
1828                                         u32 is_stacked;
1829                                         if (of_property_read_u32(np_spi,
1830                                                         "is-stacked",
1831                                                         &is_stacked) < 0) {
1832                                                 is_stacked = 0;
1833                                         }
1834                                         if (is_stacked) {
1835                                                 /* dual stacked */
1836                                                 nor->shift = 0;
1837                                                 mtd->size <<= 1;
1838                                                 info->n_sectors <<= 1;
1839                                                 nor->isstacked = 1;
1840                                                 nor->isparallel = 0;
1841                                         } else {
1842                                                 /* single */
1843                                                 nor->shift = 0;
1844                                                 nor->isstacked = 0;
1845                                                 nor->isparallel = 0;
1846                                         }
1847 #endif
1848                                 }
1849                         }
1850         }
1851 #if 0
1852         pr_info("parallel %d stacked %d shift %d mtsize %d\n",
1853                 nor->isparallel, nor->isstacked, nor->shift, mtd->size);
1854 #endif
1855 #else
1856         /* Default to single */
1857         nor->shift = 0;
1858         nor->isstacked = 0;
1859         nor->isparallel = 0;
1860 #endif
1861
1862         /* NOR protection support for STmicro/Micron chips and similar */
1863         if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1864                         info->flags & SPI_NOR_HAS_LOCK) {
1865                 nor->flash_lock = stm_lock;
1866                 nor->flash_unlock = stm_unlock;
1867                 nor->flash_is_locked = stm_is_locked;
1868         }
1869
1870         if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1871                 mtd->_lock = spi_nor_lock;
1872                 mtd->_unlock = spi_nor_unlock;
1873                 mtd->_is_locked = spi_nor_is_locked;
1874         }
1875
1876         /* sst nor chips use AAI word program */
1877         if (info->flags & SST_WRITE)
1878                 mtd->_write = sst_write;
1879         else
1880                 mtd->_write = spi_nor_write;
1881
1882         if (info->flags & USE_FSR)
1883                 nor->flags |= SNOR_F_USE_FSR;
1884         if (info->flags & SPI_NOR_HAS_TB)
1885                 nor->flags |= SNOR_F_HAS_SR_TB;
1886
1887 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1888         /* prefer "small sector" erase if possible */
1889         if (info->flags & SECT_4K) {
1890                 nor->erase_opcode = SPINOR_OP_BE_4K;
1891                 mtd->erasesize = 4096 << nor->shift;
1892         } else if (info->flags & SECT_4K_PMC) {
1893                 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1894                 mtd->erasesize = 4096 << nor->shift;
1895         } else
1896 #endif
1897         {
1898                 nor->erase_opcode = SPINOR_OP_SE;
1899                 mtd->erasesize = info->sector_size;
1900         }
1901
1902         if (info->flags & SPI_NOR_NO_ERASE)
1903                 mtd->flags |= MTD_NO_ERASE;
1904
1905         nor->jedec_id = info->id[0];
1906         mtd->dev.parent = dev;
1907         nor->page_size = info->page_size;
1908         mtd->writebufsize = nor->page_size;
1909
1910         if (np) {
1911                 /* If we were instantiated by DT, use it */
1912                 if (of_property_read_bool(np, "m25p,fast-read"))
1913                         nor->flash_read = SPI_NOR_FAST;
1914                 else
1915                         nor->flash_read = SPI_NOR_NORMAL;
1916         } else {
1917                 /* If we weren't instantiated by DT, default to fast-read */
1918                 nor->flash_read = SPI_NOR_FAST;
1919         }
1920
1921         /* Some devices cannot do fast-read, no matter what DT tells us */
1922         if (info->flags & SPI_NOR_NO_FR)
1923                 nor->flash_read = SPI_NOR_NORMAL;
1924
1925         /* Quad/Dual-read mode takes precedence over fast/normal */
1926         if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1927                 ret = set_quad_mode(nor, info);
1928                 if (ret) {
1929                         dev_err(dev, "quad mode not supported\n");
1930                         return ret;
1931                 }
1932                 nor->flash_read = SPI_NOR_QUAD;
1933         } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1934                 nor->flash_read = SPI_NOR_DUAL;
1935         }
1936
1937         /* Default commands */
1938         switch (nor->flash_read) {
1939         case SPI_NOR_QUAD:
1940                 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1941                 break;
1942         case SPI_NOR_DUAL:
1943                 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1944                 break;
1945         case SPI_NOR_FAST:
1946                 nor->read_opcode = SPINOR_OP_READ_FAST;
1947                 break;
1948         case SPI_NOR_NORMAL:
1949                 nor->read_opcode = SPINOR_OP_READ;
1950                 break;
1951         default:
1952                 dev_err(dev, "No Read opcode defined\n");
1953                 return -EINVAL;
1954         }
1955
1956         nor->program_opcode = SPINOR_OP_PP;
1957
1958         if (info->addr_width)
1959                 nor->addr_width = info->addr_width;
1960         else if (mtd->size > 0x1000000) {
1961 #ifdef CONFIG_OF
1962                 np_spi = of_get_next_parent(np);
1963                 if (of_property_match_string(np_spi, "compatible",
1964                                              "xlnx,zynq-qspi-1.0") >= 0) {
1965                         int status;
1966
1967                         nor->addr_width = 3;
1968                         set_4byte(nor, info, 0);
1969                         status = read_ear(nor, info);
1970                         if (status < 0)
1971                                 dev_warn(dev, "failed to read ear reg\n");
1972                         else
1973                                 nor->curbank = status & EAR_SEGMENT_MASK;
1974                 } else {
1975 #endif
1976                 /* enable 4-byte addressing if the device exceeds 16MiB */
1977                 nor->addr_width = 4;
1978                 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1979                         /* Dedicated 4-byte command set */
1980                         switch (nor->flash_read) {
1981                         case SPI_NOR_QUAD:
1982                                 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1983                                 break;
1984                         case SPI_NOR_DUAL:
1985                                 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1986                                 break;
1987                         case SPI_NOR_FAST:
1988                                 nor->read_opcode = SPINOR_OP_READ4_FAST;
1989                                 break;
1990                         case SPI_NOR_NORMAL:
1991                                 nor->read_opcode = SPINOR_OP_READ4;
1992                                 break;
1993                         }
1994                         nor->program_opcode = SPINOR_OP_PP_4B;
1995                         /* No small sector erase for 4-byte command set */
1996                         nor->erase_opcode = SPINOR_OP_SE_4B;
1997                         mtd->erasesize = info->sector_size;
1998                 } else {
1999                         np_spi = of_get_next_parent(np);
2000                         if (of_property_match_string(np_spi, "compatible",
2001                                                 "xlnx,xps-spi-2.00.a") >= 0) {
2002                                 nor->addr_width = 3;
2003                                 set_4byte(nor, info, 0);
2004                         } else {
2005                                 set_4byte(nor, info, 1);
2006                                 if (nor->isstacked) {
2007                                         nor->spi->master->flags |=
2008                                                         SPI_MASTER_U_PAGE;
2009                                         set_4byte(nor, info, 1);
2010                                         nor->spi->master->flags &=
2011                                                         ~SPI_MASTER_U_PAGE;
2012                                 }
2013                         }
2014                 }
2015 #ifdef CONFIG_OF
2016                 }
2017 #endif
2018         } else {
2019                 nor->addr_width = 3;
2020         }
2021
2022         if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
2023                 dev_err(dev, "address width is too large: %u\n",
2024                         nor->addr_width);
2025                 return -EINVAL;
2026         }
2027
2028         nor->read_dummy = spi_nor_read_dummy_cycles(nor);
2029
2030         dev_info(dev, "%s (%lld Kbytes)\n", info->name,
2031                         (long long)mtd->size >> 10);
2032
2033         dev_dbg(dev,
2034                 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
2035                 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
2036                 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
2037                 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
2038
2039         if (mtd->numeraseregions)
2040                 for (i = 0; i < mtd->numeraseregions; i++)
2041                         dev_dbg(dev,
2042                                 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
2043                                 ".erasesize = 0x%.8x (%uKiB), "
2044                                 ".numblocks = %d }\n",
2045                                 i, (long long)mtd->eraseregions[i].offset,
2046                                 mtd->eraseregions[i].erasesize,
2047                                 mtd->eraseregions[i].erasesize / 1024,
2048                                 mtd->eraseregions[i].numblocks);
2049         return 0;
2050 }
2051 EXPORT_SYMBOL_GPL(spi_nor_scan);
2052
2053 static const struct flash_info *spi_nor_match_id(const char *name)
2054 {
2055         const struct flash_info *id = spi_nor_ids;
2056
2057         while (id->name) {
2058                 if (!strcmp(name, id->name))
2059                         return id;
2060                 id++;
2061         }
2062         return NULL;
2063 }
2064
2065 MODULE_LICENSE("GPL");
2066 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
2067 MODULE_AUTHOR("Mike Lavender");
2068 MODULE_DESCRIPTION("framework for SPI NOR");