1 The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP
2 block is used for reading video frame data from memory (FB Read) to the device
3 and the other IP block is used for writing video frame data from the device
4 to memory (FB Write). Both the FB Read/Write IP blocks are aware of the
5 format of the data being written to or read from memory including RGB and
6 YUV in packed, planar, and semi-planar formats. Because the FB Read/Write
7 is format aware, only one buffer pointer is needed by the IP blocks even
8 when planar or semi-planar format are used.
10 FB Read Required propertie(s):
11 - compatible : Should be "xlnx,axi-frmbuf-rd-v2"
13 Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it
14 represented is no longer supported.
16 FB Write Required propertie(s):
17 - compatible : Should be "xlnx,axi-frmbuf-wr-v2"
19 Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it
20 represented is no longer supported.
22 Required Properties Common to both FB Read and FB Write:
23 - #dma-cells : should be 1
24 - interrupt-parent : Interrupt controller the interrupt is routed through
25 - interrupts : Should contain DMA channel interrupt
26 - reset-gpios : Should contain GPIO reset phandle
27 - reg : Memory map for module access
28 - xlnx,dma-addr-width : Size of dma address pointer in IP (either 32 or 64)
34 v_frmbuf_rd_0: v_frmbuf_rd@80000000 {
36 compatible = "xlnx,axi-frmbuf-rd-v2";
37 interrupt-parent = <&gic>;
38 interrupts = <0 92 4>;
39 reset-gpios = <&gpio 80 1>;
40 reg = <0x0 0x80000000 0x0 0x10000>;
41 xlnx,dma-addr-width = <32>;
46 v_frmbuf_wr_0: v_frmbuf_wr@80000000 {
48 compatible = "xlnx,axi-frmbuf-wr-v2";
49 interrupt-parent = <&gic>;
50 interrupts = <0 92 4>;
51 reset-gpios = <&gpio 80 1>;
52 reg = <0x0 0x80000000 0x0 0x10000>;
53 xlnx,dma-addr-width = <64>;