arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

   1 /*
   2  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "zynqmp.dtsi"
  17 #include "zynqmp-clk-ccf.dtsi"
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  21
  22 / {
  23         model = "ZynqMP zc1751-xm015-dc1 RevA";
  24         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  25
  26         aliases {
  27                 ethernet0 = &gem3;
  28                 gpio0 = &gpio;
  29                 i2c0 = &i2c1;
  30                 mmc0 = &sdhci0;
  31                 mmc1 = &sdhci1;
  32                 rtc0 = &rtc;
  33                 serial0 = &uart0;
  34                 spi0 = &qspi;
  35                 usb0 = &usb0;
  36         };
  37
  38         chosen {
  39                 bootargs = "earlycon";
  40                 stdout-path = "serial0:115200n8";
  41         };
  42
  43         memory@0 {
  44                 device_type = "memory";
  45                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  46         };
  47 };
  48
  49 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  50 &fpd_dma_chan1 {
  51         status = "okay";
  52         xlnx,include-sg; /* for testing purpose */
  53         xlnx,overfetch; /* for testing purpose */
  54         xlnx,ratectrl = <0>; /* for testing purpose */
  55         xlnx,src-issue = <31>;
  56 };
  57
  58 &fpd_dma_chan2 {
  59         status = "okay";
  60         xlnx,ratectrl = <100>; /* for testing purpose */
  61         xlnx,src-issue = <4>; /* for testing purpose */
  62 };
  63
  64 &fpd_dma_chan3 {
  65         status = "okay";
  66 };
  67
  68 &fpd_dma_chan4 {
  69         status = "okay";
  70         xlnx,include-sg; /* for testing purpose */
  71 };
  72
  73 &fpd_dma_chan5 {
  74         status = "okay";
  75 };
  76
  77 &fpd_dma_chan6 {
  78         status = "okay";
  79         xlnx,include-sg; /* for testing purpose */
  80 };
  81
  82 &fpd_dma_chan7 {
  83         status = "okay";
  84 };
  85
  86 &fpd_dma_chan8 {
  87         status = "okay";
  88         xlnx,include-sg; /* for testing purpose */
  89 };
  90
  91 &gem3 {
  92         status = "okay";
  93         phy-handle = <&phy0>;
  94         phy-mode = "rgmii-id";
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_gem3_default>;
  97         phy0: phy@0 {
  98                 reg = <0>;
  99         };
 100 };
 101
 102 &gpio {
 103         status = "okay";
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_gpio_default>;
 106 };
 107
 108 &gpu {
 109         status = "okay";
 110 };
 111
 112 &i2c1 {
 113         status = "okay";
 114         clock-frequency = <400000>;
 115         pinctrl-names = "default", "gpio";
 116         pinctrl-0 = <&pinctrl_i2c1_default>;
 117         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 118         scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
 119         sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
 120
 121         eeprom@55 {
 122                 compatible = "at,24c64"; /* 24AA64 */
 123                 reg = <0x55>;
 124         };
 125 };
 126
 127 &qspi {
 128         status = "okay";
 129         flash@0 {
 130                 compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 reg = <0x0>;
 134                 spi-tx-bus-width = <1>;
 135                 spi-rx-bus-width = <4>;
 136                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 137                 partition@qspi-fsbl-uboot { /* for testing purpose */
 138                         label = "qspi-fsbl-uboot";
 139                         reg = <0x0 0x100000>;
 140                 };
 141                 partition@qspi-linux { /* for testing purpose */
 142                         label = "qspi-linux";
 143                         reg = <0x100000 0x500000>;
 144                 };
 145                 partition@qspi-device-tree { /* for testing purpose */
 146                         label = "qspi-device-tree";
 147                         reg = <0x600000 0x20000>;
 148                 };
 149                 partition@qspi-rootfs { /* for testing purpose */
 150                         label = "qspi-rootfs";
 151                         reg = <0x620000 0x5E0000>;
 152                 };
 153         };
 154 };
 155
 156 &rtc {
 157         status = "okay";
 158 };
 159
 160 &sata {
 161         status = "okay";
 162         /* SATA phy OOB timing settings */
 163         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 164         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 165         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 166         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 167         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 168         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 169         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 170         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 171         phy-names = "sata-phy";
 172         phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>;
 173 };
 174
 175 /* eMMC */
 176 &sdhci0 {
 177         status = "okay";
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_sdhci0_default>;
 180         bus-width = <8>;
 181         xlnx,mio_bank = <0>;
 182 };
 183
 184 /* SD1 with level shifter */
 185 &sdhci1 {
 186         status = "okay";
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_sdhci1_default>;
 189         xlnx,mio_bank = <1>;
 190 };
 191
 192 &serdes {
 193         status = "okay";
 194 };
 195
 196 &uart0 {
 197         status = "okay";
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_uart0_default>;
 200 };
 201
 202 /* ULPI SMSC USB3320 */
 203 &usb0 {
 204         status = "okay";
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_usb0_default>;
 207 };
 208
 209 &dwc3_0 {
 210         status = "okay";
 211         dr_mode = "host";
 212         snps,usb3_lpm_capable;
 213         phy-names = "usb3-phy";
 214         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 215 };
 216
 217 &xilinx_drm {
 218         status = "okay";
 219 };
 220
 221 &xlnx_dp {
 222         status = "okay";
 223         phy-names = "dp-phy0", "dp-phy1";
 224         phys = <&lane1 PHY_TYPE_DP 0 0 27000000>,
 225                <&lane0 PHY_TYPE_DP 1 1 27000000>;
 226 };
 227
 228 &xlnx_dp_sub {
 229         status = "okay";
 230         xlnx,vid-clk-pl;
 231 };
 232
 233 &xlnx_dp_snd_pcm0 {
 234         status = "okay";
 235 };
 236
 237 &xlnx_dp_snd_pcm1 {
 238         status = "okay";
 239 };
 240
 241 &xlnx_dp_snd_card {
 242         status = "okay";
 243 };
 244
 245 &xlnx_dp_snd_codec0 {
 246         status = "okay";
 247 };
 248
 249 &xlnx_dpdma {
 250         status = "okay";
 251 };
 252
 253 &pinctrl0 {
 254         status = "okay";
 255         pinctrl_i2c1_default: i2c1-default {
 256                 mux {
 257                         groups = "i2c1_9_grp";
 258                         function = "i2c1";
 259                 };
 260
 261                 conf {
 262                         groups = "i2c1_9_grp";
 263                         bias-pull-up;
 264                         slew-rate = <SLEW_RATE_SLOW>;
 265                         io-standard = <IO_STANDARD_LVCMOS18>;
 266                 };
 267         };
 268
 269         pinctrl_i2c1_gpio: i2c1-gpio {
 270                 mux {
 271                         groups = "gpio0_36_grp", "gpio0_37_grp";
 272                         function = "gpio0";
 273                 };
 274
 275                 conf {
 276                         groups = "gpio0_36_grp", "gpio0_37_grp";
 277                         slew-rate = <SLEW_RATE_SLOW>;
 278                         io-standard = <IO_STANDARD_LVCMOS18>;
 279                 };
 280         };
 281
 282         pinctrl_uart0_default: uart0-default {
 283                 mux {
 284                         groups = "uart0_8_grp";
 285                         function = "uart0";
 286                 };
 287
 288                 conf {
 289                         groups = "uart0_8_grp";
 290                         slew-rate = <SLEW_RATE_SLOW>;
 291                         io-standard = <IO_STANDARD_LVCMOS18>;
 292                 };
 293
 294                 conf-rx {
 295                         pins = "MIO34";
 296                         bias-high-impedance;
 297                 };
 298
 299                 conf-tx {
 300                         pins = "MIO35";
 301                         bias-disable;
 302                 };
 303         };
 304
 305         pinctrl_usb0_default: usb0-default {
 306                 mux {
 307                         groups = "usb0_0_grp";
 308                         function = "usb0";
 309                 };
 310
 311                 conf {
 312                         groups = "usb0_0_grp";
 313                         slew-rate = <SLEW_RATE_SLOW>;
 314                         io-standard = <IO_STANDARD_LVCMOS18>;
 315                 };
 316
 317                 conf-rx {
 318                         pins = "MIO52", "MIO53", "MIO55";
 319                         bias-high-impedance;
 320                 };
 321
 322                 conf-tx {
 323                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 324                                "MIO60", "MIO61", "MIO62", "MIO63";
 325                         bias-disable;
 326                 };
 327         };
 328
 329         pinctrl_gem3_default: gem3-default {
 330                 mux {
 331                         function = "ethernet3";
 332                         groups = "ethernet3_0_grp";
 333                 };
 334
 335                 conf {
 336                         groups = "ethernet3_0_grp";
 337                         slew-rate = <SLEW_RATE_SLOW>;
 338                         io-standard = <IO_STANDARD_LVCMOS18>;
 339                 };
 340
 341                 conf-rx {
 342                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 343                                                                         "MIO75";
 344                         bias-high-impedance;
 345                         low-power-disable;
 346                 };
 347
 348                 conf-tx {
 349                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 350                                                                         "MIO69";
 351                         bias-disable;
 352                         low-power-enable;
 353                 };
 354
 355                 mux-mdio {
 356                         function = "mdio3";
 357                         groups = "mdio3_0_grp";
 358                 };
 359
 360                 conf-mdio {
 361                         groups = "mdio3_0_grp";
 362                         slew-rate = <SLEW_RATE_SLOW>;
 363                         io-standard = <IO_STANDARD_LVCMOS18>;
 364                         bias-disable;
 365                 };
 366         };
 367
 368         pinctrl_sdhci0_default: sdhci0-default {
 369                 mux {
 370                         groups = "sdio0_0_grp";
 371                         function = "sdio0";
 372                 };
 373
 374                 conf {
 375                         groups = "sdio0_0_grp";
 376                         slew-rate = <SLEW_RATE_SLOW>;
 377                         io-standard = <IO_STANDARD_LVCMOS18>;
 378                         bias-disable;
 379                 };
 380
 381                 mux-cd {
 382                         groups = "sdio0_0_cd_grp";
 383                         function = "sdio0_cd";
 384                 };
 385
 386                 conf-cd {
 387                         groups = "sdio0_0_cd_grp";
 388                         bias-high-impedance;
 389                         bias-pull-up;
 390                         slew-rate = <SLEW_RATE_SLOW>;
 391                         io-standard = <IO_STANDARD_LVCMOS18>;
 392                 };
 393
 394                 mux-wp {
 395                         groups = "sdio0_0_wp_grp";
 396                         function = "sdio0_wp";
 397                 };
 398
 399                 conf-wp {
 400                         groups = "sdio0_0_wp_grp";
 401                         bias-high-impedance;
 402                         bias-pull-up;
 403                         slew-rate = <SLEW_RATE_SLOW>;
 404                         io-standard = <IO_STANDARD_LVCMOS18>;
 405                 };
 406         };
 407
 408         pinctrl_sdhci1_default: sdhci1-default {
 409                 mux {
 410                         groups = "sdio1_0_grp";
 411                         function = "sdio1";
 412                 };
 413
 414                 conf {
 415                         groups = "sdio1_0_grp";
 416                         slew-rate = <SLEW_RATE_SLOW>;
 417                         io-standard = <IO_STANDARD_LVCMOS18>;
 418                         bias-disable;
 419                 };
 420
 421                 mux-cd {
 422                         groups = "sdio1_0_cd_grp";
 423                         function = "sdio1_cd";
 424                 };
 425
 426                 conf-cd {
 427                         groups = "sdio1_0_cd_grp";
 428                         bias-high-impedance;
 429                         bias-pull-up;
 430                         slew-rate = <SLEW_RATE_SLOW>;
 431                         io-standard = <IO_STANDARD_LVCMOS18>;
 432                 };
 433
 434                 mux-wp {
 435                         groups = "sdio1_0_wp_grp";
 436                         function = "sdio1_wp";
 437                 };
 438
 439                 conf-wp {
 440                         groups = "sdio1_0_wp_grp";
 441                         bias-high-impedance;
 442                         bias-pull-up;
 443                         slew-rate = <SLEW_RATE_SLOW>;
 444                         io-standard = <IO_STANDARD_LVCMOS18>;
 445                 };
 446         };
 447
 448         pinctrl_gpio_default: gpio-default {
 449                 mux {
 450                         function = "gpio0";
 451                         groups = "gpio0_38_grp";
 452                 };
 453
 454                 conf {
 455                         groups = "gpio0_38_grp";
 456                         bias-disable;
 457                         slew-rate = <SLEW_RATE_SLOW>;
 458                         io-standard = <IO_STANDARD_LVCMOS18>;
 459                 };
 460         };
 461 };