From 7b1ee684f74f1ef13aeb4249e0fc1c12ad1c98da Mon Sep 17 00:00:00 2001 From: Stanislav Marek Date: Wed, 2 Nov 2005 17:09:00 +0000 Subject: [PATCH] EDK2638 shadow registers and deb_led_out correction. darcs-hash:20051102170934-5f899-7ebbc9474f20b655c8c39594706c7e1dc3fbe35a.gz --- board/h8300/edk2638/libs/bspbase/bsp0hwinit.c | 57 +++++++------------ 1 file changed, 20 insertions(+), 37 deletions(-) diff --git a/board/h8300/edk2638/libs/bspbase/bsp0hwinit.c b/board/h8300/edk2638/libs/bspbase/bsp0hwinit.c index 7d60c1c..8f372e0 100644 --- a/board/h8300/edk2638/libs/bspbase/bsp0hwinit.c +++ b/board/h8300/edk2638/libs/bspbase/bsp0hwinit.c @@ -13,38 +13,35 @@ static void deb_led_out(char val) { - #if 0 - *DIO_P1DR &= ~0xf; - *DIO_P1DR |= ~val & 0xf; - #elif 0 - /*2,6,7*/ - *DIO_P3DR &= ~0xc4; - *DIO_P3DR |= ~(val<<5) & 0xc0; - if(!(val&1)) - *DIO_P3DR |= 4; - #else - SHADOW_REG_SET(DIO_P1DDR,(P1DDR_P15DDRm|P1DDR_P14DDRm)); /* set P1.5 and P1.4 as output */ - if (val&1) - *DIO_P1DR |=P1DR_P14DRm; + DEB_LED_ON(0); else - *DIO_P1DR &=~P1DR_P14DRm; - - if (val&2) - *DIO_P1DR |=P1DR_P15DRm; + DEB_LED_OFF(0); + if (val&2) + DEB_LED_ON(1); else - *DIO_P1DR &=~P1DR_P15DRm; - + DEB_LED_OFF(1); + if (val&4) + DEB_LED_ON(2); + else + DEB_LED_OFF(2); + if (val&8) + DEB_LED_ON(3); + else + DEB_LED_OFF(3); - #endif } void _setup_board() { - //int i, j;// POE-100 + /* set shadow registers */ + DIO_P1DDR_shadow=0; + DIO_P3DDR_shadow=0; + DIO_PFDDR_shadow=0; + DIO_PJDDR_shadow=0; - //int i, j;// POE-100 - __u8 *p; + SHADOW_REG_SET(DIO_P1DDR,(P1DDR_P15DDRm|P1DDR_P14DDRm)); /* set P1.5 and P1.4 as output */ + deb_led_out(1); /* _setup_board function entered */ #if 1 /* registers setup */ /* Internal RAM enabled, advanced interrupt mode */ @@ -57,15 +54,6 @@ void _setup_board() /* Enables access to flash control registers */ *IIC_SCRX |= SCRX_FLSHEm; - /* set shadow registers */ - DIO_P1DDR_shadow=0; - DIO_P3DDR_shadow=0; - - /* show something on debug leds */ - /* deb_led_out(0); - FlWait(2*1000000); */ - - //SHADOW_REG_SET(DIO_P3DDR,0xc4); //SHADOW_REG_SET(DIO_P1DDR,0x03); /*A20 and A21 are outputs*/ *DIO_P3DR=0x09; /* Inactive value of TxD0 and TxD1 has to be log 1 */ @@ -80,8 +68,6 @@ void _setup_board() *SYS_LPWRCR=LPWRCR_STCxm&(LPWRCR_STC0m* clkrat2stc[(CPU_SYS_HZ+CPU_REF_HZ/2)/CPU_REF_HZ]); } - /* deb_led_out(1); - FlWait(2*1000000); */ /* No clock disable, immediate change, busmaster high-speed */ *SYS_SCKCR=(0*SCKCR_PSTOPm)|(1*SCKCR_STCSm)|(0&SCKCR_SCKxm); @@ -128,9 +114,6 @@ void _setup_board() //*BUS_WCRL&=~(WCRL_W31m|WCRL_W30m); /* 0 additional wait states */ *BUS_WCRL&=~(WCRL_W01m|WCRL_W00m); /* 0 additional wait states EDK 2638*/ - /* deb_led_out(2); - FlWait(2*1000000); */ - #if 0 /* setup chipselect 4 - IDE */ *BUS_ABWCR&=~ABWCR_ABW4m; /* 16 bit width */ -- 2.39.2