From: Pavel Pisa Date: Sun, 11 Jan 2009 14:19:33 +0000 (+0100) Subject: h8s2638 MCU register addresses moved to 0xffff0000 range X-Git-Url: https://rtime.felk.cvut.cz/gitweb/sysless.git/commitdiff_plain/488a7e7bffbcf1bb63a93fb9711d4b89648ed84a h8s2638 MCU register addresses moved to 0xffff0000 range The H8S CPU supports only 24-bit addresses so upper 8-bits of 32 words are ignored, but GCC generates 16-bit addresses only for lower 32kB and last 32kB starting at 0xffff8000. This allows contributes to shrinking of code size. Signed-off-by: Pavel Pisa --- diff --git a/arch/h8300/mach-2638/defines/h8s2638h.h b/arch/h8300/mach-2638/defines/h8s2638h.h index a157d56..af4b302 100644 --- a/arch/h8300/mach-2638/defines/h8s2638h.h +++ b/arch/h8300/mach-2638/defines/h8s2638h.h @@ -45,21 +45,21 @@ /* Module HCAN1 and HCAN2 */ /* Configuration registers for HCAN0 and HCAN1 */ -#define HCAN0_MCR __PORT8 0xFFF800 /* HCAN0 Master Control Register */ -#define HCAN1_MCR __PORT8 0xFFFA00 /* HCAN1 Master Control Register */ +#define HCAN0_MCR __PORT8 0xFFFFF800 /* HCAN0 Master Control Register */ +#define HCAN1_MCR __PORT8 0xFFFFFA00 /* HCAN1 Master Control Register */ #define MCR_MCR0m 0x01 #define MCR_MCR1m 0x02 #define MCR_MCR2m 0x04 #define MCR_MCR5m 0x20 #define MCR_MCR7m 0x80 -#define HCAN0_GSR __PORT8 0xFFF801 /* HCAN0 General Status Register */ -#define HCAN1_GSR __PORT8 0xFFFA01 /* HCAN1 General Status Register */ +#define HCAN0_GSR __PORT8 0xFFFFF801 /* HCAN0 General Status Register */ +#define HCAN1_GSR __PORT8 0xFFFFFA01 /* HCAN1 General Status Register */ #define GSR_GSR0m 0x01 /* Bus Off Flag */ #define GSR_GSR1m 0x02 /* Transmit/Receive Warning Flag */ #define GSR_GSR2m 0x04 /* Message Transmission Status Flag */ #define GSR_GSR3m 0x08 /* Reset Status Bit */ -#define HCAN0_BCR __PORT16 0xFFF802 /* HCAN0 Bit Configuration Register */ -#define HCAN1_BCR __PORT16 0xFFFA02 /* HCAN1 Bit Configuration Register */ +#define HCAN0_BCR __PORT16 0xFFFFF802 /* HCAN0 Bit Configuration Register */ +#define HCAN1_BCR __PORT16 0xFFFFFA02 /* HCAN1 Bit Configuration Register */ #define BCR_BRPm 0x3f00 /* Baud Rate Prescaler (BRP) bits 8-13 */ #define BCR_BCR0m 0x0100 /* Baud Rate Prescaler (BRP) - bit 8 */ #define BCR_BCR1m 0x0200 /* Baud Rate Prescaler (BRP) - bit 9 */ @@ -80,8 +80,8 @@ #define BCR_BCR12m 0x0010 /* Time Segment 2 (TSEG2) - bit 4 */ #define BCR_BCR13m 0x0020 /* Time Segment 2 (TSEG2) - bit 5 */ #define BCR_BCR14m 0x0040 /* Time Segment 2 (TSEG2) - bit 6 */ -#define HCAN0_BCRL __PORT8 0xFFF802 /* HCAN0 Bit Configuration Register L */ -#define HCAN1_BCRL __PORT8 0xFFFA02 /* HCAN1 Bit Configuration Register L */ +#define HCAN0_BCRL __PORT8 0xFFFFF802 /* HCAN0 Bit Configuration Register L */ +#define HCAN1_BCRL __PORT8 0xFFFFFA02 /* HCAN1 Bit Configuration Register L */ #define BCRL_BCR0m 0x01 /* Time Segment 1 (TSEG1) bits 0-3 (BCR0-3) */ #define BCRL_BCR1m 0x02 #define BCRL_BCR2m 0x04 @@ -90,8 +90,8 @@ #define BCRL_BCR5m 0x20 #define BCRL_BCR6m 0x40 #define BCRL_BCR15m 0x80 /* Bit Sample Point (BSP) */ -#define HCAN0_BCRH __PORT8 0xFFF803 /* HCAN0 Bit Configuration Register H */ -#define HCAN1_BCRH __PORT8 0xFFFA03 /* HCAN1 Bit Configuration Register H */ +#define HCAN0_BCRH __PORT8 0xFFFFF803 /* HCAN0 Bit Configuration Register H */ +#define HCAN1_BCRH __PORT8 0xFFFFFA03 /* HCAN1 Bit Configuration Register H */ #define BCRH_BCR0m 0x01 /* Baud Rate Prescaler (BRP) bits 8-13 */ #define BCRH_BCR1m 0x02 #define BCRH_BCR2m 0x04 @@ -100,8 +100,8 @@ #define BCRH_BCR5m 0x20 #define BCRH_BCR6m 0x40 /* Resynchronization Jump Width bits 14-15 */ #define BCRH_BCR7m 0x80 -#define HCAN0_MBCR __PORT16 0xFFF804 /* HCAN0 Mailbox Configuration Register */ -#define HCAN1_MBCR __PORT16 0xFFFA04 /* HCAN1 Mailbox Configuration Register */ +#define HCAN0_MBCR __PORT16 0xFFFFF804 /* HCAN0 Mailbox Configuration Register */ +#define HCAN1_MBCR __PORT16 0xFFFFFA04 /* HCAN1 Mailbox Configuration Register */ #define MBCR_MBCR8m 0x0001 /* 0 = Corresponding mailbox(8) is set for transmission */ #define MBCR_MBCR9m 0x0002 #define MBCR_MBCR10m 0x0004 @@ -117,8 +117,8 @@ #define MBCR_MBCR5m 0x0200 #define MBCR_MBCR6m 0x0400 #define MBCR_MBCR7m 0x0800 -#define HCAN0_TXPR __PORT16 0xFFF806 /* HCAN0 Transmit Wait Register */ -#define HCAN1_TXPR __PORT16 0xFFFA06 /* HCAN1 Transmit wait register */ +#define HCAN0_TXPR __PORT16 0xFFFFF806 /* HCAN0 Transmit Wait Register */ +#define HCAN1_TXPR __PORT16 0xFFFFFA06 /* HCAN1 Transmit wait register */ #define TXPR_TXPR8m 0x0001 #define TXPR_TXPR9m 0x0002 #define TXPR_TXPR10m 0x0004 @@ -134,8 +134,8 @@ #define TXPR_TXPR5m 0x2000 #define TXPR_TXPR6m 0x4000 #define TXPR_TXPR7m 0x8000 -#define HCAN0_TXCR __PORT16 0xFFF808 /* HCAN0 Transmit wait cancel register */ -#define HCAN1_TXCR __PORT16 0xFFFA08 /* HCAN1 Transmit wait cancel register */ +#define HCAN0_TXCR __PORT16 0xFFFFF808 /* HCAN0 Transmit wait cancel register */ +#define HCAN1_TXCR __PORT16 0xFFFFFA08 /* HCAN1 Transmit wait cancel register */ #define TXCR_TXCR8m 0x0001 #define TXCR_TXCR9m 0x0002 #define TXCR_TXCR10m 0x0004 @@ -151,8 +151,8 @@ #define TXCR_TXCR5m 0x2000 #define TXCR_TXCR6m 0x4000 #define TXCR_TXCR7m 0x8000 -#define HCAN0_TXACK __PORT16 0xFFF80A /* HCAN0 Transmit Acknowledge Register */ -#define HCAN1_TXACK __PORT16 0xFFFA0A /* HCAN1 Transmit Acknowledge Register */ +#define HCAN0_TXACK __PORT16 0xFFFFF80A /* HCAN0 Transmit Acknowledge Register */ +#define HCAN1_TXACK __PORT16 0xFFFFFA0A /* HCAN1 Transmit Acknowledge Register */ #define TXACK_TXACK8m 0x0001 #define TXACK_TXACK9m 0x0002 #define TXACK_TXACK10m 0x0004 @@ -168,8 +168,8 @@ #define TXACK_TXACK5m 0x2000 #define TXACK_TXACK6m 0x4000 #define TXACK_TXACK7m 0x8000 -#define HCAN0_ABACK __PORT16 0xFFF80C /* HCAN0 Abort Acknowledge Register */ -#define HCAN1_ABACK __PORT16 0xFFFA0C /* HCAN1 Abort Acknowledge Register */ +#define HCAN0_ABACK __PORT16 0xFFFFF80C /* HCAN0 Abort Acknowledge Register */ +#define HCAN1_ABACK __PORT16 0xFFFFFA0C /* HCAN1 Abort Acknowledge Register */ #define ABACK_ABACK8m 0x0001 #define ABACK_ABACK9m 0x0002 #define ABACK_ABACK10m 0x0004 @@ -185,8 +185,8 @@ #define ABACK_ABACK5m 0x2000 #define ABACK_ABACK6m 0x4000 #define ABACK_ABACK7m 0x8000 -#define HCAN0_RXPR __PORT16 0xFFF80E /* HCAN0 Receive Complete Register */ -#define HCAN1_RXPR __PORT16 0xFFFA0E /* HCAN1 Receive Complete Register */ +#define HCAN0_RXPR __PORT16 0xFFFFF80E /* HCAN0 Receive Complete Register */ +#define HCAN1_RXPR __PORT16 0xFFFFFA0E /* HCAN1 Receive Complete Register */ #define RXPR_RXPR8m 0x0001 #define RXPR_RXPR9m 0x0002 #define RXPR_RXPR10m 0x0004 @@ -203,8 +203,8 @@ #define RXPR_RXPR5m 0x2000 #define RXPR_RXPR6m 0x4000 #define RXPR_RXPR7m 0x8000 -#define HCAN0_RFPR __PORT16 0xFFF810 /* HCAN0 Remote Request Register */ -#define HCAN1_RFPR __PORT16 0xFFFA10 /* HCAN1 Remote Request Register */ +#define HCAN0_RFPR __PORT16 0xFFFFF810 /* HCAN0 Remote Request Register */ +#define HCAN1_RFPR __PORT16 0xFFFFFA10 /* HCAN1 Remote Request Register */ #define RFPR_RFPR8m 0x0001 #define RFPR_RFPR9m 0x0002 #define RFPR_RFPR10m 0x0004 @@ -221,8 +221,8 @@ #define RFPR_RFPR5m 0x2000 #define RFPR_RFPR6m 0x4000 #define RFPR_RFPR7m 0x8000 -#define HCAN0_IRR __PORT16 0xFFF812 /* HCAN0 Interrupt Register */ -#define HCAN1_IRR __PORT16 0xFFFA12 /* HCAN1 Interrupt Register */ +#define HCAN0_IRR __PORT16 0xFFFFF812 /* HCAN0 Interrupt Register */ +#define HCAN1_IRR __PORT16 0xFFFFFA12 /* HCAN1 Interrupt Register */ #define IRR_IRR0m 0x0100 #define IRR_IRR1m 0x0200 #define IRR_IRR2m 0x0400 @@ -234,8 +234,8 @@ #define IRR_IRR8m 0x0001 #define IRR_IRR9m 0x0002 #define IRR_IRR12m 0x0010 -#define HCAN0_IRRL __PORT8 0xFFF812 /* HCAN0 Interrupt Register L */ -#define HCAN1_IRRL __PORT8 0xFFFA12 /* HCAN1 Interrupt Register L */ +#define HCAN0_IRRL __PORT8 0xFFFFF812 /* HCAN0 Interrupt Register L */ +#define HCAN1_IRRL __PORT8 0xFFFFFA12 /* HCAN1 Interrupt Register L */ #define IRRL_IRR0m 0x01 #define IRRL_IRR1m 0x02 #define IRRL_IRR2m 0x04 @@ -244,13 +244,13 @@ #define IRRL_IRR5m 0x20 #define IRRL_IRR6m 0x40 #define IRRL_IRR7m 0x80 -#define HCAN0_IRRH __PORT8 0xFFF813 /* HCAN0 Interrupt Register H */ -#define HCAN1_IRRH __PORT8 0xFFFA13 /* HCAN0 Interrupt Register H */ +#define HCAN0_IRRH __PORT8 0xFFFFF813 /* HCAN0 Interrupt Register H */ +#define HCAN1_IRRH __PORT8 0xFFFFFA13 /* HCAN0 Interrupt Register H */ #define IRRH_IRR8m 0x01 #define IRRH_IRR9m 0x02 #define IRRH_IRR12m 0x10 -#define HCAN0_MBIMR __PORT16 0xFFF814 /* HCAN0 Mailbox Interrupt Mask Register */ -#define HCAN1_MBIMR __PORT16 0xFFFA14 /* HCAN1 Mailbox Interrupt Mask Register */ +#define HCAN0_MBIMR __PORT16 0xFFFFF814 /* HCAN0 Mailbox Interrupt Mask Register */ +#define HCAN1_MBIMR __PORT16 0xFFFFFA14 /* HCAN1 Mailbox Interrupt Mask Register */ #define MBIMR_MBIMR8m 0x0001 #define MBIMR_MBIMR9m 0x0002 #define MBIMR_MBIMR10m 0x0004 @@ -267,8 +267,8 @@ #define MBIMR_MBIMR5m 0x2000 #define MBIMR_MBIMR6m 0x4000 #define MBIMR_MBIMR7m 0x8000 -#define HCAN0_IMR __PORT16 0xFFF816 /* HCAN0 Interrupt Mask Register */ -#define HCAN1_IMR __PORT16 0xFFFA16 /* HCAN1 Interrupt Mask Register */ +#define HCAN0_IMR __PORT16 0xFFFFF816 /* HCAN0 Interrupt Mask Register */ +#define HCAN1_IMR __PORT16 0xFFFFFA16 /* HCAN1 Interrupt Mask Register */ #define IMR_IMR8m 0x0001 #define IMR_IMR9m 0x0002 #define IMR_IMR12m 0x0010 @@ -279,8 +279,8 @@ #define IMR_IMR5m 0x2000 #define IMR_IMR6m 0x4000 #define IMR_IMR7m 0x8000 -#define HCAN0_IMRL __PORT8 0xFFF816 /* HCAN0 Interrupt Mask Register L */ -#define HCAN1_IMRL __PORT8 0xFFFA16 /* HCAN1 Interrupt Mask Register L */ +#define HCAN0_IMRL __PORT8 0xFFFFF816 /* HCAN0 Interrupt Mask Register L */ +#define HCAN1_IMRL __PORT8 0xFFFFFA16 /* HCAN1 Interrupt Mask Register L */ #define IMRL_IMR1m 0x02 #define IMRL_IMR2m 0x04 #define IMRL_IMR3m 0x08 @@ -288,17 +288,17 @@ #define IMRL_IMR5m 0x20 #define IMRL_IMR6m 0x40 #define IMRL_IMR7m 0x80 -#define HCAN0_IMRH __PORT8 0xFFF817 /* HCAN0 Interrupt Mask Register H */ -#define HCAN1_IMRH __PORT8 0xFFFA17 /* HCAN1 Interrupt Mask Register H */ +#define HCAN0_IMRH __PORT8 0xFFFFF817 /* HCAN0 Interrupt Mask Register H */ +#define HCAN1_IMRH __PORT8 0xFFFFFA17 /* HCAN1 Interrupt Mask Register H */ #define IMRH_IMR8m 0x01 #define IMRH_IMR9m 0x02 #define IMRH_IMR12m 0x10 -#define HCAN0_REC __PORT8 0xFFF818 /* HCAN0 Receive Error Counter */ -#define HCAN1_REC __PORT8 0xFFFA18 /* HCAN1 Receive Error Counter */ -#define HCAN0_TEC __PORT8 0xFFF819 /* HCAN0 Transmit Error Counter */ -#define HCAN1_TEC __PORT8 0xFFFA19 /* HCAN1 Transmit Error Counter */ -#define HCAN0_UMSR __PORT16 0xFFF81A /* HCAN0 Unread Message Status Register */ -#define HCAN1_UMSR __PORT16 0xFFFA1A /* HCAN1 Unread Message Status Register */ +#define HCAN0_REC __PORT8 0xFFFFF818 /* HCAN0 Receive Error Counter */ +#define HCAN1_REC __PORT8 0xFFFFFA18 /* HCAN1 Receive Error Counter */ +#define HCAN0_TEC __PORT8 0xFFFFF819 /* HCAN0 Transmit Error Counter */ +#define HCAN1_TEC __PORT8 0xFFFFFA19 /* HCAN1 Transmit Error Counter */ +#define HCAN0_UMSR __PORT16 0xFFFFF81A /* HCAN0 Unread Message Status Register */ +#define HCAN1_UMSR __PORT16 0xFFFFFA1A /* HCAN1 Unread Message Status Register */ #define UMSR_UMSR8m 0x0001 #define UMSR_UMSR9m 0x0002 #define UMSR_UMSR10m 0x0004 @@ -315,78 +315,78 @@ #define UMSR_UMSR5m 0x2000 #define UMSR_UMSR6m 0x4000 #define UMSR_UMSR7m 0x8000 -#define HCAN0_LAFML __PORT16 0xFFF81C /* HCAN0 Local Acceptance Filter Masks L */ -#define HCAN1_LAFML __PORT16 0xFFFA1C /* HCAN1 Local Acceptance Filter Masks L */ -#define HCAN0_LAFMH __PORT16 0xFFF81E /* HCAN0 Local Acceptance Filter Masks H */ -#define HCAN1_LAFMH __PORT16 0xFFFA1E /* HCAN1 Local Acceptance Filter Masks H */ +#define HCAN0_LAFML __PORT16 0xFFFFF81C /* HCAN0 Local Acceptance Filter Masks L */ +#define HCAN1_LAFML __PORT16 0xFFFFFA1C /* HCAN1 Local Acceptance Filter Masks L */ +#define HCAN0_LAFMH __PORT16 0xFFFFF81E /* HCAN0 Local Acceptance Filter Masks H */ +#define HCAN1_LAFMH __PORT16 0xFFFFFA1E /* HCAN1 Local Acceptance Filter Masks H */ /* Message Control and Data registers (MC0 to MC15) and (MD0 to MD15) for HCAN0 and HCAN1 */ -#define HCAN0_MC0 __PORT8 0xFFF820 /* Message Control 0 */ -#define HCAN1_MC0 __PORT8 0xFFFA20 -#define HCAN0_MC1 __PORT8 0xFFF828 /* Message Control 1 */ -#define HCAN1_MC1 __PORT8 0xFFFA28 -#define HCAN0_MC2 __PORT8 0xFFF830 /* Message Control 2 */ -#define HCAN1_MC2 __PORT8 0xFFFA30 -#define HCAN0_MC3 __PORT8 0xFFF838 /* Message Control 3 */ -#define HCAN1_MC3 __PORT8 0xFFFA38 -#define HCAN0_MC4 __PORT8 0xFFF840 /* Message Control 4 */ -#define HCAN1_MC4 __PORT8 0xFFFA40 -#define HCAN0_MC5 __PORT8 0xFFF848 /* Message Control 5 */ -#define HCAN1_MC5 __PORT8 0xFFFA48 -#define HCAN0_MC6 __PORT8 0xFFF850 /* Message Control 6 */ -#define HCAN1_MC6 __PORT8 0xFFFA50 -#define HCAN0_MC7 __PORT8 0xFFF858 /* Message Control 7 */ -#define HCAN1_MC7 __PORT8 0xFFFA58 -#define HCAN0_MC8 __PORT8 0xFFF860 /* Message Control 8 */ -#define HCAN1_MC8 __PORT8 0xFFFA60 -#define HCAN0_MC9 __PORT8 0xFFF868 /* Message Control 9 */ -#define HCAN1_MC9 __PORT8 0xFFFA68 -#define HCAN0_MC10 __PORT8 0xFFF870 /* Message Control 10 */ -#define HCAN1_MC10 __PORT8 0xFFFA70 -#define HCAN0_MC11 __PORT8 0xFFF878 /* Message Control 11 */ -#define HCAN1_MC11 __PORT8 0xFFFA78 -#define HCAN0_MC12 __PORT8 0xFFF880 /* Message Control 12 */ -#define HCAN1_MC12 __PORT8 0xFFFA80 -#define HCAN0_MC13 __PORT8 0xFFF888 /* Message Control 13 */ -#define HCAN1_MC13 __PORT8 0xFFFA88 -#define HCAN0_MC14 __PORT8 0xFFF890 /* Message Control 14 */ -#define HCAN1_MC14 __PORT8 0xFFFA90 -#define HCAN0_MC15 __PORT8 0xFFF898 /* Message Control 15 */ -#define HCAN1_MC15 __PORT8 0xFFFA98 -#define HCAN0_MD0 __PORT8 0xFFF8B0 /* Message Data 0 */ -#define HCAN1_MD0 __PORT8 0xFFFAB0 -#define HCAN0_MD1 __PORT8 0xFFF8B8 /* Message Data 1 */ -#define HCAN1_MD1 __PORT8 0xFFFAB8 -#define HCAN0_MD2 __PORT8 0xFFF8C0 /* Message Data 2 */ -#define HCAN1_MD2 __PORT8 0xFFFAC0 -#define HCAN0_MD3 __PORT8 0xFFF8C8 /* Message Data 3 */ -#define HCAN1_MD3 __PORT8 0xFFFAC8 -#define HCAN0_MD4 __PORT8 0xFFF8D0 /* Message Data 4 */ -#define HCAN1_MD4 __PORT8 0xFFFAD0 -#define HCAN0_MD5 __PORT8 0xFFF8D8 /* Message Data 5 */ -#define HCAN1_MD5 __PORT8 0xFFFAD8 -#define HCAN0_MD6 __PORT8 0xFFF8E0 /* Message Data 6 */ -#define HCAN1_MD6 __PORT8 0xFFFAE0 -#define HCAN0_MD7 __PORT8 0xFFF8E8 /* Message Data 7 */ -#define HCAN1_MD7 __PORT8 0xFFFAE8 -#define HCAN0_MD8 __PORT8 0xFFF8F0 /* Message Data 8 */ -#define HCAN1_MD8 __PORT8 0xFFFAF0 -#define HCAN0_MD9 __PORT8 0xFFF8F8 /* Message Data 9 */ -#define HCAN1_MD9 __PORT8 0xFFFAF8 -#define HCAN0_MD10 __PORT8 0xFFF900 /* Message Data 10 */ -#define HCAN1_MD10 __PORT8 0xFFFB00 -#define HCAN0_MD11 __PORT8 0xFFF908 /* Message Data 11 */ -#define HCAN1_MD11 __PORT8 0xFFFB08 -#define HCAN0_MD12 __PORT8 0xFFF910 /* Message Data 12 */ -#define HCAN1_MD12 __PORT8 0xFFFB10 -#define HCAN0_MD13 __PORT8 0xFFF918 /* Message Data 13 */ -#define HCAN1_MD13 __PORT8 0xFFFB18 -#define HCAN0_MD14 __PORT8 0xFFF920 /* Message Data 14 */ -#define HCAN1_MD14 __PORT8 0xFFFB20 -#define HCAN0_MD15 __PORT8 0xFFF928 /* Message Data 15 */ -#define HCAN1_MD15 __PORT8 0xFFFB28 +#define HCAN0_MC0 __PORT8 0xFFFFF820 /* Message Control 0 */ +#define HCAN1_MC0 __PORT8 0xFFFFFA20 +#define HCAN0_MC1 __PORT8 0xFFFFF828 /* Message Control 1 */ +#define HCAN1_MC1 __PORT8 0xFFFFFA28 +#define HCAN0_MC2 __PORT8 0xFFFFF830 /* Message Control 2 */ +#define HCAN1_MC2 __PORT8 0xFFFFFA30 +#define HCAN0_MC3 __PORT8 0xFFFFF838 /* Message Control 3 */ +#define HCAN1_MC3 __PORT8 0xFFFFFA38 +#define HCAN0_MC4 __PORT8 0xFFFFF840 /* Message Control 4 */ +#define HCAN1_MC4 __PORT8 0xFFFFFA40 +#define HCAN0_MC5 __PORT8 0xFFFFF848 /* Message Control 5 */ +#define HCAN1_MC5 __PORT8 0xFFFFFA48 +#define HCAN0_MC6 __PORT8 0xFFFFF850 /* Message Control 6 */ +#define HCAN1_MC6 __PORT8 0xFFFFFA50 +#define HCAN0_MC7 __PORT8 0xFFFFF858 /* Message Control 7 */ +#define HCAN1_MC7 __PORT8 0xFFFFFA58 +#define HCAN0_MC8 __PORT8 0xFFFFF860 /* Message Control 8 */ +#define HCAN1_MC8 __PORT8 0xFFFFFA60 +#define HCAN0_MC9 __PORT8 0xFFFFF868 /* Message Control 9 */ +#define HCAN1_MC9 __PORT8 0xFFFFFA68 +#define HCAN0_MC10 __PORT8 0xFFFFF870 /* Message Control 10 */ +#define HCAN1_MC10 __PORT8 0xFFFFFA70 +#define HCAN0_MC11 __PORT8 0xFFFFF878 /* Message Control 11 */ +#define HCAN1_MC11 __PORT8 0xFFFFFA78 +#define HCAN0_MC12 __PORT8 0xFFFFF880 /* Message Control 12 */ +#define HCAN1_MC12 __PORT8 0xFFFFFA80 +#define HCAN0_MC13 __PORT8 0xFFFFF888 /* Message Control 13 */ +#define HCAN1_MC13 __PORT8 0xFFFFFA88 +#define HCAN0_MC14 __PORT8 0xFFFFF890 /* Message Control 14 */ +#define HCAN1_MC14 __PORT8 0xFFFFFA90 +#define HCAN0_MC15 __PORT8 0xFFFFF898 /* Message Control 15 */ +#define HCAN1_MC15 __PORT8 0xFFFFFA98 +#define HCAN0_MD0 __PORT8 0xFFFFF8B0 /* Message Data 0 */ +#define HCAN1_MD0 __PORT8 0xFFFFFAB0 +#define HCAN0_MD1 __PORT8 0xFFFFF8B8 /* Message Data 1 */ +#define HCAN1_MD1 __PORT8 0xFFFFFAB8 +#define HCAN0_MD2 __PORT8 0xFFFFF8C0 /* Message Data 2 */ +#define HCAN1_MD2 __PORT8 0xFFFFFAC0 +#define HCAN0_MD3 __PORT8 0xFFFFF8C8 /* Message Data 3 */ +#define HCAN1_MD3 __PORT8 0xFFFFFAC8 +#define HCAN0_MD4 __PORT8 0xFFFFF8D0 /* Message Data 4 */ +#define HCAN1_MD4 __PORT8 0xFFFFFAD0 +#define HCAN0_MD5 __PORT8 0xFFFFF8D8 /* Message Data 5 */ +#define HCAN1_MD5 __PORT8 0xFFFFFAD8 +#define HCAN0_MD6 __PORT8 0xFFFFF8E0 /* Message Data 6 */ +#define HCAN1_MD6 __PORT8 0xFFFFFAE0 +#define HCAN0_MD7 __PORT8 0xFFFFF8E8 /* Message Data 7 */ +#define HCAN1_MD7 __PORT8 0xFFFFFAE8 +#define HCAN0_MD8 __PORT8 0xFFFFF8F0 /* Message Data 8 */ +#define HCAN1_MD8 __PORT8 0xFFFFFAF0 +#define HCAN0_MD9 __PORT8 0xFFFFF8F8 /* Message Data 9 */ +#define HCAN1_MD9 __PORT8 0xFFFFFAF8 +#define HCAN0_MD10 __PORT8 0xFFFFF900 /* Message Data 10 */ +#define HCAN1_MD10 __PORT8 0xFFFFFB00 +#define HCAN0_MD11 __PORT8 0xFFFFF908 /* Message Data 11 */ +#define HCAN1_MD11 __PORT8 0xFFFFFB08 +#define HCAN0_MD12 __PORT8 0xFFFFF910 /* Message Data 12 */ +#define HCAN1_MD12 __PORT8 0xFFFFFB10 +#define HCAN0_MD13 __PORT8 0xFFFFF918 /* Message Data 13 */ +#define HCAN1_MD13 __PORT8 0xFFFFFB18 +#define HCAN0_MD14 __PORT8 0xFFFFF920 /* Message Data 14 */ +#define HCAN1_MD14 __PORT8 0xFFFFFB20 +#define HCAN0_MD15 __PORT8 0xFFFFF928 /* Message Data 15 */ +#define HCAN1_MD15 __PORT8 0xFFFFFB28 /* Motor control PWM timer 1 */ -#define PWM_PWCR1 __PORT8 0xFFFC00 /* PWM control register 1 */ +#define PWM_PWCR1 __PORT8 0xFFFFFC00 /* PWM control register 1 */ #define PWCR1_CKS0m 0x01 #define PWCR1_CKS1m 0x02 #define PWCR1_CKS2m 0x04 @@ -398,7 +398,7 @@ #define PWCR1_CSTm 0x08 #define PWCR1_CMFm 0x10 #define PWCR1_IEm 0x20 -#define PWM_PWOCR1 __PORT8 0xFFFC02 /* PWM Output Control Register 1 */ +#define PWM_PWOCR1 __PORT8 0xFFFFFC02 /* PWM Output Control Register 1 */ #define PWOCR1_OE1Am 0x01 #define PWOCR1_OE1Bm 0x02 #define PWOCR1_OE1Cm 0x04 @@ -407,7 +407,7 @@ #define PWOCR1_OE1Fm 0x20 #define PWOCR1_OE1Gm 0x40 #define PWOCR1_OE1Hm 0x80 -#define PWM_PWPR1 __PORT8 0xFFFC04 /* PWM Polarity Register 1 */ +#define PWM_PWPR1 __PORT8 0xFFFFFC04 /* PWM Polarity Register 1 */ #define PWPR1_OPS1Am 0x01 #define PWPR1_OPS1Bm 0x02 #define PWPR1_OPS1Cm 0x04 @@ -416,29 +416,29 @@ #define PWPR1_OPS1Fm 0x20 #define PWPR1_OPS1Gm 0x40 #define PWPR1_OPS1Hm 0x80 -#define PWM_PWCYR1 __PORT16 0xFFFC06 /* PWM Cycle Register 1 */ -#define PWM_PWBFR1A __PORT16 0xFFFC08 /* PWM Buffer Register 1A */ +#define PWM_PWCYR1 __PORT16 0xFFFFFC06 /* PWM Cycle Register 1 */ +#define PWM_PWBFR1A __PORT16 0xFFFFFC08 /* PWM Buffer Register 1A */ #define PWBFR1A_DT8m 0x0100 #define PWBFR1A_DT9m 0x0200 #define PWBFR1A_DTxm 0x03ff #define PWBFR1A_OTSm 0x1000 -#define PWM_PWBFR1C __PORT16 0xFFFC0A /* PWM Buffer Register 1C */ +#define PWM_PWBFR1C __PORT16 0xFFFFFC0A /* PWM Buffer Register 1C */ #define PWBFR1C_DT8m 0x0100 #define PWBFR1C_DT9m 0x0200 #define PWBFR1C_DTxm 0x03ff #define PWBFR1C_OTSm 0x1000 -#define PWM_PWBFR1E __PORT16 0xFFFC0C /* PWM Buffer Register 1E */ +#define PWM_PWBFR1E __PORT16 0xFFFFFC0C /* PWM Buffer Register 1E */ #define PWBFR1E_DT8m 0x0100 #define PWBFR1E_DT9m 0x0200 #define PWBFR1E_DTxm 0x03ff #define PWBFR1E_OTSm 0x1000 -#define PWM_PWBFR1G __PORT16 0xFFFC0E /* PWM Buffer Register 1G */ +#define PWM_PWBFR1G __PORT16 0xFFFFFC0E /* PWM Buffer Register 1G */ #define PWBFR1G_DT8m 0x0100 #define PWBFR1G_DT9m 0x0200 #define PWBFR1G_DTxm 0x03ff #define PWBFR1G_OTSm 0x1000 /* Motor control PWM timer 2 */ -#define PWM_PWCR2 __PORT8 0xFFFC10 /* PWM Control Register 2 */ +#define PWM_PWCR2 __PORT8 0xFFFFFC10 /* PWM Control Register 2 */ #define PWCR2_CKS0m 0x01 #define PWCR2_CKS1m 0x02 #define PWCR2_CKS2m 0x04 @@ -450,7 +450,7 @@ #define PWCR2_CSTm 0x08 #define PWCR2_CMFm 0x10 #define PWCR2_IEm 0x20 -#define PWM_PWOCR2 __PORT8 0xFFFC12 /* PWM Output Control Register 2 */ +#define PWM_PWOCR2 __PORT8 0xFFFFFC12 /* PWM Output Control Register 2 */ #define PWOCR2_OE2Am 0x01 #define PWOCR2_OE2Bm 0x02 #define PWOCR2_OE2Cm 0x04 @@ -459,7 +459,7 @@ #define PWOCR2_OE2Fm 0x20 #define PWOCR2_OE2Gm 0x40 #define PWOCR2_OE2Hm 0x80 -#define PWM_PWPR2 __PORT8 0xFFFC14 /* PWM Polarity Register 2 */ +#define PWM_PWPR2 __PORT8 0xFFFFFC14 /* PWM Polarity Register 2 */ #define PWPR2_OPS2Am 0x01 #define PWPR2_OPS2Bm 0x02 #define PWPR2_OPS2Cm 0x04 @@ -468,29 +468,29 @@ #define PWPR2_OPS2Fm 0x20 #define PWPR2_OPS2Gm 0x40 #define PWPR2_OPS2Hm 0x80 -#define PWM_PWCYR2 __PORT16 0xFFFC16 /* PWM Cycle Register 2 */ -#define PWM_PWBFR2A __PORT16 0xFFFC18 /* PWM Buffer Register 2A */ +#define PWM_PWCYR2 __PORT16 0xFFFFFC16 /* PWM Cycle Register 2 */ +#define PWM_PWBFR2A __PORT16 0xFFFFFC18 /* PWM Buffer Register 2A */ #define PWBFR2A_DT8m 0x0100 #define PWBFR2A_DT9m 0x0200 #define PWBFR2A_DTxm 0x03ff #define PWBFR2A_TDSm 0x1000 -#define PWM_PWBFR2B __PORT16 0xFFFC1A /* PWM Buffer Register 2B */ +#define PWM_PWBFR2B __PORT16 0xFFFFFC1A /* PWM Buffer Register 2B */ #define PWBFR2B_DT8m 0x0100 #define PWBFR2B_DT9m 0x0200 #define PWBFR2B_DTxm 0x03ff #define PWBFR2B_TDSm 0x1000 -#define PWM_PWBFR2C __PORT16 0xFFFC1C /* PWM Buffer Register 2C */ +#define PWM_PWBFR2C __PORT16 0xFFFFFC1C /* PWM Buffer Register 2C */ #define PWBFR2C_DT8m 0x0100 #define PWBFR2C_DT9m 0x0200 #define PWBFR2C_DTxm 0x03ff #define PWBFR2C_TDSm 0x1000 -#define PWM_PWBFR2D __PORT16 0xFFFC1E /* PWM Buffer Register 2E */ +#define PWM_PWBFR2D __PORT16 0xFFFFFC1E /* PWM Buffer Register 2E */ #define PWBFR2D_DT8m 0x0100 #define PWBFR2D_DT9m 0x0200 #define PWBFR2D_DTxm 0x03ff #define PWBFR2D_TDSm 0x1000 /* Port H and J Registers */ -#define DIO_PHDDR __PORT8 0xFFFC20 /* DIO H Data Direction Register */ +#define DIO_PHDDR __PORT8 0xFFFFFC20 /* DIO H Data Direction Register */ #define PHDDR_PH0DDRm 0x01 #define PHDDR_PH1DDRm 0x02 #define PHDDR_PH2DDRm 0x04 @@ -499,7 +499,7 @@ #define PHDDR_PH5DDRm 0x20 #define PHDDR_PH6DDRm 0x40 #define PHDDR_PH7DDRm 0x80 -#define DIO_PJDDR __PORT8 0xFFFC21 /* DIO J Data Direction Register */ +#define DIO_PJDDR __PORT8 0xFFFFFC21 /* DIO J Data Direction Register */ #define PJDDR_PJ0DDRm 0x01 #define PJDDR_PJ1DDRm 0x02 #define PJDDR_PJ2DDRm 0x04 @@ -508,7 +508,7 @@ #define PJDDR_PJ5DDRm 0x20 #define PJDDR_PJ6DDRm 0x40 #define PJDDR_PJ7DDRm 0x80 -#define DIO_PHDR __PORT8 0xFFFC24 /* DIO H Data Register */ +#define DIO_PHDR __PORT8 0xFFFFFC24 /* DIO H Data Register */ #define PHDR_PH0DRm 0x01 #define PHDR_PH1DRm 0x02 #define PHDR_PH2DRm 0x04 @@ -517,7 +517,7 @@ #define PHDR_PH5DRm 0x20 #define PHDR_PH6DRm 0x40 #define PHDR_PH7DRm 0x80 -#define DIO_PJDR __PORT8 0xFFFC25 /* DIO J Data Register */ +#define DIO_PJDR __PORT8 0xFFFFFC25 /* DIO J Data Register */ #define PJDR_PJ0DRm 0x01 #define PJDR_PJ1DRm 0x02 #define PJDR_PJ2DRm 0x04 @@ -526,7 +526,7 @@ #define PJDR_PJ5DRm 0x20 #define PJDR_PJ6DRm 0x40 #define PJDR_PJ7DRm 0x80 -#define DIO_PORTH __PORT8 0xFFFC28 /* DIO H Register */ +#define DIO_PORTH __PORT8 0xFFFFFC28 /* DIO H Register */ #define PORTH_PH0m 0x01 #define PORTH_PH1m 0x02 #define PORTH_PH2m 0x04 @@ -535,7 +535,7 @@ #define PORTH_PH5m 0x20 #define PORTH_PH6m 0x40 #define PORTH_PH7m 0x80 -#define DIO_PORTJ __PORT8 0xFFFC29 /* DIO J Register */ +#define DIO_PORTJ __PORT8 0xFFFFFC29 /* DIO J Register */ #define PORTJ_PJ0m 0x01 #define PORTJ_PJ1m 0x02 #define PORTJ_PJ2m 0x04 @@ -546,11 +546,11 @@ #define PORTJ_PJ7m 0x80 /* Module IIC valid in 2630,2638 and 2639 */ -#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */ +#define IIC_SCRX __PORT8 0xFFFFFDB4 /* Serial Control Register X */ #define SCRX_IICEm 0x10 #define SCRX_IICX0m 0x20 #define SCRX_IICX1m 0x40 -#define IIC_DDCSWR __PORT8 0xFFFDB5 /* DDC Switch Register */ +#define IIC_DDCSWR __PORT8 0xFFFFFDB5 /* DDC Switch Register */ #define DDCSWR_CLR0m 0x01 #define DDCSWR_CLR1m 0x02 #define DDCSWR_CLR2m 0x04 @@ -560,36 +560,36 @@ #define DDCSWR_SWm 0x40 #define DDCSWR_SWEm 0x80 /* Module System */ -#define SYS_SBYCR __PORT8 0xFFFDE4 /* Standby Control Register */ +#define SYS_SBYCR __PORT8 0xFFFFFDE4 /* Standby Control Register */ #define SBYCR_OPEm 0x08 #define SBYCR_STS0m 0x10 #define SBYCR_STS1m 0x20 #define SBYCR_STS2m 0x40 #define SBYCR_SSBYm 0x80 -#define SYS_SYSCR __PORT8 0xFFFDE5 /* SYS Control Register */ +#define SYS_SYSCR __PORT8 0xFFFFFDE5 /* SYS Control Register */ #define SYSCR_RAMEm 0x01 #define SYSCR_NMIEGm 0x08 #define SYSCR_INTM0m 0x10 #define SYSCR_INTM1m 0x20 #define SYSCR_MACSm 0x80 -#define SYS_SCKCR __PORT8 0xFFFDE6 /* SYS Clock Control Register */ +#define SYS_SCKCR __PORT8 0xFFFFFDE6 /* SYS Clock Control Register */ #define SCKCR_SCK0m 0x01 /* Bus master clock selection */ #define SCKCR_SCK1m 0x02 /* 0=full, 1=/2, 2=/4 3=/8 */ #define SCKCR_SCK2m 0x04 /* 4=/16, 5=/32 */ #define SCKCR_SCKxm 0x07 #define SCKCR_STCSm 0x08 /* 1=Immediately change, 0=at Stby */ #define SCKCR_PSTOPm 0x80 /* 1=Clock Output Disable */ -#define SYS_MDCR __PORT8 0xFFFDE7 /* Mode Control Register */ +#define SYS_MDCR __PORT8 0xFFFFFDE7 /* Mode Control Register */ #define MDCR_MDS0m 0x01 #define MDCR_MDS1m 0x02 #define MDCR_MDS2m 0x04 -#define SYS_PFCR __PORT8 0xFFFDEB /* Pin Function Control Register */ +#define SYS_PFCR __PORT8 0xFFFFFDEB /* Pin Function Control Register */ #define PFCR_AE0m 0x01 #define PFCR_AE1m 0x02 #define PFCR_AE2m 0x04 #define PFCR_AE3m 0x08 #define PFCR_AExm 0x0f -#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */ +#define SYS_LPWRCR __PORT8 0xFFFFFDEC /* Low-Power Control Register */ #define LPWRCR_STC0m 0x01 #define LPWRCR_STC1m 0x02 #define LPWRCR_STCxm 0x03 @@ -599,9 +599,9 @@ #define LPWRCR_LSONm 0x40 #define LPWRCR_DTONm 0x80 /* Module PC Break Controller */ -#define PBC_BARA __PORT32 0xFFFE00 /* Break Address Register A */ -#define PBC_BARB __PORT32 0xFFFE04 /* Break Address Register B */ -#define PBC_BCRA __PORT8 0xFFFE08 /* Break Control Register A */ +#define PBC_BARA __PORT32 0xFFFFFE00 /* Break Address Register A */ +#define PBC_BARB __PORT32 0xFFFFFE04 /* Break Address Register B */ +#define PBC_BCRA __PORT8 0xFFFFFE08 /* Break Control Register A */ #define BCRA_BIEAm 0x01 #define BCRA_CSELA0m 0x02 #define BCRA_CSELA1m 0x04 @@ -610,7 +610,7 @@ #define BCRA_BAMRA2m 0x20 #define BCRA_CDAm 0x40 #define BCRA_CMFAm 0x80 -#define PBC_BCRB __PORT8 0xFFFE09 /* Break Control Register B */ +#define PBC_BCRB __PORT8 0xFFFFFE09 /* Break Control Register B */ #define BCRB_BIEAm 0x01 #define BCRB_CSELA0m 0x02 #define BCRB_CSELA1m 0x04 @@ -620,12 +620,12 @@ #define BCRB_CDAm 0x40 #define BCRB_CMFAm 0x80 /* Module Interrupt Controller Registers */ -#define INT_ISCRH __PORT8 0xFFFE12 /* IRQ Sence Control Register H */ +#define INT_ISCRH __PORT8 0xFFFFFE12 /* IRQ Sence Control Register H */ #define ISCRH_IRQ4SCAm 0x01 #define ISCRH_IRQ4SCBm 0x02 #define ISCRH_IRQ5SCAm 0x04 #define ISCRH_IRQ5SCBm 0x08 -#define INT_ISCRL __PORT8 0xFFFE13 /* IRQ Sence Control Register L */ +#define INT_ISCRL __PORT8 0xFFFFFE13 /* IRQ Sence Control Register L */ #define ISCRL_IRQ0SCAm 0x01 #define ISCRL_IRQ0SCBm 0x02 #define ISCRL_IRQ1SCAm 0x04 @@ -634,14 +634,14 @@ #define ISCRL_IRQ2SCBm 0x20 #define ISCRL_IRQ3SCAm 0x40 #define ISCRL_IRQ3SCBm 0x80 -#define INT_IER __PORT8 0xFFFE14 /* IRQ Enable Register */ +#define INT_IER __PORT8 0xFFFFFE14 /* IRQ Enable Register */ #define IER_IRQ0Em 0x01 #define IER_IRQ1Em 0x02 #define IER_IRQ2Em 0x04 #define IER_IRQ3Em 0x08 #define IER_IRQ4Em 0x10 #define IER_IRQ5Em 0x20 -#define INT_ISR __PORT8 0xFFFE15 /* IRQ Status Register */ +#define INT_ISR __PORT8 0xFFFFFE15 /* IRQ Status Register */ #define ISR_IRQ0Fm 0x01 #define ISR_IRQ1Fm 0x02 #define ISR_IRQ2Fm 0x04 @@ -649,7 +649,7 @@ #define ISR_IRQ4Fm 0x10 #define ISR_IRQ5Fm 0x20 -#define DTC_DTCERA __PORT8 0xFFFE16 /* DTC Enable Register A */ +#define DTC_DTCERA __PORT8 0xFFFFFE16 /* DTC Enable Register A */ #define DTCERA_DTCEA0m 0x01 #define DTCERA_DTCEA1m 0x02 #define DTCERA_DTCEA2m 0x04 @@ -658,7 +658,7 @@ #define DTCERA_DTCEA5m 0x20 #define DTCERA_DTCEA6m 0x40 #define DTCERA_DTCEA7m 0x80 -#define DTC_DTCERB __PORT8 0xFFFE17 /* DTC Enable Register B */ +#define DTC_DTCERB __PORT8 0xFFFFFE17 /* DTC Enable Register B */ #define DTCERB_DTCEB0m 0x01 #define DTCERB_DTCEB1m 0x02 #define DTCERB_DTCEB2m 0x04 @@ -667,7 +667,7 @@ #define DTCERB_DTCEB5m 0x20 #define DTCERB_DTCEB6m 0x40 #define DTCERB_DTCEB7m 0x80 -#define DTC_DTCERC __PORT8 0xFFFE18 /* DTC Enable Register C */ +#define DTC_DTCERC __PORT8 0xFFFFFE18 /* DTC Enable Register C */ #define DTCERC_DTCEC0m 0x01 #define DTCERC_DTCEC1m 0x02 #define DTCERC_DTCEC2m 0x04 @@ -676,7 +676,7 @@ #define DTCERC_DTCEC5m 0x20 #define DTCERC_DTCEC6m 0x40 #define DTCERC_DTCEC7m 0x80 -#define DTC_DTCERD __PORT8 0xFFFE19 /* DTC Enable Register D */ +#define DTC_DTCERD __PORT8 0xFFFFFE19 /* DTC Enable Register D */ #define DTCERD_DTCED0m 0x01 #define DTCERD_DTCED1m 0x02 #define DTCERD_DTCED2m 0x04 @@ -685,7 +685,7 @@ #define DTCERD_DTCED5m 0x20 #define DTCERD_DTCED6m 0x40 #define DTCERD_DTCED7m 0x80 -#define DTC_DTCERE __PORT8 0xFFFE1A /* DTC Enable Register E */ +#define DTC_DTCERE __PORT8 0xFFFFFE1A /* DTC Enable Register E */ #define DTCERE_DTCEE0m 0x01 #define DTCERE_DTCEE1m 0x02 #define DTCERE_DTCEE2m 0x04 @@ -694,7 +694,7 @@ #define DTCERE_DTCEE5m 0x20 #define DTCERE_DTCEE6m 0x40 #define DTCERE_DTCEE7m 0x80 -#define DTC_DTCERF __PORT8 0xFFFE1B /* DTC Enable Register F */ +#define DTC_DTCERF __PORT8 0xFFFFFE1B /* DTC Enable Register F */ #define DTCERF_DTCEF0m 0x01 #define DTCERF_DTCEF1m 0x02 #define DTCERF_DTCEF2m 0x04 @@ -703,7 +703,7 @@ #define DTCERF_DTCEF5m 0x20 #define DTCERF_DTCEF6m 0x40 #define DTCERF_DTCEF7m 0x80 -#define DTC_DTCERG __PORT8 0xFFFE1C /* DTC Enable Register G */ +#define DTC_DTCERG __PORT8 0xFFFFFE1C /* DTC Enable Register G */ #define DTCERG_DTCEG0m 0x01 #define DTCERG_DTCEG1m 0x02 #define DTCERG_DTCEG2m 0x04 @@ -712,7 +712,7 @@ #define DTCERG_DTCEG5m 0x20 #define DTCERG_DTCEG6m 0x40 #define DTCERG_DTCEG7m 0x80 -#define DTC_DTVECR __PORT8 0xFFFE1F /* DTC Vector Register */ +#define DTC_DTVECR __PORT8 0xFFFFFE1F /* DTC Vector Register */ #define DTVECR_DTVEC0m 0x01 #define DTVECR_DTVEC1m 0x02 #define DTVECR_DTVEC2m 0x04 @@ -722,7 +722,7 @@ #define DTVECR_DTVEC6m 0x40 #define DTVECR_SWDTEm 0x80 /* Module Programmable Pulse Generator */ -#define PPG_PCR __PORT8 0xFFFE26 /* PPG Output Control Register */ +#define PPG_PCR __PORT8 0xFFFFFE26 /* PPG Output Control Register */ #define PCR_G0CMS0m 0x01 #define PCR_G0CMS1m 0x02 #define PCR_G1CMS0m 0x04 @@ -731,7 +731,7 @@ #define PCR_G2CMS1m 0x20 #define PCR_G3CMS0m 0x40 #define PCR_G3CMS1m 0x80 -#define PPG_PMR __PORT8 0xFFFE27 /* PPG Output Mode Register */ +#define PPG_PMR __PORT8 0xFFFFFE27 /* PPG Output Mode Register */ #define PMR_G0NOVm 0x01 #define PMR_G1NOVm 0x02 #define PMR_G2NOVm 0x04 @@ -740,7 +740,7 @@ #define PMR_G1INVm 0x20 #define PMR_G2INVm 0x40 #define PMM_G3INVm 0x80 -#define PPG_NDERH __PORT8 0xFFFE28 /* Next Data Enable Register H */ +#define PPG_NDERH __PORT8 0xFFFFFE28 /* Next Data Enable Register H */ #define NDERH_NDER8m 0x01 #define NDERH_NDER9m 0x02 #define NDERH_NDER10m 0x04 @@ -749,7 +749,7 @@ #define NDERH_NDER13m 0x20 #define NDERH_NDER14m 0x40 #define NDERH_NDER15m 0x80 -#define PPG_NDERL __PORT8 0xFFFE29 /* Next Data Enable Register L */ +#define PPG_NDERL __PORT8 0xFFFFFE29 /* Next Data Enable Register L */ #define NDERL_NDER0m 0x01 #define NDERL_NDER1m 0x02 #define NDERL_NDER2m 0x04 @@ -758,7 +758,7 @@ #define NDERL_NDER5m 0x20 #define NDERL_NDER6m 0x40 #define NDERL_NDER7m 0x80 -#define PPG_PODRH __PORT8 0xFFFE2A /* Output Data Register H */ +#define PPG_PODRH __PORT8 0xFFFFFE2A /* Output Data Register H */ #define PODRH_POD8m 0x01 #define PODRH_POD9m 0x02 #define PODRH_POD10m 0x04 @@ -767,7 +767,7 @@ #define PODRH_POD13m 0x20 #define PODRH_POD14m 0x40 #define PODRH_POD15m 0x80 -#define PPG_PODRL __PORT8 0xFFFE2B /* Output Data Register L */ +#define PPG_PODRL __PORT8 0xFFFFFE2B /* Output Data Register L */ #define PODRL_POD0m 0x01 #define PODRL_POD1m 0x02 #define PODRL_POD2m 0x04 @@ -776,7 +776,7 @@ #define PODRL_POD5m 0x20 #define PODRL_POD6m 0x40 #define PODRL_POD7m 0x80 -//#define PPG_NDRH __PORT8 0xFFFE2C /* Next data register H */ /* Use when group2 and group3 have the same output trigger selected */ +//#define PPG_NDRH __PORT8 0xFFFFFE2C /* Next data register H */ /* Use when group2 and group3 have the same output trigger selected */ #define NDRH_NDR8m 0x01 /* Use for group2 if group3 have different output triger to group2 */ #define NDRH_NDR9m 0x02 #define NDRH_NDR10m 0x04 @@ -785,7 +785,7 @@ #define NDRH_NDR13m 0x20 #define NDRH_NDR14m 0x40 #define NDRH_NDR15m 0x80 -//#define PPG_NDRL __PORT8 0xFFFE2D /* Next data register L */ /* Use when group2 and group3 have the same output trigger selected */ +//#define PPG_NDRL __PORT8 0xFFFFFE2D /* Next data register L */ /* Use when group2 and group3 have the same output trigger selected */ #define NDRL_NDR0m 0x01 /* Use for group2 if group3 have different output triger to group2 */ #define NDRL_NDR1m 0x02 #define NDRL_NDR2m 0x04 @@ -794,18 +794,18 @@ #define NDRL_NDR5m 0x20 #define NDRL_NDR6m 0x40 #define NDRL_NDR7m 0x80 -//#define PPG_NDRH __PORT8 0xFFFE2E /* Next Data Register H */ /* Use for group3 if group2 and group3 have different triggers */ +//#define PPG_NDRH __PORT8 0xFFFFFE2E /* Next Data Register H */ /* Use for group3 if group2 and group3 have different triggers */ #define NDRH_NDR8m 0x01 #define NDRH_NDR9m 0x02 #define NDRH_NDR10m 0x04 #define NDRH_NDR11m 0x08 -//#define PPG_NDRL __PORT8 0xFFFE2F /* Next Data Register L */ /* Use for group3 if group2 and group3 have different triggers */ +//#define PPG_NDRL __PORT8 0xFFFFFE2F /* Next Data Register L */ /* Use for group3 if group2 and group3 have different triggers */ #define NDRL_NDR0m 0x01 #define NDRL_NDR1m 0x02 #define NDRL_NDR2m 0x04 #define NDRL_NDR3m 0x08 /* Module Port */ -#define DIO_P1DDR __PORT8 0xFFFE30 /* DIO 1 Data Direction Register */ +#define DIO_P1DDR __PORT8 0xFFFFFE30 /* DIO 1 Data Direction Register */ #define P1DDR_P10DDRm 0x01 #define P1DDR_P11DDRm 0x02 #define P1DDR_P12DDRm 0x04 @@ -814,19 +814,19 @@ #define P1DDR_P15DDRm 0x20 #define P1DDR_P16DDRm 0x40 #define P1DDR_P17DDRm 0x80 -#define DIO_P3DDR __PORT8 0xFFFE32 /* DIO 3 Data Direction Register */ +#define DIO_P3DDR __PORT8 0xFFFFFE32 /* DIO 3 Data Direction Register */ #define P3DDR_P30DDRm 0x01 #define P3DDR_P31DDRm 0x02 #define P3DDR_P32DDRm 0x04 #define P3DDR_P33DDRm 0x08 #define P3DDR_P34DDRm 0x10 #define P3DDR_P35DDRm 0x20 -#define DIO_PADDR __PORT8 0xFFFE39 /* DIO A Data Direction Register */ +#define DIO_PADDR __PORT8 0xFFFFFE39 /* DIO A Data Direction Register */ #define PADDR_PA0DDRm 0x01 #define PADDR_PA1DDRm 0x02 #define PADDR_PA2DDRm 0x04 #define PADDR_PA3DDRm 0x08 -#define DIO_PBDDR __PORT8 0xFFFE3A /* DIO B Data Direction Register */ +#define DIO_PBDDR __PORT8 0xFFFFFE3A /* DIO B Data Direction Register */ #define PBDDR_PB0DDRm 0x01 #define PBDDR_PB1DDRm 0x02 #define PBDDR_PB2DDRm 0x04 @@ -835,7 +835,7 @@ #define PBDDR_PB5DDRm 0x20 #define PBDDR_PB6DDRm 0x40 #define PBDDR_PB7DDRm 0x80 -#define DIO_PCDDR __PORT8 0xFFFE3B /* DIO C Data Direction Register */ +#define DIO_PCDDR __PORT8 0xFFFFFE3B /* DIO C Data Direction Register */ #define PCDDR_PC0DDRm 0x01 #define PCDDR_PC1DDRm 0x02 #define PCDDR_PC2DDRm 0x04 @@ -844,7 +844,7 @@ #define PCDDR_PC5DDRm 0x20 #define PCDDR_PC6DDRm 0x40 #define PCDDR_PC7DDRm 0x80 -#define DIO_PDDDR __PORT8 0xFFFE3C /* DIO D Data Direction Register */ +#define DIO_PDDDR __PORT8 0xFFFFFE3C /* DIO D Data Direction Register */ #define PDDDR_PD0DDRm 0x01 #define PDDDR_PD1DDRm 0x02 #define PDDDR_PD2DDRm 0x04 @@ -853,7 +853,7 @@ #define PDDDR_PD5DDRm 0x20 #define PDDDR_PD6DDRm 0x40 #define PDDDR_PD7DDRm 0x80 -#define DIO_PEDDR __PORT8 0xFFFE3D /* DIO E Data Direction Register */ +#define DIO_PEDDR __PORT8 0xFFFFFE3D /* DIO E Data Direction Register */ #define PEDDR_PE0DDRm 0x01 #define PEDDR_PE1DDRm 0x02 #define PEDDR_PE2DDRm 0x04 @@ -862,19 +862,19 @@ #define PEDDR_PE5DDRm 0x20 #define PEDDR_PE6DDRm 0x40 #define PEDDR_PE7DDRm 0x80 -#define DIO_PFDDR __PORT8 0xFFFE3E /* DIO F Data Direction Register */ +#define DIO_PFDDR __PORT8 0xFFFFFE3E /* DIO F Data Direction Register */ #define PFDDR_PF0DDRm 0x01 #define PFDDR_PF3DDRm 0x08 #define PFDDR_PF4DDRm 0x10 #define PFDDR_PF5DDRm 0x20 #define PFDDR_PF6DDRm 0x40 #define PFDDR_PF7DDRm 0x80 -#define DIO_PAPCR __PORT8 0xFFFE40 /* DIO A MOS Pull-Up Control Register */ +#define DIO_PAPCR __PORT8 0xFFFFFE40 /* DIO A MOS Pull-Up Control Register */ #define PAPCR_PA0PCRm 0x01 #define PAPCR_PA1PCRm 0x02 #define PAPCR_PA2PCRm 0x04 #define PAPCR_PA3PCRm 0x08 -#define DIO_PBPCR __PORT8 0xFFFE41 /* DIO B MOS Pull-Up Control Register */ +#define DIO_PBPCR __PORT8 0xFFFFFE41 /* DIO B MOS Pull-Up Control Register */ #define PBPCR_PB0PCRm 0x01 #define PBPCR_PB1PCRm 0x02 #define PBPCR_PB2PCRm 0x04 @@ -883,7 +883,7 @@ #define PBPCR_PB5PCRm 0x20 #define PBPCR_PB6PCRm 0x40 #define PBPCR_PB7PCRm 0x80 -#define DIO_PCPCR __PORT8 0xFFFE42 /* DIO C MOS Pull-Up Control Register */ +#define DIO_PCPCR __PORT8 0xFFFFFE42 /* DIO C MOS Pull-Up Control Register */ #define PCPCR_PC0PCRm 0x01 #define PCPCR_PC1PCRm 0x02 #define PCPCR_PC2PCRm 0x04 @@ -892,7 +892,7 @@ #define PCPCR_PC5PCRm 0x20 #define PCPCR_PC6PCRm 0x40 #define PCPCR_PC7PCRm 0x80 -#define DIO_PDPCR __PORT8 0xFFFE43 /* DIO D MOS Pull-Up Control Register */ +#define DIO_PDPCR __PORT8 0xFFFFFE43 /* DIO D MOS Pull-Up Control Register */ #define PDPCR_PD0PCRm 0x01 #define PDPCR_PD1PCRm 0x02 #define PDPCR_PD2PCRm 0x04 @@ -901,7 +901,7 @@ #define PDPCR_PD5PCRm 0x20 #define PDPCR_PD6PCRm 0x40 #define PDPCR_PD7PCRm 0x80 -#define DIO_PEPCR __PORT8 0xFFFE44 /* DIO E MOS Pull-Up Control Register */ +#define DIO_PEPCR __PORT8 0xFFFFFE44 /* DIO E MOS Pull-Up Control Register */ #define PEPCR_PE0PCRm 0x01 #define PEPCR_PE1PCRm 0x02 #define PEPCR_PE2PCRm 0x04 @@ -910,19 +910,19 @@ #define PEPCR_PE5PCRm 0x20 #define PEPCR_PE6PCRm 0x40 #define PEPCR_PE7PCRm 0x80 -#define DIO_P3ODR __PORT8 0xFFFE46 /* DIO 3 Open Drain Control Register */ +#define DIO_P3ODR __PORT8 0xFFFFFE46 /* DIO 3 Open Drain Control Register */ #define P3ODR_P30ODRm 0x01 #define P3ODR_P31ODRm 0x02 #define P3ODR_P32ODRm 0x04 #define P3ODR_P33ODRm 0x08 #define P3ODR_P34ODRm 0x10 #define P3ODR_P35ODRm 0x20 -#define DIO_PAODR __PORT8 0xFFFE47 /* DIO A Open Drain Control Register */ +#define DIO_PAODR __PORT8 0xFFFFFE47 /* DIO A Open Drain Control Register */ #define PAODR_PA0ODRm 0x01 #define PAODR_PA1ODRm 0x02 #define PAODR_PA2ODRm 0x04 #define PAODR_PA3ODRm 0x08 -#define DIO_PBODR __PORT8 0xFFFE48 /* DIO B Open Drain Control Register */ +#define DIO_PBODR __PORT8 0xFFFFFE48 /* DIO B Open Drain Control Register */ #define PBODR_PB0ODRm 0x01 #define PBODR_PB1ODRm 0x02 #define PBODR_PB2ODRm 0x04 @@ -931,7 +931,7 @@ #define PBODR_PB5ODRm 0x20 #define PBODR_PB6ODRm 0x40 #define PBODR_PB7ODRm 0x80 -#define DIO_PCODR __PORT8 0xFFFE49 /* DIO C Open Drain Control Register */ +#define DIO_PCODR __PORT8 0xFFFFFE49 /* DIO C Open Drain Control Register */ #define PCODR_PC0ODRm 0x01 #define PCODR_PC1ODRm 0x02 #define PCODR_PC2ODRm 0x04 @@ -941,7 +941,7 @@ #define PCODR_PC6ODRm 0x40 #define PCODR_PC7ODRm 0x80 /* Module Time pulse unit */ -#define TPU_TCR3 __PORT8 0xFFFE80 /* Timer Control Register 3 */ +#define TPU_TCR3 __PORT8 0xFFFFFE80 /* Timer Control Register 3 */ #define TCR3_TPSC0m 0x01 #define TCR3_TPSC1m 0x02 #define TCR3_TPSC2m 0x04 @@ -950,14 +950,14 @@ #define TCR3_CCLR0m 0x20 #define TCR3_CCLR1m 0x40 #define TCR3_CCLR2m 0x80 -#define TPU_TMDR3 __PORT8 0xFFFE81 /* Timer Mode Register 3 */ +#define TPU_TMDR3 __PORT8 0xFFFFFE81 /* Timer Mode Register 3 */ #define TMDR3_MD0m 0x01 #define TMDR3_MD1m 0x02 #define TMDR3_MD2m 0x04 #define TMDR3_MD3m 0x08 #define TMDR3_BFAm 0x10 #define TMDR3_BFBm 0x20 -#define TPU_TIOR3H __PORT8 0xFFFE82 /* Timer IO Control Register 3H */ +#define TPU_TIOR3H __PORT8 0xFFFFFE82 /* Timer IO Control Register 3H */ #define TIOR3H_IOA0m 0x01 #define TIOR3H_IOA1m 0x02 #define TIOR3H_IOA2m 0x04 @@ -966,7 +966,7 @@ #define TIOR3H_IOB1m 0x20 #define TIOR3H_IOB2m 0x40 #define TIOR3H_IOB3m 0x80 -#define TPU_TIOR3L __PORT8 0xFFFE83 /* Timer IO Control Register 3L */ +#define TPU_TIOR3L __PORT8 0xFFFFFE83 /* Timer IO Control Register 3L */ #define TIOR3L_IOC0m 0x01 #define TIOR3L_IOC1m 0x02 #define TIOR3L_IOC2m 0x04 @@ -975,25 +975,25 @@ #define TIOR3L_IOD1m 0x20 #define TIOR3L_IOD2m 0x40 #define TIOR3L_IOD3m 0x80 -#define TPU_TIER3 __PORT8 0xFFFE84 /* -Timer INT Enable Register 3 */ +#define TPU_TIER3 __PORT8 0xFFFFFE84 /* -Timer INT Enable Register 3 */ #define TIER3_TGIEAm 0x01 #define TIER3_TGIEBm 0x02 #define TIER3_TGIECm 0x04 #define TIER3_TGIEDm 0x08 #define TIER3_TCIEVm 0x10 #define TIER3_TTGEm 0x80 -#define TPU_TSR3 __PORT8 0xFFFE85 /* Timer Status Register 3 */ +#define TPU_TSR3 __PORT8 0xFFFFFE85 /* Timer Status Register 3 */ #define TSR3_TGFAm 0x01 #define TSR3_TGFBm 0x02 #define TSR3_TGFCm 0x04 #define TSR3_TGFDm 0x08 #define TSR3_TCFVm 0x10 -#define TPU_TCNT3 __PORT16 0xFFFE86 /* Timer Counter 3 */ -#define TPU_TGR3A __PORT16 0xFFFE88 /* Timer General Register 3A */ -#define TPU_TGR3B __PORT16 0xFFFE8A /* Timer General Register 3B */ -#define TPU_TGR3C __PORT16 0xFFFE8C /* Timer General Register 3C */ -#define TPU_TGR3D __PORT16 0xFFFE8E /* Timer General Register 3D */ -#define TPU_TCR4 __PORT8 0xFFFE90 /* Timer Control Register 4 */ +#define TPU_TCNT3 __PORT16 0xFFFFFE86 /* Timer Counter 3 */ +#define TPU_TGR3A __PORT16 0xFFFFFE88 /* Timer General Register 3A */ +#define TPU_TGR3B __PORT16 0xFFFFFE8A /* Timer General Register 3B */ +#define TPU_TGR3C __PORT16 0xFFFFFE8C /* Timer General Register 3C */ +#define TPU_TGR3D __PORT16 0xFFFFFE8E /* Timer General Register 3D */ +#define TPU_TCR4 __PORT8 0xFFFFFE90 /* Timer Control Register 4 */ #define TCR4_TPSC0m 0x01 #define TCR4_TPSC1m 0x02 #define TCR4_TPSC2m 0x04 @@ -1001,12 +1001,12 @@ #define TCR4_CKEG1m 0x10 #define TCR4_CCLR0m 0x20 #define TCR4_CCLR1m 0x40 -#define TPU_TMDR4 __PORT8 0xFFFE91 /* Timer Mode Register 4 */ +#define TPU_TMDR4 __PORT8 0xFFFFFE91 /* Timer Mode Register 4 */ #define TMDR4_MD0m 0x01 #define TMDR4_MD1m 0x02 #define TMDR4_MD2m 0x04 #define TMDR4_MD3m 0x08 -#define TPU_TIOR4 __PORT8 0xFFFE92 /* Timer IO Control Register 4 */ +#define TPU_TIOR4 __PORT8 0xFFFFFE92 /* Timer IO Control Register 4 */ #define TIOR4_IOA0m 0x01 #define TIOR4_IOA1m 0x02 #define TIOR4_IOA2m 0x04 @@ -1015,22 +1015,22 @@ #define TIOR4_IOB1m 0x20 #define TIOR4_IOB2m 0x40 #define TIOR4_IOB3m 0x80 -#define TPU_TIER4 __PORT8 0xFFFE94 /* Timer INT Enable Register 4 */ +#define TPU_TIER4 __PORT8 0xFFFFFE94 /* Timer INT Enable Register 4 */ #define TIER4_TGIEAm 0x01 #define TIER4_TGIEBm 0x02 #define TIER4_TCIEVm 0x10 #define TIER4_TCIEUm 0x20 #define TIER4_TTGEm 0x80 -#define TPU_TSR4 __PORT8 0xFFFE95 /* Timer Status Register 4 */ +#define TPU_TSR4 __PORT8 0xFFFFFE95 /* Timer Status Register 4 */ #define TSR4_TGFAm 0x01 #define TSR4_TGFBm 0x02 #define TSR4_TCFVm 0x10 #define TSR4_TCFUm 0x20 #define TSR4_TCFDm 0x80 -#define TPU_TCNT4 __PORT16 0xFFFE96 /* Timer Counter 4 */ -#define TPU_TGR4A __PORT16 0xFFFE98 /* Timer General Register 4A */ -#define TPU_TGR4B __PORT16 0xFFFE9A /* Timer General Register 4B */ -#define TPU_TCR5 __PORT8 0xFFFEA0 /* Timer Control Register 5 */ +#define TPU_TCNT4 __PORT16 0xFFFFFE96 /* Timer Counter 4 */ +#define TPU_TGR4A __PORT16 0xFFFFFE98 /* Timer General Register 4A */ +#define TPU_TGR4B __PORT16 0xFFFFFE9A /* Timer General Register 4B */ +#define TPU_TCR5 __PORT8 0xFFFFFEA0 /* Timer Control Register 5 */ #define TCR5_TPSC0m 0x01 #define TCR5_TPSC1m 0x02 #define TCR5_TPSC2m 0x04 @@ -1038,9 +1038,9 @@ #define TCR5_CKEG1m 0x10 #define TCR5_CCLR0m 0x20 #define TCR5_CCLR1m 0x40 -#define TPU_TMDR5 __PORT8 0xFFFEA1 /* Timer Mode Register 5 */ +#define TPU_TMDR5 __PORT8 0xFFFFFEA1 /* Timer Mode Register 5 */ -#define TPU_TIOR5 __PORT8 0xFFFEA2 /* Timer IO Control Register 5 */ +#define TPU_TIOR5 __PORT8 0xFFFFFEA2 /* Timer IO Control Register 5 */ #define TIOR5_IOA0m 0x01 #define TIOR5_IOA1m 0x02 #define TIOR5_IOA2m 0x04 @@ -1049,29 +1049,29 @@ #define TIOR5_IOB1m 0x20 #define TIOR5_IOB2m 0x40 #define TIOR5_IOB3m 0x80 -#define TPU_TIER5 __PORT8 0xFFFEA4 /* Timer INT Enable Register 5 */ +#define TPU_TIER5 __PORT8 0xFFFFFEA4 /* Timer INT Enable Register 5 */ #define TIER5_TGIEAm 0x01 #define TIER5_TGIEBm 0x02 #define TIER5_TCIEVm 0x10 #define TIER5_TCIEUm 0x20 #define TIER5_TTGEm 0x80 -#define TPU_TSR5 __PORT8 0xFFFEA5 /* Timer Status Register 5 */ +#define TPU_TSR5 __PORT8 0xFFFFFEA5 /* Timer Status Register 5 */ #define TSR5_TGFAm 0x01 #define TSR5_TGFBm 0x02 #define TSR5_TCFVm 0x10 #define TSR5_TCFUm 0x20 #define TSR5_TCFDm 0x80 -#define TPU_TCNT5 __PORT16 0xFFFEA6 /* Timer Counter 5 */ -#define TPU_TGR5A __PORT16 0xFFFEA8 /* Timer General Register 5A */ -#define TPU_TGR5B __PORT16 0xFFFEAA /* Timer General Register 5B */ -#define TPU_TSTR __PORT8 0xFFFEB0 /* Timer Start Register */ +#define TPU_TCNT5 __PORT16 0xFFFFFEA6 /* Timer Counter 5 */ +#define TPU_TGR5A __PORT16 0xFFFFFEA8 /* Timer General Register 5A */ +#define TPU_TGR5B __PORT16 0xFFFFFEAA /* Timer General Register 5B */ +#define TPU_TSTR __PORT8 0xFFFFFEB0 /* Timer Start Register */ #define TSTR_CST0m 0x01 #define TSTR_CST1m 0x02 #define TSTR_CST2m 0x04 #define TSTR_CST3m 0x08 #define TSTR_CST4m 0x10 #define TSTR_CST5m 0x20 -#define TPU_TSYR __PORT8 0xFFFEB1 /* Timer Synchro Register */ +#define TPU_TSYR __PORT8 0xFFFFFEB1 /* Timer Synchro Register */ #define TSYR_SYNC0m 0x01 #define TSYR_SYNC1m 0x02 #define TSYR_SYNC2m 0x04 @@ -1079,68 +1079,68 @@ #define TSYR_SYNC4m 0x10 #define TSYR_SYNC5m 0x20 /* Module Interrupt */ -#define INT_IPRA __PORT8 0xFFFEC0 /* Interrupt Priority Register A */ +#define INT_IPRA __PORT8 0xFFFFFEC0 /* Interrupt Priority Register A */ #define IPRA_IPR0m 0x01 #define IPRA_IPR1m 0x02 #define IPRA_IPR2m 0x04 #define IPRA_IPR4m 0x10 #define IPRA_IPR5m 0x20 #define IPRA_IPR6m 0x40 -#define INT_IPRB __PORT8 0xFFFEC1 /* Interrupt Priority Register B */ +#define INT_IPRB __PORT8 0xFFFFFEC1 /* Interrupt Priority Register B */ #define IPRB_IPR0m 0x01 #define IPRB_IPR1m 0x02 #define IPRB_IPR2m 0x04 #define IPRB_IPR4m 0x10 #define IPRB_IPR5m 0x20 #define IPRB_IPR6m 0x40 -#define INT_IPRC __PORT8 0xFFFEC2 /* Interrupt Priority Register C */ +#define INT_IPRC __PORT8 0xFFFFFEC2 /* Interrupt Priority Register C */ #define IPRC_IPR0m 0x01 #define IPRC_IPR1m 0x02 #define IPRC_IPR2m 0x04 -#define INT_IPRD __PORT8 0xFFFEC3 /* Interrupt Priority Register D */ +#define INT_IPRD __PORT8 0xFFFFFEC3 /* Interrupt Priority Register D */ #define IPRD_IPR4m 0x10 #define IPRD_IPR5m 0x20 #define IPRD_IPR6m 0x40 -#define INT_IPRE __PORT8 0xFFFEC4 /* Interrupt Priority Register E */ +#define INT_IPRE __PORT8 0xFFFFFEC4 /* Interrupt Priority Register E */ #define IPRE_IPR0m 0x01 #define IPRE_IPR1m 0x02 #define IPRE_IPR2m 0x04 #define IPRE_IPR4m 0x10 #define IPRE_IPR5m 0x20 #define IPRE_IPR6m 0x40 -#define INT_IPRF __PORT8 0xFFFEC5 /* Interrupt Priority Register F */ +#define INT_IPRF __PORT8 0xFFFFFEC5 /* Interrupt Priority Register F */ #define IPRF_IPR0m 0x01 #define IPRF_IPR1m 0x02 #define IPRF_IPR2m 0x04 #define IPRF_IPR4m 0x10 #define IPRF_IPR5m 0x20 #define IPRF_IPR6m 0x40 -#define INT_IPRG __PORT8 0xFFFEC6 /* Interrupt Priority Register G */ +#define INT_IPRG __PORT8 0xFFFFFEC6 /* Interrupt Priority Register G */ #define IPRG_IPR0m 0x01 #define IPRG_IPR1m 0x02 #define IPRG_IPR2m 0x04 #define IPRG_IPR4m 0x10 #define IPRG_IPR5m 0x20 #define IPRG_IPR6m 0x40 -#define INT_IPRH __PORT8 0xFFFEC7 /* Interrupt Priority Register H */ +#define INT_IPRH __PORT8 0xFFFFFEC7 /* Interrupt Priority Register H */ #define IPRH_IPR0m 0x01 #define IPRH_IPR1m 0x02 #define IPRH_IPR2m 0x04 #define IPRH_IPR4m 0x10 #define IPRH_IPR5m 0x20 #define IPRH_IPR6m 0x40 -#define INT_IPRJ __PORT8 0xFFFEC9 /* Interrupt Priority Register J */ +#define INT_IPRJ __PORT8 0xFFFFFEC9 /* Interrupt Priority Register J */ #define IPRJ_IPR0m 0x01 #define IPRJ_IPR1m 0x02 #define IPRJ_IPR2m 0x04 -#define INT_IPRK __PORT8 0xFFFECA /* Interrupt Priority Register K */ +#define INT_IPRK __PORT8 0xFFFFFECA /* Interrupt Priority Register K */ #define IPRK_IPR0m 0x01 #define IPRK_IPR1m 0x02 #define IPRK_IPR2m 0x04 #define IPRK_IPR4m 0x10 #define IPRK_IPR5m 0x20 #define IPRK_IPR6m 0x40 -#define INT_IPRM __PORT8 0xFFFECC /* Interrupt Priority Register M */ +#define INT_IPRM __PORT8 0xFFFFFECC /* Interrupt Priority Register M */ #define IPRM_IPR0m 0x01 #define IPRM_IPR1m 0x02 #define IPRM_IPR2m 0x04 @@ -1148,7 +1148,7 @@ #define IPRM_IPR5m 0x20 #define IPRM_IPR6m 0x40 /* Module BUS controler */ -#define BUS_ABWCR __PORT8 0xFFFED0 /* Bus Width Control Register */ +#define BUS_ABWCR __PORT8 0xFFFFFED0 /* Bus Width Control Register */ #define ABWCR_ABW0m 0x01 #define ABWCR_ABW1m 0x02 #define ABWCR_ABW2m 0x04 @@ -1157,7 +1157,7 @@ #define ABWCR_ABW5m 0x20 #define ABWCR_ABW6m 0x40 #define ABWCR_ABW7m 0x80 -#define BUS_ASTCR __PORT8 0xFFFED1 /* Access State Control Register */ +#define BUS_ASTCR __PORT8 0xFFFFFED1 /* Access State Control Register */ #define ASTCR_AST0m 0x01 #define ASTCR_AST1m 0x02 #define ASTCR_AST2m 0x04 @@ -1166,7 +1166,7 @@ #define ASTCR_AST5m 0x20 #define ASTCR_AST6m 0x40 #define ASTCR_AST7m 0x80 -#define BUS_WCRH __PORT8 0xFFFED2 /* Wait Control Register H */ +#define BUS_WCRH __PORT8 0xFFFFFED2 /* Wait Control Register H */ #define WCRH_W40m 0x01 #define WCRH_W41m 0x02 #define WCRH_W50m 0x04 @@ -1175,7 +1175,7 @@ #define WCRH_W61m 0x20 #define WCRH_W70m 0x40 #define WCRH_W71m 0x80 -#define BUS_WCRL __PORT8 0xFFFED3 /* Wait Control Register L */ +#define BUS_WCRL __PORT8 0xFFFFFED3 /* Wait Control Register L */ #define WCRL_W00m 0x01 #define WCRL_W01m 0x02 #define WCRL_W10m 0x04 @@ -1184,16 +1184,16 @@ #define WCRL_W21m 0x20 #define WCRL_W30m 0x40 #define WCRL_W31m 0x80 -#define BUS_BCRH __PORT8 0xFFFED4 /* Bus Control Register H */ +#define BUS_BCRH __PORT8 0xFFFFFED4 /* Bus Control Register H */ #define BCRH_BRSTS0m 0x08 #define BCRH_BRSTS1m 0x10 #define BCRH_BRSTRMm 0x20 #define BCRH_ICIS0m 0x40 #define BCRH_ICIS1m 0x80 -#define BUS_BCRL __PORT8 0xFFFED5 /* Bus Control Register L */ +#define BUS_BCRL __PORT8 0xFFFFFED5 /* Bus Control Register L */ #define BCRL_WDBEm 0x02 /* Module Flash */ -#define FLM_RAMER __PORT8 0xFFFEDB /* RAM Emulation Register */ +#define FLM_RAMER __PORT8 0xFFFFFEDB /* RAM Emulation Register */ #define RAMER_RAM0m 0x01 #define RAMER_RAM1m 0x02 #define RAMER_RAM2m 0x04 @@ -1201,7 +1201,7 @@ #define RAMER_RAMSm 0x08 /* Module Port */ -#define DIO_P1DR __PORT8 0xFFFF00 /* DIO 1 Data Register */ +#define DIO_P1DR __PORT8 0xFFFFFF00 /* DIO 1 Data Register */ #define P1DR_P10DRm 0x01 #define P1DR_P11DRm 0x02 #define P1DR_P12DRm 0x04 @@ -1210,19 +1210,19 @@ #define P1DR_P15DRm 0x20 #define P1DR_P16DRm 0x40 #define P1DR_P17DRm 0x80 -#define DIO_P3DR __PORT8 0xFFFF02 /* DIO 3 Data Register */ +#define DIO_P3DR __PORT8 0xFFFFFF02 /* DIO 3 Data Register */ #define P3DR_P30DRm 0x01 #define P3DR_P31DRm 0x02 #define P3DR_P32DRm 0x04 #define P3DR_P33DRm 0x08 #define P3DR_P34DRm 0x10 #define P3DR_P35DRm 0x20 -#define DIO_PADR __PORT8 0xFFFF09 /* DIO A Data Register */ +#define DIO_PADR __PORT8 0xFFFFFF09 /* DIO A Data Register */ #define PADR_PA0DRm 0x01 #define PADR_PA1DRm 0x02 #define PADR_PA2DRm 0x04 #define PADR_PA3DRm 0x08 -#define DIO_PBDR __PORT8 0xFFFF0A /* DIO B Data Register */ +#define DIO_PBDR __PORT8 0xFFFFFF0A /* DIO B Data Register */ #define PBDR_PB0DRm 0x01 #define PBDR_PB1DRm 0x02 #define PBDR_PB2DRm 0x04 @@ -1231,7 +1231,7 @@ #define PBDR_PB5DRm 0x20 #define PBDR_PB6DRm 0x40 #define PBDR_PB7DRm 0x80 -#define DIO_PCDR __PORT8 0xFFFF0B /* DIO C Data Register */ +#define DIO_PCDR __PORT8 0xFFFFFF0B /* DIO C Data Register */ #define PCDR_PC0DRm 0x01 #define PCDR_PC1DRm 0x02 #define PCDR_PC2DRm 0x04 @@ -1240,7 +1240,7 @@ #define PCDR_PC5DRm 0x20 #define PCDR_PC6DRm 0x40 #define PCDR_PC7DRm 0x80 -#define DIO_PDDR __PORT8 0xFFFF0C /* DIO D Data Register */ +#define DIO_PDDR __PORT8 0xFFFFFF0C /* DIO D Data Register */ #define PDDR_PD0DRm 0x01 #define PDDR_PD1DRm 0x02 #define PDDR_PD2DRm 0x04 @@ -1249,7 +1249,7 @@ #define PDDR_PD5DRm 0x20 #define PDDR_PD6DRm 0x40 #define PDDR_PD7DRm 0x80 -#define DIO_PEDR __PORT8 0xFFFF0D /* DIO E Data Register */ +#define DIO_PEDR __PORT8 0xFFFFFF0D /* DIO E Data Register */ #define PEDR_PE0DRm 0x01 #define PEDR_PE1DRm 0x02 #define PEDR_PE2DRm 0x04 @@ -1258,7 +1258,7 @@ #define PEDR_PE5DRm 0x20 #define PEDR_PE6DRm 0x40 #define PEDR_PE7DRm 0x80 -#define DIO_PFDR __PORT8 0xFFFF0E /* DIO F Data Register */ +#define DIO_PFDR __PORT8 0xFFFFFF0E /* DIO F Data Register */ #define PFDR_PF0DRm 0x01 #define PFDR_PF1DRm 0x02 #define PFDR_PF2DRm 0x04 @@ -1269,7 +1269,7 @@ #define PFDR_PF7DRm 0x80 /* Module Time pulse unit */ //see other definitions at the end of the file -#define TPU_TCR0 __PORT8 0xFFFF10 /* Timer Control Register 0 */ +#define TPU_TCR0 __PORT8 0xFFFFFF10 /* Timer Control Register 0 */ #define TCR0_TPSC0m 0x01 #define TCR0_TPSC1m 0x02 #define TCR0_TPSC2m 0x04 @@ -1278,14 +1278,14 @@ #define TCR0_CCLR0m 0x20 #define TCR0_CCLR1m 0x40 #define TCR0_CCLR2m 0x80 -#define TPU_TMDR0 __PORT8 0xFFFF11 /* Timer Mode Register 0 */ +#define TPU_TMDR0 __PORT8 0xFFFFFF11 /* Timer Mode Register 0 */ #define TMDR0_MD0m 0x01 #define TMDR0_MD1m 0x02 #define TMDR0_MD2m 0x04 #define TMDR0_MD3m 0x08 #define TMDR0_BFAm 0x10 #define TMDR0_BFBm 0x20 -#define TPU_TIOR0H __PORT8 0xFFFF12 /* Timer IO Control Register 0H */ +#define TPU_TIOR0H __PORT8 0xFFFFFF12 /* Timer IO Control Register 0H */ #define TIOR0H_IOA0m 0x01 #define TIOR0H_IOA1m 0x02 #define TIOR0H_IOA2m 0x04 @@ -1294,7 +1294,7 @@ #define TIOR0H_IOB1m 0x20 #define TIOR0H_IOB2m 0x40 #define TIOR0H_IOB3m 0x80 -#define TPU_TIOR0L __PORT8 0xFFFF13 /* Timer IO Control Register 0L */ +#define TPU_TIOR0L __PORT8 0xFFFFFF13 /* Timer IO Control Register 0L */ #define TIOR0L_IOC0m 0x01 #define TIOR0L_IOC1m 0x02 #define TIOR0L_IOC2m 0x04 @@ -1303,29 +1303,29 @@ #define TIOR0L_IOD1m 0x20 #define TIOR0L_IOD2m 0x40 #define TIOR0L_IOD3m 0x80 -#define TPU_TIER0 __PORT8 0xFFFF14 /* Timer INT Enable Register 0 */ +#define TPU_TIER0 __PORT8 0xFFFFFF14 /* Timer INT Enable Register 0 */ #define TIER0_TGIEAm 0x01 #define TIER0_TGIEBm 0x02 #define TIER0_TGIECm 0x04 #define TIER0_TGIEDm 0x08 #define TIER0_TCIEVm 0x10 #define TIER0_TTGEm 0x80 -#define TPU_TSR0 __PORT8 0xFFFF15 /* Timer Status Register 0 */ +#define TPU_TSR0 __PORT8 0xFFFFFF15 /* Timer Status Register 0 */ #define TSR0_TGFAm 0x01 #define TSR0_TGFBm 0x02 #define TSR0_TGFCm 0x04 #define TSR0_TGFDm 0x08 #define TSR0_TCFVm 0x10 -#define TPU_TCNT0 __PORT16 0xFFFF16 /* Timer Counter 0 */ -#define TPU_TGR0A __PORT16 0xFFFF18 /* Timer General Register 0A */ -#define TPU_TGR0B __PORT16 0xFFFF1A /* Timer General Register 0B */ +#define TPU_TCNT0 __PORT16 0xFFFFFF16 /* Timer Counter 0 */ +#define TPU_TGR0A __PORT16 0xFFFFFF18 /* Timer General Register 0A */ +#define TPU_TGR0B __PORT16 0xFFFFFF1A /* Timer General Register 0B */ #define by_standbym 0x02 #define data_tom 0x02 #define data_tom 0x02 #define to_slavem 0x02 -#define TPU_TGR0C __PORT16 0xFFFF1C /* Timer General Register 0C */ -#define TPU_TGR0D __PORT16 0xFFFF1E /* Timer General Register 0D */ -#define TPU_TCR1 __PORT8 0xFFFF20 /* Timer Control Register 1 */ +#define TPU_TGR0C __PORT16 0xFFFFFF1C /* Timer General Register 0C */ +#define TPU_TGR0D __PORT16 0xFFFFFF1E /* Timer General Register 0D */ +#define TPU_TCR1 __PORT8 0xFFFFFF20 /* Timer Control Register 1 */ #define TCR1_TPSC0m 0x01 #define TCR1_TPSC1m 0x02 #define TCR1_TPSC2m 0x04 @@ -1333,12 +1333,12 @@ #define TCR1_CKEG1m 0x10 #define TCR1_CCLR0m 0x20 #define TCR1_CCLR1m 0x40 -#define TPU_TMDR1 __PORT8 0xFFFF21 /* Timer Mode Register 1 */ +#define TPU_TMDR1 __PORT8 0xFFFFFF21 /* Timer Mode Register 1 */ #define TMDR1_MD0m 0x01 #define TMDR1_MD1m 0x02 #define TMDR1_MD2m 0x04 #define TMDR1_MD3m 0x08 -#define TPU_TIOR1 __PORT8 0xFFFF22 /* Timer IO Control Register 1 */ +#define TPU_TIOR1 __PORT8 0xFFFFFF22 /* Timer IO Control Register 1 */ #define TIOR1_IOA0m 0x01 #define TIOR1_IOA1m 0x02 #define TIOR1_IOA2m 0x04 @@ -1347,22 +1347,22 @@ #define TIOR1_IOB1m 0x20 #define TIOR1_IOB2m 0x40 #define TIOR1_IOB3m 0x80 -#define TPU_TIER1 __PORT8 0xFFFF24 /* Timer INT Enable Register 1 */ +#define TPU_TIER1 __PORT8 0xFFFFFF24 /* Timer INT Enable Register 1 */ #define TIER1_TGIEAm 0x01 #define TIER1_TGIEBm 0x02 #define TIER1_TCIEVm 0x10 #define TIER1_TCIEUm 0x20 #define TIER1_TTGEm 0x80 -#define TPU_TSR1 __PORT8 0xFFFF25 /* Timer Status Register 1 */ +#define TPU_TSR1 __PORT8 0xFFFFFF25 /* Timer Status Register 1 */ #define TSR1_TGFAm 0x01 #define TSR1_TGFBm 0x02 #define TSR1_TCFVm 0x10 #define TSR1_TCFUm 0x20 #define TSR1_TCFDm 0x80 -#define TPU_TCNT1 __PORT16 0xFFFF26 /* Timer Counter 1 */ -#define TPU_TGR1A __PORT16 0xFFFF28 /* Timer General Register 1A */ -#define TPU_TGR1B __PORT16 0xFFFF2A /* Timer General Register 1B */ -#define TPU_TCR2 __PORT8 0xFFFF30 /* Timer Control Register 2 */ +#define TPU_TCNT1 __PORT16 0xFFFFFF26 /* Timer Counter 1 */ +#define TPU_TGR1A __PORT16 0xFFFFFF28 /* Timer General Register 1A */ +#define TPU_TGR1B __PORT16 0xFFFFFF2A /* Timer General Register 1B */ +#define TPU_TCR2 __PORT8 0xFFFFFF30 /* Timer Control Register 2 */ #define TCR2_TPSC0m 0x01 #define TCR2_TPSC1m 0x02 #define TCR2_TPSC2m 0x04 @@ -1370,12 +1370,12 @@ #define TCR2_CKEG1m 0x10 #define TCR2_CCLR0m 0x20 #define TCR2_CCLR1m 0x40 -#define TPU_TMDR2 __PORT8 0xFFFF31 /* Timer Mode Register 2 */ +#define TPU_TMDR2 __PORT8 0xFFFFFF31 /* Timer Mode Register 2 */ #define TMDR2_MD0m 0x01 #define TMDR2_MD1m 0x02 #define TMDR2_MD2m 0x04 #define TMDR2_MD3m 0x08 -#define TPU_TIOR2 __PORT8 0xFFFF32 /* Timer IO Control Register 2 */ +#define TPU_TIOR2 __PORT8 0xFFFFFF32 /* Timer IO Control Register 2 */ #define TIOR2_IOA0m 0x01 #define TIOR2_IOA1m 0x02 #define TIOR2_IOA2m 0x04 @@ -1384,26 +1384,26 @@ #define TIOR2_IOB1m 0x20 #define TIOR2_IOB2m 0x40 #define TIOR2_IOB3m 0x80 -#define TPU_TIER2 __PORT8 0xFFFF34 /* Timer INT Enable Register 2 */ +#define TPU_TIER2 __PORT8 0xFFFFFF34 /* Timer INT Enable Register 2 */ #define TIER2_TGIEAm 0x01 #define TIER2_TGIEBm 0x02 #define TIER2_TCIEVm 0x10 #define TIER2_TCIEUm 0x20 #define TIER2_TTGEm 0x80 -#define TPU_TSR2 __PORT8 0xFFFF35 /* Timer Status Register 2 */ +#define TPU_TSR2 __PORT8 0xFFFFFF35 /* Timer Status Register 2 */ #define TSR2_TGFAm 0x01 #define TSR2_TGFBm 0x02 #define TSR2_TCFVm 0x10 #define TSR2_TCFUm 0x20 #define TSR2_TCFDm 0x80 -#define TPU_TCNT2 __PORT16 0xFFFF36 /* Timer Counter 2 */ -#define TPU_TGR2A __PORT16 0xFFFF38 /* Timer General Register 2A */ -#define TPU_TGR2B __PORT16 0xFFFF3A /* Timer General Register 2B */ +#define TPU_TCNT2 __PORT16 0xFFFFFF36 /* Timer Counter 2 */ +#define TPU_TGR2A __PORT16 0xFFFFFF38 /* Timer General Register 2A */ +#define TPU_TGR2B __PORT16 0xFFFFFF3A /* Timer General Register 2B */ /* Module Watchdog timer */ /* WDT0 register definitions start */ -#define WDT_WTCSR0r __PORT8 0xFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */ -#define WDT_WTCSR0w __PORT16 0xFFFF74 /* writte address - password 0xa500 */ +#define WDT_WTCSR0r __PORT8 0xFFFFFF74 /* Timer ControlStatus Register 0 (RD/WC7) */ +#define WDT_WTCSR0w __PORT16 0xFFFFFF74 /* writte address - password 0xa500 */ #define WTCSR0_CKS0m 0x01 #define WTCSR0_CKS1m 0x02 #define WTCSR0_CKS2m 0x04 @@ -1411,10 +1411,10 @@ #define WTCSR0_TMEm 0x20 #define WTCSR0_WTITm 0x40 #define WTCSR0_WOVFm 0x80 -#define WDT_WTCNT0r __PORT8 0xFFFF75 /* Timer Counter 0 (RD) */ -#define WDT_WTCNT0w __PORT16 0xFFFF74 /* writte address - password 0x5a00 */ -#define WDT_WRSTCSRr __PORT8 0xFFFF77 /* Reset ControlStatus Register (RD/WC7) */ -#define WDT_WRSTCSRw __PORT16 0xFFFF76 /* clear WOVF - password 0xa500 */ +#define WDT_WTCNT0r __PORT8 0xFFFFFF75 /* Timer Counter 0 (RD) */ +#define WDT_WTCNT0w __PORT16 0xFFFFFF74 /* writte address - password 0x5a00 */ +#define WDT_WRSTCSRr __PORT8 0xFFFFFF77 /* Reset ControlStatus Register (RD/WC7) */ +#define WDT_WRSTCSRw __PORT16 0xFFFFFF76 /* clear WOVF - password 0xa500 */ /* set bits - password 0x5a00 */ #define WRSTCSR_RSTSm 0x20 #define WRSTCSR_RSTEm 0x40 @@ -1503,7 +1503,7 @@ /* SCI common registers and bits end */ -#define SCI_SMR0 __PORT8 0xFFFF78 /* Serial Mode Register 0 */ +#define SCI_SMR0 __PORT8 0xFFFFFF78 /* Serial Mode Register 0 */ #define SMR0_CKS0m 0x01 #define SMR0_CKS1m 0x02 #define SMR0_MPm 0x04 @@ -1512,13 +1512,13 @@ #define SMR0_PEm 0x20 #define SMR0_CHRm 0x40 #define SMR0_CAm 0x80 -#define Smart_SMR0 __PORT8 0xFFFF78 /* Smart Card Mode Register 0 */ -#define IIC_ICCR0 __PORT8 0xFFFF78 /* I2C Bus Control Register */ -#define SCI_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */ -#define Smart_BRR0 __PORT8 0xFFFF79 /* Bit Rate Register 0 */ -#define IIC_ICSR0 __PORT8 0xFFFF79 /* I2C Bus Status Register */ -#define SCI_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */ -#define Smart_SCR0 __PORT8 0xFFFF7A /* Serial Control Register 0 */ +#define Smart_SMR0 __PORT8 0xFFFFFF78 /* Smart Card Mode Register 0 */ +#define IIC_ICCR0 __PORT8 0xFFFFFF78 /* I2C Bus Control Register */ +#define SCI_BRR0 __PORT8 0xFFFFFF79 /* Bit Rate Register 0 */ +#define Smart_BRR0 __PORT8 0xFFFFFF79 /* Bit Rate Register 0 */ +#define IIC_ICSR0 __PORT8 0xFFFFFF79 /* I2C Bus Status Register */ +#define SCI_SCR0 __PORT8 0xFFFFFF7A /* Serial Control Register 0 */ +#define Smart_SCR0 __PORT8 0xFFFFFF7A /* Serial Control Register 0 */ #define SCR0_CKE0m 0x01 #define SCR0_CKE1m 0x02 #define SCR0_TEIEm 0x04 @@ -1527,9 +1527,9 @@ #define SCR0_TEm 0x20 #define SCR0_RIEm 0x40 #define SCR0_TIEm 0x80 -#define SCI_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */ -#define Smart_TDR0 __PORT8 0xFFFF7B /* Transmit Data Register 0 */ -#define SCI_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */ +#define SCI_TDR0 __PORT8 0xFFFFFF7B /* Transmit Data Register 0 */ +#define Smart_TDR0 __PORT8 0xFFFFFF7B /* Transmit Data Register 0 */ +#define SCI_SSR0 __PORT8 0xFFFFFF7C /* Serial Status Register 0 */ #define SSR0_MPBTm 0x01 #define SSR0_MPBm 0x02 #define SSR0_TENDm 0x04 @@ -1538,16 +1538,16 @@ #define SSR0_ORERm 0x20 #define SSR0_RDRFm 0x40 #define SSR0_TDREm 0x80 -#define Smart_SSR0 __PORT8 0xFFFF7C /* Serial Status Register 0 */ -#define SCI_RDR0 __PORT8 0xFFFF7D /* Receive Data Register 0 */ -#define SCI_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */ +#define Smart_SSR0 __PORT8 0xFFFFFF7C /* Serial Status Register 0 */ +#define SCI_RDR0 __PORT8 0xFFFFFF7D /* Receive Data Register 0 */ +#define SCI_SCMR0 __PORT8 0xFFFFFF7E /* Smart Card Mode Register 0 */ #define SCMR0_SMIFm 0x01 #define SCMR0_SINVm 0x04 #define SCMR0_SDIRm 0x08 -#define Smart_SCMR0 __PORT8 0xFFFF7E /* Smart Card Mode Register 0 */ -#define IIC_ICDR0 __PORT8 0xFFFF7E /* I2C Bus Data Register */ -#define IIC_SARX0 __PORT8 0xFFFF7E /* 2nd Slave Address Register */ -#define IIC_ICMR0 __PORT8 0xFFFF7F /* I2C Bus Mode Register */ +#define Smart_SCMR0 __PORT8 0xFFFFFF7E /* Smart Card Mode Register 0 */ +#define IIC_ICDR0 __PORT8 0xFFFFFF7E /* I2C Bus Data Register */ +#define IIC_SARX0 __PORT8 0xFFFFFF7E /* 2nd Slave Address Register */ +#define IIC_ICMR0 __PORT8 0xFFFFFF7F /* I2C Bus Mode Register */ #define ICMR0_BC0FSm 0x01 #define ICMR0_BC1m 0x02 #define ICMR0_BC2m 0x04 @@ -1556,8 +1556,8 @@ #define ICMR0_CKS2m 0x20 #define ICMR0_WAITm 0x40 #define ICMR0_MLSm 0x80 -#define IIC_SAR0 __PORT8 0xFFFF7F /* Slave Address Register */ -#define SCI_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */ +#define IIC_SAR0 __PORT8 0xFFFFFF7F /* Slave Address Register */ +#define SCI_SMR1 __PORT8 0xFFFFFF80 /* Serial Mode Register 1 */ #define SMR1_CKS0m 0x01 #define SMR1_CKS1m 0x02 #define SMR1_MPm 0x04 @@ -1566,12 +1566,12 @@ #define SMR1_PEm 0x20 #define SMR1_CHRm 0x40 #define SMR1_CAm 0x80 -#define IIC_ICCR1 __PORT8 0xFFFF80 /* I2C Bus Control Register */ -#define Smart_SMR1 __PORT8 0xFFFF80 /* Serial Mode Register 1 */ -#define SCI_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */ -#define Smart_BRR1 __PORT8 0xFFFF81 /* Bit Rate Register 1 */ -#define IIC_ICSR1 __PORT8 0xFFFF81 /* I2C Bus Status Register */ -#define SCI_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */ +#define IIC_ICCR1 __PORT8 0xFFFFFF80 /* I2C Bus Control Register */ +#define Smart_SMR1 __PORT8 0xFFFFFF80 /* Serial Mode Register 1 */ +#define SCI_BRR1 __PORT8 0xFFFFFF81 /* Bit Rate Register 1 */ +#define Smart_BRR1 __PORT8 0xFFFFFF81 /* Bit Rate Register 1 */ +#define IIC_ICSR1 __PORT8 0xFFFFFF81 /* I2C Bus Status Register */ +#define SCI_SCR1 __PORT8 0xFFFFFF82 /* Serial Control Register 1 */ #define SCR1_CKE0m 0x01 #define SCR1_CKE1m 0x02 #define SCR1_TEIEm 0x04 @@ -1580,10 +1580,10 @@ #define SCR1_TEm 0x20 #define SCR1_RIEm 0x40 #define SCR1_TIEm 0x80 -#define Smart_SCR1 __PORT8 0xFFFF82 /* Serial Control Register 1 */ -#define SCI_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */ -#define Smart_TDR1 __PORT8 0xFFFF83 /* Transmit Data Register 1 */ -#define SCI_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */ +#define Smart_SCR1 __PORT8 0xFFFFFF82 /* Serial Control Register 1 */ +#define SCI_TDR1 __PORT8 0xFFFFFF83 /* Transmit Data Register 1 */ +#define Smart_TDR1 __PORT8 0xFFFFFF83 /* Transmit Data Register 1 */ +#define SCI_SSR1 __PORT8 0xFFFFFF84 /* Serial Status Register 1 */ #define SSR1_MPBTm 0x01 #define SSR1_MPBm 0x02 #define SSR1_TENDm 0x04 @@ -1592,16 +1592,16 @@ #define SSR1_ORERm 0x20 #define SSR1_RDRFm 0x40 #define SSR1_TDREm 0x80 -#define Smart_SSR1 __PORT8 0xFFFF84 /* Serial Status Register 1 */ -#define SCI_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */ -#define Smart_RDR1 __PORT8 0xFFFF85 /* Receive Data Register 1 */ -#define SCI_SCMR1 __PORT8 0xFFFF86 /* Smart Card Mode Register 1 */ +#define Smart_SSR1 __PORT8 0xFFFFFF84 /* Serial Status Register 1 */ +#define SCI_RDR1 __PORT8 0xFFFFFF85 /* Receive Data Register 1 */ +#define Smart_RDR1 __PORT8 0xFFFFFF85 /* Receive Data Register 1 */ +#define SCI_SCMR1 __PORT8 0xFFFFFF86 /* Smart Card Mode Register 1 */ #define SCMR1_SMIFm 0x01 #define SCMR1_SINVm 0x04 #define SCMR1_SDIRm 0x08 -#define IIC_ICDR1 __PORT8 0xFFFF86 /* I2C Bus Data Register */ -#define IIC_SARX1 __PORT8 0xFFFF86 /* 2nd Slave Address Register */ -#define IIC_ICMR1 __PORT8 0xFFFF87 /* -I2C Bus Mode Register */ +#define IIC_ICDR1 __PORT8 0xFFFFFF86 /* I2C Bus Data Register */ +#define IIC_SARX1 __PORT8 0xFFFFFF86 /* 2nd Slave Address Register */ +#define IIC_ICMR1 __PORT8 0xFFFFFF87 /* -I2C Bus Mode Register */ #define ICMR1_BC0FSm 0x01 #define ICMR1_BC1m 0x02 #define ICMR1_BC2m 0x04 @@ -1610,8 +1610,8 @@ #define ICMR1_CKS2m 0x20 #define ICMR1_WAITm 0x40 #define ICMR1_MLSm 0x80 -#define IIC_SAR1 __PORT8 0xFFFF87 /* Slave Address Register */ -#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */ +#define IIC_SAR1 __PORT8 0xFFFFFF87 /* Slave Address Register */ +#define SCI_SMR2 __PORT8 0xFFFFFF88 /* Serial Mode Register 2 */ #define SMR2_CKS0m 0x01 #define SMR2_CKS1m 0x02 #define SMR2_MPm 0x04 @@ -1620,10 +1620,10 @@ #define SMR2_PEm 0x20 #define SMR2_CHRm 0x40 #define SMR2_CAm 0x80 -#define Smart_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */ -#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */ -#define Smart_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */ -#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */ +#define Smart_SMR2 __PORT8 0xFFFFFF88 /* Serial Mode Register 2 */ +#define SCI_BRR2 __PORT8 0xFFFFFF89 /* Bit Rate Register 2 */ +#define Smart_BRR2 __PORT8 0xFFFFFF89 /* Bit Rate Register 2 */ +#define SCI_SCR2 __PORT8 0xFFFFFF8A /* Serial Control Register 2 */ #define SCR2_CKE0m 0x01 #define SCR2_CKE1m 0x02 #define SCR2_TEIEm 0x04 @@ -1632,10 +1632,10 @@ #define SCR2_TEm 0x20 #define SCR2_RIEm 0x40 #define SCR2_TIEm 0x80 -#define Smart_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */ -#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */ -#define Smart_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */ -#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */ +#define Smart_SCR2 __PORT8 0xFFFFFF8A /* Serial Control Register 2 */ +#define SCI_TDR2 __PORT8 0xFFFFFF8B /* Transmit Data Register 2 */ +#define Smart_TDR2 __PORT8 0xFFFFFF8B /* Transmit Data Register 2 */ +#define SCI_SSR2 __PORT8 0xFFFFFF8C /* Serial Status Register 2 */ #define SSR2_MPBTm 0x01 #define SSR2_MPBm 0x02 #define SSR2_TENDm 0x04 @@ -1644,16 +1644,16 @@ #define SSR2_ORERm 0x20 #define SSR2_RDRFm 0x40 #define SSR2_TDREm 0x80 -#define Smart_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */ -#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */ -#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */ -#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */ +#define Smart_SSR2 __PORT8 0xFFFFFF8C /* Serial Status Register 2 */ +#define SCI_RDR2 __PORT8 0xFFFFFF8D /* Receive Data Register 2 */ +#define SCI_SCMR2 __PORT8 0xFFFFFF8E /* Smart Card Mode Register 2 */ +#define SCI_SCMR2 __PORT8 0xFFFFFF8E /* Smart Card Mode Register 2 */ #define SCMR2_SMIFm 0x01 #define SCMR2_SINVm 0x04 #define SCMR2_SDIRm 0x08 /* Module A/D Converter */ -#define AD_ADDRAH __PORT8 0xFFFF90 /* AD Data Register AH */ +#define AD_ADDRAH __PORT8 0xFFFFFF90 /* AD Data Register AH */ #define ADDRAH_AD2m 0x01 #define ADDRAH_AD3m 0x02 #define ADDRAH_AD4m 0x04 @@ -1662,10 +1662,10 @@ #define ADDRAH_AD7m 0x20 #define ADDRAH_AD8m 0x40 #define ADDRAH_AD9m 0x80 -#define AD_ADDRAL __PORT8 0xFFFF91 /* AD Data Register AL*/ +#define AD_ADDRAL __PORT8 0xFFFFFF91 /* AD Data Register AL*/ #define ADDRAL_AD0m 0x40 #define ADDRAL_AD1m 0x80 -#define AD_ADDRBH __PORT8 0xFFFF92 /* AD Data Register BH*/ +#define AD_ADDRBH __PORT8 0xFFFFFF92 /* AD Data Register BH*/ #define ADDRBH_AD2m 0x01 #define ADDRBH_AD3m 0x02 #define ADDRBH_AD4m 0x04 @@ -1674,10 +1674,10 @@ #define ADDRBH_AD7m 0x20 #define ADDRBH_AD8m 0x40 #define ADDRBH_AD9m 0x80 -#define AD_ADDRBL __PORT8 0xFFFF93 /* AD Data Register BL*/ +#define AD_ADDRBL __PORT8 0xFFFFFF93 /* AD Data Register BL*/ #define ADDRBL_AD0m 0x40 #define ADDRBL_AD1m 0x80 -#define AD_ADDRCH __PORT8 0xFFFF94 /* AD Data Register CH */ +#define AD_ADDRCH __PORT8 0xFFFFFF94 /* AD Data Register CH */ #define ADDRCH_AD2m 0x01 #define ADDRCH_AD3m 0x02 #define ADDRCH_AD4m 0x04 @@ -1686,10 +1686,10 @@ #define ADDRCH_AD7m 0x20 #define ADDRCH_AD8m 0x40 #define ADDRCH_AD9m 0x80 -#define AD_ADDRCL __PORT8 0xFFFF95 /* AD Data Register CH */ +#define AD_ADDRCL __PORT8 0xFFFFFF95 /* AD Data Register CH */ #define ADDRCL_AD0m 0x40 #define ADDRCL_AD1m 0x80 -#define AD_ADDRDH __PORT8 0xFFFF96 /* AD Data Register DH */ +#define AD_ADDRDH __PORT8 0xFFFFFF96 /* AD Data Register DH */ #define ADDRDH_AD2m 0x01 #define ADDRDH_AD3m 0x02 #define ADDRDH_AD4m 0x04 @@ -1698,10 +1698,10 @@ #define ADDRDH_AD7m 0x20 #define ADDRDH_AD8m 0x40 #define ADDRDH_AD9m 0x80 -#define AD_ADDRDL __PORT8 0xFFFF97 /* AD Data Register DL */ +#define AD_ADDRDL __PORT8 0xFFFFFF97 /* AD Data Register DL */ #define ADDRDL_AD0m 0x40 #define ADDRDL_AD1m 0x80 -#define AD_ADCSR __PORT8 0xFFFF98 /* AD ControlStatus Register */ +#define AD_ADCSR __PORT8 0xFFFFFF98 /* AD ControlStatus Register */ #define ADCSR_CH0m 0x01 #define ADCSR_CH1m 0x02 #define ADCSR_CH2m 0x04 @@ -1710,27 +1710,27 @@ #define ADCSR_ADSTm 0x20 #define ADCSR_ADIEm 0x40 #define ADCSR_ADFm 0x80 -#define AD_ADCR __PORT8 0xFFFF99 /* AD Control Register */ +#define AD_ADCR __PORT8 0xFFFFFF99 /* AD Control Register */ #define ADCR_CKS0m 0x04 #define ADCR_CKS1m 0x08 #define ADCR_TRGS0m 0x40 #define ADCR_TRGS1m 0x80 /* Module Timer*/ -#define TMR_TCSR1 __PORT8 0xFFFFA2 /* (R/W) Timer ControlStatus Register 1 */ +#define TMR_TCSR1 __PORT8 0xFFFFFFA2 /* (R/W) Timer ControlStatus Register 1 */ #define TCSR1_CKS0m 0x01 #define TCSR1_CKS1m 0x02 #define TCSR1_CKS2m 0x04 #define TCSR1_OVFm 0x80 -#define TMR_TCNT1 __PORT8 0xFFFFA3 /* (R) Timer Counter 1 */ +#define TMR_TCNT1 __PORT8 0xFFFFFFA3 /* (R) Timer Counter 1 */ /* Module A/D Converter */ -#define DA_DADR0 __PORT8 0xFFFFA4 /* DA Data Register 0 */ -#define DA_DADR1 __PORT8 0xFFFFA5 /* DA Data Register 1 */ -#define DA_DACR01 __PORT8 0xFFFFA6 /* DA Control Register 01 */ +#define DA_DADR0 __PORT8 0xFFFFFFA4 /* DA Data Register 0 */ +#define DA_DADR1 __PORT8 0xFFFFFFA5 /* DA Data Register 1 */ +#define DA_DACR01 __PORT8 0xFFFFFFA6 /* DA Control Register 01 */ #define DACR01_DAEm 0x20 #define DACR01_DAOE0m 0x40 #define DACR01_DAOE1m 0x80 /* Module Flash Memory */ -#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */ +#define FLM_FLMCR1 __PORT8 0xFFFFFFA8 /* Flash Memory Control Register 1 */ #define FLMCR1_Pm 0x01 /* Transition to program mode */ #define FLMCR1_Em 0x02 /* Transition to erase mode */ #define FLMCR1_PVm 0x04 /* Transition to program-verify mode */ @@ -1739,9 +1739,9 @@ #define FLMCR1_ESUm 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */ #define FLMCR1_SWEm 0x40 /* 1= enable writes when FWE=1 */ #define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */ -#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */ +#define FLM_FLMCR2 __PORT8 0xFFFFFFA9 /* Flash Memory Control Register 2 */ #define FLMCR2_FLERm 0x80 /* Flash memory modification error */ -#define FLM_EBR1 __PORT8 0xFFFFAA /* Erase Block Register 1 */ +#define FLM_EBR1 __PORT8 0xFFFFFFAA /* Erase Block Register 1 */ #define EBR1_EB0m 0x01 /* Selects block to erase */ #define EBR1_EB1m 0x02 #define EBR1_EB2m 0x04 @@ -1750,17 +1750,17 @@ #define EBR1_EB5m 0x20 #define EBR1_EB6m 0x40 #define EBR1_EB7m 0x80 -#define FLM_EBR2 __PORT8 0xFFFFAB /* Erase Block Register 2 */ +#define FLM_EBR2 __PORT8 0xFFFFFFAB /* Erase Block Register 2 */ #define EBR2_EB8m 0x01 #define EBR2_EB9m 0x02 #define EBR2_EB10m 0x04 #define EBR2_EB11m 0x08 #define EBR2_EB12m 0x10 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */ #define EBR2_EB13m 0x20 /* Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0 */ -#define FLM_FLPWCR __PORT8 0xFFFFAC /* Flash Memory Power Control Register */ +#define FLM_FLPWCR __PORT8 0xFFFFFFAC /* Flash Memory Power Control Register */ #define FLPWCR_PDWNDm 0x80 /* Module Port */ -#define DIO_PORT1 __PORT8 0xFFFFB0 /* DIO 1 Register */ +#define DIO_PORT1 __PORT8 0xFFFFFFB0 /* DIO 1 Register */ #define PORT1_P10m 0x01 #define PORT1_P11m 0x02 #define PORT1_P12m 0x04 @@ -1769,14 +1769,14 @@ #define PORT1_P15m 0x20 #define PORT1_P16m 0x40 #define PORT1_P17m 0x80 -#define DIO_PORT3 __PORT8 0xFFFFB2 /* DIO 3 Register */ +#define DIO_PORT3 __PORT8 0xFFFFFFB2 /* DIO 3 Register */ #define PORT3_P30m 0x01 #define PORT3_P31m 0x02 #define PORT3_P32m 0x04 #define PORT3_P33m 0x08 #define PORT3_P34m 0x10 #define PORT3_P35m 0x20 -#define DIO_PORT4 __PORT8 0xFFFFB3 /* DIO 4 Register */ +#define DIO_PORT4 __PORT8 0xFFFFFFB3 /* DIO 4 Register */ #define PORT4_P40m 0x01 #define PORT4_P41m 0x02 #define PORT4_P42m 0x04 @@ -1785,17 +1785,17 @@ #define PORT4_P45m 0x20 #define PORT4_P46m 0x40 #define PORT4_P47m 0x80 -#define DIO_PORT9 __PORT8 0xFFFFB8 /* DIO 9 Register */ +#define DIO_PORT9 __PORT8 0xFFFFFFB8 /* DIO 9 Register */ #define PORT9_P90m 0x01 #define PORT9_P91m 0x02 #define PORT9_P92m 0x04 #define PORT9_P93m 0x08 -#define DIO_PORTA __PORT8 0xFFFFB9 /* DIO A Register */ +#define DIO_PORTA __PORT8 0xFFFFFFB9 /* DIO A Register */ #define PORTA_PA0m 0x01 #define PORTA_PA1m 0x02 #define PORTA_PA2m 0x04 #define PORTA_PA3m 0x08 -#define DIO_PORTB __PORT8 0xFFFFBA /* DIO B Register */ +#define DIO_PORTB __PORT8 0xFFFFFFBA /* DIO B Register */ #define PORTB_PB0m 0x01 #define PORTB_PB1m 0x02 #define PORTB_PB2m 0x04 @@ -1804,7 +1804,7 @@ #define PORTB_PB5m 0x20 #define PORTB_PB6m 0x40 #define PORTB_PB7m 0x80 -#define DIO_PORTC __PORT8 0xFFFFBB /* DIO C Register */ +#define DIO_PORTC __PORT8 0xFFFFFFBB /* DIO C Register */ #define PORTC_PC0m 0x01 #define PORTC_PC1m 0x02 #define PORTC_PC2m 0x04 @@ -1813,7 +1813,7 @@ #define PORTC_PC5m 0x20 #define PORTC_PC6m 0x40 #define PORTC_PC7m 0x80 -#define DIO_PORTD __PORT8 0xFFFFBC /* DIO D Register */ +#define DIO_PORTD __PORT8 0xFFFFFFBC /* DIO D Register */ #define PORTD_PD0m 0x01 #define PORTD_PD1m 0x02 #define PORTD_PD2m 0x04 @@ -1822,7 +1822,7 @@ #define PORTD_PD5m 0x20 #define PORTD_PD6m 0x40 #define PORTD_PD7m 0x80 -#define DIO_PORTE __PORT8 0xFFFFBD /* DIO E Register */ +#define DIO_PORTE __PORT8 0xFFFFFFBD /* DIO E Register */ #define PORTE_PE0m 0x01 #define PORTE_PE1m 0x02 #define PORTE_PE2m 0x04 @@ -1831,7 +1831,7 @@ #define PORTE_PE5m 0x20 #define PORTE_PE6m 0x40 #define PORTE_PE7m 0x80 -#define DIO_PORTF __PORT8 0xFFFFBE /* DIO F Register */ +#define DIO_PORTF __PORT8 0xFFFFFFBE /* DIO F Register */ #define PORTF_PF0m 0x01 #define PORTF_PF3m 0x08 #define PORTF_PF4m 0x10 @@ -1842,14 +1842,14 @@ // aditional definition -#define IIC_SCRX __PORT8 0xFFFDB4 /* Serial Control Register X */ +#define IIC_SCRX __PORT8 0xFFFFFDB4 /* Serial Control Register X */ #define SCRX_FLSHEm 0x08 #define SCRX_IICEm 0x10 #define SCRX_IICX0m 0x20 #define SCRX_IICX1m 0x40 -#define SYS_LPWRCR __PORT8 0xFFFDEC /* Low-Power Control Register */ +#define SYS_LPWRCR __PORT8 0xFFFFFDEC /* Low-Power Control Register */ #define LPWRCR_STC0m 0x01 /* */ #define LPWRCR_STC1m 0x02 #define LPWRCR_STCxm 0x03 @@ -1862,7 +1862,7 @@ /* define serial control registers */ -#define SCI_SMR2 __PORT8 0xFFFF88 /* Serial Mode Register 2 */ +#define SCI_SMR2 __PORT8 0xFFFFFF88 /* Serial Mode Register 2 */ #define SMR2_CKS0m 0x01 #define SMR2_CKS1m 0x02 #define SMR2_MPm 0x04 @@ -1871,8 +1871,8 @@ #define SMR2_PEm 0x20 #define SMR2_CHRm 0x40 #define SMR2_CAm 0x80 -#define SCI_BRR2 __PORT8 0xFFFF89 /* Bit Rate Register 2 */ -#define SCI_SCR2 __PORT8 0xFFFF8A /* Serial Control Register 2 */ +#define SCI_BRR2 __PORT8 0xFFFFFF89 /* Bit Rate Register 2 */ +#define SCI_SCR2 __PORT8 0xFFFFFF8A /* Serial Control Register 2 */ #define SCR2_CKE0m 0x01 #define SCR2_CKE1m 0x02 #define SCR2_TEIEm 0x04 @@ -1881,8 +1881,8 @@ #define SCR2_TEm 0x20 #define SCR2_RIEm 0x40 #define SCR2_TIEm 0x80 -#define SCI_TDR2 __PORT8 0xFFFF8B /* Transmit Data Register 2 */ -#define SCI_SSR2 __PORT8 0xFFFF8C /* Serial Status Register 2 */ +#define SCI_TDR2 __PORT8 0xFFFFFF8B /* Transmit Data Register 2 */ +#define SCI_SSR2 __PORT8 0xFFFFFF8C /* Serial Status Register 2 */ #define SSR2_MPBTm 0x01 #define SSR2_MPBm 0x02 #define SSR2_TENDm 0x04 @@ -1891,8 +1891,8 @@ #define SSR2_ORERm 0x20 #define SSR2_RDRFm 0x40 #define SSR2_TDREm 0x80 -#define SCI_RDR2 __PORT8 0xFFFF8D /* Receive Data Register 2 */ -#define SCI_SCMR2 __PORT8 0xFFFF8E /* Smart Card Mode Register 2 */ +#define SCI_RDR2 __PORT8 0xFFFFFF8D /* Receive Data Register 2 */ +#define SCI_SCMR2 __PORT8 0xFFFFFF8E /* Smart Card Mode Register 2 */ #define SCMR2_SMIFm 0x01 #define SCMR2_SINVm 0x04 #define SCMR2_SDIRm 0x08 @@ -1900,7 +1900,7 @@ /* Module Stop Control Register */ -#define SYS_MSTPCRA __PORT8 0xFFFDE8 /* Module Stop Control Register A */ +#define SYS_MSTPCRA __PORT8 0xFFFFFDE8 /* Module Stop Control Register A */ #define MSTPCRA_MSTPA0m 0x01 #define MSTPCRA_MSTPA1m 0x02 #define MSTPCRA_ADCm 0x02 @@ -1914,7 +1914,7 @@ #define MSTPCRA_MSTPA6m 0x40 #define MSTPCRA_DTCm 0x40 #define MSTPCRA_MSTPA7m 0x80 -#define SYS_MSTPCRB __PORT8 0xFFFDE9 /* Module Stop Control Register B */ +#define SYS_MSTPCRB __PORT8 0xFFFFFDE9 /* Module Stop Control Register B */ #define MSTPCRB_MSTPB0m 0x01 #define MSTPCRB_MSTPB1m 0x02 #define MSTPCRB_MSTPB2m 0x04 @@ -1928,7 +1928,7 @@ #define MSTPCRB_SCI1m 0x40 #define MSTPCRB_MSTPB7m 0x80 #define MSTPCRB_SCI0m 0x80 -#define SYS_MSTPCRC __PORT8 0xFFFDEA /* Module Stop Control Register C */ +#define SYS_MSTPCRC __PORT8 0xFFFFFDEA /* Module Stop Control Register C */ #define MSTPCRC_MSTPC0m 0x01 #define MSTPCRC_MSTPC1m 0x02 #define MSTPCRC_MSTPC2m 0x04 @@ -1942,13 +1942,13 @@ #define MSTPCRC_SCI4m 0x40 #define MSTPCRC_MSTPC7m 0x80 #define MSTPCRC_SCI3m 0x80 -#define SYS_MSTPCRD __PORT8 0xFFFC60 /* Module Stop Control Register D */ +#define SYS_MSTPCRD __PORT8 0xFFFFFC60 /* Module Stop Control Register D */ #define MSTPCRD_MSTPD7m 0x80 #define MSTPCRD_PWMm 0x80 /* END Module Stop Control Register */ /* start Flash register compatibility with 2633 programs (only different names of existing FLMCR1 bits)*/ /* // comented are the same */ -//#define FLM_FLMCR1 __PORT8 0xFFFFA8 /* Flash Memory Control Register 1 */ +//#define FLM_FLMCR1 __PORT8 0xFFFFFFA8 /* Flash Memory Control Register 1 */ #define FLMCR1_P1m 0x01 /* Transition to program mode */ #define FLMCR1_E1m 0x02 /* Transition to erase mode */ #define FLMCR1_PV1m 0x04 /* Transition to program-verify mode */ @@ -1957,7 +1957,7 @@ #define FLMCR1_ESU1m 0x20 /* Erase setup when FWE = 1 and SWE1 = 1 */ #define FLMCR1_SWE1m 0x40 /* 1= enable writes when FWE=1 */ //#define FLMCR1_FWEm 0x80 /* 1 = programming enabled by FWE pin */ -//#define FLM_FLMCR2 __PORT8 0xFFFFA9 /* Flash Memory Control Register 2 */ +//#define FLM_FLMCR2 __PORT8 0xFFFFFFA9 /* Flash Memory Control Register 2 */ //#define FLMCR2_FLERm 0x80 /* Flash memory modification error */ /* end Flash register compatibility with 2633 (only different names of FLMCR1 bits)*/