board/arm/ul_usb1/libs/bspbase/bsp0hwinit.c

   1 #include "local_config.h"
   2 #include <system_def.h>
   3 #ifdef CONFIG_KEYVAL
   4   #include <keyvalpb.h>
   5   #include <lpciap.h>
   6   #include <lpciap_kvpb.h>
   7 #endif /* CONFIG_KEYVAL */
   8 #ifdef CONFIG_STDIO_COM_PORT
   9   #include <uart.h>
  10 #endif
  11 #ifdef CONFIG_OC_UL_DRV_SYSLESS
  12   #include <ul_lib/ulan.h>
  13   #include <string.h>
  14   #include <ul_drv_init.h>
  15   #include <ul_drv_iac.h>
  16   #include <ul_lib/ul_drvdef.h>
  17   extern long int uld_jiffies;
  18 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
  19 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  20   #include <i2c_drv.h>
  21 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
  22 #ifdef CONFIG_OC_PBM_DRV
  23   #include <pbmcore.h>
  24   #include <pbm_8250.h>
  25   #include <pbm_drv_init.h>
  26 #endif /* CONFIG_OC_PBM_DRV */
  27 #include <hal_machperiph.h>
  28 #include <hal_intr.h>
  29
  30 /* timers */
  31 volatile lt_ticks_t sys_timer_ticks;
  32
  33 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  34 #define I2C_DRV_NA_MSTIMEOUT    10
  35 i2c_drv_t i2c_drv;
  36 int i2c_drv_na_timer=0;
  37 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
  38
  39 static void sysInit(void)
  40 {
  41
  42   lpc_pll_off();
  43   lpc_pll_on();
  44
  45   // setup & enable the MAM
  46   MAMCR = 0;
  47   MAMTIM = MAMTIM_CYCLES;
  48   MAMCR = MAMCR_FULL;
  49
  50   // set the peripheral bus speed
  51   // value computed from config.h
  52   VPBDIV = VPBDIV_VALUE;                // set the peripheral bus clock speed
  53
  54   // setup the parallel port pin
  55   IO0CLR = P0IO_ZERO_BITS;                // clear the ZEROs output
  56   IO0SET = P0IO_ONE_BITS;                 // set the ONEs output
  57   IO0DIR = P0IO_OUTPUT_BITS;              // set the output bit direction
  58
  59  #ifdef P1IO_OUTPUT_BITS
  60   IO1CLR = P1IO_ZERO_BITS;                // clear the ZEROs output
  61   IO1SET = P1IO_ONE_BITS;                 // set the ONEs output
  62   IO1DIR = P1IO_OUTPUT_BITS;              // set the output bit direction
  63  #endif
  64
  65   PINSEL1 = (PINSEL1 & 0x3FFFFFFF);
  66
  67   IO0CLR = LED1_BIT;                      // Indicate functional state on the LED1
  68 }
  69
  70 void timer0_isr(void)
  71 {
  72   unsigned int ir;
  73   ir=T0IR;
  74   if (ir&TIR_MR0I) {
  75     do {
  76       T0MR0+=PCLK/SYS_TIMER_HZ;
  77       T0IR=TIR_MR0I;               // Clear match0 interrupt
  78      #ifdef CONFIG_OC_UL_DRV_SYSLESS
  79       uld_jiffies++;
  80      #endif
  81      #ifdef CONFIG_OC_PBM_DRV
  82       pbm_jiffies++;
  83      #endif
  84      #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  85       if (i2c_drv.flags&I2C_DRV_MS_INPR) {
  86         if (i2c_drv.flags&I2C_DRV_NA)
  87           i2c_drv_na_timer++;
  88           if (i2c_drv_na_timer>I2C_DRV_NA_MSTIMEOUT) {
  89              if (i2c_drv.stroke_fnc)
  90               i2c_drv.stroke_fnc(&i2c_drv);
  91             i2c_drv_na_timer=0;
  92           }
  93         else {
  94           i2c_drv_na_timer=0;
  95         }
  96         i2c_drv.flags|=I2C_DRV_NA;
  97       }
  98      #endif
  99       sys_timer_ticks++;
 100     } while (((int32_t)(T0MR0-T0TC))<0);
 101   }
 102 }
 103
 104 void timerInit(void)
 105 {
 106   sys_timer_ticks=0;
 107
 108   HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_TIMER0,timer0_isr,0);
 109   HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_TIMER0);
 110
 111   T0TC=0;
 112   T0MCR=0;
 113
 114   T0MR0=PCLK/SYS_TIMER_HZ;                            /* ms tics */
 115   T0MCR|=TMCR_MR0_I;
 116
 117   T0TCR = TCR_ENABLE; //Run timer 0
 118 }
 119
 120 #ifdef CONFIG_STDIO_COM_PORT
 121
 122 int uartcon_write(int file, const char * ptr, int len)
 123 {
 124   int cnt;
 125   unsigned char ch;
 126   for(cnt=0;cnt<len;cnt++,ptr++){
 127     ch=*ptr;
 128     if(ch==0xa)
 129       uart0Putch(0xd);
 130     uart0Putch(ch);
 131   }
 132   return cnt;
 133 }
 134
 135 void init_system_stub(void) {
 136   system_stub_ops.write=uartcon_write;
 137 }
 138
 139 #endif /* CONFIG_STDIO_COM_PORT */
 140
 141 #ifdef CONFIG_OC_UL_DRV_SYSLESS
 142
 143 extern unsigned uld_debug_flg; /* Left application  set defaults */
 144
 145 #ifndef CONFIG_KEYVAL
 146 unsigned long lpciap_buff[ISP_RAM2FLASH_BLOCK_SIZE/4];
 147 #endif /* CONFIG_KEYVAL */
 148
 149 #define UL_MTYPE_START32BIT 0x100
 150
 151 static inline int ul_iac_mem_head_rd(uint8_t *buf, int len,
 152                       uint32_t* pmtype, uint32_t* pstart, uint32_t* plen)
 153 {
 154   uint32_t val, mtype;
 155   if (len<6) return -1;
 156   mtype=*(buf++);       /* memory type */
 157   mtype+=*(buf++)<<8;
 158   val=*(buf++);           /* start address */
 159   val+=*(buf++)<<8;
 160   if(mtype&UL_MTYPE_START32BIT){
 161     if (len<8) return -1;
 162     val+=(uint32_t)*(buf++)<<16;
 163     val+=(uint32_t)*(buf++)<<24;
 164   }
 165   *pstart=val;
 166   val=*(buf++);           /* length */
 167   val+=*(buf++)<<8;
 168   if(mtype&UL_MTYPE_START32BIT){
 169     if (len==10) {
 170       val+=(uint32_t)*(buf++)<<16;
 171       val+=(uint32_t)*(buf++)<<24;
 172     }
 173   }
 174   *plen=val;
 175   mtype&=~UL_MTYPE_START32BIT;       /* 32-bit start address */
 176   *pmtype=mtype;
 177   return 0;
 178 }
 179
 180 int ul_iac_call_rdm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 181 {
 182   uint32_t mtype,start,len;
 183
 184   data->len=0;
 185
 186   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 187     return UL_IAC_RC_PROC;
 188
 189   if (mtype==0x00) {
 190     data->len=len;
 191     data->buff=(char*)start;
 192     return UL_IAC_RC_FREEMSG;
 193   }
 194   return UL_IAC_RC_PROC;
 195 }
 196
 197 int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 198 {
 199   uint32_t mtype,start,len;
 200
 201   data->len=0;
 202
 203   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 204     return UL_IAC_RC_PROC;
 205
 206  #ifdef CONFIG_KEYVAL
 207   if (mtype==0x01) {
 208     lpcisp_erase((void*)start,len);
 209     data->len=0;
 210     return UL_IAC_RC_FREEMSG;
 211   }
 212  #endif /* CONFIG_KEYVAL */
 213   return UL_IAC_RC_PROC;
 214 }
 215
 216 int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 217 {
 218   uint32_t mtype,start,len;
 219
 220   data->len=0;
 221
 222   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 223     return UL_IAC_RC_PROC;
 224
 225   if (mtype==0x00) {
 226     memcpy((void*)start,data->buff,data->len);
 227     return UL_IAC_RC_FREEMSG;
 228   }
 229  #ifdef CONFIG_KEYVAL
 230   if (mtype==0x01) {
 231     lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE);
 232     return UL_IAC_RC_FREEMSG;
 233   }
 234  #endif /* CONFIG_KEYVAL */
 235   return UL_IAC_RC_PROC;
 236 }
 237
 238
 239 int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 240 {
 241   uint32_t debcmd,mtype,start;
 242   uint8_t *p=(uint8_t*)ibuff;
 243
 244   if (msginfo->len<1) return UL_IAC_RC_PROC;
 245   debcmd=*(p++);
 246   switch (debcmd) {
 247     case 0x10: /* goto */
 248       data->len=0;
 249       if (msginfo->len<5) return UL_IAC_RC_PROC;
 250       mtype=*(p++);
 251       mtype+=*(p++)<<8;
 252       start=*(p++);
 253       start+=*(p++)<<8;
 254       if(mtype&UL_MTYPE_START32BIT){
 255         mtype&=~UL_MTYPE_START32BIT;
 256         if (msginfo->len<7) return UL_IAC_RC_PROC;
 257         start+=(uint32_t)*(p++)<<16;
 258         start+=(uint32_t)*(p++)<<24;
 259       }
 260       if (mtype==0x00)
 261         ((void (*)())start)();
 262     default:break;
 263   }
 264   return UL_IAC_RC_PROC;
 265 }
 266
 267 int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 268 {
 269   uint32_t rescmd,pass;
 270   uint8_t *p=(uint8_t*)ibuff;
 271
 272   if (msginfo->len<1) return UL_IAC_RC_PROC;
 273   rescmd=*(p++);
 274   switch (rescmd) {
 275     case ULRES_CPU: /* CPU */
 276       data->len=0;
 277       if (msginfo->len<3) return UL_IAC_RC_PROC;
 278       pass=*(p++);
 279       pass+=*(p++)<<8;
 280       if (pass==0xaa55) {
 281         MEMMAP=MEMMAP_FLASH;
 282         lpc_watchdog_init(1,10); /* 10ms */
 283         lpc_watchdog_feed();
 284         while(1);
 285       }
 286     default:break;
 287   }
 288   return UL_IAC_RC_PROC;
 289 }
 290
 291 int uLanInit()
 292 {
 293   struct ul_drv *udrv;
 294
 295   /* set rs485 mode for UART1 */
 296   PINSEL0 = (PINSEL0 & ~0xFFFF0000) | 0x01550000; /* dsr(txd), cts(rxd), rts(rs485_dir), rxd, txd */
 297
 298   udrv=ul_drv_new(UL_DRV_SYSLESS_PORT,      /* port */
 299              UL_DRV_SYSLESS_IRQ,            /* irq */
 300              UL_DRV_SYSLESS_BAUD,           /* baud */
 301              UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */
 302         #ifdef CONFIG_OC_UL_DRV_U450_VARPINS
 303           #if defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) && defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
 304              "16450-dirneg-msrswap",        /* chip name */
 305           #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
 306              "16450-msrswap",               /* chip name */
 307           #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG)
 308              "16450-dirneg",                /* chip name */
 309           #else
 310              "16450",                       /* chip name */
 311           #endif
 312         #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/
 313              "16450",                       /* chip name */
 314         #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/
 315              0);                            /* baud base - default */
 316
 317   if (udrv==NULL)
 318     return -1;
 319
 320   ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL,0);
 321   ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 322   ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 323   ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 324   ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 325
 326   return ul_drv_add_dev(udrv);
 327 }
 328 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
 329
 330 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
 331
 332 int
 333 i2cInit(void)
 334 {
 335
 336   /* set io pins */
 337  #if (I2C_DRV_SYSLESS_IRQ==9)
 338   PINSEL0 = (PINSEL0 & ~0x000000F0) | 0x00000050; /* I2C0 - SCL0, SDA0 */
 339  #elif (I2C_DRV_SYSLESS_IRQ==19)
 340   PINSEL0 = (PINSEL0 & ~0x30C00000) | 0x30C00000; /* I2C1 - SCL1, SDA1 */
 341  #else
 342    #error "wrong I2C pin maping!"
 343  #endif
 344
 345   if (i2c_drv_init(&i2c_drv,
 346                I2C_DRV_SYSLESS_PORT,
 347                I2C_DRV_SYSLESS_IRQ,
 348                I2C_DRV_SYSLESS_BITRATE,
 349                I2C_DRV_SYSLESS_SLADR)<0) return -1;
 350
 351   return 1;
 352 }
 353
 354 #endif /*CONFIG_OC_I2C_DRV_SYSLESS*/
 355
 356 #ifdef CONFIG_OC_PBM_DRV
 357
 358 void pbm_drv_init()
 359 {
 360         int rv = 0;
 361
 362         /* set rs485 mode for UART1 */
 363         /* dsr(txd), cts(rxd), rts(rs485_dir), rxd, txd */
 364         PINSEL0 = (PINSEL0 & ~0xFFFF0000) | 0x01550000;
 365
 366         PBMCHIP_INFO(PBMCHIP_DRV_DESCRIPTION ", "
 367                         PBMCHIP_DRV_VERSION ", "
 368                         PBMCHIP_DRV_COPYRIGHT "\n");
 369
 370         pbm_dev = pbm_alloc_dev(PBM_UART);
 371         if (!pbm_dev)
 372                 PBM_PRINT("unable to allocate device\n");
 373
 374         PBM_LOCK_INIT(&pbm_dev->lock);
 375         PBM_LOCK_INIT(&pbm_dev->irq_lock);
 376
 377         pbm_dev->node_res = &pbm_8250_res;
 378         pbm_8250_res.ioport = PBM_8250_PORT;
 379         pbm_8250_res.irq = PBM_8250_IRQ;
 380         PBMCHIP_INFO("port=0x%04x irq=%d\n",
 381                         pbm_8250_res.ioport, pbm_8250_res.irq);
 382
 383         /* disable all interrupts */
 384         pbm_outb(pbm_dev, UART_IER, 0x00);
 385
 386         /* get default parameters*/
 387         pbm_8250_get_params(pbm_dev, 0);
 388         /* chip operations and registering to pbmcore */
 389         pbm_dev->chops = chops;
 390         rv = pbm_register_chip(pbm_dev);
 391         if (rv)
 392                 PBM_PRINT("unable to register chip\n");
 393
 394         rv = request_irq(pbm_8250_res.irq, pbm_8250_intr, 0, "pbm_8250", pbm_dev);
 395
 396         pbm_8250_int_off_all(pbm_dev);
 397         pbm_8250_int_on_all(pbm_dev);
 398
 399         /* a hack to generate THRE interrupt on LPC2148 */
 400         pbm_outb(pbm_dev, UART_TX, 0x00);
 401 }
 402
 403 #endif /* CONFIG_OC_PBM_DRV */
 404
 405 void _setup_board()
 406 {
 407   // initialize the system
 408   sysInit();
 409
 410   #ifdef WATCHDOG_ENABLED
 411     lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS);
 412     lpc_watchdog_feed();
 413   #endif /* WATCHDOG_ENABLED */
 414
 415   // initialize the system timer
 416   timerInit();
 417
 418   #ifdef CONFIG_STDIO_COM_PORT
 419     uart0Init( B57600 , UART_8N1, UART_FIFO_8);
 420     init_system_stub();
 421   #endif /* CONFIG_STDIO_COM_PORT */
 422
 423   #ifdef CONFIG_OC_UL_DRV_SYSLESS
 424 //    uld_debug_flg=0x3ff;
 425     uLanInit();
 426   #endif /* CONFIG_OC_UL_DRV_SYSLESS */
 427
 428   #ifdef CONFIG_OC_I2C_DRV_SYSLESS
 429     i2cInit();
 430   #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
 431
 432   #ifdef CONFIG_OC_PBM_DRV
 433     pbm_drv_init();
 434   #endif /* CONFIG_OC_PBM_DRV */
 435
 436 }