media: tegra_v4l2_camera: set clock rate for pll_d

media: tegra_v4l2_camera: set clock rate for pll_d

Test pattern generator in VI needs PLL_D running at certain clock
rate, then CSI clock is a child of PLL_D can get the right clock
for operation.

If DC disable DSI and set PLL_D as a very low frequency and VI driver
forgets to set PLL_D rate back, test pattern generator won't work.

This patch will set PLL_D as 927M when we do test pattern generator
testing.

Bug 1515755

Change-Id: I8fd27d193a436e1057ce2bce8f8153630dc5cdce
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/489043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>