rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/log

misc: tegra-profiler: fix resource leaks

Fix Coverity issue of resource leaks
Coverity id : 26481
Coverity id : 26483

Bug 1416640

Change-Id: Ib71950f196b5421ccbc21b3ac8d620e790e83366
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/411421
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

arm64: tegra13: Enable MAX77620 CLK, REGULATOR, POWER_OFF

Bug 1441241

Change-Id: I84f07080c3a13ba63a6a8e674f0faeecc0dc9aa6
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/411908
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

power: reset: max77620: Add Max77620 poweroff support

Bug 1441241

Change-Id: I0cca14cfbc069074286f35dde2f3ec049229500a
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/411985
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

clk: max77620: Add Support for Max77620 clk driver

Bug 1441241

Change-Id: I5ba093de0697eb6ae381f10d6cb8292fe9ea31fe
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/411827
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

regulator: max77620: regulator driver for max77620

max77620 has four DC-to-DC Step-Down regulators and
nine Low-Dropout Linear regulators. This driver allows
software control of these regulators.

Bug 1441241

Change-Id: Ib30a2199239ce8722a5d0207ee4c578842946ea9
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/407928
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

staging: iio: light: ltr659: remove suspend resume

ltr659 resume callback waits for 600 msec as ltr558 needed power on
delay. This affects device resume time as all devices use same
thread to resume.

Removing the delay for ltr659 could resolve this issue, but since
Sensorservice takes care of enabling/disabling the sensor device as
required, suspend/resume remain a overhead anyway. So, remove them.

Bug 200002359

Change-Id: Ib847cc015ae3169c45c25d252588e9439da9b1d3
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/408755
(cherry picked from commit fb566c5ae4dd161db35463683b0fdefab04032c1)
Reviewed-on: http://git-master/r/410743
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

perf tools: Fix the cross compile build

Bug 200006243

Change-Id: Ic8974fccd175e44ee1c712bf5865791e26a88188
Signed-off-by: Janne Hellsten <jhellsten@nvidia.com>
Reviewed-on: http://git-master/r/412475
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

gpu: nvgpu: Use old ctxsw boot method on gm20b

Boot FECS/GPCCS with old method on gm20b. We don't yet have
bootloader for it.

Change-Id: I09046960cd86b0402d3ea2cd8e4c92597766fa10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/412604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

misc: nct1008: set standby mode while configuring

Make sure sensor enters standby mode before reprogramming shutdown limit
with extended temp range.

Bug 1510704

Change-Id: Id7e92ceee2b4b8dea32af8d3d524b83c178b4b7f
Signed-off-by: Josh Kuo <joshk@nvidia.com>
Reviewed-on: http://git-master/r/411271
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

arm: config: vcm30t124: Enable MAX15569 & PID gov

CONFIG_REGULATOR_MAX15569=y - VDD_GPU voltage control
CONFIG_THERMAL_GOV_PID=y - Thermal governor type

Bug 1410223

Change-Id: Id07228c0fe56b350f3fcc32d6c7f221594c0e034
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/407536
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

HID: hidraw: close underlying device at removal of last reader

Even though device exist bit is set the underlying
HW device should be closed when the last reader
of the device is closed i.e. open count drops to zero.

bug 1307434
bug 200004331

Change-Id: Ibdbf0cac829135b8bf1c462197f3a24a69cd69e1
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/376328
(cherry picked from commit c2dadc835dab7a3e05810ec8e666b195f3df8e08)
Reviewed-on: http://git-master/r/408783
Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Tested-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

vcm30t124: minimal_defconfig for kernel boot time improvement

bug 1470179

Change-Id: Id47ee597025a5140c5bd53c9cff66aa5faf7eea1
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/401923
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

ARM: Tegra: Loki: Load EMC Tables from DeviceTree

Change-Id: Id09e6fbefd36351d2dcf38d51c054ad377873e2a
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: http://git-master/r/409704
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

ARM: tegra: fix flowctrl programming in tegra_resume

Change-Id: Ied2ce412d6cd0a99adb9d59467bd78400d96d82a
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/412294
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

clock: tegra21: Add new clocks

Add new clocks: MC_CPU, DBGAPB, DPAUX1, PLLP_OUT_CPU, MIPIBIF

Bug 1413190

Change-Id: Ief451f57110f2e915e6d4290e6bb3455ec24b330
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/409211
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

clock: tegra21: Update gpu dvfs table

Update max gpu dvfs frequency to exact multiple of
oscillator frequency(38.4MHz).

Change-Id: I9fa510e9fec45b08ca6aa1a5ef12223c2c97e8d6
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/411595
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

clock: tegra21: modify gpu clock names for gm20b

Except gbus clock, all other gpu clocks are re-named to
gm20b. gbus clock name change needs code change in nvgpu
code, so it will be done along with nvgpu driver code.

Bug 1514021

Change-Id: I0728110d277d27e6e06218eef7ce885c8260eece
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/409981
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

arm64: tegra: Add device name alias for gm20b

Bug 1514021

Change-Id: Ib75e8e70d05d7fd33806cc1a5dc321c572c02185
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/409980
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

clock: tegra21: Re-implement Tegra21 PLLD2/DP support

Re-defined PLLD2 and PLLDP objects, and re-implemented PLLD2/DP
operations to match Tegra21 specification including SDM fractional
feedback divider and Spread Spectrum modes support.

Bug 1413190

Change-Id: If6db9772c2886d84b4ba3af24af6fb35d9f703dc
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/411137
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

clock: tegra21: Add PLL Spread Spectrum control

Added Spread Spectrum control to PLL enable/disable operations:
start SSC after PLL is enabled and locked, stop before it is disabled.

No PLL object with SSC support is instanced, for now.

Bug 1413190

Change-Id: Ia2ea65ec0dbcb7f8c2940f57c15c21262f04b05e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/411136
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

clock: tegra21: Update PLL set defaults procedures

If PLL is enabled during initialization, configure default settings
that can be updated in flight unconditionally (used to do it only if
other mandatory defaults are correctly set by boot-loader). All
other settings are updated the 1st time PLL rate is set after boot.

If PLL is disabled during initialization, set defaults before initial
values for PLL dividers (was reversed order).

Bug 1413190

Change-Id: I0ce9932d09697e94bba43b144cda346dfe8102a2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/411135
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

arm:tegra:loki: Pull for UARTD pins

Bug 1470493

Change-Id: I63d70e704a29632bec3e6e815f74d16e302681f4
Signed-off-by: David Dastous <ddastoussthi@nvidia.com>
Reviewed-on: http://git-master/r/403972
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/409051
GVS: Gerrit_Virtual_Submit

iio: meter: ina230: change permissions of ui_input

Change permissions of ui_input to read only by user and group.

Bug 1513829

Change-Id: I0b651ac75bbb5445a286882e8973b2fc05156dec
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/411363
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Steve Rogers <srogers@nvidia.com>

arm64: tegra: dts: add DT support for xusb

add xusb DT support for laguna_t132

Bug 200005813

Change-Id: Ife73dc16e705c4b559aa90599f6fd19c11325cac
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/411410
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Joy Wang <joyw@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: arch_timer: Enable PL0 access to the CNTVCT

Enable usermode access to the generic virtual counter.

Change-Id: Ie2802027b5584207695dfc09a71510d277c3513f
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/407675
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

arm: tegra: tzram: pass skip iova gap attr to dma_map_linear_attrs

Pass DMA_ATTR_SKIP_IOVA_GAP attribute to dma_map_linear_attrs API.
This is necessary to avoid linear mapping failures for the carveout
memory that is next to tzram in physical.

Bug 200006420

Change-Id: I48cab59329d31599283ba09b853f0f1c2e5e04ea
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/412115
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

video: tegra: nvmap: avoid oom with nvmap background fillings

Avoid OOM killings with nvmap background fillings by specifying
the GFP flags NOMEMALLOC and NORETRY. This flags would avoid
allocations from reserve pools and don't cause unnecessary page
cache drain operations for background fills.

Change-Id: I9a130d151845d6496b16c99e09b728f56eee7a28
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/411028

video: tegra: nvmap: remove page pool filling during its init

Remove explicit page pool filling dring page pool init. Let
the background thread do the filling.

Change-Id: I04e8af02c628394491a8f358f21e73f3e66d7222
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/411069

i2c-algo-bit: fix scheduling while atomic

i2c transfer using bit-banging may be in atomic context.
This patch avoid relinquishing processor during try_address()
in case of atomic context transfer.

Bug 200005734

Change-Id: I5ed18588acc9f7d46c840f218d194086ac09bb94
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/411560
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

gpio: max77620: pass of_node when adding gpio

For DT client, it is require to pass the of_node of device when
adding gpio so that gpio client can refer the node of this gpio.

Change-Id: I50754f125b4969bfa51c6b4deae2eaffff6376b8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/411530
Reviewed-by: Automatic_Commit_Validation_User

drivers: spi: Add qspi controller driver

This driver is derived from tegra spi master driver.
The changes include new controller driver for quad spi.
The driver supports programming X1/X2/X4, SDR/DDR, Dummy cycle,
DMA and PIO mode. Any request to the controller driver should combine
multiple transactions (command/address/data) into single message.

Bug 1375793

Change-Id: If6b1689ed6b6b93c07ea54d1cfee773f1ce34be1
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/405745
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Ashutosh Patel <ashutoshp@nvidia.com>

arm64: tegra: t210: Add qpsi entry into auxdata table

Bug 1375793

Change-Id: Ie4c9a41ae57ee6b2c9d8f3edb985e55effc176ba
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/410847
Reviewed-by: Shardar Mohammed <smohammed@nvidia.com>
Reviewed-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm64: dts: tegra210: Add dt entry for qspi

Bug 1375793

Change-Id: Ic46be73a6d56ad3608af6a59ddb35f4c0eca3f8f
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/410784
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-by: Shardar Mohammed <smohammed@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Revert "Revert "arm: tegra12: enable the PTM driver""

This reverts commit fc13d8524ce45ac29c13a22a3e07dc5aff7101d5.
Re-enabling PTM driver as actual issue fixed re-sizing kernel
image.

Bug 200005809
Bug 9622188

Change-Id: Ifeeae91650942cd3e3f7484279d3a99ad23f16f0
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/412065
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

arm: tegra: nvmap: Fix incorrect declaraion of vpr and carveout memory

resizable cma memory should be declared only when
NVMAP_USE_CMA_FOR_CARVEOUT is enaled.

Change-Id: I5ffe999d0e76245e35843b50ce71d0a0dd20e616
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/412170
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm: tegra: use vpr base and size from bl

Use vpr base and size from bootloader, when nvmap cma carveout is disabled.
Use vpr size from board file, when nvmap cma carveout is enabled.

Change-Id: I05f120f949572c225187981640d35da54f121580
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/412169
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: nvmap: use correct dev ptr during heap create

Use correct dev ptr during nvmap heap create.

Change-Id: If1b74cc3f779e4e773065f4281fecdc3654539ac
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/406026
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm: tegra: nvmap: pass dma_dev arg for carveouts

Pass dma_dev arg for carveouts. This is necessary
to allocate from carveouts via Dma API.

Change-Id: I9c3fea752c9399fb40dccffc09bd572e1713a930
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/412168
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm: tegra: nvmap: add dma device for iram

This device tegra_iram_dev can be used to allocate
from IRAM via Dma API.

Change-Id: I5129c223485d2bed7ba659b7b479c6ccc3f618b3
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/412167
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

ARM: tegra: Use LZMA compression for kernel

Kernel has grown so that when it is uncompressed it overwrites the initrd.
Compress kernel with LZMA so that it becomes smaller and again fits into
the given space.

Bug 1515385

Change-Id: I36f1c580b95de5daa868a721e7c23d89b3c22f41
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/411933

ARM: tegra: ardbeg: Add device if config present

Register tegra_ptm_device when CONFIG_TEGRA_PTM enabled

Change-Id: Ib9ffd24a2d6fee998d3167b5319ce86d3dc541ed
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/411425
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

cfboost: initialize boost values to 0

boost_freq, boost_emc and boost_cpus should be 0
initially if these parameters are not set.

Bug 1385013

Change-Id: I39a6e1f216eb109915ec0f9bc2cb9f2456fdcaef
Reviewed-on: http://git-master/r/406475
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/409697
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>

cfboost: add boost_cpus

cfboost might want to change the number of min online cpus.
This change adds a new nodes for that.

Bug 1385013

Change-Id: I69aaa1eb93298f3c8413a77ca5cb2fbe39bb345c
Reviewed-on: http://git-master/r/404690
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/409696
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>

input: cfboost: Add EMC boost

Change-Id: Id9b7ea216b8c93e291cc95d7522ba21d15701eeb
Reviewed-on: http://git-master/r/397838
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/402484
Reviewed-by: Li Li (SW-TEGRA) <lli5@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

usb: phy: tegra: Add usb_phy_reset for HSIC

usb_phy_reset was missing from uhsic_phy_ops
hence USB_TXFILLTUNING kept incorrect value after ehci_reset
then resulted in DataBufferErr on out endpoint

Bug 200002033

Change-Id: Id8ac624174b5bdca740925092fff7c26481ef46e
Signed-off-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-on: http://git-master/r/406720
(cherry picked from commit f2884247f7557593c8b7fd4fa6a7fa5297c69b58)
Reviewed-on: http://git-master/r/409180
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

nvdumper: Add kernel config file option

Bug 1498965

Reviewed-on: http://git-master/r/399158
(cherry picked from commit d8b41004f38dda7a16ba972ef0852d850b264927)

Change-Id: I6913db3d5a4d6a47339642986daee638194f507e
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/409011
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: add armv8 cpu registers to nvdumper

Bug 1498965

Reviewed-on: http://git-master/r/400929
(cherry picked from commit fe58eed2a3a88559370b7a2694178c6ecd049ec4)

Change-Id: I19e377808dacf1a84d79030206f40a06f04fab62
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/409124
Reviewed-by: Mark Peters <mpeters@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: add armv8 cpu registers to nvdumper

Bug 1498965

Change-Id: I353b383acd5ae32338ef38468787644fc9eafe48
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/400929
(cherry picked from commit fe58eed2a3a88559370b7a2694178c6ecd049ec4)
Reviewed-on: http://git-master/r/406021
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

nvdumper: Added feature for 64-bit kernel

Bug 1498965

Change-Id: I93c985a4583b884989a8fe8b4ee5c33a2ef6a3b5
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/399158
(cherry picked from commit d8b41004f38dda7a16ba972ef0852d850b264927)
Reviewed-on: http://git-master/r/405998
Reviewed-by: Mark Peters <mpeters@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

spi: tegra114: transfer size should be ceil(bpw/8)

This change adds the check for the transfer size
of spi packet to be a multiple of bits_per_word/8
rounded to next higher integer.

Bug 1506109
Change-Id: I3f19ead0629f4b1bdaf3946cd5cb07b6c36cbb19
Signed-off-by: Yousuf A <yousufa@nvidia.com>
Reviewed-on: http://git-master/r/406534
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

spi: tegra114: enforce tegra supported bpw 4-32

This change adds the bpw mask selecting all
bits per word from 4-32.

Bug 1506113
Change-Id: Iab1bf7901e6a3709b3a7a49bde52873e18aab96e
Signed-off-by: Yousuf A <yousufa@nvidia.com>
Reviewed-on: http://git-master/r/406533
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

spi: tegra114: Adding sanity check for spi packets

This change checks the following sanity checks on
each of the transfer requested,
- length is greater than 0
- either of tx or rx buffer should be provided

Bug 1506109

Change-Id: Iff60f9fcc542df4742fad1c098dbaf5775a1be8b
Signed-off-by: Yousuf A <yousufa@nvidia.com>
Reviewed-on: http://git-master/r/404338
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

spi: tegra114: add support for lsb first transfer

This fix adds supports for LSB first transfer

Bug 1506110

Change-Id: I1e3917493fef4e5fa6698357052ecd241dd0aaf5
Signed-off-by: Yousuf A <yousufa@nvidia.com>
Reviewed-on: http://git-master/r/403354
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

spi: tegra114: flush rx/tx fifo if not empty

This fix flushes rx/tx fifo if they are not empty before a transfer

Bug 1506112
Change-Id: Ic43b33dfe9158533235c03d702265e4ee468c39d
Signed-off-by: Yousuf A <yousufa@nvidia.com>
Reviewed-on: http://git-master/r/400842
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: disable VPR resizing

Bug 1496920

Change-Id: I3d0f55722fdb6bebdbbb14340b401f248a247c5f
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/404621
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

gpu: nvgpu: Add gk20a semaphore APIs

Add semaphore_gk20a.c/h that implement a new semaphore management API
for the gk20a driver. The API introduces two entities, 'semaphore pools'
and 'semaphores'.

Semaphore pools are memory areas dedicated for hosting one or more
semaphores. Typically, one pool equals one 4K page. A semaphore pool
is always mapped to the kernel memory, and it can be mapped and
unmapped to gpu address spaces using gk20a_semaphore_pool_map/unmap.

Semaphores are backed by 16 bytes of memory allocated from a semaphore
pool. The value of a semaphore can be 0=acuired or 1=released. When
allocated, the semaphores are initialized to the acquired state. They
can be released, or their releasing can be waited for by the CPU or GPU.

Semaphores are intended to be used only once, and after they are
released they should be freed so that the slot within the semaphore
pool can be reused. However GPU jobs must take references to the
semaphores that they use (similarly as they take references on memory
buffers that they use) so that the semaphore backing memory is not
reused too soon.

Bug 1450122
Bug 1445450

Change-Id: I3fd35f34ca55035decc3e06a9c0ede20c1d48db9
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/374842
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm: tegra: handle CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT disable

Let VPR continue with VPR carved out by BL when
CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT is disabled.

Bug 1496920

Change-Id: I2454bd7d93b24e43f54a97f6f76485ff03bc5193
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/404596
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

usb: phy: pad protection for T210

The 20soc process is not tolerant to 3.3V and
USB2 pads has some protection circuits which
need to be activated by SW for T210 alone

Bug 1499560

Change-Id: Ief5a26d9f06a4fa674aa26f6fb7a2943cbf16e1b
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/410716
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

video: tegra: host: balance pm_runtime calls

pm_runtime_get_sync increments usage count first and
then carry out actual resume operation. if pm_runtime_get_sync
failed needs to decrement usage count to balance count.

Bug 1459733

Change-Id: I844c59310b992c7cac12b134c772f30857c5dec3
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/368416
Reviewed-on: http://git-master/r/411248
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

tegra: vcm30t124: Conditionally compile sdhci-1

This change makes the vcm30_t124_sdhci.c file compilation
dependent on bcm43241 wifi driver.

bug 1503589

Change-Id: Id342cdf90f15d7e41b07ac17182108361b45bc9b
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/408250
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

video: tegra: host: support gather filter on T124/T132

This patch adds support to enable gather filter on T124 and T132
This support can be added per device through "gather_filter_enabled"
bool flag in nvhost_device_data
For now set false to this flag for all devices

Bug 1259826

Change-Id: I9a65765cb5306dc0936f976a23721539d914a5fb
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/289084
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: add gather filter h/w accessor

Add hardware accessor for kernel gather filter

Bug 1259826

Change-Id: I43598f8a12f01c897f127ae0500be43fb9b3a83f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/393409
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

mmc:tegra: Pass platfrom data member "id" from DT

For sdhci instance 3, DDR mode is enabled by setting
SDMMC_VENDOR_MISC_CNTRL_0[8].

When DT is enabled for SDHCI, id value is not passed,
and due to this DDR mode was not enabled.

bug 1367536

Change-Id: I004bbc02cb929e970ed079b97799256ffd46be51
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/405294
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

gpu: nvgpu: Balance usage count on resume fail

If PM runtime resume fails, pm_runtime_get_sync() still increments
the usage count. Balance the usage count by decrementing it on
fail.

Bug 200003289

Change-Id: I127d2697ff2601d4884a4ecfdec8ad50894bf7d0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/411285
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
GVS: Gerrit_Virtual_Submit

video: tegra: host: add API to get clk from pdata

Add API to get clk from pdata given clock name.

Bug 1436477

Change-Id: I1e58e14099a89387342f436bcfb228200daab133
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/409329
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

ARM: tegra: add property avdd_dsi_csi-supply for vi

Add regulator handle for T124-ardbeg A00/A03 VI driver with
E1733 and E1735 PMIC.

Bug 1436477

Change-Id: I3f58ab16b2cca0bc1b72a936876e7c4681abb42c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/408124
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

video: tegra: host: reset correct sensor on powergate

- add reset callback for vi single device separately
- don't set device id explicitly for vi single device

Bug 1436477

Change-Id: I2b5956a49da46b7a0a681a6ad84c116016cab05e
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/404329
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

video: tegra: host: add vi platform data for t12x

- Add Vi device node seperately
- set number of channels as 2
- remove slave instance and so set device id as -1
- add all cil sensor clocks

Bug 1436477

Change-Id: I32a9d92a9a6c06e9082208914dc0d084b317e0b8
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/404328
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

ARM: tegra12: clock: update clocks for vi device

Add clocks for vi single device

Bug 1436477

Change-Id: I08acc00d24a03277461bae457c39879f103d61c8
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/404327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

ARM: tegra: Add OF_AUXDATA for Vi device

If single device present for VI then use "vi" as
device name instead "vi.0"

Bug 1436477

Change-Id: Ia39a8d7698ccd739135b61a1a00b74b8fb3ca6fb
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/404326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

t210: fpga: set parent clk of debug port to clk_m

- Set parent of debug console to clk_m for fpga.
- Set the debug uart clk rate for non fpga

Change-Id: I9d36901584e64c3ce8d3f39805a0aeebfbf7a2ab
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/410835
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

gpu: nvgpu: gk20a: fix syncpt names for gk20a

nvhost_get_syncpt_host_managed() creates syncpt name based on
platform_device pointer passed to it
Passing host1x's pointer to this API results in setting gk20a
syncpt names as "host1x_0" which is conflicting

Hence to restore this pass gk20a's device pointer
which gives syncpt names as "gk20a.0_0"

Also, add a syncpt check for sycnpt received.

Bug 1305024

Change-Id: I4ff96c7c9ebff2dca385c5787a85b4a9451b9514
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/410121
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: use global variable to get nvhost_master

In nvhost_get_syncpt_host_managed(), we receive platform_device
of client and then call nvhost_get_host(pdev) to get pointer to
nvhost_master

In nvhost_get_host(), we check if pdev or parent of pdev is host1x.
But this fails if we pass gk20a's platform device as pdev since
gk20a is now moved outside of nvhost and it does not have host1x as
its parent

Hence to get pointer to nvhost_master, use global variable nvhost
directly instead of calling nvhost_get_host()

Bug 1305024

Change-Id: Ic55e6b73e69de30a4ec926bbf7a2dbd524330348
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/410120
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: handle syncpt over allocation

When we run out of syncpts, do following :
- release the syncpt lock
- call shcedule() so that other process will get chance to release
some syncpts
- take syncpt lock and again check is syncpt is now free
- do this checking for a certain timeout (1 sec for now)

Bug 1305024

Change-Id: Id428b14b70cf1940ebd96e0b46d83af7e92fe1e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/405203
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: host: Skip IOVA gap in Tsec carveout mapping

When mapping Tsec carveout to IOVA space, do not add IOVA gap page at
the end. Otherwise, if there is another carveout already mapped that
starts right after the Tsec carveout, the first page of it will be
incorrectly mapped to the IOVA gap page.

Bug 1499804

Change-Id: I3f8d9fc8efb26c2f6300a2802dae5ab139d1e5a4
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/410932
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm64: tegra: Enable MAX77620 GPIO, RTC, PINCTRL

Enabled configs of MAX77620 GPIO, RTC, PINCTRL
drivers in tegra21 and tegra13 configs.

Bug 1441241

Change-Id: Ic79d78d98618811cfb012f5d15cd2153577ef188
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/406914
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

pinctrl: max77620: Add pinctrl driver for Max77620

Added pinctrl driver for max77620. The Max77620
PMIC has 8 pins that can function as GPIO or in
alternate modes. The pinmux support added here will
help in configuring one of the modes.

Bug 1441241

Change-Id: Ia2fdee7e721a6553addff7e7778344241861c5ec
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/406794
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

rtc: max77620: Add max77620 rtc driver support

Bug 1441241

Change-Id: I50ba2753dfc79776f1c2fb541bd852e551f04c57
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/402840
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

gpio: max77620: Add Maxim Max77620 GPIO driver

Bug 1441241

Change-Id: I52d9afffccbb55c3baa1f54bad3c0a7b26186a5f
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/402085
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

Revert "arm: tegra12: enable the PTM driver"

This reverts commit 10dee12380dda003e7edf208cf70fa62493423d1.
With Original change T12x devices fails to boot on android builds.

Bug 200005809
Original Bug 9622188

Original change : http://git-master/r/#/c/338002/

Change-Id: I59dc5753be173ef33110a7d6fb4835a9dc23b6dc
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/411268
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

ARM: tegra: correct LDOUSB-IN1 and LDOUSB-IN2 supply for TN8

Correct the LDOUSB-IN1 and IN2 supply as per TN8 schematics.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/407517
Reviewed-by: Tony Ly <tly@nvidia.com>
Tested-by: Tony Ly <tly@nvidia.com>
(cherry picked from commit 045a7592e953fb44be908075b5124b7d7e5e3557)

Change-Id: I51601d7ad8aa448dc39a7d47d6ef06d4b2a0520c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/410818

ARM: tegra: correct voltage value of ldousb-in switching threshold

LDOUSB input is switched on IN1 or IN2 based on the input voltage on
that pins. The threshold voltage level is specified on uV.

Correct the property value to reflect on correct unit.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/397519
(cherry picked from commit a38e069ed605c1d3fe6c9db2cd1f935d26aca3a4)

Change-Id: Icd853d77f1bc987865804b1e32b4023706711028
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/410816
Tested-by: Venkat Reddy Talla <vreddytalla@nvidia.com>

iio: adc: palmas: get proper device data

Get proper device data from device pointer on different
platform driver callbacks.

bug 1493891

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/392295
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
(cherry picked from commit dd2523a794e27697a2bfe9827a8eb58251857473)
Change-Id: Ib4cfba02928cc4d7cbf125e3a117f75139f1127a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/410812
Tested-by: Venkat Reddy Talla <vreddytalla@nvidia.com>

arm: tegra: pm: move err print to debug print

Unwanted print, that too with err level is moved
to debug level

Bug 1501662

Change-Id: I0fbfa966ab69ec40dd4a218e4e03226ab197a8da
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/408038
(cherry picked from commit c01a80c066f97e34f1850c705b9022a9165638bd)
Reviewed-on: http://git-master/r/409216
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

cpufreq: remove race while accessing cur_policy

While accessing cur_policy during executing events
CPUFREQ_GOV_START, CPUFREQ_GOV_STOP, CPUFREQ_GOV_LIMITS
same mutex lock is not taken, dbs_data->mutex, which leads
to race and data corruption while running continious suspend
resume test.

Bug 1455519

Change-Id: I6b385578c791648681746b749d33f671d00154f3
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/407589
(cherry picked from commit 893243039ee4785099603dac1f3221311e3c219f)
Reviewed-on: http://git-master/r/409215
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>

media: ad5823: Back to default position on exit

Move focuser back to default position gradually before
turning off power. This can reduce the popping sound
when exiting camera app.

Bug 200000851

Change-Id: I14c2fed1e99ec5754120fcc8b8b3adb55a2966cb
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/407175
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sudhir Vyas <svyas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

arm: loki: Add new dts file for t124 c00

Added the pinmux/gpio changed required for t124 c00 board
Also renamed a file that was incorrect due to board name
changing from e to p prefix.

Change-Id: I2449f47358d93197a3c548b84ddf906dc51c79e4
Signed-off-by: David Dastous <ddastoussthi@nvidia.com>
Reviewed-on: http://git-master/r/384018

asm-generic: atomic.h: relaxed atomic_read

Defining relaxed version of atomic read as cpu_relaxed_read_atomic
which will be used for improving power efficiency for arm64.

bug 1440421

Change-Id: I6ac26653ec3d62f74d8c21f250dcdaf9dfb75b9b
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

arm64: atomic.h: defining relaxed atomic_read

Defining relaxed version of atomic read as cpu_relaxed_read_atomic
which will be used for improving power efficiency for arm64.

bug 1440421

Change-Id: I5a88b8e66ec3021335905109010efc856ffa7c7e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>

clock: tegra21: Re-implement Tegra21 PLLA support

Re-defined PLLA object, and re-implemented PLLA operations to match
Tegra21 specification (including SDM fractional feedback divider),
and use common pll operations.

Bug 1413190

Change-Id: Ibbc682e35c2825b91b1f44a5ee3eb9015556fcbd
Signed-off-by: Alex Frid <afrid@nvidia.com>

clock tegra21: Update PLLCX init procedure

Updated PLLCX initialization procedure to make it more generic (it is,
in fact, re-used by all re-implemented Tegra21 PLLs):
- for PLLs that do not support SDM: clipped VCO minimum margin to
comparison frequency (rather than to input frequency before PLL input
divider)
- for PLLs with SDM: limited the margin to SDM resolution
- when configuring initial rate: specified post-divider ratio, rather
than setting, and use per-pll conversion function to find setting
- when configuring initial rate: preserved non standard base fields
(let per-pll set defaults function update these fields if necessary)

Bug 1413190

Change-Id: I55bc1fbd0e7d4e6f2adc25fdb34c9de50ced1f4b
Signed-off-by: Alex Frid <afrid@nvidia.com>

arm64 : fixes a bug in __sys_trace

In __sys_trace, when the system call number is greater
than the syscall limit, do_ni_syscall is executed which
should be followed by a branch to
__sys_trace_return instead of ret_fast_syscall.

Bug 1488764

Change-Id: I3072df5198a58bfd7825e12808cc376058da3e85
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>

arm: tegra12: enable the PTM driver

bug 9622188

Change-Id: I569c0c41002dcd1b518187e75a4ce4203c02e032
Signed-off-by: Xin Xie <xxie@nvidia.com>

arm: tegra: ardbeg: add the PTM device

bug 9622188

Change-Id: I77eba679cf03b67ba2776954f78329300d2e1ecf
Signed-off-by: Xin Xie <xxie@nvidia.com>

arm: tegra: fix PTM dead locking on tight loop

If one core is executing a tight loop and generating huge number of PTM
packets on funnel, it will cause other core dead locking on the PTM
flushing during the WFI entrance.

This patch will replace the "cpu_relax()" with "smp_mb()", and it can
relax the CPU tight loop and allow other CPU's PTM packet being flushed
properly.

bug 9622188

Change-Id: Ibe17fc91a74a5446d560f71ef9308f3dbd32f6c9
Signed-off-by: Xin Xie <xxie@nvidia.com>

clock tegra21: Add support for fractional PLL divider

Added support for fractional PLL feedback dividers. The effective N
value on such PLL is equal to N = NDIV + 1/2 + SDM_DIN/2^13, where
NDIV is integer feedback divider, SDM_DIN is Sigma Delta Modulator
(SDM) setting.

No PLL objects with SDM is instanced, for now.

Bug 1413190

Change-Id: I047eb4d75e74bc5bff79fe10cd95392f5339ae72
Signed-off-by: Alex Frid <afrid@nvidia.com>

video: tegra: nvmap: Fix wake up conditions

Fix the wakeup conditions for the nvmap-bz thread. There was
the possibility of negative wrap-around in low memory cases
due to using and unsigned type.

Change-Id: I0023ccd3c56c2eccf7264fdb031d147f31a66547
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/410374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

arm: atomic.h: defined relaxed atomic_read

Defining relaxed version of atomic read as cpu_relaxed_read_atomic.

bug 1440421

Change-Id: I39303d72350985890c7eb5a1afc768c3f8064b47
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>

clock: tegra21: Re-implement Tegra21 PLLX support

Re-defined PLLX object, and re-implemented PLLX support to match
Tegra21 specification and use common pll operations.

Bug 1413190

Change-Id: I85ce14e3fd25b6e36b5d144d020fc71595cfc87f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/409902
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>