usb: xhci: tegra: fix wake from LP1

We have VDD_CORE on when LP1. xusb use padctl interrupt to
wake from LP1. Keep interrupt enabled when system suspend.

Bug 1583860

Change-Id: I276594d69a051ea84034c32015589a6574ded7f1
Signed-off-by: Joy Wang <joyw@nvidia.com>
Reviewed-on: http://git-master/r/658281
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>

arm/arm64: dma-mapping: fix broken dma_alloc*() for iommu

We have used IOVA prefetch/guard pages to protect a buffer against some
overriding from other buffers. In dma_alloc*() case, we wrongly mapped
those pages after each physical chunk. Those incorrect page mapping can
prevent the next iteration of chunk to be mapped since it checks the
vacancy of PTE.

Bug 200045503
Bug 1410705

Change-Id: I9a2069d3c16cbd23129b6579153a6f289e7b4932
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reported-by: Bryan Wu <pengw@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/658992

Jetson: xusb: update xusb port map for Jetson.

bug 1583246

Change-Id: I3722eda7dd0607b4126bc9f5c708f9699fc66c14
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/658727
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

rtc: hctosys: add support to set start time to 2013-1-1

Add support to set the system time to 2013/1/1 if current time is earlier
than this. This is require to run SPEC 2006 tests.

This support is config variable protected.

bug 1475345

Change-Id: I309f52282523a841005338edf99005511dffe2c5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/659003
GVS: Gerrit_Virtual_Submit

usb: gadget: xudc: enable FE_INFINITE_SS_RETRY

Enable FE_INFINITE_SS_RETRY to prevent device from entering
USDPORT.Disabled_Error state if it is attached to some kinds of special
buggy SS hubs (e.g. VIA 812 SS hub).

We can use below command to disable FE_INFINITE_SS_RETRY via sysfs:
echo N > /sys/module/tegra_xudc/parameters/enable_fe_infinite_ss_retry

Bug 200046293

Change-Id: I127fe9e431457409b0fd9453dd501ac594900868
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/658359
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>

arm: dts: pwms property relocation

pwms property relocation to search pwm device with specified
backlight node

Bug 1371533
Bug 200052337

Change-Id: I427349b9530d485d6b676f210c29cc851780ef19
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/593711
Reviewed-by: Mitch Luban <mluban@nvidia.com>

video: backlight: pwm_bl: find pwm based on node

This change add step 2 to search pwm device.
1. search pwm device with backlight dev node.
2. if not searched, search pwm device with specified
   backlight node which is child backlight node.
3. if not searched, try legacy mode.

Step 2 is needed since required pwm frequency
may be different for each panel, so it is necessary
to parse pwms property from each child backlight node.

Bug 1371533
Bug 200052337

Change-Id: Ie22e1374b0d8c72188b353d492e83060376092c8
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/592637
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

misc: tegra-baseband: support pre boost gpio

Support turning off pre boost regulator gpio before entering LP0, and
turning on pre boost regulator gpio after exiting LP0. This is to save
extra power in LP0 starting from Loki E03.

Also add devicetree documentation for modem power driver.

Bug 200052631

Change-Id: Ia29dd4e76253fa96383e015ac4524658bb7688b6
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://git-master/r/603956
(cherry picked from commit f65a55245b865092ae067551d2d0da9dc357e5a1)
Reviewed-on: http://git-master/r/655298
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-by: Neil Patel <neilp@nvidia.com>
Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

HID: usbhid: schedule a hid_reset() for -75 irq_in

Bug 200043145

Change-Id: I0ca6da8ba4665e3820783f3cb0504a70c59fe5ba
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/657943
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

drivers: tegra210: Threaded cluster switch

Previously, the clusterswitch operation used an IPI via an smp_cross_call..()
to put all non-C7 cores into C7 prior to shutting down the cluster. However,
there exists a race between the shutdown_core IPI and the
fpsimd_restore_current_state() call as seen below:

ret_to_user
    do_notify_resume
        fpsimd_restore_current_state
            test_and_clear_thread_flag => flag cleared

=> IPI comes in to suspend current CPU

CPU_PM_ENTER
    TIF_FOREIGN_FPSTATE not set as it was just cleared
        fpsimd_save_state => Overrides current thread's context with stale data

In order to avoid the above issue, call cpu_suspend from a threaded context
instead. The context switch to the stopper thread will ensure that the fpsimd
state has been saved properly.

Bug 1567470

Change-Id: Ie9f51b08a384007b3f0dafb62b674ca81dbbe914
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/604460
Reviewed-by: Bo Yan <byan@nvidia.com>

misc: tegra-profiler: fix vsp increment

Decode the unwinding instructions (AArch32): fix incorrect
increment of virtual stack pointer (vsp).

Bug 1584541

Change-Id: I4ec64eb21a758b9283df9e6bd6b87a0555180eab
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/658441
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com>
Tested-by: Maxim Morin <mmorin@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

tegra-profiler: record offset of the stack pointer

Tegra Profiler: when collecting backtraces, record
remaining data stack size.

Bug 1584533

Change-Id: I608ab73f8e1b7da84221a17a782080fdf5598111
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/658431
GVS: Gerrit_Virtual_Submit
Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com>
Tested-by: Maxim Morin <mmorin@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

misc: tegra-profiler: add Cortex-A57 events

Tegra Profiler: add ARMv8 Cortex-A57 specific pmu events.

Bug 1582354

Change-Id: I72b1e1ccea3d455d91492cb6ad8538f2405c3937
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/654818
GVS: Gerrit_Virtual_Submit
Tested-by: Andrey Trachenko <atrachenko@nvidia.com>
Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

nvdumper: add debugfs to enable dump after WDT reset

Change-Id: I362268beb77e4001e5d41016d103fd580b3ee33b
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/658572
Reviewed-by: Mark Peters <mpeters@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

iommu/tegra: smmu: NOPTC/NOTLB config

For debugging purpose, add NOPTC/NOTLB kernel config.

Bug 200045503

Change-Id: I0a146fd3c8de8e57849cb476eab8ad3c00312ff1
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/658841
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

tegra: soctherm: modify thermal-zone configuration

Rename MEM-therm zone as LCPU-therm since it is the temp sensor for
the slow-CPU-cluster.

Remove shutdown trip point from PLL thermal zone because it's not
right to have shutdown enabled without any throttling policy.

Change-Id: I65d183b56ed8ba481f0a15510654a0ceac3af028
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/658637

video: tegra: dc: Allocate fb using dma_alloc_attrs()

Framebuffer need not have physically contiguous memory.
It just needs contiguous IOVA. dma_alloc_attrs()
guarantees us the same.

This will avoid the need for framebuffer carveout.

Bug 200022149

Change-Id: I86b713e1ea9a323c7e85c82716894339cb9a1ef3
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/590792
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

tegra: therm_est: fix incorrect ERR_PTR handling

therm_est_get_pdata returns errors via ERR_PTR so we must use
IS_ERR_OR_NULL to properly check for errors.

Change-Id: Ie8b2f1487cf9fd6b7cc7c551e62dbd1a8abbee24
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/658670
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

platform: ape: enable clocks during ape reset

Before APE is reset, adsp clock must be enabled as
part of APE power up sequence. Once APE is reset
adsp clock is disabled again.

Also, enable/disable apb2ape clock on APE powering
on/off triggers.

Bug 1548886

Change-Id: Ibad36e46f09cd220067b2c9987f7861978b8bd86
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/656207
(cherry picked from commit 1a57b27a3845daf139844cdb9fa5b19f26f65bdd)
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/654761

clock: tegra21: Revert "remove apbif clock"

This revert Change-Id: I734b28ce0a5bfcfd07e434a4d1d9379966357bb3
This clock is clock gate APB2APE and part of clock tree
which should not be removed although it is not used in audio
driver

Also rename apbif to apb2ape to match spec.

Change-Id: I51ecee0f7db93e67ccc98501801865d4dfc501ea
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/656206
(cherry picked from commit 12fcc69046f06e01c84cb92dc94310428863c12b)
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/590954

PM/Domain: fix delayed genpd poweroff

The delayed genpd poweroff incorrectly powers off
the genpd for the last active device. This happens as
there is only one pending delayed poweroff work for
device(s) and only one device (last active) is not
suspended.

To fix this, the busy check for genpd with power off
delays has been updated to consider the last active
device while delayed genpd poweroff is used.

Bug 200056291

Change-Id: Id987c70ee135d92ce827bbb045c00b25307cf18f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/656657
(cherry picked from commit 68737800ace6880ea8a29161d409ea8eca801e93)
Reviewed-on: http://git-master/r/658363
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: vgpu: debugger interface fixes

To run CUDA apps, the following minimal changes have been
made:
- power-gating is disabled for vgpu
- regop rd/wr returns -ENOSYS

Tools (debugger/profiler) support is known to not work and
not needed at this time.

Bug 200043227

Change-Id: I923caad78450e72d310fb9290cf2849ed5460ad5
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/592878
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

ARM64: configs: tegra21: MMC RTPM enable

bug 200023075
bug 200041791
bug 200040417

Change-Id: Iea5c011c0a5747e768fc7522eb42a6b36ff80bb2
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/657412

video: tegra: host: tsec: Add t186 bindings

This patch adds T186 bindings to TSEC driver.

Bug 1525992

Change-Id: Iddfa2925c37845a945957f89a4931285f63670d6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/655427

ARM64: configs: tegra21: ksetup menuconfig sync

Used ksetup menuconfig to generate defconfig
for TOT

Change-Id: I4788e35a15598efa415f3e20dc7706af5b76844b
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/657411
Reviewed-by: Automatic_Commit_Validation_User

ARM64: DT: tegra21: disable delayed clock gate

Delayed clock gate is disabled for following
T210 boards -
    loki
    foster
    T210 ERS - E2220
The clock gating is now done through
runtime power management

bug 200023075
bug 200041791
bug 200040417

Change-Id: I7019f1c2660f3f476678d98badf6f97e36ebfdfa

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Change-Id: Iaf6d2a63409811fe811ae4a79a9a15ea80fa2c94
Reviewed-on: http://git-master/r/657410

mmc: sdhci: tegra: runtime pm support

This implementation of Tegra sdhci runtime pm
is coupled with clock gate

The regression caused by original commit 844336c
is addressed in this patch with non-standard
implementation of runtime callbacks

bug 200023075
bug 200041791
bug 200040417

Change-Id: I6b44a43d70f0fed1ec07c14c842f88c67a183943
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/556715
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

Merge "Merge branch 'linux-3.10.61' into dev-kernel-3.10" into dev-kernel-3.10

arm64: dts: tegra210: remove dap trisate pins

-remove dynamic Tristating on DAP pins
 for loki and foster.

bug 1544200

Change-Id: I25e598fa9f9ed36c6a859c5396bc48c6ec8af6d2
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/656567
(cherry picked from commit 3498574bb419c029443df916017994563844a71a)
Reviewed-on: http://git-master/r/657251
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

gpu: nvgpu: Enable syncpt reclaim only on gm20b

gm20b has more channels than sync points. We use aggressive reclaim
of sync points to offset that. Disable aggressive reclaim for gk20a
because it is not needed there.

Bug 1583849

Change-Id: I2a74b0504150a54cb8a97016effe20c5d905ac95
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657095
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

ASoC: tegra-alt: Fix coverity failures

Coverity ID: 28084

Bug 1416640

Change-Id: I533cc8c0ca4c35d9f2996390445da6e728796234
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/658366
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

iommu/tegra: smmu: use ->add_device()

This is a preparation to introduce the upstream IOMMU framework to
control device population order.

Change-Id: I75d23cbea96dbf2ebe3d86fbe20fefad2609e509
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/657548
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

arch: arm64: add comm's DT file for Hawkeye

- Add base DT node Comm's common GPIO's, bcmdhd,
bluedroid_pm by importing tegra210-comms dtsi file
- add and disable DT node for Second Wi-Fi

Bug 200061348

Change-Id: I07b6ef5a6e118f87823f58038c01cb5393573b37
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: http://git-master/r/658248
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm64: dts:Add Top/pinmux/gpio DT files for ERS Char

Add top dts file for E2220 ERS Char Configuration.
Also add gpio & pinmux dtsi files for the same.

Bug 200052840

Change-Id: I9de827e816b151daddd2cb42751b859cb15676b4
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/658239
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

platform: nvadsp: pm suspend if os fails to starts

Decrement the usage counter, if adsp fails to start. Otherwise, the
clocks will always be switched on.

Bug 200007507

Change-Id: I9ac6dc2b5f2e60734a528fd748e3ab53a7ca26f0
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/655479
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

spi: tegra: propery check the iomap return value

io_remap returns the pointer whenthe call success or fail.
On this case, return value need to be check with IS_ERR()
instead of the null pointer check.

Correcting the error check.

Change-Id: Id2fa49ea263b5f7b0936366123b1719f04d0550b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/658417

iommu/tegra: smmu: cache stat supports 64bit

32bit range can be too short since TLB/PTC miss/hit counters easily
overwraps 32bit H/W range. Now those values are kept in 64bit variable.

Bug 1581082

Change-Id: If1c388baf81774b18c60d929c3f5f176c4fe1b88
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/606882
Reviewed-by: Automatic_Commit_Validation_User

tegra: adsp: dfs: fix pr_*() to dev_*()

As dev_*() print the name of the relevant device
in standard form, ensuring that it's always possible
to associate a message with the device that generated it,
replacing pr_*() prints.

bug 200052931

Change-Id: I304f4414af0a7da195e29d12c1e0bc19f4e28e1e
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/658508
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

tegra: adsp: avoid setting same clk value

Currently adsp dfs sets same clock as it doesn't refer
adsp_freq_table before setting requested freq.

This change first refer adsp_freq_table to get target freq,
come-up with final target freq, If previous freq and target freq
is same, returns from there.

This will avoid communication to adsp after setting adsp clk as
previous and requested freq remain same.

bug 200052931

Change-Id: I6c13b31ddcbb953839a83cf1a18c6bc5596edad0
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/658507
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

ASoC: tegra-alt: Fix coverity issues in dmic

Coverity id : 28230
Bug 1416640

Change-Id: Ie0a5b28541c9c750ac6d45e8fe2f088757bcbe3f
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/658389
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

tegra: dc: sor: parse xbar control from dt

Add logic to parse xbar control register
settings from dt

Bug 200049498

Change-Id: Id8eb47fa9f1eb006f5d11a08a5d0da8a4d073e62
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/658518
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

usb: tegra: Control UTMIPLL IDDQ under sw for t210

Enable/disable the utmipll iddq through software
control when both xusb and snps are enabled.

Bug 1551627

Change-Id: I5d12c96e29c468bdcec4f919382eb993617df05b
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/604187
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

usb: tegra: fix sparse warnings

Fix below tegra sparse warnings.

nvxxx_udc.c:4931 'tegra_prod_set_by_name' from incompatible pointer type
nvxxx_udc.c:5090 'tegra_periph_reset_deassert' from incompatible pointer type
tegra_udc.c:1139:25: warning: incorrect type in argument 2
tegra_udc.c:1148:17: warning: incorrect type in argument 1
tegra_udc.c:1148:17: warning: incorrect type in argument 2
tegra_udc.c:2448:6: warning: symbol 'tegra_udc_set_cpu_freq_normal' was not declared
phy-tegra-usb.c:102:22: warning: symbol 'get_tegra_phy' was not declared
phy-tegra-usb.c:328:5: warning: symbol 'tegra_usb_phy_init' was not declared
tegra-xotg.c:247:13: warning: symbol 'xotg_irq' was not declared.
tegra-xotg.c:407:24: warning: symbol 'xotg_driver' was not declared.

Bug 200032218

Change-Id: I38a711854f937cd32777559ab27f5b517ec21dba
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/606225
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Tested-by: Venkat Moganty <vmoganty@nvidia.com>

power: reset: max77620: Clear interrupts in power-off

Clear RTC, TOP and ON/FF interrupts before power-off

Bug 200039104

Change-Id: I1f8bf7ef7844900369d51b09f934a8c2c987557e
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/656956
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/658249

ARM: tegra: populate powerdetect supplies for ERS

bug 200058317

Change-Id: I98d59930eedff9c2be94f4059bca352d7a4c9d00
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/657213
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/658316

ARM: tegra: populate powerdetect supplies for Foster

Bug 200058317

Change-Id: I6b080081ae7005afb145c91063337ba7b7338bc3
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/657173
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/658318

clock: tegra: Add CPU cluster clock edp safe rate

Added EDP safe rate field to CPU cluster clock objects, and accessors
interfaces. Implemented the respective debugfs nodes.

Bug 1572128

Change-Id: I241ee6bbf667b3d19da4c90467bc5cb99535a422
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/656587
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

dvfs: tegra: Add mutual clock throttling interface

Implemented mutual throttling for two clocks with "butterfly" scheme:

Input: F1in, F2in

V1 = V1(F1in)
V2 = V2(F2in)
Vthrot = min (V1, V2)
F1throt = F1(Vthrot)
F2throt = F2(Vthrot)
F1out = min(F1in, F1throt)
F2out = min(F2in, F2throt)

Output: F1out, F2out

Where Vi(F) and Fi(V) DVFS relations for the respective clocks
(i = 1,2) including maximum thermal floor limit.

Bug 1572128

Change-Id: Ie5f4a8018e2fd6e6e6f7472eccf380ab8b5444d2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/656404
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

clock: tegra21: set sc7 entry frequency to boot rate

Revert this change once SC7 is fixed to allow any
frequency lower than 400MHz.

Bug 200053189

Change-Id: Iad51e09aa0d83c7a3296646a17a7581e654b8fd4
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/607059
(cherry picked from commit da386487717fc517c94c85b9f4ecb7bf3fe635eb)
Reviewed-on: http://git-master/r/658354
Reviewed-by: Bo Yan <byan@nvidia.com>

Adding sysfs entries for additional features

->Timestamp
->Cycle accurate
->Address Match
->Formatter
->Userspace tracing
->ETR

Bug 1512961

Change-Id: I058b52357207b99c0a8076cf06050c8d83abdb5a
Signed-off-by: Megha Dey <mdey@nvidia.com>
Reviewed-on: http://git-master/r/654405
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

arm64: dts: thermal: CPU and GPU soctherm trips

Update new thermal trip points for CPU and GPU: balanced, heavy and shutdown.

Bug 1563145

Change-Id: I463cf33fe7a90ebe8ef8553b044a31d09453fb2f
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/604451
(cherry picked from commit 619cc2c4173b36bfef07828cef4e354dabb4c9e3)
Reviewed-on: http://git-master/r/656397
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

ARM: tegra: support multiple sets of coefficients

enable multlple sets of coefficients.

Bug 1582735

Change-Id: I0afd9037335fe6c24e1d6b7e4f560d9b1949922b
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/655577
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

tegra: therm_est: support multiple sets of coefficients

enable multlple sets of coefficients.

Bug 1582735

Change-Id: If0c31037fdf1d8004c9ee241e0387ceef1bb022f
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/655573
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

ARM: tegra: Add TBoard and Tdiode in DT

add Tboard and Tdiode zones in DT for bowmore.

Bug 1566581

Change-Id: I241501d2824c3f803f26642920f44daa6b74300f
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/654990
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

ARM: tegra: fix therm_est's toffset for T132 FFD

change toffset for therm_est for T132 FFD to 708.

Bug 1582712

Change-Id: Iefb1479151917fdbb7170b2cfef2899f7f6c19f8
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/655042
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Thermal: add sanity check and clean codes

add sanity check and clean codes

Bug 1494806

Change-Id: If04130b4fc23c806c7de3f6a49584c500767505a
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/604945
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

ARM: tegra: Fix therm_est_sensor in DT for T210

"#thermal-sensor-cells" is mandatory property for sensor description and
it is missing for T210.

add "#thermal-sensor-cells" to therm_est_sensor node for T210

Bug 1582680

Change-Id: I2194c803215e0ccad8e085dbe44e7a9cd877fd22
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/655029
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

arm64: dts: loki: Base panel sequence fix

nvidia,out-flags is overwritten in incorrect location.
Added rotation to default-disp-out
LCD 3V3 is 3v3_sys and through a load switch now, need to toggle pin G3
LCD enable is on pin H7 for base panel
Also renamed regulator 1v8 to 3v3.

Note:
ALS trigger 3v0_disp rail before the panel sequence do.
May cause an issue in power sequence

Bug 1556009
Bug 1371533

Change-Id: Ie9c7d750fc107e4fa7e4a76abbd2ded2e4c5ea26
Signed-off-by: David Dastous <ddastoussthi@nvidia.com>
Reviewed-on: http://git-master/r/602932
(cherry picked from commit 005479bf0333a8e80c200a1d6b3c1b6e702154e6)
Reviewed-on: http://git-master/r/601430
Reviewed-by: Mitch Luban <mluban@nvidia.com>

tegra: soctherm: update trip temperatures for ERS

update trip temperatures for T210-ERS platform per thermal margins XLS
file: //hw/ar/doc/t210/thermal/T210_ThermalSensing_Margining_Tables.xls

Bug 1580599

Change-Id: I428d63df1c67cad73131e5945683aeaa5fbd9337
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/656337
Reviewed-on: http://git-master/r/656384

arm64: dts: tegra210: match thermal zone names from prior chips

Chips prior to T210 have used the names 'xxx-therm' (with dashes) for
the CPU, GPU, MEM and PLL thermal zones. Adjust T210 dtsi files to do
the same.

Bug 1576205

Change-Id: I815eb072e761cbc631575d3a4fd00b9cc2056da0
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/654859
Reviewed-on: http://git-master/r/656377

dvfs: tegra: Add DVFS rail get voltage accessor

Bug 1572128

Change-Id: Iab3ab45de5cfbc12821bfda2923f42a552db9172
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/656586
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

dvfs: tegra: Selectively defer DVCO calibration

Current CL-DVFS code always defers DVCO minimum rate calibration while
DFLL is sending to PMIC voltage request matching forced voltage value.
This maybe helpful on Tegra SoC with CPU power management controller
that forces voltage underneath CL-DVFS driver on exit from the idle
state.

Not deferring calibration while this enforced voltage is applied may
result in under-estimated DVCO minimum rate, and respectively inaccurate
settings for rates at/below DVCO minimum.

However, deferring calibration may result in over-estimating of DVCO
minimum rate, that in turn may increase voltage set at low rates 1 PMIC
step above Vmin, although the rates themselves would be accurately set.

This commit added TEGRA_CL_DVFS_DEFER_FORCE_CALIBRATE flag that allows
to enable calibration deferral per-Soc, or per-platform from DT.

Set this flag for all T132 SoC platforms, where above trade-offs were
resolved in favor of deferral.

Change-Id: I9976cdabb34266417408479ce09a133fc43696da
Signed-off-by: Alex Frid <afrid@nvidia.com>

ARM64: tegra21: Update GPU regulator delay

- Replaced regulator-ramp-delay with voltage-time-sel to specify
  voltage change delay for GPU regulator exponential output
- Set voltage-time-sel to 80us

Bug 1559684

Change-Id: Ic16cb83e8e5b28b98a39e8877732368ec2ee5766
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/603788
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM64: tegra21: Update DFLL timing parameters

- Changed DFLL sample rate to 25kHz (from 50kHz)
- Changed number of sample periods to maintain forced voltage value
  to 6 (from 10)

Bug 1559684

Change-Id: Ib7fa3943a98666554da717df6b95eb9cd8950d63
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/603787
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

ARM64: DTS: Loki: Add device tree entries for sysedp-dynamic capping.

Update initial budget for Loki.

Bug 1576219

(cherry picked from commit fc9e9070d89b0a341d7b0ff1defb899cf880a2c7)

Change-Id: I66a57960a75c500711c3c192813c560d75407a4a
Signed-off-by: Anand Prasad <anprasad@nvidia.com>
Reviewed-on: http://git-master/r/607133
Reviewed-on: http://git-master/r/555811
Reviewed-by: Timo Alho <talho@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

arch: arm: mach-tegra: Enable hdmi node for parker

Change-Id: Ie060f3f69396b19455ad5239a5d404994f1b26a6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/654984
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

misc: tegra-baseband: enhance enum with XHCI HSIC

We used to postpone modem booting to later stage when XHCI is used
because XHCI driver keeps HSIC bus in IDLE too early before it can
properly handle HSIC CONNECT from modem. Now XHCI driver will only keep
bus in IDLE after client enables HSIC power through sysfs node, so we
boot modem early when driver is loaded.

This change also cleans some codes.

Bug 200039977

Change-Id: Iacb5c00a11a4b11606fdf2fcffd56de4a3951483
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://git-master/r/599934
Reviewed-by: Neil Patel <neilp@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

dvfs: tegra21:  Integrate p4v15 core DVFS table

Integrated p4v15 core DVFS table. Added bin 2, and updated binning
thresholds. Set nominal core voltage per bin.

Bug 1558421
Bug 1582037

Change-Id: Ifb3e1174d86ad5ba474e6353ea05240851121d6a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/653939
Reviewed-by: Mitch Luban <mluban@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

ARM: tegra: set SD0 power up slot to 0

Set FPS power up slot for SD0 (VDD_CORE) to 1 to correct
power up sequence after LP0.

bug 200058612

Change-Id: Iaba0174fbd1fc900159b73b9fdfd62761927cee0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/658440
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

tegra: remove watchdog device from board file

Bug 1562336

Change-Id: Ia72735a60b622d74c1ba9d7901c1a27ea64ffa64
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Reviewed-on: http://git-master/r/555053
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

arm64: dts: provide xbar control values via dt

Provide xbar control values via dt

Bug 200049498

Change-Id: Ia5014ee5586a65fcbf4050d2467e4ecbb3847e6b
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/657254
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

usb: gadget: tegra-xudc: fix BLCG settings

Disable DFPCI/UFPCI/FE bits of BLCG.

Bug 200037805

Change-Id: If7ef8cb39a23e3ec9720f782629cf48c0a0108ac
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/655389
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

usb: gadget: composite: enable BESL support

According to USB 2.0 ECN Errata for Link Power
Management (USB2-LPM-Errata-final.pdf), BESL
must be enabled if LPM is enabled.

This helps with USB30CV TD 9.21 LPM L1
Suspend Resume Test.

Pulled from upstream mainline kernel.
(Commit: a6615937bcd9234e6d6bb817c3701fce44d0a84d)

Bug 200033741

Change-Id: Iec4f8607fc67266649a7061150bbfc14e3490bc4
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Ray Sung <rsung@nvidia.com>
Reviewed-on: http://git-master/r/655289
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Hui Fu <hfu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

video: tegra: host: Suspend cdma at host1x suspend

Currently host1x cdma is suspended when the client device is
clockgated, however, there is no good reason for doing this
operation at that point - especially per-client as the channels
are host1x resources.

This patch modifies channel suspend to happen at the same time
with host1x suspend.

Bug 1551195
Bug 200060820

Change-Id: I09570059c3ca1ad1b9d38ed75d0be9c9e5cb068b
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/603854

video: tegra: host: Simplify channel allocation

This patch simplifies channel allocation/initialization functions
by..:
- merging channel initialization functions
- moving initialization of unmodified data (i.e. chid, mutexes,
cdma) into host1x channel initialization
- simplifying finding of free channel

Bug 1551195
Bug 200060820

Change-Id: Ibb788bc5089304da98d1e68283130c64c29e3345
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/603853

arm: tegra: p1859: Add modem dt

Add pca953x I/O expander to initialize modem related gpios.
Add modem DT to set up gpio.
Remove pca953x init routine from board files.

Bug 1548385

Change-Id: Iabdccfb8ad69d43b7dede4db180a039289a8d5c3
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/603944
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

dma: tegra: empty cb list in tegra_dma_terminate_all

empty cb list in tegra_dma_terminate_all when no
pending requests to fix below DMA crash

Unable to handle kernel paging request at virtual address 00100108
PC is at tegra_dma_tasklet+0x50/0xf4
LR is at tegra_dma_tasklet+0xc0/0xf4
pc : [<ffffffc00044acc8>] lr : [<ffffffc00044ad38>] pstate: 200001c5
sp : ffffffc0bbeeb910
x29: ffffffc0bbeeb910 x28: 0000000000000000
x27: 0000000000000100 x26: 0000000000000200

Change-Id: Ifcae6f8b3026da38b6053ca1097ffd3ff8bdd61c
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/657995
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

Revert "arm64: t210: dts: disable xusb for loki and ers"

This reverts commit 73ff73a4554549aaf17822856dc3e16a9e306536.

Bug 200060396

Change-Id: Ie09377c0b9988e036513bf0747d38238ddbfbbe5
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/657469
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

usb: xhci: tegra: fix LP0 stability issue

Bug 200060396

Change-Id: I538df7ca87b60ed3f53460e3300de1cd0c942394
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/657102
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

iommu/arm-smmu: reset debugfs context_filter

Non numerical value will reset the context_filter.

Change-Id: I1d0526d906e61a4200d9ec31a5e20327f12df92b
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/657537
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

iommu/arm-smmu: fix debugfs CB# validation

Use the runtime detection value instead of spec limitation.

Change-Id: I8d684eb013ece4e13ef8d7bd161b950c87ab7ee9
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/657536
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

iommu/arm-smmu: ifdef to exclude WAR

Introduced CONFIG_ARM_SMMU_WAR to exclude all workaround code if
CONFIG_ARM_SMMU_WAR==n.

Change-Id: I7079cb0f4de8c160115d62e0da9628231dd3b245
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/657535
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

iommu/arm-smmu: exclude workaround for non-simlator

Exclude workaround for non-simlator conditionally.

Change-Id: Ie3dde39106dddafb853e72e482d70d116096dedd
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/657534
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>

ARM: tegra: create tegra132 base SOC dtsi with all node disable

Create base dtsi file for tegra132 to have all node disable. Also
create shield base dtsi file where some of the nodes are enabled
for all shield product.

Bug 200052304

Change-Id: I17c40aeb2e28b7476af930e7bf80313439f8e9d7
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/657340
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: create tegra124 base SOC dtsi with all node disable

Create base dtsi file for tegra124 to have all node disable. Also
create shield base dtsi file where some of the nodes are enabled
for all shield product.

Bug 200052304

Change-Id: Icdc2c7fec75d46d9583ab6f1e7e18d6939ddba44
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/657214
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: populate powerdetect supplies for Loki

bug 200058317

Change-Id: I7775c38ab5b07a242739c19e07b9d0da51df74b5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/657164

ARM: powerdetect: add support for Tegra210 IO rails

As on tegra210, IO rail has been changed from previous SoCs, it
is required to update the rail name on power-detect for the T210.
Also it is require to handle PWR_DET and PWR_DET_VAL as per T210 on
which PWR_DET cells are not able to detect voltage rail other than
SPI_HV.

bug 200058317

Change-Id: I28f5d56d5bb8782c87b44e279960aa0f2741f8b1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/656792

video: tegra: dc: Return error on pin windows failure

Return an error code when tegra_dc_ext_pin_windows fails.

Bug 1583281

Change-Id: I7d56bb360cf32071338db33f5e2cd5f8547d7887
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: http://git-master/r/656126
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

Merge branch 'linux-3.10.61' into dev-kernel-3.10

Bug 200060080

Change-Id: Ie46708ceb16b207e959ac0d4555e19ebfbd7eacf
Signed-off-by: Ishan Mittal <imittal@nvidia.com>

Merge branch 'linux-3.10.61' into dev-kernel-3.10

Bug 200060080

Change-Id: I585caad7dbaaff7c1bdb56bef772a0d867bd1ce7
Signed-off-by: Ishan Mittal <imittal@nvidia.com>

video: tegra: dc: have proper of_node_put

of_node_put is needed before discarding a value received
from of_find_node_by_path, of_parse_phandle and
of_find_compatible_node in error handling code or when the
device node is no longer used, in order to avoid any
memory leak.

Bug 1371533

Change-Id: I824d10bca984e4d6e46bf2f41e30dd441f0f0668
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/655213
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Fix address space sparse warns

This fixes sparse warnings:
incorrect type in argument 2 (different address spaces)

Bug 1573777

Change-Id: I019124614bb7976ccb35e7228c572443cdfa866e
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/656609
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

pinctrl: tegra: Do WARN_ON in parse error case

Do WARN_ON in case of nvidia,pins parse error
and add node name, ret values in error print
so that we can identify which pinmux node is the
reason for failure of pinmux configurations mapping

Change-Id: Iee02fadd4ae65acc1adf2c672ca1b4b6a9c30547
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/656958
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM64: mm: Increase dma coherent pool size

Increase default dma coherent pool size to 1M
from 256KB. This is to avoid ring expansion
failure issues seen when performing huge usb
transfers.

Bug 200044549

Change-Id: I1527d3dcebe9d5a37bc5f733a728299d82305c9d
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/604836
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM64: tegra: loki: add T210 loki E03 top level dts file

Loki E03 will use XHCI UTMI for modem. Change related dts properties.

Bug 200054049

Change-Id: Ie3a4cb319e4bd0e6d7368b8433d3b00789063df0
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://git-master/r/602655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>

Revert "TEMP: arm64: tegra21: config: disable USB XHCI"

This reverts commit 7963e657ec02b2983c554e93ef9a1c00f941f990
to fix mouse functionality on Foster.

Instead of disabling XUSB through config, there is as separate
change merged to disable it only on Loki-E and ERS platforms
through DT. See commit 73ff73a4554.

Bug 200060737

Change-Id: I5510800fb57e231e8e41a941031f79fab2544526
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/657162
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

arm64: t210: dts: disable xusb for loki and ers

Change-Id: I411fb73b42b379b066b14059d3b4e4e1f47f93a1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/657161
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

gpu:nvgpu:gm20b: update pg sequencer data

bug 1553301

sequencer data picked up from p4sw #19041893

Change-Id: I3d05972201572e3db31d1b46e93c03dda3e58d54
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/657023
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

arm: tegra: mcerr: ftrace support

"mcerr" should be traced in ftrace as well as DMA API ftrace to find
inconsistent DMA mapping usage.

ex) accessing iova=0x82200000 after unmapped.

   120.754121: dmadebug_map_sg: device=isp.0, iova=0x82200000, size=786432 phys=dc280000 platformdata=1
   120.765973: dmadebug_unmap_sg: device=isp.0, iova=0x82200000, size=786432 phys=dc280000 platformdata=1
[  120.782853] mc-err: [mcerr] (isp2) csw_ispwa: EMEM decode error on PDE or PTE entry
[  120.791069] mc-err: [mcerr]   status = 0x60010046; addr = 0x82200000
[  120.797751] mc-err: [mcerr]   secure: no, access-type: write, SMMU fault: nr-nw-s

Bug 200049709
Bug 200045503

Change-Id: Ifd03f633aa25358273d7dd18b5e3a3d4805e5d38
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/655332
Reviewed-by: Avinash Magdum <amagdum@nvidia.com>
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>

platform: tegra: add a system reboot handler

Register a new handler with the system so that it can be called before
the system restarts. The handler gets called from machine_restart()
and receives all the restart commands.

PSCI v0.2 adds its own restart handler during psci_init(). In case the
platform does not support PSCI v0.2, we use our own handler instead.

Testing - Verified that the 'reboot' command works as expected. A sample
command and output pasted below.

-----------------------------------------------------------------------
shell@t210_int:/ # reboot bootloader

<snip>
[   60.330324] tegra-i2c tegra21-i2c.0: Bus is shutdown down..
[   60.336310] gk20a gpu.0: shutting down
[   60.340839] Shutting down tegra ...
[   60.344324] reboot: Restarting system with command 'bootloader'
<snip>
-----------------------------------------------------------------------

Change-Id: I46cee25e74a51ae59156d74052292092a7b7f4c5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/606074
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>