From: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Date: Tue, 7 Jun 2016 02:19:47 +0000 (-0700)
Subject: iio: imu: nvi v.330 MPL520 support
X-Git-Tag: tegra-l4t-r24.2~21
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/sojka/nv-tegra/linux-3.10.git/commitdiff_plain/c132e4fa9b1073fd1a4ef5fb5daa2897e5aeac5d

iio: imu: nvi v.330 MPL520 support

- Add sensor dependency for wake interrupt.
- Sensor mounting matrix is now globally based.

Bug 1768847

Change-Id: I24c0db40ed7ef4ff75da5b629276ee950673eb1f
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/1159846
(cherry picked from commit 3a3706e3c23a2cfe50cb82581bb71223b7085a10)
Reviewed-on: http://git-master/r/1185050
GVS: Gerrit_Virtual_Submit
Tested-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
---

diff --git a/drivers/iio/imu/nvi_mpu/nvi.c b/drivers/iio/imu/nvi_mpu/nvi.c
index b37b0d552ff..1efe07ac6a5 100644
--- a/drivers/iio/imu/nvi_mpu/nvi.c
+++ b/drivers/iio/imu/nvi_mpu/nvi.c
@@ -29,7 +29,7 @@
 
 #include "nvi.h"
 
-#define NVI_DRIVER_VERSION		(329)
+#define NVI_DRIVER_VERSION		(330)
 #define NVI_VENDOR			"Invensense"
 #define NVI_NAME			"mpu6xxx"
 #define NVI_NAME_MPU6050		"mpu6050"
@@ -3856,8 +3856,13 @@ static struct sensor_cfg nvi_cfg_dflt[] = {
 		.ch_n			= AXIS_N,
 		.ch_sz			= -2,
 		.vendor			= NVI_VENDOR,
+		.max_range		= {
+			.ival		= 3,
+		},
 		.delay_us_min		= 10000,
 		.delay_us_max		= 255000,
+		.float_significance	= NVS_FLOAT_NANO,
+		.ch_n_max		= AXIS_N,
 	},
 };
 
diff --git a/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.c b/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.c
index 78e1faf0cd0..80d5733ab5c 100644
--- a/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.c
+++ b/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.c
@@ -14,49 +14,64 @@
 #include "nvi.h"
 #include "nvi_dmp_mpu.h"
 
-#define MPU_DMP_PERIOD_US		(5000)
+#define NVI_6QUAT_EN			(1)
 
+#define MPU_DMP_PERIOD_US		(5000)
 #define DMP_HDR_LEN_MAX			(4)
 #define DMP_DEV_ABLE_LEN		(2)
-
-struct nvi_dmp_mpu {
-};
+#define AUX_PORT_DEV_GMF		(0)
+#define MSK_AUX_PORTS_DEV_GMF		(0x3)
+#define AUX_PORT_DEV_PRS		(2)
+#define MSK_AUX_PORTS_DEV_PRS		(0xC)
+#define MSK_EN_AUX_PORTS		(((1 << (AUX_PORT_IO + DEV_N_AUX)) - \
+					  1) & ~MSK_DEV_SNSR)
 
 struct nvi_dmp_dev {
 	unsigned int dev;
 	unsigned int aux_port;
 	unsigned int depend_msk;	/* sensor dependencies */
 	unsigned int buf_n;
-	unsigned int hdr_n;
-	u8 hdr[DMP_HDR_LEN_MAX];
-	u8 hdr_msk[DMP_HDR_LEN_MAX];
 	u16 en_addr;
 	u8 en_len;
 	u8 en[DMP_DEV_ABLE_LEN];
 	u8 dis[DMP_DEV_ABLE_LEN];
 	u16 odr_cfg;
 	u16 odr_cntr;
-	int (*fn_init)(struct nvi_state *st);
+	int (*fn_init)(struct nvi_state *st, unsigned int *en_msk);
+};
+
+struct nvi_dmp_hdr {
+	unsigned int dev;
+	unsigned int aux_port;
+	unsigned int buf_n;
+	unsigned int hdr_n;
+	u8 hdr[DMP_HDR_LEN_MAX];
+	u8 hdr_msk[DMP_HDR_LEN_MAX];
 };
 
 
 /* prs = pressure */
-static int nvi_dmp_prs_init(struct nvi_state *st)
+static int nvi_dmp_prs_init(struct nvi_state *st, unsigned int *en_msk)
 {
 	return 1;
 }
 
 /* gmf = GeoMagnetic Field (compass) */
-static int nvi_dmp_gmf_init(struct nvi_state *st)
+static int nvi_dmp_gmf_init(struct nvi_state *st, unsigned int *en_msk)
 {
-	if (st->aux.port[0].nmp.type != SECONDARY_SLAVE_TYPE_COMPASS)
+	if (st->aux.port[AUX_PORT_DEV_GMF].nmp.type !=
+						  SECONDARY_SLAVE_TYPE_COMPASS)
 		/* DMP shouldn't run if AUX device not supported */
 		return -EINVAL;
 
+	if (!st->aux.port[AUX_PORT_DEV_GMF].nmp.handler)
+		/* no handler */
+		return 1;
+
 	return 0;
 }
 
-static int nvi_dmp_sm_init(struct nvi_state *st)
+static int nvi_dmp_sm_init(struct nvi_state *st, unsigned int *en_msk)
 {
 	int ret;
 
@@ -76,9 +91,6 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 	{
 		.dev			= DEV_ACC,
 		.buf_n			= 6,
-		.hdr_n			= 2,
-		.hdr			= { 0x40, 0x00 },
-		.hdr_msk		= { 0xFF, 0xF0 },
 		.en_addr		= CFG_OUT_ACCL,
 		.en_len			= 2,
 		.en			= { 0xA3, 0xA3 },
@@ -89,9 +101,6 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 	{
 		.dev			= DEV_GYR,
 		.buf_n			= 6,
-		.hdr_n			= 2,
-		.hdr			= { 0x20, 0x00 },
-		.hdr_msk		= { 0xFF, 0xF0 },
 		.en_addr		= CFG_OUT_GYRO,
 		.en_len			= 2,
 		.en			= { 0xA3, 0xA3 },
@@ -99,14 +108,12 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 		.odr_cfg		= KEY_CFG_GYRO_ODR,
 		.odr_cntr		= KEY_ODR_CNTR_GYRO,
 	},
+#ifdef NVI_6QUAT_EN
 	{
 		.dev			= DEV_QTN,
 		.depend_msk		= (1 << DEV_ACC) |
 					  (1 << DEV_GYR),
 		.buf_n			= 12,
-		.hdr_n			= 4,
-		.hdr			= { 0x04, 0x00, 0x04, 0x00 },
-		.hdr_msk		= { 0xFF, 0xF0, 0xFF, 0xF0 },
 		.en_addr		= CFG_OUT_6QUAT,
 		.en_len			= 2,
 		.en			= { 0xA3, 0xA3 },
@@ -114,11 +121,24 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 		.odr_cfg		= KEY_CFG_6QUAT_ODR,
 		.odr_cntr		= KEY_ODR_CNTR_6QUAT,
 	},
+#else /* !NVI_6QUAT_EN */
+	{
+		.dev			= DEV_QTN,
+		.depend_msk		= (1 << DEV_ACC) |
+					  (1 << DEV_GYR),
+		.buf_n			= 12,
+		.en_addr		= CFG_OUT_3QUAT,
+		.en_len			= 2,
+		.en			= { 0xA3, 0xA3 },
+		.dis			= { 0xF4, 0x13 },
+		.odr_cfg		= KEY_CFG_3QUAT_ODR,
+		.odr_cntr		= KEY_ODR_CNTR_3QUAT,
+	},
+#endif /* NVI_6QUAT_EN */
 	{
 		.dev			= DEV_SM,
 		.depend_msk		= (1 << DEV_ACC),
 		.buf_n			= 1,
-		.hdr_n			= 0,
 		.fn_init		= &nvi_dmp_sm_init,
 		.en_addr		= D_SMD_ENABLE,
 		.en_len			= 2,
@@ -127,12 +147,9 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 	},
 	{
 		.dev			= DEV_AUX,
-		.aux_port		= 0,
-		.depend_msk		= (0x03 << DEV_N_AUX),
+		.aux_port		= AUX_PORT_DEV_GMF,
+		.depend_msk		= (MSK_AUX_PORTS_DEV_GMF << DEV_N_AUX),
 		.buf_n			= 6,
-		.hdr_n			= 2,
-		.hdr			= { 0x10, 0x00 },
-		.hdr_msk		= { 0xFF, 0xF0 },
 		.fn_init		= &nvi_dmp_gmf_init,
 		.en_addr		= CFG_OUT_CPASS,
 		.en_len			= 2,
@@ -143,12 +160,9 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 	},
 	{
 		.dev			= DEV_AUX,
-		.aux_port		= 2,
-		.depend_msk		= (0x0C << DEV_N_AUX),
+		.aux_port		= AUX_PORT_DEV_PRS,
+		.depend_msk		= (MSK_AUX_PORTS_DEV_PRS << DEV_N_AUX),
 		.buf_n			= 6,
-		.hdr_n			= 2,
-		.hdr			= { 0x80, 0x00 },
-		.hdr_msk		= { 0xFF, 0xF0 },
 		.fn_init		= &nvi_dmp_prs_init,
 		.en_addr		= CFG_OUT_PRESS,
 		.en_len			= 2,
@@ -159,11 +173,77 @@ static struct nvi_dmp_dev nvi_dmp_devs[] = {
 	},
 };
 
+static struct nvi_dmp_hdr nvi_dmp_hdrs[] = {
+	{
+		.dev			= DEV_ACC,
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x40, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_GYR,
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x20, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_QTN, /* 3QUAT */
+		.buf_n			= 12,
+		.hdr_n			= 4,
+		.hdr			= { 0x08, 0x00, 0x08, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0, 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_QTN, /* 6QUAT */
+		.buf_n			= 12,
+		.hdr_n			= 4,
+		.hdr			= { 0x04, 0x00, 0x04, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0, 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_SM,
+		.buf_n			= 1,
+		.hdr_n			= 0,
+	},
+	{
+		.dev			= DEV_AUX, /* GMF */
+		.aux_port		= AUX_PORT_DEV_GMF,
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x10, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_AUX, /* PRS */
+		.aux_port		= AUX_PORT_DEV_PRS,
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x80, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+	{
+		.dev			= DEV_STP,
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x01, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+	{
+		.dev			= -1, /* PQUAT */
+		.buf_n			= 6,
+		.hdr_n			= 2,
+		.hdr			= { 0x02, 0x00 },
+		.hdr_msk		= { 0xFF, 0xF0 },
+	},
+};
+
 static int nvi_dmp_rd(struct nvi_state *st, s64 ts, unsigned int n)
 {
-	const struct nvi_dmp_dev *dd;
+	const struct nvi_dmp_hdr *dh;
 	struct aux_port *ap;
-	unsigned int dd_i;
+	unsigned int dh_i;
 	unsigned int i;
 	u8 byte;
 
@@ -171,21 +251,21 @@ static int nvi_dmp_rd(struct nvi_state *st, s64 ts, unsigned int n)
 		if (st->sts & (NVS_STS_SUSPEND | NVS_STS_SHUTDOWN))
 			return -1;
 
-		for (dd_i = 0; dd_i < st->hal->dmp->dd_n; dd_i++) {
-			dd = &st->hal->dmp->dd[dd_i];
-			if (!dd->hdr_n)
+		for (dh_i = 0; dh_i < ARRAY_SIZE(nvi_dmp_hdrs); dh_i++) {
+			dh = &nvi_dmp_hdrs[dh_i];
+			if (!dh->hdr_n)
 				continue;
 
-			for (i = 0; i < dd->hdr_n; i++) {
+			for (i = 0; i < dh->hdr_n; i++) {
 				byte = st->buf[st->buf_i + i];
-				byte &= dd->hdr_msk[i];
-				if (byte != dd->hdr[i])
+				byte &= dh->hdr_msk[i];
+				if (byte != dh->hdr[i])
 					break;
 			}
-			if (i >= dd->hdr_n)
+			if (i >= dh->hdr_n)
 				break;
 		}
-		if (dd_i >= st->hal->dmp->dd_n) {
+		if (dh_i >= ARRAY_SIZE(nvi_dmp_hdrs)) {
 			/* unknown header: lost DMP sync so DMP reset */
 			if (st->sts & NVI_DBG_SPEW_FIFO)
 				dev_err(&st->i2c->dev,
@@ -198,27 +278,27 @@ static int nvi_dmp_rd(struct nvi_state *st, s64 ts, unsigned int n)
 			return -1;
 		}
 
-		if (n > dd->buf_n + i) {
-			if (dd->dev == DEV_AUX) {
+		if (n > dh->buf_n + i) {
+			if (dh->dev == DEV_AUX) {
 				if (st->sts & NVI_DBG_SPEW_FIFO)
 					dev_info(&st->i2c->dev,
 						 "%s DMP HDR: AUX port=%u\n",
-						 __func__, dd->aux_port);
-				ap = &st->aux.port[dd->aux_port];
+						 __func__, dh->aux_port);
+				ap = &st->aux.port[dh->aux_port];
 				ap->nmp.handler(&st->buf[st->buf_i + i],
-						dd->buf_n,
-						nvi_ts_dev(st, ts, dd->dev,
-							   dd->aux_port),
+						dh->buf_n,
+						nvi_ts_dev(st, ts, dh->dev,
+							   dh->aux_port),
 						ap->nmp.ext_driver);
-			} else if (dd->dev < DEV_N) {
+			} else if (dh->dev < DEV_N) {
 				if (st->sts & NVI_DBG_SPEW_FIFO)
 					dev_info(&st->i2c->dev,
 						 "%s DMP HDR: %s\n", __func__,
-						 st->snsr[dd->dev].cfg.name);
-				nvi_push(st, dd->dev, &st->buf[st->buf_i + i],
-					 nvi_ts_dev(st, ts, dd->dev, 0));
+						 st->snsr[dh->dev].cfg.name);
+				nvi_push(st, dh->dev, &st->buf[st->buf_i + i],
+					 nvi_ts_dev(st, ts, dh->dev, 0));
 			}
-			i += dd->buf_n;
+			i += dh->buf_n;
 			st->buf_i += i;
 			n -= i;
 		} else {
@@ -234,11 +314,11 @@ static int nvi_dmp_clk_n(struct nvi_state *st, u32 *clk_n)
 	return nvi_mem_rd_le(st, D_DMP_RUN_CNTR, 4, clk_n);
 }
 
-static int nvi_dmp_irq(struct nvi_state *st)
+static int nvi_dmp_irq(struct nvi_state *st, unsigned int en_msk)
 {
 	u32 able;
 
-	if ((st->en_msk & MSK_DEV_ALL) & ~((1 << DEV_SM) | (1 << DEV_STP)))
+	if ((en_msk & MSK_DEV_ALL) & ~((1 << DEV_SM) | (1 << DEV_STP)))
 		/* DMP requires FIFO IRQ */
 		able = 0xFE;
 	else
@@ -278,38 +358,48 @@ static int nvi_dd_odr(struct nvi_state *st, struct nvi_dmp_dev *dd)
 	return ret;
 }
 
-static int nvi_dd_able(struct nvi_state *st, struct nvi_dmp_dev *dd, bool en)
+static int nvi_dd_able(struct nvi_state *st, struct nvi_dmp_dev *dd,
+		       unsigned int *en_msk)
 {
-	int ret;
+	bool en = false;
+	int ret = 0;
 
-	if (dd->dev >= DEV_N_AUX)
+	if (dd->dev == DEV_AUX) {
+		if (*en_msk & (1 << (dd->aux_port + DEV_N_AUX)))
+			en = true;
+	} else if (dd->dev < DEV_AUX) {
+		if (*en_msk & (1 << dd->dev))
+			en = true;
+	} else {
 		return 0;
+	}
 
 	if (en) {
-		if (dd->fn_init)
-			ret = dd->fn_init(st);
-		else
-			ret = 0;
-		if (ret > 0) {
-			/* ignore without error */
-			ret = 0;
-		} else if (!ret) {
-			ret = nvi_dd_odr(st, dd);
-			ret |= nvi_mem_wr(st, dd->en_addr, dd->en_len,
-					  &dd->en[0], false);
+		if (dd->fn_init) {
+			ret = dd->fn_init(st, en_msk);
+			if (ret < 0)
+				return ret;
+
+			if (ret > 0)
+				/* disable without error */
+				en = false;
 		}
-		if (dd->dev != DEV_AUX) {
-			if (ret) {
-				st->en_msk &= ~(1 << dd->dev);
-			} else {
-				st->en_msk |= (1 << dd->dev);
-				st->snsr[dd->dev].buf_n = dd->buf_n;
-			}
-		}
-	} else {
-		ret = nvi_mem_wr(st, dd->en_addr, dd->en_len,
-				 &dd->dis[0], false);
 	}
+
+	if (en) {
+		ret = nvi_dd_odr(st, dd);
+		ret |= nvi_mem_wr(st, dd->en_addr, dd->en_len, dd->en, false);
+		if (ret)
+			en = false;
+	}
+	if (!en)
+		nvi_mem_wr(st, dd->en_addr, dd->en_len, dd->dis, false);
+	if (en)
+		st->snsr[dd->dev].buf_n = dd->buf_n;
+	else if (dd->dev == DEV_AUX)
+		*en_msk &= ~(dd->depend_msk & MSK_EN_AUX_PORTS);
+	else
+		*en_msk &= ~(1 << dd->dev);
 	return ret;
 }
 
@@ -345,6 +435,7 @@ static int nvi_dd_batch(struct nvi_state *st, unsigned int dev, int port)
 static int nvi_dd_init(struct nvi_state *st, unsigned int dev)
 {
 	struct nvi_dmp_dev *dd;
+	unsigned int en_msk = st->en_msk & MSK_DEV_SNSR;
 	int ret = -EINVAL;
 
 	dd = nvi_dd(st, dev, -1);
@@ -352,7 +443,7 @@ static int nvi_dd_init(struct nvi_state *st, unsigned int dev)
 		return -EINVAL;
 
 	if (dd->fn_init)
-		ret = dd->fn_init(st);
+		ret = dd->fn_init(st, &en_msk);
 	return ret;
 }
 
@@ -373,7 +464,7 @@ static u8 nvi_dmp_fcfg_gyro_b[8][3] = {
 	{ 0x36, 0x57, 0x76 },
 	{ 0x37, 0x57, 0x76 },
 	{ 0x37, 0x56, 0x76 },
-	{ 0x37, 0x46, 0x77 },
+	{ 0x37, 0x57, 0x77 },
 	{ 0x37, 0x56, 0x77 },
 	{ 0x36, 0x57, 0x77 },
 	{ 0x36, 0x56, 0x77 },
@@ -464,8 +555,8 @@ static int nvi_dmp_init(struct nvi_state *st)
 static int nvi_dmp_en(struct nvi_state *st)
 {
 	struct nvi_dmp_dev *dd;
-	bool en;
 	unsigned int i;
+	unsigned int irq_msk = 0;
 	unsigned int en_msk = 0;
 	int ret = 0;
 
@@ -474,20 +565,22 @@ static int nvi_dmp_en(struct nvi_state *st)
 		dd = &nvi_dmp_devs[i];
 		if (dd->dev == DEV_AUX) {
 			if (st->snsr[DEV_AUX].enable & (1 << dd->aux_port)) {
+				irq_msk |= (1 << DEV_AUX);
 				en_msk |= (1 << DEV_AUX);
-				en_msk |= (1 << dd->aux_port);
+				en_msk |= (1 << (dd->aux_port + DEV_N_AUX));
 				en_msk |= dd->depend_msk;
 			}
 		} else if (dd->dev < DEV_AUX) {
 			if (st->snsr[dd->dev].enable) {
+				irq_msk |= (1 << dd->dev);
 				en_msk |= (1 << dd->dev);
 				en_msk |= dd->depend_msk;
 			}
 		}
 	}
 
-	st->aux.dmp_en_msk = en_msk >> DEV_N_AUX;
 	st->src[SRC_DMP].period_us_src = MPU_DMP_PERIOD_US;
+	st->src[SRC_MPU].period_us_src = MPU_DMP_PERIOD_US;
 	ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1, 0x03,
 			     __func__, &st->rc.gyro_config1);
 	ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2, 0x18,
@@ -499,27 +592,21 @@ static int nvi_dmp_en(struct nvi_state *st)
 	if (ret)
 		return ret;
 
-	for (i = 0; i < ARRAY_SIZE(nvi_dmp_devs); i++) {
-		dd = &nvi_dmp_devs[i];
-		if (dd->dev > DEV_AUX)
-			continue;
+	for (i = 0; i < ARRAY_SIZE(nvi_dmp_devs); i++)
+		ret |= nvi_dd_able(st, &nvi_dmp_devs[i], &en_msk);
+	if (ret)
+		return ret;
 
-		en = false;
-		if (dd->dev == DEV_AUX) {
-			if (en_msk & (1 << (dd->aux_port + DEV_N_AUX)))
-				en = true;
-		} else if (dd->dev < DEV_AUX) {
-			if (en_msk & (1 << dd->dev))
-				en = true;
-		}
-		ret = nvi_dd_able(st, dd, en);
+	st->aux.dmp_en_msk = en_msk >> DEV_N_AUX;
+	if (st->aux.dmp_en_msk) {
+		ret = nvi_aux_enable(st, __func__, true, true);
 		if (ret)
 			return ret;
 	}
-
-	ret = nvi_dmp_irq(st);
-	ret |= nvi_aux_delay(st, __func__);
+	ret = nvi_aux_delay(st, __func__);
+	ret |= nvi_dmp_irq(st, irq_msk & en_msk);
 	if (!ret) {
+		st->en_msk |= (en_msk & ((1 << DEV_N_AUX) - 1));
 		nvi_push_delay(st);
 		ret = nvi_reset(st, __func__, true, false, true);
 	}
diff --git a/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.h b/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.h
index 02ba21d6bb6..91b1d9a02fe 100644
--- a/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.h
+++ b/drivers/iio/imu/nvi_mpu/nvi_dmp_mpu.h
@@ -58,38 +58,38 @@
 #define D_0_232				(232)
 #define D_0_236				(236)
 
-#define D_1_2				(256 + 2)
-#define D_1_4				(256 + 4)
-#define D_1_8				(256 + 8)
-#define D_1_10				(256 + 10)
-#define D_1_24				(256 + 24)
-#define D_1_28				(256 + 28)
-#define D_1_36				(256 + 36)
-#define D_1_40				(256 + 40)
-#define D_1_44				(256 + 44)
-#define D_1_72				(256 + 72)
-#define D_1_74				(256 + 74)
-#define D_1_79				(256 + 79)
-#define D_1_88				(256 + 88)
-#define D_1_90				(256 + 90)
-#define D_1_92				(256 + 92)
-#define D_1_96				(256 + 96)
-#define D_1_98				(256 + 98)
-#define D_1_106				(256 + 106)
-#define D_1_108				(256 + 108)
-#define D_1_112				(256 + 112)
+#define D_1_2				(256 + 2)	/* 0x0102 */
+#define D_1_4				(256 + 4)	/* 0x0104 */
+#define D_1_8				(256 + 8)	/* 0x0108 */
+#define D_1_10				(256 + 10)	/* 0x010A */
+#define D_1_24				(256 + 24)	/* 0x0118 */
+#define D_1_28				(256 + 28)	/* 0x011C */
+#define D_1_36				(256 + 36)	/* 0x0124 */
+#define D_1_40				(256 + 40)	/* 0x0128 */
+#define D_1_44				(256 + 44)	/* 0x012C */
+#define D_1_72				(256 + 72)	/* 0x0148 */
+#define D_1_74				(256 + 74)	/* 0x014A */
+#define D_1_79				(256 + 79)	/* 0x014F */
+#define D_1_88				(256 + 88)	/* 0x0158 */
+#define D_1_90				(256 + 90)	/* 0x015A */
+#define D_1_92				(256 + 92)	/* 0x015C */
+#define D_1_96				(256 + 96)	/* 0x0160 */
+#define D_1_98				(256 + 98)	/* 0x0162 */
+#define D_1_106				(256 + 106)	/* 0x016A */
+#define D_1_108				(256 + 108)	/* 0x016C */
+#define D_1_112				(256 + 112)	/* 0x0170 */
 #define D_1_128				(256 + 144)
 #define D_1_152				(256 + 12)
-#define D_1_160				(256 + 160)
-#define D_1_176				(256 + 176)
-#define D_1_178				(256 + 178)
-#define D_1_218				(256 + 218)
-#define D_1_232				(256 + 232)
-#define D_1_236				(256 + 236)
-#define D_1_240				(256 + 240)
-#define D_1_244				(256 + 244)
-#define D_1_250				(256 + 250)
-#define D_1_252				(256 + 252)
+#define D_1_160				(256 + 160)	/* 0x01A0 */
+#define D_1_176				(256 + 176)	/* 0x01B0 */
+#define D_1_178				(256 + 178)	/* 0x01B2 */
+#define D_1_218				(256 + 218)	/* 0x01DA */
+#define D_1_232				(256 + 232)	/* 0x01E8 */
+#define D_1_236				(256 + 236)	/* 0x01EC */
+#define D_1_240				(256 + 240)	/* 0x01F0 */
+#define D_1_244				(256 + 244)	/* 0x01F4 */
+#define D_1_250				(256 + 250)	/* 0x01FA */
+#define D_1_252				(256 + 252)	/* 0x01FC */
 #define D_2_12				(512 + 12)
 #define D_2_96				(512 + 96)
 #define D_2_108				(512 + 108)
@@ -99,118 +99,118 @@
 #define D_2_244				(512 + 244)
 #define D_2_248				(512 + 248)
 #define D_2_252				(512 + 252)
-#define CPASS_BIAS_X			(30 * 16 + 4)
-#define CPASS_BIAS_Y			(30 * 16 + 8)
-#define CPASS_BIAS_Z			(30 * 16 + 12)
-#define CPASS_MTX_00			(32 * 16 + 4)
-#define CPASS_MTX_01			(32 * 16 + 8)
-#define CPASS_MTX_02			(36 * 16 + 12)
-#define CPASS_MTX_10			(33 * 16)
-#define CPASS_MTX_11			(33 * 16 + 4)
-#define CPASS_MTX_12			(33 * 16 + 8)
-#define CPASS_MTX_20			(33 * 16 + 12)
-#define CPASS_MTX_21			(34 * 16 + 4)
-#define CPASS_MTX_22			(34 * 16 + 8)
-#define D_EXT_GYRO_BIAS_X		(61 * 16)
-#define D_EXT_GYRO_BIAS_Y		(61 * 16 + 4)
-#define D_EXT_GYRO_BIAS_Z		(61 * 16 + 8)
-#define D_ACT0				(40 * 16)
-#define D_ACSX				(40 * 16 + 4)
-#define D_ACSY				(40 * 16 + 8)
-#define D_ACSZ				(40 * 16 + 12)
+#define CPASS_BIAS_X			(30 * 16 + 4)	/* 0x01E4 */
+#define CPASS_BIAS_Y			(30 * 16 + 8)	/* 0x01E8 */
+#define CPASS_BIAS_Z			(30 * 16 + 12)	/* 0x01EC */
+#define CPASS_MTX_00			(32 * 16 + 4)	/* 0x0204 */
+#define CPASS_MTX_01			(32 * 16 + 8)	/* 0x0208 */
+#define CPASS_MTX_02			(36 * 16 + 12)	/* 0x024C */
+#define CPASS_MTX_10			(33 * 16)	/* 0x0210 */
+#define CPASS_MTX_11			(33 * 16 + 4)	/* 0x0214 */
+#define CPASS_MTX_12			(33 * 16 + 8)	/* 0x0218 */
+#define CPASS_MTX_20			(33 * 16 + 12)	/* 0x021C */
+#define CPASS_MTX_21			(34 * 16 + 4)	/* 0x0224 */
+#define CPASS_MTX_22			(34 * 16 + 8)	/* 0x0228 */
+#define D_EXT_GYRO_BIAS_X		(61 * 16)	/* 0x03D0 */
+#define D_EXT_GYRO_BIAS_Y		(61 * 16 + 4)	/* 0x03D4 */
+#define D_EXT_GYRO_BIAS_Z		(61 * 16 + 8)	/* 0x03D8 */
+#define D_ACT0				(40 * 16)	/* 0x0280 */
+#define D_ACSX				(40 * 16 + 4)	/* 0x0284 */
+#define D_ACSY				(40 * 16 + 8)	/* 0x0288 */
+#define D_ACSZ				(40 * 16 + 12)	/* 0x028C */
 
-#define FLICK_MSG			(45 * 16 + 4)
-#define FLICK_COUNTER			(45 * 16 + 8)
-#define FLICK_LOWER			(45 * 16 + 12)
-#define FLICK_UPPER			(46 * 16 + 12)
+#define FLICK_MSG			(45 * 16 + 4)	/* 0x02D4 */
+#define FLICK_COUNTER			(45 * 16 + 8)	/* 0x02D8 */
+#define FLICK_LOWER			(45 * 16 + 12)	/* 0x02DC */
+#define FLICK_UPPER			(46 * 16 + 12)	/* 0x02EC */
 
 #define D_SMD_ENABLE			(18 * 16)	/* 0x0120 */
 #define D_SMD_MOT_THLD			(21 * 16 + 8)	/* 0x0158 */
 #define D_SMD_DELAY_THLD		(21 * 16 + 4)	/* 0x0154 */
 #define D_SMD_DELAY2_THLD		(21 * 16 + 12)	/* 0x015C */
-#define D_SMD_EXE_STATE			(22 * 16)
-#define D_SMD_DELAY_CNTR		(21 * 16)
+#define D_SMD_EXE_STATE			(22 * 16)	/* 0x0160 */
+#define D_SMD_DELAY_CNTR		(21 * 16)	/* 0x0150 */
 
-#define D_WF_GESTURE_TIME_THRSH		(25 * 16 + 8)
-#define D_WF_GESTURE_TILT_ERROR		(25 * 16 + 12)
-#define D_WF_GESTURE_TILT_THRSH		(26 * 16 + 8)
-#define D_WF_GESTURE_TILT_REJECT_THRSH	(26 * 16 + 12)
+#define D_WF_GESTURE_TIME_THRSH		(25 * 16 + 8)	/* 0x0198 */
+#define D_WF_GESTURE_TILT_ERROR		(25 * 16 + 12)	/* 0x019C */
+#define D_WF_GESTURE_TILT_THRSH		(26 * 16 + 8)	/* 0x01A8 */
+#define D_WF_GESTURE_TILT_REJECT_THRSH	(26 * 16 + 12)	/* 0x01AC */
 
 #define D_AUTH_OUT			(992)
 #define D_AUTH_IN			(996)
 #define D_AUTH_A			(1000)
 #define D_AUTH_B			(1004)
 
-#define D_PEDSTD_BP_B			(768 + 0x1C)
-#define D_PEDSTD_BP_A4			(768 + 0x40)
-#define D_PEDSTD_BP_A3			(768 + 0x44)
-#define D_PEDSTD_BP_A2			(768 + 0x48)
-#define D_PEDSTD_BP_A1			(768 + 0x4C)
-#define D_PEDSTD_SB			(768 + 0x28)
-#define D_PEDSTD_SB_TIME		(768 + 0x2C)
-#define D_PEDSTD_PEAKTHRSH		(768 + 0x98)
-#define D_PEDSTD_TIML			(768 + 0x2A)
-#define D_PEDSTD_TIMH			(768 + 0x2E)
-#define D_PEDSTD_PEAK			(768 + 0x94)
-#define D_PEDSTD_STEPCTR		(768 + 0x60)
-#define D_PEDSTD_STEPCTR2		(58 * 16 + 8)
+#define D_PEDSTD_BP_B			(768 + 0x1C)	/* 0x031C */
+#define D_PEDSTD_BP_A4			(768 + 0x40)	/* 0x0340 */
+#define D_PEDSTD_BP_A3			(768 + 0x44)	/* 0x0344 */
+#define D_PEDSTD_BP_A2			(768 + 0x48)	/* 0x0348 */
+#define D_PEDSTD_BP_A1			(768 + 0x4C)	/* 0x034C */
+#define D_PEDSTD_SB			(768 + 0x28)	/* 0x0328 */
+#define D_PEDSTD_SB_TIME		(768 + 0x2C)	/* 0x032C */
+#define D_PEDSTD_PEAKTHRSH		(768 + 0x98)	/* 0x0398 */
+#define D_PEDSTD_TIML			(768 + 0x2A)	/* 0x032A */
+#define D_PEDSTD_TIMH			(768 + 0x2E)	/* 0x032E */
+#define D_PEDSTD_PEAK			(768 + 0x94)	/* 0x0394 */
+#define D_PEDSTD_STEPCTR		(768 + 0x60)	/* 0x0360 */
+#define D_PEDSTD_STEPCTR2		(58 * 16 + 8)	/* 0x03A8 */
 #define D_PEDSTD_TIMECTR		(964)
-#define D_PEDSTD_DECI			(768 + 0xA0)
-#define D_PEDSTD_SB2			(60 * 16 + 14)
-#define D_STPDET_TIMESTAMP		(28 * 16 + 8)
+#define D_PEDSTD_DECI			(768 + 0xA0)	/* 0x03A0 */
+#define D_PEDSTD_SB2			(60 * 16 + 14)	/* 0x03CE */
+#define D_STPDET_TIMESTAMP		(28 * 16 + 8)	/* 0x01C8 */
 #define D_PEDSTD_DRIVE_STATE		(58)
 
 #define D_HOST_NO_MOT			(976)
 #define D_ACCEL_BIAS			(660)
 
-#define D_BM_BATCH_CNTR			(27 * 16 + 4)
-#define D_BM_BATCH_THLD			(27 * 16 + 12)
-#define D_BM_ENABLE			(28 * 16 + 6)
-#define D_BM_NUMWORD_TOFILL		(28 * 16 + 4)
+#define D_BM_BATCH_CNTR			(27 * 16 + 4)	/* 0x01B4 */
+#define D_BM_BATCH_THLD			(27 * 16 + 12)	/* 0x01BC */
+#define D_BM_ENABLE			(28 * 16 + 6)	/* 0x01C6 */
+#define D_BM_NUMWORD_TOFILL		(28 * 16 + 4)	/* 0x01C4 */
 
-#define D_SO_DATA			(4 * 16 + 2)
+#define D_SO_DATA			(4 * 16 + 2)	/* 0x0042 */
 
-#define D_P_HW_ID			(22 * 16 + 10)
-#define D_P_INIT			(22 * 16 + 2)
+#define D_P_HW_ID			(22 * 16 + 10)	/* 0x016A */
+#define D_P_INIT			(22 * 16 + 2)	/* 0x0162 */
 
 #define D_DMP_RUN_CNTR			(24 * 16)	/* 0x0180 */
 
-#define D_ODR_S0			(45 * 16 + 8)
-#define D_ODR_S1			(45 * 16 + 12)
-#define D_ODR_S2			(45 * 16 + 10)
-#define D_ODR_S3			(45 * 16 + 14)
-#define D_ODR_S4			(46 * 16 + 8)
-#define D_ODR_S5			(46 * 16 + 12)
+#define D_ODR_S0			(45 * 16 + 8)	/* 0x02D8 */
+#define D_ODR_S1			(45 * 16 + 12)	/* 0x02DC */
+#define D_ODR_S2			(45 * 16 + 10)	/* 0x02DA */
+#define D_ODR_S3			(45 * 16 + 14)	/* 0x02DE */
+#define D_ODR_S4			(46 * 16 + 8)	/* 0x02E8 */
+#define D_ODR_S5			(46 * 16 + 12)	/* 0x02EC */
 #define D_ODR_S6			(46 * 16 + 10)	/* 0x02EA */
-#define D_ODR_S7			(46 * 16 + 14)
-#define D_ODR_S8			(42 * 16 + 8)
-#define D_ODR_S9			(42 * 16 + 12)
+#define D_ODR_S7			(46 * 16 + 14)	/* 0x02EE */
+#define D_ODR_S8			(42 * 16 + 8)	/* 0x02A8 */
+#define D_ODR_S9			(42 * 16 + 12)	/* 0x02AC */
 
-#define D_ODR_CNTR_S0			(45 * 16)
-#define D_ODR_CNTR_S1			(45 * 16 + 4)
-#define D_ODR_CNTR_S2			(45 * 16 + 2)
-#define D_ODR_CNTR_S3			(45 * 16 + 6)
-#define D_ODR_CNTR_S4			(46 * 16)
-#define D_ODR_CNTR_S5			(46 * 16 + 4)
+#define D_ODR_CNTR_S0			(45 * 16)	/* 0x02D0 */
+#define D_ODR_CNTR_S1			(45 * 16 + 4)	/* 0x02D4 */
+#define D_ODR_CNTR_S2			(45 * 16 + 2)	/* 0x02D2 */
+#define D_ODR_CNTR_S3			(45 * 16 + 6)	/* 0x02D6 */
+#define D_ODR_CNTR_S4			(46 * 16)	/* 0x02E0 */
+#define D_ODR_CNTR_S5			(46 * 16 + 4)	/* 0x02E4 */
 #define D_ODR_CNTR_S6			(46 * 16 + 2)	/* 0x02E2 */
-#define D_ODR_CNTR_S7			(46 * 16 + 6)
-#define D_ODR_CNTR_S8			(42 * 16)
-#define D_ODR_CNTR_S9			(42 * 16 + 4)
+#define D_ODR_CNTR_S7			(46 * 16 + 6)	/* 0x02E6 */
+#define D_ODR_CNTR_S8			(42 * 16)	/* 0x02A0 */
+#define D_ODR_CNTR_S9			(42 * 16 + 4)	/* 0x02A4 */
 
-#define D_FS_LPQ0			(59 * 16)
-#define D_FS_LPQ1			(59 * 16 + 4)
-#define D_FS_LPQ2			(59 * 16 + 8)
-#define D_FS_LPQ3			(59 * 16 + 12)
+#define D_FS_LPQ0			(59 * 16)	/* 0x03B0 */
+#define D_FS_LPQ1			(59 * 16 + 4)	/* 0x03B4 */
+#define D_FS_LPQ2			(59 * 16 + 8)	/* 0x03B8 */
+#define D_FS_LPQ3			(59 * 16 + 12)	/* 0x03BC */
 
-#define D_FS_Q0				(12 * 16)
-#define D_FS_Q1				(12 * 16 + 4)
-#define D_FS_Q2				(12 * 16 + 8)
-#define D_FS_Q3				(12 * 16 + 12)
+#define D_FS_Q0				(12 * 16)	/* 0x00C0 */
+#define D_FS_Q1				(12 * 16 + 4)	/* 0x00C4 */
+#define D_FS_Q2				(12 * 16 + 8)	/* 0x00C8 */
+#define D_FS_Q3				(12 * 16 + 12)	/* 0x00CC */
 
-#define D_FS_9Q0			(2 * 16)
-#define D_FS_9Q1			(2 * 16 + 4)
-#define D_FS_9Q2			(2 * 16 + 8)
-#define D_FS_9Q3			(2 * 16 + 12)
+#define D_FS_9Q0			(2 * 16)	/* 0x0020 */
+#define D_FS_9Q1			(2 * 16 + 4)	/* 0x0024 */
+#define D_FS_9Q2			(2 * 16 + 8)	/* 0x0028 */
+#define D_FS_9Q3			(2 * 16 + 12)	/* 0x002C */
 
 #define KEY_CFG_OUT_ACCL		CFG_OUT_ACCL
 #define KEY_CFG_OUT_GYRO		CFG_OUT_GYRO
diff --git a/drivers/iio/imu/nvi_mpu/nvi_mpu.c b/drivers/iio/imu/nvi_mpu/nvi_mpu.c
index ba1cc6cb718..79d2ad22521 100644
--- a/drivers/iio/imu/nvi_mpu/nvi_mpu.c
+++ b/drivers/iio/imu/nvi_mpu/nvi_mpu.c
@@ -276,8 +276,6 @@ int inv_init_6050(struct nvi_state *st)
 	short index;
 	struct inv_chip_info_s *chip_info = &st->chip_info;
 
-	st->snsr[DEV_ACC].matrix = true;
-	st->snsr[DEV_GYR].matrix = true;
 	if (st->snsr[DEV_ACC].cfg.thresh_hi > 0)
 		st->en_msk |= (1 << EN_LP);
 	else
@@ -345,8 +343,6 @@ int inv_init_6050(struct nvi_state *st)
 
 static int nvi_init_6500(struct nvi_state *st)
 {
-	st->snsr[DEV_ACC].matrix = true;
-	st->snsr[DEV_GYR].matrix = true;
 	if (st->snsr[DEV_ACC].cfg.thresh_hi > 0)
 		st->en_msk |= (1 << EN_LP);
 	else
diff --git a/drivers/iio/magnetometer/nvi_ak89xx.c b/drivers/iio/magnetometer/nvi_ak89xx.c
index 75bf39cf0e1..9eed90a9443 100644
--- a/drivers/iio/magnetometer/nvi_ak89xx.c
+++ b/drivers/iio/magnetometer/nvi_ak89xx.c
@@ -1468,6 +1468,7 @@ static int akm_id_dev(struct akm_state *st, const char *name)
 				nmp.addr = st->i2c_addr;
 				nmp.reg = st->hal->reg_mode;
 				nmp.ctrl = 1;
+				nmp.dmp_ctrl = nmp.ctrl;
 				nmp.data_out = AKM_MODE_SINGLE;
 				nmp.delay_ms = AKM_HW_DELAY_TSM_MS;
 				nmp.delay_us = 0;