ARM: tegra: dvfs: Swap CL-DVFS barrier and read fence

ARM: tegra: dvfs: Swap CL-DVFS barrier and read fence

To assure completion of the previous writes through Tegra interconnect
CL-DVFS driver used memory write barrier followed by read fence.

Removed the preceding memory barrier, since it has no additional to
read fence effect (given Tegra IO mapping as device). Added barrier
after read fence. The latter is needed to avoid partial overlap of
read operation and propagation delay after read (if any). Such overlap
is possible because architectural timer used as delay counter is not
MMIO register.

Bug 1484343

Change-Id: Ic0bcbeb980e5b728e5b1ee949f1aacfe94309931
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/390284
Reviewed-by: Hoang Pham <hopham@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>