clock: tegra21: Don't disable PLLE under h/w control

clock: tegra21: Don't disable PLLE under h/w control

Prevented s/w disable operation to actually disable PLLE if PLLE
control is already transferred to h/w sequencer. Updated s/w disable
procedure in case when h/w sequencer is not engaged.

Bug 200068549

Change-Id: Idc97de202064fb86f438a75b603f9bc437eb392c
Signed-off-by: Joy Wang <joyw@nvidia.com>
Reviewed-on: http://git-master/r/667114
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/810576
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: TW Chiu <twchiu@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
GVS: Gerrit_Virtual_Submit