dvfs: tegra: Add DFLL calibration option to set Vmin

dvfs: tegra: Add DFLL calibration option to set Vmin

Added an option to forcefully set Vmin voltage during DFLL Fmax at Vmin
calibration; option is selected by TEGRA_CL_DVFS_CALIBRATE_FORCE_VMIN
platform flag that can be set in DT DFLL node. Considerations for
setting the flag:

- if SoC includes power management controller that changes DFLL voltage
  while CPU cluster is idle, and restores/forces voltage on idle exit,
  the following trade-offs are applied:

  a) if TEGRA_CL_DVFS_CALIBRATE_FORCE_VMIN is selected, DFLL
     calibration is accurate, but calibration time is increased by two
     sample periods and target module maybe under-clocked during that
     time.
  b) if TEGRA_CL_DVFS_CALIBRATE_FORCE_VMIN is not selected, calibration
     results depend on whether flag TEGRA_CL_DVFS_DEFER_FORCE_CALIBRATE
     is set (see commit a6cef0b3caa4a1de31d392d385a401b58c0ec233).

- if SoC does not change DFLL voltage in CPU cluster idle state, no
  need to select TEGRA_CL_DVFS_CALIBRATE_FORCE_VMIN flag.

This commit does not select set Vmin option on any Tegra platform.

Bug 1632845

Change-Id: I43abcd43d5c89a659eda0017d7caed9a8f8fb441
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/727772
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>