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(parent: 3d39c66) | patch
ARM: tegra: dvfs: Re-factor DFLL output force control
authorAlex Frid <afrid@nvidia.com>
Sun, 16 Mar 2014 05:35:50 +0000 (22:35 -0700)
committerYu-Huan Hsu <yhsu@nvidia.com>
Wed, 19 Mar 2014 23:05:02 +0000 (16:05 -0700)
commitad8caa9c93e56b0158fc9c55411a41094b1e59a5
tree665672c5997119dbe73a30b42048cd32bc28480atree | snapshot
parent3d39c66cbf286544f9c2c4ccacb44db306d73d40commit | diff
ARM: tegra: dvfs: Re-factor DFLL output force control

Implemented output force register access functions, and re-factored
clients, respectively.

Updated debugfs force output control: enabled I2C PMIC control, fixed
order (swapped) of locking DFLL register access and enabling access
clock.

Change-Id: I33d656dfb384e97f55b46a0404578e6b0bc9b873
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/383657
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/mach-tegra/tegra_cl_dvfs.c diff | blob | history