PCIE: tegra: resume timing correction

PCIE: tegra: resume timing correction

The time from +1.05V_RUN to PEX_L1_RST_L signal
(PEX_L1_RST_N on T124) should be 100ms minimum

Bug 1500840

Change-Id: I170ed3225f80b5ef0ccaf4b38565d3adf94a674a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/402841
(cherry picked from commit d380528e5e865437681c21befc40de430b39f9a9)
Reviewed-on: http://git-master/r/406394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>