arm: tegra: hawkeye: update panel timings
The DSI block requires Htotal to be evenly
divisible across all data lanes in ganged mode.
The panel vendor provided an updated
set of panel timings that satisfies this
requirement.
Bug
1619492
Change-Id: I60ea7d739727eeca9baa5987388aaf6c24248842
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/728760
(cherry picked from commit
1cc89eea5f1d4be79d2c031c8d460525797c8a89)
Reviewed-on: http://git-master/r/741035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>