ARM: tegra: clock: Use exact PLL rate in resume

ARM: tegra: clock: Use exact PLL rate in resume

Removed 1Hz margin from target rate request during PLL resume.
Although the PLL output rate is restored correctly in any case, PLL
dividers settings may differ from tabulated targets (if any) when non
exact rate is requested.

Bug 1479262

Change-Id: I78a338145f8f552b71362fffb1bdb608f620e548
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/380498
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>