video: tegra: nvmap: fix kernel cache maintenance

video: tegra: nvmap: fix kernel cache maintenance

On begin cpu access, flush the memory being accessed.
On end cpu access, update latest entries in pages.
Here we assume that client do not access memory that is currently
part of a DMA transfer.

Change-Id: I0410878682188358940af0cf3275ea6e5c59321b
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/390723
(cherry picked from commit b30505d6e98ca74b727f1adebc4f5d3a65cdf246)
Reviewed-on: http://git-master/r/405094
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>