dvfs: tegra: Update conditions to skip DVFS enable

dvfs: tegra: Update conditions to skip DVFS enable

Moved check for conditions when DVFS table initialization on particular
clock can be skipped to a separate function. This function is checking
the following three conditions (each of them allows to skip):

a) clock can reach maximum rate at minimum voltage - same as before this
commit

b) UART clock has a flat DVFS table - DVFS rates in the entire voltage
range are the same. Before this commit the flat table condition was not
limited to UART. However, in general, it is covered by (a) when maximum
clock rate is at/below maximum DVFS rate. UART is a special case, since
UART driver may use its own baud rate divider directly, and apply baud
rate limits based on platform data transparently to DVFS.

c) single-voltage range (minimum and nominal DVFS rail voltages are the
same). This condition is applied to non-shared bus clock provided clock
maximum rate is at/below maximum DVFS rate (the shared bus exception is
added, because shared buses may need DVFS initialized to define possible
rates). It is a new condition introduced by this commit.

Bug 1602537
Bug 1625003

Change-Id: I8d40cabcf8dd233931e15ca95a52c7ef2df516a2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/726568
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>