ARM: tegra: dvfs: Add DFLL output clamping interface

ARM: tegra: dvfs: Add DFLL output clamping interface

Added DFLL output voltage clamping interface: set maximum and minimum
voltage limits the same to the lowest safe (at current temperature and
tuning range) level. In this state target clock rate is ignored, DFLL
output rate is determined by the clamped limit. Interface has clamp
control parameter, and can be used to release clamping as well. In any
case clamping is released when switching out of closed loop mode.

This interface is intended to be used during SiMon grading only.

Bug 1343366

Change-Id: Id004f520bdfc85376e3ff00e83041a3be7d79ee4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/383658
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>