tegra: usb: phy: increase timeout for bus connect

tegra: usb: phy: increase timeout for bus connect

Increasing timeout to 25ms for bus connect and bus idle.
New bus_reset times out for the first time, fix this by
changing USB phy mode to HSIC.

Bug 922444
Reviewed-on: http://git-master/r/73367

Change-Id: I717c98a4e3e8d943a8a922c70442211a0f7fd9be
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78017
Reviewed-by: Automatic_Commit_Validation_User
Rebase-Id: R7387f2ae89ab6ff62e93b70ce4d22afcbb6962a6