ARM: tegra12: clock: Update PLLC2/3 settings

ARM: tegra12: clock: Update PLLC2/3 settings

- Set VCO range to PROD limits 650MHz/1.3GHz
- Increased locking timeout to 360us (x2 of PROD)
- Fixed initial post-divider setting - set it to 1 for intended
  ratio 1:2 (current setting 2 results in 1:3 ratio).
- Since new VCOmin is not aligned at reference rate 12MHz boundary,
  configuration of some close/above VCOmin rates may fail crossing
  VCOmax limit. Clamp VCO output to maximum in such case instead of
  failing configuration.

Bug 1494125

Change-Id: I23d960a65ee119c0a2dd4597340f700cd1fb897e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/392209
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>