misc: tegra-profiler: add Cortex-A57 events

[sojka/nv-tegra/linux-3.10.git] / drivers / misc / tegra-profiler / armv8_events.h

diff --git a/drivers/misc/tegra-profiler/armv8_events.h b/drivers/misc/tegra-profiler/armv8_events.h
index 1d675ddddabf5517af181117e663cae0934a9db3..7c21437aeb5d13e1d3c14b4aecd39bf73acccd60 100644 (file)
--- a/drivers/misc/tegra-profiler/armv8_events.h
+++ b/drivers/misc/tegra-profiler/armv8_events.h
@@ -22,13 +22,14 @@
 #define QUADD_AA64_CPU_IMP_NVIDIA      'N'
 
 #define QUADD_AA64_CPU_IDCODE_CORTEX_A57       0x01
-
+#define QUADD_AA64_CPU_IDCODE_CORTEX_A53       0x03
 
 enum {
        QUADD_AA64_CPU_TYPE_UNKNOWN = 1,
+       QUADD_AA64_CPU_TYPE_UNKNOWN_IMP,
        QUADD_AA64_CPU_TYPE_ARM,
+       QUADD_AA64_CPU_TYPE_CORTEX_A53,
        QUADD_AA64_CPU_TYPE_CORTEX_A57,
-       QUADD_AA64_CPU_TYPE_UNKNOWN_IMP,
        QUADD_AA64_CPU_TYPE_DENVER,
 };
 
@@ -128,6 +129,16 @@ enum {
        QUADD_ARMV8_HW_EVENT_BUS_CYCLES                         = 0x1D,
 };
 
+/*
+ * ARMv8 Cortex-A57 specific event types.
+ */
+enum {
+       QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_LD    = 0x42,
+       QUADD_ARMV8_A57_HW_EVENT_L1D_CACHE_REFILL_ST    = 0x43,
+       QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_LD    = 0x52,
+       QUADD_ARMV8_A57_HW_EVENT_L2D_CACHE_REFILL_ST    = 0x53,
+};
+
 #define QUADD_ARMV8_UNSUPPORTED_EVENT  0xff00
 #define QUADD_ARMV8_CPU_CYCLE_EVENT    0xffff