1 /* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 * This software is licensed under the terms of the GNU General Public
4 * License version 2, as published by the Free Software Foundation, and
5 * may be copied, distributed, and modified under those terms.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/time.h>
15 #include <linux/delay.h>
17 #include "nvi_dmp_icm.h"
19 #define BYTES_PER_SENSOR 6
20 /* full scale and LPF setting */
21 #define ICM_SELFTEST_GYRO_FS ((0 << 3) | 1)
22 #define ICM_SELFTEST_ACCEL_FS ((7 << 3) | 1)
23 /* register settings */
24 #define ICM_SELFTEST_GYRO_SMPLRT_DIV 10
25 #define ICM_SELFTEST_GYRO_AVGCFG 3
26 #define ICM_SELFTEST_ACCEL_SMPLRT_DIV 10
27 #define ICM_SELFTEST_ACCEL_DEC3_CFG 2
28 #define ICM_SELFTEST_GYRO_SENS (32768 / 250)
29 #define BIT_ACCEL_CTEN 0x1C
30 #define BIT_GYRO_CTEN 0x38
31 /* wait time before collecting data */
32 #define ICM_MAX_PACKETS 20
33 #define ICM_SELFTEST_WAIT_TIME (ICM_MAX_PACKETS * 10)
34 #define ICM_GYRO_ENGINE_UP_TIME 50
35 #define ICM_ST_STABLE_TIME 20
36 #define ICM_GYRO_SCALE 131
37 #define ICM_ST_PRECISION 1000
38 #define ICM_ST_ACCEL_FS_MG 2000UL
39 #define ICM_ST_SCALE 32768
40 #define ICM_ST_TRY_TIMES 2
41 #define ICM_ST_SAMPLES 200
42 #define ICM_ACCEL_ST_SHIFT_DELTA_MIN 500
43 #define ICM_ACCEL_ST_SHIFT_DELTA_MAX 1500
44 #define ICM_GYRO_CT_SHIFT_DELTA 500
45 /* Gyro Offset Max Value (dps) */
46 #define ICM_GYRO_OFFSET_MAX 20
47 /* Gyro Self Test Absolute Limits ST_AL (dps) */
48 #define ICM_GYRO_ST_AL 60
49 /* Accel Self Test Absolute Limits ST_AL (mg) */
50 #define ICM_ACCEL_ST_AL_MIN ((225 * ICM_ST_SCALE \
51 / ICM_ST_ACCEL_FS_MG) * ICM_ST_PRECISION)
52 #define ICM_ACCEL_ST_AL_MAX ((675 * ICM_ST_SCALE \
53 / ICM_ST_ACCEL_FS_MG) * ICM_ST_PRECISION)
56 static const u16 icm_st_tb[256] = {
57 2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808,
58 2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041,
59 3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293,
60 3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566,
61 3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862,
62 3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182,
63 4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528,
64 4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903,
65 4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310,
66 5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750,
67 5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226,
68 6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742,
69 6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301,
70 7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906,
71 7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561,
72 8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270,
73 9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038,
74 10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870,
75 10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771,
76 11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746,
77 12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802,
78 13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946,
79 15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184,
80 16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526,
81 17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978,
82 19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550,
83 20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253,
84 22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097,
85 24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093,
86 26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255,
87 28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597,
88 30903, 31212, 31524, 31839, 32157, 32479, 32804
92 * inv_icm_st_gyr_chk() - check gyro self test.
93 * this function returns zero as success. A non-zero return
94 * value indicates failure in self test.
95 * @*st: main data structure.
96 * @*reg_avg: average value of normal test.
97 * @*st_avg: average value of self test
99 static int inv_icm_st_gyr_chk(struct nvi_state *st, int *reg_avg, int *st_avg)
103 int otp_value_zero = 0;
104 int st_shift_prod[AXIS_N];
105 int st_shift_cust[AXIS_N];
108 regs = &st->st_data[DEV_GYR][0];
109 if (st->sts & NVI_DBG_SPEW_MSG)
110 dev_info(&st->i2c->dev, "%s data: %02x %02x %02x\n",
111 __func__, regs[0], regs[1], regs[2]);
112 for (i = 0; i < AXIS_N; i++) {
114 st_shift_prod[i] = icm_st_tb[regs[i] - 1];
116 st_shift_prod[i] = 0;
120 if (st->sts & NVI_DBG_SPEW_MSG)
121 dev_info(&st->i2c->dev,
122 "%s st_shift_prod: %+d %+d %+d\n", __func__,
123 st_shift_prod[0], st_shift_prod[1], st_shift_prod[2]);
124 for (i = 0; i < AXIS_N; i++) {
125 st_shift_cust[i] = st_avg[i] - reg_avg[i];
126 if (!otp_value_zero) {
127 /* Self Test Pass/Fail Criteria A */
128 if (st_shift_cust[i] < (ICM_GYRO_CT_SHIFT_DELTA *
131 if (st->sts & NVI_DBG_SPEW_MSG)
132 dev_info(&st->i2c->dev,
133 "%s FAIL A axis %d\n",
137 /* Self Test Pass/Fail Criteria B */
138 if (st_shift_cust[i] < (ICM_GYRO_ST_AL *
139 ICM_SELFTEST_GYRO_SENS *
142 if (st->sts & NVI_DBG_SPEW_MSG)
143 dev_info(&st->i2c->dev,
144 "%s FAIL B axis %d\n",
150 if (st->sts & NVI_DBG_SPEW_MSG)
151 dev_info(&st->i2c->dev, "%s st_shift_cust: %+d %+d %+d\n",
153 st_shift_cust[0], st_shift_cust[1], st_shift_cust[2]);
155 /* Self Test Pass/Fail Criteria C */
156 for (i = 0; i < AXIS_N; i++) {
157 if (abs(reg_avg[i]) > (ICM_GYRO_OFFSET_MAX *
158 ICM_SELFTEST_GYRO_SENS *
161 if (st->sts & NVI_DBG_SPEW_MSG)
162 dev_info(&st->i2c->dev,
163 "%s FAIL C axis %d\n",
173 * inv_icm_st_acc_chk() - check accel self test.
174 * this function returns zero as success. A non-zero return
175 * value indicates failure in self test.
176 * @*st: main data structure.
177 * @*reg_avg: average value of normal test.
178 * @*st_avg: average value of self test
180 static int inv_icm_st_acc_chk(struct nvi_state *st, int *reg_avg, int *st_avg)
184 int st_shift_prod[AXIS_N];
185 int st_shift_cust[AXIS_N];
186 int otp_value_zero = 0;
189 regs = &st->st_data[DEV_ACC][0];
190 if (st->sts & NVI_DBG_SPEW_MSG)
191 dev_info(&st->i2c->dev, "%s data: %02x %02x %02x\n",
192 __func__, regs[0], regs[1], regs[2]);
193 for (i = 0; i < AXIS_N; i++) {
195 st_shift_prod[i] = icm_st_tb[regs[i] - 1];
197 st_shift_prod[i] = 0;
202 if (st->sts & NVI_DBG_SPEW_MSG)
203 dev_info(&st->i2c->dev,
204 "%s st_shift_prod: %+d %+d %+d\n", __func__,
205 st_shift_prod[0], st_shift_prod[1], st_shift_prod[2]);
206 if (!otp_value_zero) {
207 /* Self Test Pass/Fail Criteria A */
208 for (i = 0; i < AXIS_N; i++) {
209 st_shift_cust[i] = st_avg[i] - reg_avg[i];
210 if (st_shift_cust[i] < (ICM_ACCEL_ST_SHIFT_DELTA_MIN *
213 if (st->sts & NVI_DBG_SPEW_MSG)
214 dev_info(&st->i2c->dev,
215 "%s FAIL A (min) axis %d\n",
218 if (st_shift_cust[i] > (ICM_ACCEL_ST_SHIFT_DELTA_MAX *
221 if (st->sts & NVI_DBG_SPEW_MSG)
222 dev_info(&st->i2c->dev,
223 "%s FAIL A (max) axis %d\n",
228 /* Self Test Pass/Fail Criteria B */
229 for (i = 0; i < AXIS_N; i++) {
230 st_shift_cust[i] = abs(st_avg[i] - reg_avg[i]);
231 if ((st_shift_cust[i] < ICM_ACCEL_ST_AL_MIN) ||
232 (st_shift_cust[i] > ICM_ACCEL_ST_AL_MAX)) {
234 if (st->sts & NVI_DBG_SPEW_MSG)
235 dev_info(&st->i2c->dev,
236 "%s FAIL B axis %d\n",
242 if (st->sts & NVI_DBG_SPEW_MSG)
243 dev_info(&st->i2c->dev, "%s st_shift_cust: %+d %+d %+d\n",
245 st_shift_cust[0], st_shift_cust[1], st_shift_cust[2]);
249 static int inv_icm_st_setup(struct nvi_state *st)
254 /* Wake up and stop sensors */
255 ret = nvi_pm_wr(st, __func__, INV_CLK_PLL, BIT_PWR_PRESSURE_STBY |
256 BIT_PWR_ACCEL_STBY | BIT_PWR_GYRO_STBY, 0);
257 /* Perform a soft-reset of the chip
258 * This will clear any prior states in the chip
260 ret |= nvi_wr_pm1(st, __func__, BIT_H_RESET);
264 msleep(POWER_UP_TIME);
266 ret = nvi_wr_pm1(st, __func__, INV_CLK_PLL);
267 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->user_ctrl, BIT_FIFO_EN,
268 __func__, &st->rc.user_ctrl);
270 ret |= nvi_wr_fifo_cfg(st, -1);
272 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->lp_config, 0x70,
273 __func__, &st->rc.lp_config);
274 /* Configure FSR and DLPF */
275 ret |= nvi_i2c_write_rc(st, &st->hal->reg->smplrt[DEV_GYR],
276 ICM_SELFTEST_GYRO_SMPLRT_DIV, __func__,
277 (u8 *)&st->rc.smplrt[DEV_GYR], true);
278 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1,
279 ICM_SELFTEST_GYRO_FS,
280 __func__, &st->rc.gyro_config1);
281 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2,
282 ICM_SELFTEST_GYRO_AVGCFG,
283 __func__, &st->rc.gyro_config2);
284 ret |= nvi_i2c_write_rc(st, &st->hal->reg->smplrt[DEV_ACC],
285 ICM_SELFTEST_ACCEL_SMPLRT_DIV, __func__,
286 (u8 *)&st->rc.smplrt[DEV_ACC], true);
287 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config,
288 ICM_SELFTEST_ACCEL_FS,
289 __func__, &st->rc.accel_config);
290 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
291 ICM_SELFTEST_ACCEL_DEC3_CFG,
292 __func__, &st->rc.accel_config2);
296 /* Read selftest values */
297 for (axis = 0; axis < AXIS_N; axis++)
298 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_g[axis],
299 &st->st_data[DEV_GYR][axis]);
301 for (axis = 0; axis < AXIS_N; axis++)
302 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_a[axis],
303 &st->st_data[DEV_ACC][axis]);
305 ret |= nvi_pm_wr(st, __func__, INV_CLK_PLL,
306 BIT_PWR_PRESSURE_STBY, 0x70);
310 msleep(ICM_GYRO_ENGINE_UP_TIME);
314 static int inv_icm_st_rd(struct nvi_state *st, int dev,
315 int *sum_result, int *s)
319 u8 d[ICM_MAX_PACKETS * BYTES_PER_SENSOR];
326 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, 0,
327 __func__, (u8 *)&st->rc.fifo_en, false);
329 ret |= nvi_i2c_wr(st, &st->hal->reg->fifo_rst,
331 ret |= nvi_i2c_wr(st, &st->hal->reg->fifo_rst,
336 while (*s < ICM_ST_SAMPLES) {
337 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en,
338 st->hal->dev[dev]->fifo_en_msk,
339 __func__, (u8 *)&st->rc.fifo_en, false);
343 msleep(ICM_SELFTEST_WAIT_TIME);
344 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, 0,
345 __func__, (u8 *)&st->rc.fifo_en, false);
349 ret = nvi_i2c_rd(st, &st->hal->reg->fifo_count_h, d);
353 fifo_count = be16_to_cpup((__be16 *)(&d[0]));
354 if (st->sts & NVI_DBG_SPEW_MSG)
355 dev_info(&st->i2c->dev, "%s fifo_count=%d\n",
356 __func__, fifo_count);
357 if (ICM_MAX_PACKETS * BYTES_PER_SENSOR < fifo_count) {
358 ret = nvi_i2c_r(st, st->hal->reg->fifo_rw.bank,
359 st->hal->reg->fifo_rw.reg,
360 ICM_MAX_PACKETS * BYTES_PER_SENSOR, d);
361 packet_count = ICM_MAX_PACKETS;
363 ret = nvi_i2c_r(st, st->hal->reg->fifo_rw.bank,
364 st->hal->reg->fifo_rw.reg,
366 packet_count = fifo_count / BYTES_PER_SENSOR;
372 while (i < packet_count) {
373 for (j = 0; j < AXIS_N; j++) {
374 t = 2 * j + i * BYTES_PER_SENSOR;
375 vals[j] = (s16)be16_to_cpup((__be16 *)(&d[t]));
376 sum_result[j] += vals[j];
378 if (st->sts & NVI_DBG_SPEW_MSG)
379 dev_info(&st->i2c->dev,
380 "%s %s %d: %+d %+d %+d\n",
381 __func__, st->snsr[dev].cfg.name,
382 *s, vals[0], vals[1], vals[2]);
392 * inv_icm_st_acc_do() - do the actual test of self testing
394 static int inv_icm_st_acc_do(struct nvi_state *st,
395 int *accel_result, int *accel_st_result)
402 for (i = 0; i < AXIS_N; i++) {
404 accel_st_result[i] = 0;
407 ret = inv_icm_st_rd(st, DEV_ACC, accel_result, &accel_s);
408 if (ret || accel_s <= 0)
411 for (j = 0; j < AXIS_N; j++) {
412 accel_result[j] = accel_result[j] / accel_s;
413 accel_result[j] *= ICM_ST_PRECISION;
415 /* Set Self-Test Bit */
416 ret = nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
417 BIT_ACCEL_CTEN | ICM_SELFTEST_ACCEL_DEC3_CFG,
418 __func__, &st->rc.accel_config2);
422 msleep(ICM_ST_STABLE_TIME);
424 ret = inv_icm_st_rd(st, DEV_ACC, accel_st_result, &accel_s);
425 if (ret || accel_s <= 0)
428 for (j = 0; j < AXIS_N; j++) {
429 accel_st_result[j] = accel_st_result[j] / accel_s;
430 accel_st_result[j] *= ICM_ST_PRECISION;
432 if (st->sts & NVI_DBG_SPEW_MSG)
433 dev_info(&st->i2c->dev, "%s %d, %d, %d\n", __func__,
434 accel_result[0], accel_result[1], accel_result[2]);
440 * inv_icm_st_gyr_do() - do the actual test of self testing
442 static int inv_icm_st_gyr_do(struct nvi_state *st,
443 int *gyro_result, int *gyro_st_result)
450 for (i = 0; i < AXIS_N; i++) {
452 gyro_st_result[i] = 0;
455 ret = inv_icm_st_rd(st, DEV_GYR, gyro_result, &gyro_s);
456 if (ret || gyro_s <= 0)
459 for (j = 0; j < AXIS_N; j++) {
460 gyro_result[j] = gyro_result[j] / gyro_s;
461 gyro_result[j] *= ICM_ST_PRECISION;
463 /* Set Self-Test Bit */
464 ret = nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2,
465 BIT_GYRO_CTEN | ICM_SELFTEST_GYRO_AVGCFG,
466 __func__, &st->rc.gyro_config2);
470 msleep(ICM_ST_STABLE_TIME);
472 ret = inv_icm_st_rd(st, DEV_GYR, gyro_st_result, &gyro_s);
473 if (ret || gyro_s <= 0)
476 for (j = 0; j < AXIS_N; j++) {
477 gyro_st_result[j] = gyro_st_result[j] / gyro_s;
478 gyro_st_result[j] *= ICM_ST_PRECISION;
480 if (st->sts & NVI_DBG_SPEW_MSG)
481 dev_info(&st->i2c->dev, "%s %d, %d, %d\n", __func__,
482 gyro_result[0], gyro_result[1], gyro_result[2]);
486 static int inv_st_gyr_icm(struct nvi_state *st)
489 int gyr_bias_st[AXIS_N];
490 int gyr_bias_regular[AXIS_N];
495 ret = inv_icm_st_setup(st);
499 test_times = ICM_ST_TRY_TIMES;
500 while (test_times > 0) {
501 ret = inv_icm_st_gyr_do(st, gyr_bias_regular, gyr_bias_st);
510 if (st->sts & NVI_DBG_SPEW_MSG) {
511 dev_info(&st->i2c->dev, "%s gyro bias_regular: %+d %+d %+d\n",
512 __func__, gyr_bias_regular[0], gyr_bias_regular[1],
513 gyr_bias_regular[2]);
514 dev_info(&st->i2c->dev, "%s gyro bias_st: %+d %+d %+d\n",
515 __func__, gyr_bias_st[0], gyr_bias_st[1],
518 for (i = 0; i < AXIS_N; i++)
519 st->bias[DEV_GYR][i] = (gyr_bias_regular[i] /
521 gyro_result = inv_icm_st_gyr_chk(st, gyr_bias_regular, gyr_bias_st);
522 if (st->sts & NVI_DBG_SPEW_MSG)
523 dev_info(&st->i2c->dev, "%s gyro_result %hhd\n",
524 __func__, gyro_result);
529 static int inv_st_acc_icm(struct nvi_state *st)
532 int acc_bias_st[AXIS_N];
533 int acc_bias_regular[AXIS_N];
538 ret = inv_icm_st_setup(st);
542 test_times = ICM_ST_TRY_TIMES;
543 while (test_times > 0) {
544 ret = inv_icm_st_acc_do(st, acc_bias_regular, acc_bias_st);
553 if (st->sts & NVI_DBG_SPEW_MSG) {
554 dev_info(&st->i2c->dev, "%s acc_bias_regular: %+d %+d %+d\n",
555 __func__, acc_bias_regular[0],
556 acc_bias_regular[1], acc_bias_regular[2]);
557 dev_info(&st->i2c->dev, "%s acc_bias_st: %+d %+d %+d\n",
558 __func__, acc_bias_st[0], acc_bias_st[1],
561 for (i = 0; i < AXIS_N; i++)
562 st->bias[DEV_ACC][i] = (acc_bias_regular[i] /
564 accel_result = inv_icm_st_acc_chk(st, acc_bias_regular, acc_bias_st);
565 if (st->sts & NVI_DBG_SPEW_MSG)
566 dev_info(&st->i2c->dev, "%s accel_result %hhd\n",
567 __func__, accel_result);
571 static int nvi_pm_icm(struct nvi_state *st, u8 pm1, u8 pm2, u8 lp)
575 ret = nvi_i2c_wr_rc(st, &st->hal->reg->lp_config, 0x70,
576 __func__, &st->rc.lp_config);
577 /* the DMP changes pm2 so we can't use the cache */
578 ret |= nvi_i2c_wr(st, &st->hal->reg->pm2, pm2, __func__);
579 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm1, pm1,
580 __func__, &st->rc.pm1);
584 static int nvi_en_gyr_icm(struct nvi_state *st)
590 st->snsr[DEV_GYR].buf_n = 6;
591 for (i = 0; i < AXIS_N; i++)
592 ret |= nvi_wr_gyro_offset(st, i,
593 (u16)(st->rom_offset[DEV_GYR][i] +
594 st->dev_offset[DEV_GYR][i]));
595 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2, 0,
596 __func__, &st->rc.gyro_config2);
597 val = (st->snsr[DEV_GYR].usr_cfg << 1) | 0x01;
598 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1, val,
599 __func__, &st->rc.gyro_config1);
603 static int nvi_en_acc_icm(struct nvi_state *st)
609 st->snsr[DEV_ACC].buf_n = 6;
610 st->snsr[DEV_ACC].buf_shft = 0;
611 for (i = 0; i < AXIS_N; i++)
612 ret |= nvi_wr_accel_offset(st, i,
613 (u16)(st->rom_offset[DEV_ACC][i] +
614 (st->dev_offset[DEV_ACC][i] << 1)));
615 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2, 0,
616 __func__, &st->rc.accel_config2);
617 val = (st->snsr[DEV_ACC].usr_cfg << 1);
618 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config, val,
619 __func__, &st->rc.accel_config);
623 static int nvi_init_icm(struct nvi_state *st)
630 st->snsr[DEV_ACC].cfg.thresh_hi = 0; /* no ACC LP on ICM */
631 st->snsr[DEV_SM].cfg.thresh_lo = ICM_SMD_THLD_INIT;
632 st->snsr[DEV_SM].cfg.thresh_hi = ICM_SMD_THLD_N_INIT;
633 st->snsr[DEV_SM].cfg.delay_us_min = ICM_SMD_TIMER_INIT;
634 st->snsr[DEV_SM].cfg.delay_us_max = ICM_SMD_TIMER2_INIT;
635 st->snsr[DEV_SM].cfg.report_n = ICM_SMD_RESET_INIT;
636 ret = nvi_i2c_rd(st, &st->hal->reg->tbc_pll, &val);
643 st->src[SRC_GYR].base_t = NSEC_PER_SEC - t * 769903 + ((t * 769903) /
645 st->src[SRC_ACC].base_t = NSEC_PER_SEC;
646 st->src[SRC_AUX].base_t = NSEC_PER_SEC;
647 for (src = 0; src < st->hal->src_n; src++)
648 st->src[src].base_t /= ICM_BASE_SAMPLE_RATE;
650 /* calculate the period_us_max */
651 st->src[SRC_GYR].period_us_max = (st->src[SRC_GYR].base_t *
653 /* WAR: limit SRC_ACC to SRC_GYR since same period required by WAR */
654 st->src[SRC_ACC].period_us_max = st->src[SRC_GYR].period_us_max;
655 st->src[SRC_AUX].period_us_max = st->hal->src[SRC_AUX].period_us_max;
656 for (src = 0; src < st->hal->src_n; src++)
657 st->src[src].period_us_min = st->hal->src[src].period_us_min;
664 struct nvi_fn nvi_fn_icm = {
666 .init = nvi_init_icm,
667 .st_acc = inv_st_acc_icm,
668 .st_gyr = inv_st_gyr_icm,
669 .en_acc = nvi_en_acc_icm,
670 .en_gyr = nvi_en_gyr_icm,
674 static int nvi_src(struct nvi_state *st, unsigned int src)
679 rate = (st->src[src].period_us_req * 1000) / st->src[src].base_t;
682 ret = nvi_i2c_write_rc(st, &st->hal->reg->smplrt[src], rate,
683 __func__, (u8 *)&st->rc.smplrt[src], true);
685 st->src[src].period_us_src = ((rate + 1) *
686 st->src[src].base_t) / 1000;
687 if (st->sts & (NVS_STS_SPEW_MSG | NVI_DBG_SPEW_MSG))
688 dev_info(&st->i2c->dev,
689 "%s src[%u] period_req=%u period_src=%u err=%d\n",
690 __func__, src, st->src[src].period_us_req,
691 st->src[src].period_us_src, ret);
695 static int nvi_src_gyr(struct nvi_state *st)
697 return nvi_src(st, SRC_GYR);
700 static int nvi_src_acc(struct nvi_state *st)
702 return nvi_src(st, SRC_ACC);
705 static unsigned int nvi_aux_period_us[] = {
720 static int nvi_src_aux(struct nvi_state *st)
726 for (i = 0; i < ARRAY_SIZE(nvi_aux_period_us); i++) {
727 if (st->src[SRC_AUX].period_us_req >= nvi_aux_period_us[i])
730 if (i >= ARRAY_SIZE(nvi_aux_period_us))
731 i = ARRAY_SIZE(nvi_aux_period_us) - 1;
733 ret = nvi_i2c_wr_rc(st, &st->hal->reg->i2c_mst_odr_config, val,
734 __func__, &st->rc.i2c_mst_odr_config);
736 st->src[SRC_AUX].period_us_src = nvi_aux_period_us[i];
737 ret = nvi_aux_delay(st, __func__);
739 if (st->sts & (NVS_STS_SPEW_MSG | NVI_DBG_SPEW_MSG))
740 dev_info(&st->i2c->dev, "%s src[SRC_AUX]: period=%u err=%d\n",
741 __func__, st->src[SRC_AUX].period_us_req, ret);
745 static const struct nvi_hal_src src[] = {
747 .dev_msk = (1 << DEV_GYR) | (1 << DEV_GYU),
748 .period_us_min = 10000,
749 .period_us_max = 200000,
750 .fn_period = nvi_src_gyr,
753 .dev_msk = (1 << DEV_ACC),
754 .period_us_min = 10000,
755 .period_us_max = 200000,
756 .fn_period = nvi_src_acc,
759 .dev_msk = (1 << DEV_AUX),
760 .period_us_min = 14222,
761 .period_us_max = 29127111,
762 .fn_period = nvi_src_aux,
766 static int nvi_fifo_devs[] = {
773 static const unsigned long nvi_lp_dly_us_tbl[] = {
788 static struct nvi_rr nvi_rr_acc[] = {
789 /* all accelerometer values are in g's fval = NVS_FLOAT_NANO */
832 static struct nvi_rr nvi_rr_gyr[] = {
833 /* rad / sec fval = NVS_FLOAT_NANO */
876 static struct nvi_rr nvi_rr_tmp[] = {
889 static struct nvi_rr nvi_rr_dmp[] = {
902 static const struct nvi_hal_dev nvi_hal_acc = {
905 .rr_0n = ARRAY_SIZE(nvi_rr_acc) - 1,
909 .fval = 500000000, /* NVS_FLOAT_NANO */
911 .fifo_en_msk = 0x1000,
916 static const struct nvi_hal_dev nvi_hal_gyr = {
919 .rr_0n = ARRAY_SIZE(nvi_rr_gyr) - 1,
923 .fval = 700000000, /* NVS_FLOAT_NANO */
925 .fifo_en_msk = 0x0E00,
930 static const struct nvi_hal_dev nvi_hal_tmp = {
933 .rr_0n = ARRAY_SIZE(nvi_rr_tmp) - 1,
937 .fval = 334082700, /* NVS_FLOAT_NANO */
941 .fval = 137625600, /* NVS_FLOAT_NANO */
945 .fval = 700000000, /* NVS_FLOAT_NANO */
949 static const struct nvi_hal_dev nvi_hal_aux = {
951 .fifo_en_msk = 0x000F,
954 static const struct nvi_hal_dev nvi_hal_dmp = {
957 .rr_0n = ARRAY_SIZE(nvi_rr_dmp) - 1,
961 .fval = 500000, /* NVS_FLOAT_MICRO */
966 static const struct nvi_hal_reg nvi_hal_reg_icm = {
967 /* register bank 0 */
1007 .ext_sens_data_00 = {
1011 .signal_path_reset = {
1075 /* register bank 1 */
1076 .self_test_g[AXIS_X] = {
1080 .self_test_g[AXIS_Y] = {
1084 .self_test_g[AXIS_Z] = {
1088 .self_test_a[AXIS_X] = {
1092 .self_test_a[AXIS_Y] = {
1096 .self_test_a[AXIS_Z] = {
1100 .a_offset_h[AXIS_X] = {
1105 .a_offset_h[AXIS_Y] = {
1110 .a_offset_h[AXIS_Z] = {
1123 /* register bank 2 */
1124 .smplrt[SRC_GYR] = {
1137 .g_offset_h[AXIS_X] = {
1142 .g_offset_h[AXIS_Y] = {
1147 .g_offset_h[AXIS_Z] = {
1152 .smplrt[SRC_ACC] = {
1170 /* register bank 3 */
1171 .i2c_mst_odr_config = {
1179 .i2c_mst_delay_ctrl = {
1183 .i2c_slv_addr[0] = {
1187 .i2c_slv_addr[1] = {
1191 .i2c_slv_addr[2] = {
1195 .i2c_slv_addr[3] = {
1199 .i2c_slv_addr[4] = {
1223 .i2c_slv_ctrl[0] = {
1227 .i2c_slv_ctrl[1] = {
1231 .i2c_slv_ctrl[2] = {
1235 .i2c_slv_ctrl[3] = {
1269 static const struct nvi_hal_bit nvi_hal_bit_icm = {
1277 .int_data_rdy_0 = 8,
1278 .int_data_rdy_1 = 9,
1279 .int_data_rdy_2 = 10,
1280 .int_data_rdy_3 = 11,
1281 .int_fifo_ovrflw_0 = 16,
1282 .int_fifo_ovrflw_1 = 17,
1283 .int_fifo_ovrflw_2 = 18,
1284 .int_fifo_ovrflw_3 = 19,
1285 .int_fifo_wm_0 = 24,
1286 .int_fifo_wm_1 = 25,
1287 .int_fifo_wm_2 = 26,
1288 .int_fifo_wm_3 = 27,
1289 .slv_fifo_en[0] = 0,
1290 .slv_fifo_en[1] = 1,
1291 .slv_fifo_en[2] = 2,
1292 .slv_fifo_en[3] = 3,
1295 const struct nvi_hal nvi_hal_20628 = {
1299 .src_n = ARRAY_SIZE(src),
1300 .fifo_dev = nvi_fifo_devs,
1301 .fifo_n = ARRAY_SIZE(nvi_fifo_devs),
1302 .lp_tbl = nvi_lp_dly_us_tbl,
1303 .lp_tbl_n = ARRAY_SIZE(nvi_lp_dly_us_tbl),
1304 .dev[DEV_ACC] = &nvi_hal_acc,
1305 .dev[DEV_GYR] = &nvi_hal_gyr,
1306 .dev[DEV_TMP] = &nvi_hal_tmp,
1307 .dev[DEV_SM] = &nvi_hal_dmp,
1308 .dev[DEV_STP] = &nvi_hal_dmp,
1309 .dev[DEV_QTN] = &nvi_hal_dmp,
1310 .dev[DEV_GMR] = &nvi_hal_dmp,
1311 .dev[DEV_GYU] = &nvi_hal_gyr,
1312 .dev[DEV_AUX] = &nvi_hal_aux,
1313 .reg = &nvi_hal_reg_icm,
1314 .bit = &nvi_hal_bit_icm,
1316 .dmp = &nvi_dmp_icm,
1318 EXPORT_SYMBOL(nvi_hal_20628);