drivers/spi/spi-tegra114.c

   1 /*
   2  * SPI driver for NVIDIA's Tegra114 SPI Controller.
   3  *
   4  * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmapool.h>
  25 #include <linux/err.h>
  26 #include <linux/gpio.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kernel.h>
  31 #include <linux/kthread.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pinctrl/consumer.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/of_gpio.h>
  39 #include <linux/spi/spi.h>
  40 #include <linux/spi/spi-tegra.h>
  41 #include <linux/clk/tegra.h>
  42 #include <linux/tegra_prod.h>
  43
  44 #define SPI_COMMAND1                            0x000
  45 #define SPI_BIT_LENGTH(x)                       (((x) & 0x1f) << 0)
  46 #define SPI_PACKED                              (1 << 5)
  47 #define SPI_TX_EN                               (1 << 11)
  48 #define SPI_RX_EN                               (1 << 12)
  49 #define SPI_BOTH_EN_BYTE                        (1 << 13)
  50 #define SPI_BOTH_EN_BIT                         (1 << 14)
  51 #define SPI_LSBYTE_FE                           (1 << 15)
  52 #define SPI_LSBIT_FE                            (1 << 16)
  53 #define SPI_BIDIROE                             (1 << 17)
  54 #define SPI_IDLE_SDA_DRIVE_LOW                  (0 << 18)
  55 #define SPI_IDLE_SDA_DRIVE_HIGH                 (1 << 18)
  56 #define SPI_IDLE_SDA_PULL_LOW                   (2 << 18)
  57 #define SPI_IDLE_SDA_PULL_HIGH                  (3 << 18)
  58 #define SPI_IDLE_SDA_MASK                       (3 << 18)
  59 #define SPI_CS_SS_VAL                           (1 << 20)
  60 #define SPI_CS_SW_HW                            (1 << 21)
  61 /* SPI_CS_POL_INACTIVE bits are default high */
  62 #define SPI_CS_POL_INACTIVE                     22
  63 #define SPI_CS_POL_INACTIVE_0                   (1 << 22)
  64 #define SPI_CS_POL_INACTIVE_1                   (1 << 23)
  65 #define SPI_CS_POL_INACTIVE_2                   (1 << 24)
  66 #define SPI_CS_POL_INACTIVE_3                   (1 << 25)
  67 #define SPI_CS_POL_INACTIVE_MASK                (0xF << 22)
  68
  69 #define SPI_CS_SEL_0                            (0 << 26)
  70 #define SPI_CS_SEL_1                            (1 << 26)
  71 #define SPI_CS_SEL_2                            (2 << 26)
  72 #define SPI_CS_SEL_3                            (3 << 26)
  73 #define SPI_CS_SEL_MASK                         (3 << 26)
  74 #define SPI_CS_SEL(x)                           (((x) & 0x3) << 26)
  75 #define SPI_CONTROL_MODE_0                      (0 << 28)
  76 #define SPI_CONTROL_MODE_1                      (1 << 28)
  77 #define SPI_CONTROL_MODE_2                      (2 << 28)
  78 #define SPI_CONTROL_MODE_3                      (3 << 28)
  79 #define SPI_CONTROL_MODE_MASK                   (3 << 28)
  80 #define SPI_MODE_SEL(x)                         (((x) & 0x3) << 28)
  81 #define SPI_MODE_VAL(x)                         (((x) >> 28) & 0x3)
  82 #define SPI_M_S                                 (1 << 30)
  83 #define SPI_PIO                                 (1 << 31)
  84
  85 #define SPI_COMMAND2                            0x004
  86 #define SPI_TX_TAP_DELAY(x)                     (((x) & 0x3F) << 6)
  87 #define SPI_RX_TAP_DELAY(x)                     (((x) & 0x3F) << 0)
  88
  89 #define SPI_CS_TIMING1                          0x008
  90 #define SPI_SETUP_HOLD(setup, hold)             (((setup) << 4) | (hold))
  91 #define SPI_CS_SETUP_HOLD(reg, cs, val)                 \
  92                 ((((val) & 0xFFu) << ((cs) * 8)) |      \
  93                 ((reg) & ~(0xFFu << ((cs) * 8))))
  94
  95 #define SPI_CS_TIMING2                          0x00C
  96 #define CYCLES_BETWEEN_PACKETS_0(x)             (((x) & 0x1F) << 0)
  97 #define CS_ACTIVE_BETWEEN_PACKETS_0             (1 << 5)
  98 #define CYCLES_BETWEEN_PACKETS_1(x)             (((x) & 0x1F) << 8)
  99 #define CS_ACTIVE_BETWEEN_PACKETS_1             (1 << 13)
 100 #define CYCLES_BETWEEN_PACKETS_2(x)             (((x) & 0x1F) << 16)
 101 #define CS_ACTIVE_BETWEEN_PACKETS_2             (1 << 21)
 102 #define CYCLES_BETWEEN_PACKETS_3(x)             (((x) & 0x1F) << 24)
 103 #define CS_ACTIVE_BETWEEN_PACKETS_3             (1 << 29)
 104 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)         \
 105                 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) |      \
 106                         ((reg) & ~(1 << ((cs) * 8 + 5))))
 107 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)            \
 108                 (reg = (((val) & 0x1F) << ((cs) * 8)) |         \
 109                         ((reg) & ~(0x1F << ((cs) * 8))))
 110
 111 #define SPI_TRANS_STATUS                        0x010
 112 #define SPI_BLK_CNT(val)                        (((val) >> 0) & 0xFFFF)
 113 #define SPI_SLV_IDLE_COUNT(val)                 (((val) >> 16) & 0xFF)
 114 #define SPI_RDY                                 (1 << 30)
 115
 116 #define SPI_FIFO_STATUS                         0x014
 117 #define SPI_RX_FIFO_EMPTY                       (1 << 0)
 118 #define SPI_RX_FIFO_FULL                        (1 << 1)
 119 #define SPI_TX_FIFO_EMPTY                       (1 << 2)
 120 #define SPI_TX_FIFO_FULL                        (1 << 3)
 121 #define SPI_RX_FIFO_UNF                         (1 << 4)
 122 #define SPI_RX_FIFO_OVF                         (1 << 5)
 123 #define SPI_TX_FIFO_UNF                         (1 << 6)
 124 #define SPI_TX_FIFO_OVF                         (1 << 7)
 125 #define SPI_ERR                                 (1 << 8)
 126 #define SPI_TX_FIFO_FLUSH                       (1 << 14)
 127 #define SPI_RX_FIFO_FLUSH                       (1 << 15)
 128 #define SPI_TX_FIFO_EMPTY_COUNT(val)            (((val) >> 16) & 0x7F)
 129 #define SPI_RX_FIFO_FULL_COUNT(val)             (((val) >> 23) & 0x7F)
 130 #define SPI_FRAME_END                           (1 << 30)
 131 #define SPI_CS_INACTIVE                         (1 << 31)
 132
 133 #define SPI_FIFO_ERROR                          (SPI_RX_FIFO_UNF | \
 134                         SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 135 #define SPI_FIFO_EMPTY                  (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 136
 137 #define SPI_TX_DATA                             0x018
 138 #define SPI_RX_DATA                             0x01C
 139
 140 #define SPI_DMA_CTL                             0x020
 141 #define SPI_TX_TRIG_1                           (0 << 15)
 142 #define SPI_TX_TRIG_4                           (1 << 15)
 143 #define SPI_TX_TRIG_8                           (2 << 15)
 144 #define SPI_TX_TRIG_16                          (3 << 15)
 145 #define SPI_TX_TRIG_MASK                        (3 << 15)
 146 #define SPI_RX_TRIG_1                           (0 << 19)
 147 #define SPI_RX_TRIG_4                           (1 << 19)
 148 #define SPI_RX_TRIG_8                           (2 << 19)
 149 #define SPI_RX_TRIG_16                          (3 << 19)
 150 #define SPI_RX_TRIG_MASK                        (3 << 19)
 151 #define SPI_IE_TX                               (1 << 28)
 152 #define SPI_IE_RX                               (1 << 29)
 153 #define SPI_CONT                                (1 << 30)
 154 #define SPI_DMA                                 (1 << 31)
 155 #define SPI_DMA_EN                              SPI_DMA
 156
 157 #define SPI_DMA_BLK                             0x024
 158 #define SPI_DMA_BLK_SET(x)                      (((x) & 0xFFFF) << 0)
 159
 160 #define SPI_TX_FIFO                             0x108
 161 #define SPI_RX_FIFO                             0x188
 162
 163 #define SPI_INTR_MASK           0x18c
 164 #define SPI_INTR_RX_FIFO_UNF_MASK               (1 << 25)
 165 #define SPI_INTR_RX_FIFO_OVF_MASK               (1 << 26)
 166 #define SPI_INTR_TX_FIFO_UNF_MASK               (1 << 27)
 167 #define SPI_INTR_TX_FIFO_OVF_MASK               (1 << 28)
 168 #define SPI_INTR_RDY_MASK                       (1 << 29)
 169 #define SPI_INTR_ALL_MASK                       (0xfe << 25)
 170
 171 #define MAX_CHIP_SELECT                         4
 172 #define SPI_FIFO_DEPTH                          64
 173 #define DATA_DIR_TX                             (1 << 0)
 174 #define DATA_DIR_RX                             (1 << 1)
 175
 176 #define SPI_DMA_TIMEOUT                         (msecs_to_jiffies(10000))
 177 #define DEFAULT_SPI_DMA_BUF_LEN                 (16*1024)
 178 #define TX_FIFO_EMPTY_COUNT_MAX                 (0x40)
 179 #define RX_FIFO_FULL_COUNT_ZERO                 (0)
 180 #define MAX_HOLD_CYCLES                         16
 181 #define SPI_DEFAULT_SPEED                       25000000
 182
 183 #define MAX_CHIP_SELECT                         4
 184 #define SPI_FIFO_DEPTH                          64
 185 #define SPI_FIFO_FLUSH_MAX_DELAY                2000
 186
 187 #define SPI_SPEED_TAP_DELAY_MARGIN 35000000
 188 #define SPI_DEFAULT_RX_TAP_DELAY 10
 189 #define SPI_POLL_TIMEOUT 10000
 190 #define SPI_AUTOSUSPEND_DELAY 100       /* 100ms */
 191
 192 struct tegra_spi_chip_data {
 193         bool intr_mask_reg;
 194         bool set_rx_tap_delay;
 195 };
 196
 197 struct tegra_spi_data {
 198         struct device                           *dev;
 199         struct spi_master                       *master;
 200         spinlock_t                              lock;
 201
 202         struct clk                              *clk;
 203         void __iomem                            *base;
 204         phys_addr_t                             phys;
 205         unsigned                                irq;
 206         bool                                    clock_always_on;
 207         bool                                    polling_mode;
 208         bool                                    boost_reg_access;
 209         bool                                    runtime_pm;
 210         u32                                     spi_max_frequency;
 211         u32                                     cur_speed;
 212         unsigned                                min_div;
 213
 214         struct spi_device                       *cur_spi;
 215         unsigned                                cur_pos;
 216         unsigned                                cur_len;
 217         unsigned                                words_per_32bit;
 218         unsigned                                bytes_per_word;
 219         unsigned                                curr_dma_words;
 220         unsigned                                cur_direction;
 221
 222         unsigned                                cur_rx_pos;
 223         unsigned                                cur_tx_pos;
 224
 225         unsigned                                dma_buf_size;
 226         unsigned                                max_buf_size;
 227         bool                                    is_curr_dma_xfer;
 228         bool                                    is_hw_based_cs;
 229         bool                                    transfer_in_progress;
 230
 231         struct completion                       rx_dma_complete;
 232         struct completion                       tx_dma_complete;
 233
 234         u32                                     tx_status;
 235         u32                                     rx_status;
 236         u32                                     status_reg;
 237         bool                                    is_packed;
 238         unsigned long                           packed_size;
 239
 240         u32                                     command1_reg;
 241         u32                                     dma_control_reg;
 242         u32                                     def_command1_reg;
 243         u32                                     def_command2_reg;
 244         u32                                     spi_cs_timing;
 245         u8                                      def_chip_select;
 246
 247         struct completion                       xfer_completion;
 248         struct spi_transfer                     *curr_xfer;
 249         struct dma_chan                         *rx_dma_chan;
 250         u32                                     *rx_dma_buf;
 251         dma_addr_t                              rx_dma_phys;
 252         struct dma_async_tx_descriptor          *rx_dma_desc;
 253
 254         struct dma_chan                         *tx_dma_chan;
 255         u32                                     *tx_dma_buf;
 256         dma_addr_t                              tx_dma_phys;
 257         struct dma_async_tx_descriptor          *tx_dma_desc;
 258         const struct tegra_spi_chip_data  *chip_data;
 259         struct tegra_spi_device_controller_data cdata[MAX_CHIP_SELECT];
 260         bool                                    cs_gpio_reqstd[MAX_CHIP_SELECT];
 261         struct tegra_prod_list *prod_list;
 262         struct pinctrl *pinctrl;
 263         struct pinctrl_state *enable_interface;
 264 };
 265
 266
 267 static int tegra_spi_runtime_suspend(struct device *dev);
 268 static int tegra_spi_runtime_resume(struct device *dev);
 269 static int tegra_spi_status_poll(struct tegra_spi_data *tspi);
 270 static int tegra_spi_set_clock_rate(struct tegra_spi_data *tspi, u32 speed);
 271
 272
 273 static inline unsigned long tegra_spi_readl(struct tegra_spi_data *tspi,
 274                 unsigned long reg)
 275 {
 276         return readl(tspi->base + reg);
 277 }
 278
 279 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 280                 unsigned long val, unsigned long reg)
 281 {
 282         /* Read back register to make sure that register writes completed */
 283         if ((reg == SPI_COMMAND1) && (val & SPI_PIO))
 284                 readl(tspi->base + SPI_COMMAND1);
 285
 286         writel(val, tspi->base + reg);
 287 }
 288
 289 static inline int tegra_spi_runtime_get(struct tegra_spi_data *tspi)
 290 {
 291         if (!tspi->runtime_pm)
 292                 return 0;
 293
 294         return pm_runtime_get_sync(tspi->dev);
 295 }
 296
 297 static inline int tegra_spi_runtime_put(struct tegra_spi_data *tspi)
 298 {
 299         if (!tspi->runtime_pm)
 300                 return 0;
 301
 302         pm_runtime_mark_last_busy(tspi->dev);
 303         return pm_runtime_put_autosuspend(tspi->dev);
 304 }
 305
 306 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 307 {
 308         unsigned long val;
 309
 310         /* Write 1 to clear status register */
 311         val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 312         if (val & SPI_RDY)
 313                 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 314
 315         /* Clear fifo status error if any */
 316         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 317         if (tspi->status_reg & SPI_ERR)
 318                 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 319                                 SPI_FIFO_STATUS);
 320 }
 321
 322 static unsigned tegra_spi_calculate_curr_xfer_param(
 323         struct spi_device *spi, struct tegra_spi_data *tspi,
 324         struct spi_transfer *t)
 325 {
 326         unsigned remain_len = t->len - tspi->cur_pos;
 327         unsigned max_word;
 328         unsigned bits_per_word ;
 329         unsigned max_len;
 330         unsigned total_fifo_words;
 331
 332         bits_per_word = t->bits_per_word ? t->bits_per_word :
 333                                                 spi->bits_per_word;
 334         tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
 335
 336         if ((bits_per_word == 8 || bits_per_word == 16) && (t->len > 3)) {
 337                 tspi->is_packed = 1;
 338                 tspi->words_per_32bit = 32/bits_per_word;
 339         } else {
 340                 tspi->is_packed = 0;
 341                 tspi->words_per_32bit = 1;
 342         }
 343
 344         if (tspi->is_packed) {
 345                 max_len = min(remain_len, tspi->max_buf_size);
 346                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 347                 total_fifo_words = (max_len + 3)/4;
 348         } else {
 349                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 350                 max_word = min(max_word, tspi->max_buf_size/4);
 351                 tspi->curr_dma_words = max_word;
 352                 total_fifo_words = max_word;
 353         }
 354         return total_fifo_words;
 355 }
 356
 357 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 358         struct tegra_spi_data *tspi, struct spi_transfer *t)
 359 {
 360         unsigned nbytes;
 361         unsigned tx_empty_count;
 362         unsigned max_n_32bit;
 363         unsigned i, count;
 364         unsigned long x;
 365         unsigned int written_words;
 366         unsigned fifo_words_left;
 367         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 368
 369         tx_empty_count = TX_FIFO_EMPTY_COUNT_MAX;
 370
 371         if (tspi->is_packed) {
 372                 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 373                 written_words = min(fifo_words_left, tspi->curr_dma_words);
 374                 nbytes = written_words * tspi->bytes_per_word;
 375                 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 376                 for (count = 0; count < max_n_32bit; count++) {
 377                         x = 0;
 378                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 379                                 x |= (*tx_buf++) << (i*8);
 380                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 381                 }
 382         } else {
 383                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 384                 written_words = max_n_32bit;
 385                 nbytes = written_words * tspi->bytes_per_word;
 386                 for (count = 0; count < max_n_32bit; count++) {
 387                         x = 0;
 388                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
 389                                                         i++, nbytes--)
 390                                 x |= ((*tx_buf++) << i*8);
 391                         tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 392                 }
 393         }
 394         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 395         return written_words;
 396 }
 397
 398 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 399                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 400 {
 401         unsigned rx_full_count;
 402         unsigned long fifo_status;
 403         unsigned i, count;
 404         unsigned long x;
 405         unsigned int read_words = 0;
 406         unsigned len;
 407         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 408
 409         fifo_status = tspi->status_reg;
 410         rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 411         if (tspi->is_packed) {
 412                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 413                 for (count = 0; count < rx_full_count; count++) {
 414                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 415                         for (i = 0; len && (i < 4); i++, len--)
 416                                 *rx_buf++ = (x >> i*8) & 0xFF;
 417                 }
 418                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 419                 read_words += tspi->curr_dma_words;
 420         } else {
 421                 unsigned int bits_per_word;
 422
 423                 bits_per_word = t->bits_per_word ? t->bits_per_word :
 424                                                 tspi->cur_spi->bits_per_word;
 425                 for (count = 0; count < rx_full_count; count++) {
 426                         x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 427                         for (i = 0; (i < tspi->bytes_per_word); i++)
 428                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 429                 }
 430                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
 431                 read_words += rx_full_count;
 432         }
 433         return read_words;
 434 }
 435
 436 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 437                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 438 {
 439         unsigned len;
 440
 441         /* Make the dma buffer to read by cpu */
 442         dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 443                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 444
 445         if (tspi->is_packed) {
 446                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 447                 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 448         } else {
 449                 unsigned int i;
 450                 unsigned int count;
 451                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 452                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 453                 unsigned int x;
 454
 455                 for (count = 0; count < tspi->curr_dma_words; count++) {
 456                         x = 0;
 457                         for (i = 0; consume && (i < tspi->bytes_per_word);
 458                                                         i++, consume--)
 459                                 x |= ((*tx_buf++) << i * 8);
 460                         tspi->tx_dma_buf[count] = x;
 461                 }
 462         }
 463         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 464
 465         /* Make the dma buffer to read by dma */
 466         dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 467                                 tspi->dma_buf_size, DMA_TO_DEVICE);
 468 }
 469
 470 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 471                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 472 {
 473         unsigned len;
 474
 475         /* Make the dma buffer to read by cpu */
 476         dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 477                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 478
 479         if (tspi->is_packed) {
 480                 len = tspi->curr_dma_words * tspi->bytes_per_word;
 481                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 482         } else {
 483                 unsigned int i;
 484                 unsigned int count;
 485                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 486                 unsigned int x;
 487                 unsigned int rx_mask, bits_per_word;
 488
 489                 bits_per_word = t->bits_per_word ? t->bits_per_word :
 490                                                 tspi->cur_spi->bits_per_word;
 491                 rx_mask = (1ULL << bits_per_word) - 1;
 492                 for (count = 0; count < tspi->curr_dma_words; count++) {
 493                         x = tspi->rx_dma_buf[count];
 494                         x &= rx_mask;
 495                         for (i = 0; (i < tspi->bytes_per_word); i++)
 496                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
 497                 }
 498         }
 499         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 500
 501         /* Make the dma buffer to read by dma */
 502         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 503                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 504 }
 505
 506 static void tegra_spi_dma_complete(void *args)
 507 {
 508         struct completion *dma_complete = args;
 509
 510         complete(dma_complete);
 511 }
 512
 513 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 514 {
 515         INIT_COMPLETION(tspi->tx_dma_complete);
 516         tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 517                                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 518                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 519         if (!tspi->tx_dma_desc) {
 520                 dev_err(tspi->dev, "Not able to get desc for Tx\n");
 521                 return -EIO;
 522         }
 523
 524         tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 525         tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 526
 527         dmaengine_submit(tspi->tx_dma_desc);
 528         dma_async_issue_pending(tspi->tx_dma_chan);
 529         return 0;
 530 }
 531
 532 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 533 {
 534         INIT_COMPLETION(tspi->rx_dma_complete);
 535         tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 536                                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 537                                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 538         if (!tspi->rx_dma_desc) {
 539                 dev_err(tspi->dev, "Not able to get desc for Rx\n");
 540                 return -EIO;
 541         }
 542
 543         tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 544         tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 545
 546         dmaengine_submit(tspi->rx_dma_desc);
 547         dma_async_issue_pending(tspi->rx_dma_chan);
 548         return 0;
 549 }
 550
 551 static int check_and_clear_fifo(struct tegra_spi_data *tspi)
 552 {
 553         unsigned long status = tspi->status_reg;
 554         int cnt = SPI_FIFO_FLUSH_MAX_DELAY;
 555
 556         /* Make sure that Rx and Tx fifo are empty */
 557         if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 558                 /* flush the fifo */
 559                 status |= (SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH);
 560                 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
 561                 do {
 562                         status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 563                         if ((status & SPI_FIFO_EMPTY) == SPI_FIFO_EMPTY)
 564                                 return 0;
 565                         udelay(1);
 566                 } while (cnt--);
 567                 dev_err(tspi->dev,
 568                         "Rx/Tx fifo are not empty status 0x%08lx\n", status);
 569                 return -EIO;
 570         }
 571         return 0;
 572 }
 573
 574 static int tegra_spi_start_dma_based_transfer(
 575                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 576 {
 577         unsigned long val, cmd1;
 578         unsigned int len;
 579         unsigned long flags;
 580         int ret = 0, maxburst;
 581         struct dma_slave_config dma_sconfig;
 582         u32 speed;
 583
 584         /* Make sure that Rx and Tx fifo are empty */
 585         ret = check_and_clear_fifo(tspi);
 586         if (ret != 0)
 587                 return ret;
 588
 589         val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 590         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 591
 592         if (tspi->is_packed)
 593                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 594                                         4) * 4;
 595         else
 596                 len = tspi->curr_dma_words * 4;
 597
 598         /* Set attention level based on length of transfer */
 599         if (len & 0xF) {
 600                 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 601                 maxburst = 1;
 602         } else if (((len) >> 4) & 0x1) {
 603                 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 604                 maxburst = 4;
 605         } else {
 606                 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 607                 maxburst = 8;
 608         }
 609
 610         if (!tspi->chip_data->intr_mask_reg) {
 611                 if (!tspi->polling_mode) {
 612                         if (tspi->cur_direction & DATA_DIR_TX)
 613                                 val |= SPI_IE_TX;
 614                         if (tspi->cur_direction & DATA_DIR_RX)
 615                                 val |= SPI_IE_RX;
 616                 }
 617         }
 618
 619         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 620         tspi->dma_control_reg = val;
 621
 622         if (tspi->cur_direction & DATA_DIR_TX) {
 623                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 624                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 625                 dma_sconfig.dst_maxburst = maxburst;
 626                 dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
 627
 628                 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 629                 ret = tegra_spi_start_tx_dma(tspi, len);
 630                 if (ret < 0) {
 631                         dev_err(tspi->dev,
 632                                 "Starting tx dma failed, err %d\n", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         if (tspi->cur_direction & DATA_DIR_RX) {
 638                 /* Make the dma buffer to read by dma */
 639                 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 640                                 tspi->dma_buf_size, DMA_FROM_DEVICE);
 641                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 642                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 643                 dma_sconfig.src_maxburst = maxburst;
 644                 dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
 645
 646                 ret = tegra_spi_start_rx_dma(tspi, len);
 647                 if (ret < 0) {
 648                         dev_err(tspi->dev,
 649                                 "Starting rx dma failed, err %d\n", ret);
 650                         if (tspi->cur_direction & DATA_DIR_TX)
 651                                 dmaengine_terminate_all(tspi->tx_dma_chan);
 652                         return ret;
 653                 }
 654         }
 655
 656         if (tspi->boost_reg_access) {
 657                 speed = t->speed_hz ? t->speed_hz :
 658                                 tspi->cur_spi->max_speed_hz;
 659                 ret = tegra_spi_set_clock_rate(tspi, speed);
 660                 if (ret < 0)
 661                         return ret;
 662         }
 663
 664         spin_lock_irqsave(&tspi->lock, flags);
 665         cmd1 = tspi->command1_reg;
 666         if (tspi->cur_direction & DATA_DIR_TX)
 667                 cmd1 |= SPI_TX_EN;
 668         if (tspi->cur_direction & DATA_DIR_RX)
 669                 cmd1 |= SPI_RX_EN;
 670         tegra_spi_writel(tspi, cmd1, SPI_COMMAND1);
 671
 672         tspi->is_curr_dma_xfer = true;
 673         tspi->dma_control_reg = val;
 674
 675         tspi->transfer_in_progress = true;
 676         val |= SPI_DMA_EN;
 677         tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 678         spin_unlock_irqrestore(&tspi->lock, flags);
 679         return ret;
 680 }
 681
 682 static int tegra_spi_start_cpu_based_transfer(
 683                 struct tegra_spi_data *tspi, struct spi_transfer *t)
 684 {
 685         unsigned long val;
 686         unsigned long flags;
 687         unsigned cur_words;
 688         int ret;
 689         u32 speed;
 690
 691         ret = check_and_clear_fifo(tspi);
 692         if (ret != 0)
 693                 return ret;
 694
 695         if (tspi->cur_direction & DATA_DIR_TX)
 696                 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 697         else
 698                 cur_words = tspi->curr_dma_words;
 699
 700         val = SPI_DMA_BLK_SET(cur_words - 1);
 701         tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 702
 703         val = 0;
 704
 705         if (!tspi->chip_data->intr_mask_reg) {
 706                 if (!tspi->polling_mode) {
 707                         if (tspi->cur_direction & DATA_DIR_TX)
 708                                 val |= SPI_IE_TX;
 709                         if (tspi->cur_direction & DATA_DIR_RX)
 710                                 val |= SPI_IE_RX;
 711                 }
 712                 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 713         }
 714
 715         tspi->dma_control_reg = val;
 716
 717         if (tspi->boost_reg_access) {
 718                 speed = t->speed_hz ? t->speed_hz :
 719                                 tspi->cur_spi->max_speed_hz;
 720                 ret = tegra_spi_set_clock_rate(tspi, speed);
 721                 if (ret < 0)
 722                         return ret;
 723         }
 724
 725         spin_lock_irqsave(&tspi->lock, flags);
 726         tspi->is_curr_dma_xfer = false;
 727         val = tspi->command1_reg;
 728         if (tspi->cur_direction & DATA_DIR_TX)
 729                 val |= SPI_TX_EN;
 730         if (tspi->cur_direction & DATA_DIR_RX)
 731                 val |= SPI_RX_EN;
 732
 733         tspi->transfer_in_progress = true;
 734         val |= SPI_PIO;
 735         tegra_spi_writel(tspi, val, SPI_COMMAND1);
 736         spin_unlock_irqrestore(&tspi->lock, flags);
 737         return 0;
 738 }
 739
 740 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 741                         bool dma_to_memory)
 742 {
 743         struct dma_chan *dma_chan;
 744         u32 *dma_buf;
 745         dma_addr_t dma_phys;
 746         int ret;
 747         struct dma_slave_config dma_sconfig;
 748
 749         dma_chan = dma_request_slave_channel_reason(tspi->dev,
 750                                         dma_to_memory ? "rx" : "tx");
 751         if (IS_ERR(dma_chan)) {
 752                 ret = PTR_ERR(dma_chan);
 753                 if (ret != -EPROBE_DEFER)
 754                         dev_err(tspi->dev,
 755                                 "Dma channel is not available: %d\n", ret);
 756                 return ret;
 757         }
 758
 759         dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 760                                 &dma_phys, GFP_KERNEL);
 761         if (!dma_buf) {
 762                 dev_err(tspi->dev, "Not able to allocate the dma buffer\n");
 763                 dma_release_channel(dma_chan);
 764                 return -ENOMEM;
 765         }
 766
 767         if (dma_to_memory) {
 768                 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 769                 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 770                 dma_sconfig.src_maxburst = 0;
 771         } else {
 772                 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 773                 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 774                 dma_sconfig.dst_maxburst = 0;
 775         }
 776
 777         ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
 778         if (ret)
 779                 goto scrub;
 780         if (dma_to_memory) {
 781                 tspi->rx_dma_chan = dma_chan;
 782                 tspi->rx_dma_buf = dma_buf;
 783                 tspi->rx_dma_phys = dma_phys;
 784         } else {
 785                 tspi->tx_dma_chan = dma_chan;
 786                 tspi->tx_dma_buf = dma_buf;
 787                 tspi->tx_dma_phys = dma_phys;
 788         }
 789         return 0;
 790
 791 scrub:
 792         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 793         dma_release_channel(dma_chan);
 794         return ret;
 795 }
 796
 797 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 798         bool dma_to_memory)
 799 {
 800         u32 *dma_buf;
 801         dma_addr_t dma_phys;
 802         struct dma_chan *dma_chan;
 803
 804         if (dma_to_memory) {
 805                 dma_buf = tspi->rx_dma_buf;
 806                 dma_chan = tspi->rx_dma_chan;
 807                 dma_phys = tspi->rx_dma_phys;
 808                 tspi->rx_dma_chan = NULL;
 809                 tspi->rx_dma_buf = NULL;
 810         } else {
 811                 dma_buf = tspi->tx_dma_buf;
 812                 dma_chan = tspi->tx_dma_chan;
 813                 dma_phys = tspi->tx_dma_phys;
 814                 tspi->tx_dma_buf = NULL;
 815                 tspi->tx_dma_chan = NULL;
 816         }
 817         if (!dma_chan)
 818                 return;
 819
 820         dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 821         dma_release_channel(dma_chan);
 822 }
 823
 824 static void set_best_clk_source(struct tegra_spi_data *tspi,
 825                 unsigned long rate)
 826 {
 827         long new_rate;
 828         unsigned long err_rate, crate, prate;
 829         unsigned int cdiv, fin_err = rate;
 830         int ret;
 831         struct clk *pclk, *fpclk = NULL;
 832         const char *pclk_name, *fpclk_name;
 833         struct device_node *node;
 834         struct property *prop;
 835
 836         node = tspi->master->dev.of_node;
 837         if (!of_property_count_strings(node, "nvidia,clk-parents"))
 838                 return;
 839
 840         /* when parent of a clk changes divider is not changed
 841          * set a min div with which clk will not cross max rate
 842          */
 843         if (!tspi->min_div) {
 844                 of_property_for_each_string(node, "nvidia,clk-parents",
 845                                 prop, pclk_name) {
 846                         pclk = clk_get(tspi->dev, pclk_name);
 847                         if (IS_ERR(pclk))
 848                                 continue;
 849                         prate = clk_get_rate(pclk);
 850                         crate = tspi->spi_max_frequency;
 851                         cdiv = DIV_ROUND_UP(prate, crate);
 852                         if (cdiv > tspi->min_div)
 853                                 tspi->min_div = cdiv;
 854                 }
 855         }
 856
 857         pclk = clk_get_parent(tspi->clk);
 858         crate = clk_get_rate(tspi->clk);
 859         prate = clk_get_rate(pclk);
 860         cdiv = DIV_ROUND_UP(prate, crate);
 861         if (cdiv < tspi->min_div) {
 862                 crate = DIV_ROUND_UP(prate, tspi->min_div);
 863                 clk_set_rate(tspi->clk, crate);
 864         }
 865
 866         of_property_for_each_string(node, "nvidia,clk-parents",
 867                                 prop, pclk_name) {
 868                 pclk = clk_get(tspi->dev, pclk_name);
 869                 if (IS_ERR(pclk))
 870                         continue;
 871
 872                 ret = clk_set_parent(tspi->clk, pclk);
 873                 if (ret < 0) {
 874                         dev_warn(tspi->dev,
 875                                 "Error in setting parent clk src %s\n",
 876                                 pclk_name);
 877                         continue;
 878                 }
 879
 880                 new_rate = clk_round_rate(tspi->clk, rate);
 881                 if (new_rate < 0)
 882                         continue;
 883
 884                 err_rate = abs(new_rate - rate);
 885                 if (err_rate < fin_err) {
 886                         fpclk = pclk;
 887                         fin_err = err_rate;
 888                         fpclk_name = pclk_name;
 889                 }
 890         }
 891
 892         if (fpclk) {
 893                 dev_dbg(tspi->dev, "Setting clk_src %s\n",
 894                                 fpclk_name);
 895                 clk_set_parent(tspi->clk, fpclk);
 896         }
 897 }
 898
 899 static int tegra_spi_set_clock_rate(struct tegra_spi_data *tspi, u32 speed)
 900 {
 901         int ret;
 902
 903         if (speed == tspi->cur_speed)
 904                 return 0;
 905         set_best_clk_source(tspi, speed);
 906         ret = clk_set_rate(tspi->clk, speed);
 907         if (ret) {
 908                 dev_err(tspi->dev, "Failed to set clk freq %d\n", ret);
 909                 return -EINVAL;
 910         }
 911         tspi->cur_speed = speed;
 912
 913         return 0;
 914 }
 915 static int tegra_spi_start_transfer_one(struct spi_device *spi,
 916                 struct spi_transfer *t, bool is_first_of_msg,
 917                 bool is_single_xfer)
 918 {
 919         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 920         u32 speed;
 921         u32 spi_cs_timing2 = 0;
 922         u8 bits_per_word;
 923         unsigned total_fifo_words;
 924         int ret;
 925         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
 926         unsigned long command1;
 927         int req_mode;
 928         char prod_name[15];
 929
 930         bits_per_word = t->bits_per_word;
 931         speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 932                 /* set max clock for faster register access */
 933         if (tspi->boost_reg_access)
 934                 ret = tegra_spi_set_clock_rate(tspi, tspi->spi_max_frequency);
 935         else
 936                 ret = tegra_spi_set_clock_rate(tspi, speed);
 937         if (ret < 0)
 938                 return ret;
 939
 940         tspi->cur_spi = spi;
 941         tspi->cur_pos = 0;
 942         tspi->cur_rx_pos = 0;
 943         tspi->cur_tx_pos = 0;
 944         tspi->curr_xfer = t;
 945         tspi->tx_status = 0;
 946         tspi->rx_status = 0;
 947         total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 948
 949         /* Check that the all words are available */
 950         if (t->len % tspi->bytes_per_word != 0)
 951                 return -EINVAL;
 952
 953         if (is_first_of_msg) {
 954                 tegra_spi_clear_status(tspi);
 955
 956                 command1 = tspi->def_command1_reg;
 957                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 958
 959                 command1 &= ~SPI_CONTROL_MODE_MASK;
 960                 req_mode = spi->mode & 0x3;
 961                 if (req_mode == SPI_MODE_0)
 962                         command1 |= SPI_CONTROL_MODE_0;
 963                 else if (req_mode == SPI_MODE_1)
 964                         command1 |= SPI_CONTROL_MODE_1;
 965                 else if (req_mode == SPI_MODE_2)
 966                         command1 |= SPI_CONTROL_MODE_2;
 967                 else if (req_mode == SPI_MODE_3)
 968                         command1 |= SPI_CONTROL_MODE_3;
 969
 970                 /* Apply mode setting before switching chip select */
 971                 if (SPI_MODE_VAL(command1) !=
 972                     SPI_MODE_VAL(tspi->def_command1_reg))
 973                         tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 974
 975                 /* possibly use the hw based chip select */
 976                 tspi->is_hw_based_cs = false;
 977                 if (cdata && cdata->is_hw_based_cs && is_single_xfer &&
 978                         ((tspi->curr_dma_words * tspi->bytes_per_word) ==
 979                                                 (t->len - tspi->cur_pos))) {
 980                         u32 set_count;
 981                         u32 hold_count;
 982                         u32 spi_cs_timing;
 983                         u32 spi_cs_setup;
 984
 985                         set_count = min(cdata->cs_setup_clk_count, 16);
 986                         if (set_count)
 987                                 set_count--;
 988
 989                         hold_count = min(cdata->cs_hold_clk_count, 16);
 990                         if (hold_count)
 991                                 hold_count--;
 992
 993                         spi_cs_setup = SPI_SETUP_HOLD(set_count,
 994                                         hold_count);
 995                         spi_cs_timing = tspi->spi_cs_timing;
 996                         spi_cs_timing = SPI_CS_SETUP_HOLD(spi_cs_timing,
 997                                                 spi->chip_select,
 998                                                 spi_cs_setup);
 999                         tspi->spi_cs_timing = spi_cs_timing;
1000                         tegra_spi_writel(tspi, spi_cs_timing,
1001                                                 SPI_CS_TIMING1);
1002                         tspi->is_hw_based_cs = true;
1003                 }
1004
1005                 if (cdata && cdata->cs_inactive_cycles) {
1006                         u32 inactive_cycles;
1007
1008                         SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing2,
1009                                                 spi->chip_select,
1010                                                 0);
1011                         inactive_cycles = min(cdata->cs_inactive_cycles, 32);
1012                         SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing2,
1013                                                 spi->chip_select,
1014                                                 inactive_cycles);
1015                         tegra_spi_writel(tspi, spi_cs_timing2, SPI_CS_TIMING2);
1016                         tspi->is_hw_based_cs = true;
1017                 } else {
1018                         SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing2,
1019                                                 spi->chip_select, 1);
1020                         SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing2,
1021                                                 spi->chip_select, 0);
1022                         tegra_spi_writel(tspi, spi_cs_timing2, SPI_CS_TIMING2);
1023                 }
1024
1025                 if (!tspi->is_hw_based_cs) {
1026                         command1 |= SPI_CS_SW_HW;
1027                         if (spi->mode & SPI_CS_HIGH)
1028                                 command1 |= SPI_CS_SS_VAL;
1029                         else
1030                                 command1 &= ~SPI_CS_SS_VAL;
1031                 } else {
1032                         command1 &= ~SPI_CS_SW_HW;
1033                         command1 &= ~SPI_CS_SS_VAL;
1034                 }
1035
1036                 if (cdata && gpio_is_valid(cdata->cs_gpio)) {
1037                         int gval = 0;
1038                         if (spi->mode & SPI_CS_HIGH)
1039                                 gval = 1;
1040                         gpio_set_value(cdata->cs_gpio, gval);
1041                 }
1042
1043                 if (tspi->prod_list) {
1044                         sprintf(prod_name, "prod_c_cs%d", spi->chip_select);
1045                         tegra_prod_set_by_name(&tspi->base, prod_name,
1046                                 tspi->prod_list);
1047                         tegra_prod_set_by_name(&tspi->base, "prod",
1048                                 tspi->prod_list);
1049                 } else {
1050                         u32 command2_reg;
1051                         command2_reg = tspi->def_command2_reg;
1052                         if (tspi->chip_data->set_rx_tap_delay) {
1053                                 if (speed > SPI_SPEED_TAP_DELAY_MARGIN) {
1054                                         command2_reg = command2_reg &
1055                                                 (~SPI_RX_TAP_DELAY(63));
1056                                         command2_reg = command2_reg |
1057                                                 SPI_RX_TAP_DELAY(
1058                                                 SPI_DEFAULT_RX_TAP_DELAY);
1059                                 }
1060                         }
1061                         if (command2_reg != tspi->def_command2_reg)
1062                                 tegra_spi_writel(tspi, command2_reg,
1063                                                         SPI_COMMAND2);
1064                 }
1065         } else {
1066                 command1 = tspi->command1_reg;
1067                 command1 &= ~SPI_BIT_LENGTH(~0);
1068                 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
1069         }
1070
1071         if (spi->mode & SPI_LSBYTE_FIRST)
1072                 command1 |= SPI_LSBYTE_FE;
1073         else
1074                 command1 &= ~SPI_LSBYTE_FE;
1075
1076         if (spi->mode & SPI_LSB_FIRST)
1077                 command1 |= SPI_LSBIT_FE;
1078         else
1079                 command1 &= ~SPI_LSBIT_FE;
1080
1081         if (spi->mode & SPI_3WIRE)
1082                 command1 |= SPI_BIDIROE;
1083         else
1084                 command1 &= ~SPI_BIDIROE;
1085
1086         command1 &=  ~SPI_BOTH_EN_BIT;
1087         if ((t->rx_nbits == SPI_NBITS_DUAL) ||
1088                         (t->tx_nbits == SPI_NBITS_DUAL))
1089                 command1 |=  SPI_BOTH_EN_BIT;
1090
1091         if (tspi->is_packed)
1092                 command1 |= SPI_PACKED;
1093
1094         command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
1095         tspi->cur_direction = 0;
1096         if (t->rx_buf)
1097                 tspi->cur_direction |= DATA_DIR_RX;
1098         if (t->tx_buf)
1099                 tspi->cur_direction |= DATA_DIR_TX;
1100
1101         command1 |= SPI_CS_SEL(spi->chip_select);
1102         tspi->command1_reg = command1;
1103
1104         dev_dbg(tspi->dev, "The def 0x%x and written 0x%lx\n",
1105                                 tspi->def_command1_reg, command1);
1106
1107         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1108
1109         if (total_fifo_words > SPI_FIFO_DEPTH)
1110                 ret = tegra_spi_start_dma_based_transfer(tspi, t);
1111         else
1112                 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
1113         return ret;
1114 }
1115
1116 static struct tegra_spi_device_controller_data
1117         *tegra_spi_get_cdata_dt(struct spi_device *spi,
1118                         struct tegra_spi_data *tspi)
1119 {
1120         struct tegra_spi_device_controller_data *cdata;
1121         struct device_node *slave_np, *data_np;
1122         int ret;
1123
1124         slave_np = spi->dev.of_node;
1125         if (!slave_np) {
1126                 dev_dbg(&spi->dev, "device node not found\n");
1127                 return NULL;
1128         }
1129
1130         data_np = of_get_child_by_name(slave_np, "controller-data");
1131         if (!data_np) {
1132                 dev_dbg(&spi->dev, "child node 'controller-data' not found\n");
1133                 return NULL;
1134         }
1135
1136         cdata = &tspi->cdata[spi->chip_select];
1137         memset(cdata, 0, sizeof(*cdata));
1138
1139         ret = of_property_read_bool(data_np, "nvidia,enable-hw-based-cs");
1140         if (ret)
1141                 cdata->is_hw_based_cs = 1;
1142
1143         of_property_read_u32(data_np, "nvidia,cs-setup-clk-count",
1144                         &cdata->cs_setup_clk_count);
1145         of_property_read_u32(data_np, "nvidia,cs-hold-clk-count",
1146                         &cdata->cs_hold_clk_count);
1147         of_property_read_u32(data_np, "nvidia,rx-clk-tap-delay",
1148                         &cdata->rx_clk_tap_delay);
1149         of_property_read_u32(data_np, "nvidia,tx-clk-tap-delay",
1150                         &cdata->tx_clk_tap_delay);
1151         of_property_read_u32(data_np, "nvidia,cs-inactive-cycles",
1152                         &cdata->cs_inactive_cycles);
1153         of_property_read_u32(data_np, "nvidia,clk-delay-between-packets",
1154                         &cdata->clk_delay_between_packets);
1155
1156         if (cdata->cs_inactive_cycles && cdata->clk_delay_between_packets) {
1157                 dev_err(&spi->dev,
1158                         "CS inactive time and packet delay cannot coexist\n");
1159                 return NULL;
1160         }
1161
1162         if (cdata->clk_delay_between_packets)
1163                 cdata->cs_inactive_cycles = cdata->clk_delay_between_packets;
1164
1165         cdata->cs_gpio = -EINVAL;
1166         if (of_find_property(data_np, "nvidia,chipselect-gpio", NULL))
1167                 cdata->cs_gpio = of_get_named_gpio(data_np,
1168                                         "nvidia,chipselect-gpio", 0);
1169         if ((cdata->cs_gpio < 0) && (cdata->cs_gpio != -EINVAL)) {
1170                 dev_err(&spi->dev,
1171                         "CS GPIO is not found on node %s: %d\n",
1172                         data_np->name, cdata->cs_gpio);
1173                 return NULL;
1174         }
1175         if ((cdata->cs_gpio < 0) && (cdata->clk_delay_between_packets)) {
1176                 dev_err(&spi->dev,
1177                         "CS packet delay requires gpio chip select\n");
1178                 return NULL;
1179         }
1180
1181         of_node_put(data_np);
1182         return cdata;
1183 }
1184
1185 static int tegra_spi_setup(struct spi_device *spi)
1186 {
1187         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
1188         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
1189         unsigned long val;
1190         unsigned long flags;
1191         unsigned long intr_mask;
1192         int ret;
1193         unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
1194                         SPI_CS_POL_INACTIVE_0,
1195                         SPI_CS_POL_INACTIVE_1,
1196                         SPI_CS_POL_INACTIVE_2,
1197                         SPI_CS_POL_INACTIVE_3,
1198         };
1199
1200         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
1201                 spi->bits_per_word,
1202                 spi->mode & SPI_CPOL ? "" : "~",
1203                 spi->mode & SPI_CPHA ? "" : "~",
1204                 spi->max_speed_hz);
1205
1206         if (!cdata) {
1207                 cdata = tegra_spi_get_cdata_dt(spi, tspi);
1208                 spi->controller_data = cdata;
1209         }
1210         if (cdata)
1211                 if (cdata->clk_delay_between_packets)
1212                         cdata->cs_inactive_cycles =
1213                                 cdata->clk_delay_between_packets;
1214
1215         /* Set speed to the spi max fequency if spi device has not set */
1216         spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
1217
1218         ret = tegra_spi_runtime_get(tspi);
1219         if (ret < 0) {
1220                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
1221                 return ret;
1222         }
1223
1224         if (cdata && gpio_is_valid(cdata->cs_gpio)) {
1225                 if (!tspi->cs_gpio_reqstd[spi->chip_select]) {
1226                         int gpio_flag = GPIOF_OUT_INIT_HIGH;
1227                         if (spi->mode & SPI_CS_HIGH)
1228                                 gpio_flag = GPIOF_OUT_INIT_LOW;
1229
1230                         ret = devm_gpio_request_one(tspi->dev, cdata->cs_gpio,
1231                                         gpio_flag, "cs_gpio");
1232                         if (ret < 0) {
1233                                 dev_err(&spi->dev,
1234                                         "GPIO request failed: %d\n", ret);
1235                                 return ret;
1236                         }
1237                         tspi->cs_gpio_reqstd[spi->chip_select] = true;
1238                 } else {
1239                         int val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
1240                         gpio_set_value(cdata->cs_gpio, val);
1241                 }
1242         }
1243
1244         if (tspi->chip_data->intr_mask_reg) {
1245                 if ((tspi->cur_direction & DATA_DIR_TX) ||
1246                     (tspi->cur_direction & DATA_DIR_RX)) {
1247                         intr_mask = tegra_spi_readl(tspi, SPI_INTR_MASK);
1248                         if (!tspi->polling_mode)
1249                                 intr_mask &= ~(SPI_INTR_ALL_MASK);
1250                         else
1251                                 intr_mask |= SPI_INTR_ALL_MASK;
1252                         tegra_spi_writel(tspi, intr_mask, SPI_INTR_MASK);
1253                 }
1254         }
1255         spin_lock_irqsave(&tspi->lock, flags);
1256         val = tspi->def_command1_reg;
1257         if (spi->mode & SPI_CS_HIGH)
1258                 val &= ~cs_pol_bit[spi->chip_select];
1259         else
1260                 val |= cs_pol_bit[spi->chip_select];
1261         if (tspi->def_chip_select == spi->chip_select)
1262                 val |= SPI_MODE_SEL(spi->mode & 0x3);
1263
1264         tspi->def_command1_reg = val;
1265         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1266         spin_unlock_irqrestore(&tspi->lock, flags);
1267
1268         tegra_spi_runtime_put(tspi);
1269         return 0;
1270 }
1271
1272 static  int tegra_spi_cs_low(struct spi_device *spi,
1273                 bool state)
1274 {
1275         struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
1276         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
1277         int ret;
1278         unsigned long val;
1279         unsigned long flags;
1280         unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
1281                         SPI_CS_POL_INACTIVE_0,
1282                         SPI_CS_POL_INACTIVE_1,
1283                         SPI_CS_POL_INACTIVE_2,
1284                         SPI_CS_POL_INACTIVE_3,
1285         };
1286
1287         ret = tegra_spi_runtime_get(tspi);
1288         if (ret < 0) {
1289                 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
1290                 return ret;
1291         }
1292
1293         if (cdata && gpio_is_valid(cdata->cs_gpio))
1294                 gpio_set_value(cdata->cs_gpio, 0);
1295
1296         spin_lock_irqsave(&tspi->lock, flags);
1297         if (!(spi->mode & SPI_CS_HIGH)) {
1298                 val = tegra_spi_readl(tspi, SPI_COMMAND1);
1299                 if (state)
1300                         val &= ~cs_pol_bit[spi->chip_select];
1301                 else
1302                         val |= cs_pol_bit[spi->chip_select];
1303                 tegra_spi_writel(tspi, val, SPI_COMMAND1);
1304         }
1305
1306         spin_unlock_irqrestore(&tspi->lock, flags);
1307         tegra_spi_runtime_put(tspi);
1308
1309         return 0;
1310 }
1311
1312 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
1313 {
1314         u32 command1_reg;
1315         u32 fifo_status_reg;
1316         u32 dma_ctrl_reg;
1317         u32 trans_status_reg;
1318
1319         command1_reg = tegra_spi_readl(tspi, SPI_COMMAND1);
1320         fifo_status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1321         dma_ctrl_reg = tegra_spi_readl(tspi, SPI_DMA_CTL);
1322         trans_status_reg = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
1323
1324         dev_err(tspi->dev,
1325                         "SPI_ERR: CMD_0: 0x%08x, FIFO_STS: 0x%08x\n",
1326                         command1_reg, fifo_status_reg);
1327         dev_err(tspi->dev,
1328                         "SPI_ERR: DMA_CTL: 0x%08x, TRANS_STS: 0x%08x\n",
1329                         dma_ctrl_reg, trans_status_reg);
1330 }
1331
1332 static int tegra_spi_wait_on_message_xfer(struct tegra_spi_data *tspi)
1333 {
1334         int ret;
1335
1336         if (tspi->polling_mode)
1337                 ret = tegra_spi_status_poll(tspi);
1338         else
1339                 ret = wait_for_completion_timeout(&tspi->xfer_completion,
1340                                 SPI_DMA_TIMEOUT);
1341         if (WARN_ON(ret == 0)) {
1342                 dev_err(tspi->dev,
1343                                 "spi trasfer timeout, err %d\n", ret);
1344                 tegra_spi_dump_regs(tspi);
1345                 tegra_periph_reset_assert(tspi->clk);
1346                 udelay(2);
1347                 tegra_periph_reset_deassert(tspi->clk);
1348                 if (tspi->is_curr_dma_xfer &&
1349                                 (tspi->cur_direction & DATA_DIR_TX))
1350                         dmaengine_terminate_all(tspi->tx_dma_chan);
1351                 if (tspi->is_curr_dma_xfer &&
1352                                 (tspi->cur_direction & DATA_DIR_RX))
1353                         dmaengine_terminate_all(tspi->rx_dma_chan);
1354                 ret = -EIO;
1355                 return ret;
1356         }
1357         if (tspi->tx_status ||  tspi->rx_status) {
1358                 dev_err(tspi->dev, "Error in Transfer\n");
1359                 tegra_spi_dump_regs(tspi);
1360                 check_and_clear_fifo(tspi);
1361                 ret = -EIO;
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int tegra_spi_wait_remain_message(struct tegra_spi_data *tspi,
1368                 struct spi_transfer *xfer)
1369 {
1370         unsigned total_fifo_words;
1371         int ret = 0;
1372
1373         INIT_COMPLETION(tspi->xfer_completion);
1374
1375         if (tspi->is_curr_dma_xfer) {
1376                 total_fifo_words = tegra_spi_calculate_curr_xfer_param(
1377                                 tspi->cur_spi, tspi, xfer);
1378                 if (total_fifo_words > SPI_FIFO_DEPTH)
1379                         ret = tegra_spi_start_dma_based_transfer(tspi, xfer);
1380                 else
1381                         ret = tegra_spi_start_cpu_based_transfer(tspi, xfer);
1382         } else {
1383                 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, xfer);
1384                 tegra_spi_start_cpu_based_transfer(tspi, xfer);
1385         }
1386
1387         ret = tegra_spi_wait_on_message_xfer(tspi);
1388
1389         return ret;
1390 }
1391
1392 static int tegra_spi_handle_message(struct tegra_spi_data *tspi,
1393                 struct spi_transfer *xfer)
1394 {
1395         int ret = 0;
1396         long wait_status;
1397
1398         if (tspi->boost_reg_access) {
1399                 /* set max clock for faster register access */
1400                 ret = tegra_spi_set_clock_rate(tspi, tspi->spi_max_frequency);
1401                 if (ret < 0)
1402                         return ret;
1403         }
1404
1405         if (!tspi->is_curr_dma_xfer) {
1406                 if (tspi->cur_direction & DATA_DIR_RX)
1407                         tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, xfer);
1408                 if (tspi->cur_direction & DATA_DIR_TX)
1409                         tspi->cur_pos = tspi->cur_tx_pos;
1410                 else if (tspi->cur_direction & DATA_DIR_RX)
1411                         tspi->cur_pos = tspi->cur_rx_pos;
1412                 else
1413                         WARN_ON(1);
1414         } else {
1415                 if (tspi->cur_direction & DATA_DIR_TX) {
1416                         wait_status = wait_for_completion_interruptible_timeout(
1417                                         &tspi->tx_dma_complete,
1418                                         SPI_DMA_TIMEOUT);
1419                         if (wait_status <= 0) {
1420                                 dmaengine_terminate_all(tspi->tx_dma_chan);
1421                                 dev_err(tspi->dev, "TxDma Xfer failed, wait_status - %ld\n",
1422                                                 wait_status);
1423                                 tegra_spi_dump_regs(tspi);
1424                                 tegra_periph_reset_assert(tspi->clk);
1425                                 udelay(2);
1426                                 tegra_periph_reset_deassert(tspi->clk);
1427                                 ret = -EIO;
1428                                 return ret;
1429                         }
1430                 }
1431                 if (tspi->cur_direction & DATA_DIR_RX) {
1432                         wait_status = wait_for_completion_interruptible_timeout(
1433                                         &tspi->rx_dma_complete,
1434                                         SPI_DMA_TIMEOUT);
1435                         if (wait_status <= 0) {
1436                                 dmaengine_terminate_all(tspi->rx_dma_chan);
1437                                 dev_err(tspi->dev,
1438                                                 "RxDma Xfer failed, wait_status -  %ld\n",
1439                                                 wait_status);
1440                                 tegra_spi_dump_regs(tspi);
1441                                 tegra_periph_reset_assert(tspi->clk);
1442                                 udelay(2);
1443                                 tegra_periph_reset_deassert(tspi->clk);
1444                                 ret = -EIO;
1445                                 return ret;
1446                         }
1447                 }
1448                 if (tspi->cur_direction & DATA_DIR_RX)
1449                         tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, xfer);
1450
1451                 if (tspi->cur_direction & DATA_DIR_TX)
1452                         tspi->cur_pos = tspi->cur_tx_pos;
1453                 else
1454                         tspi->cur_pos = tspi->cur_rx_pos;
1455
1456         }
1457         return 0;
1458 }
1459
1460 static int tegra_spi_transfer_one_message(struct spi_master *master,
1461                         struct spi_message *msg)
1462 {
1463         bool is_first_msg = true;
1464         bool is_new_msg = true;
1465         int single_xfer;
1466         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1467         struct spi_transfer *xfer;
1468         struct spi_device *spi = msg->spi;
1469         struct tegra_spi_device_controller_data *cdata = spi->controller_data;
1470         int ret;
1471         int gval = 1;
1472
1473         msg->status = 0;
1474         msg->actual_length = 0;
1475
1476         if (spi->mode & SPI_CS_HIGH)
1477                 gval = 0;
1478
1479         ret = tegra_spi_runtime_get(tspi);
1480         if (ret < 0) {
1481                 dev_err(tspi->dev, "runtime PM get failed: %d\n", ret);
1482                 msg->status = ret;
1483                 spi_finalize_current_message(master);
1484                 return ret;
1485         }
1486
1487         single_xfer = list_is_singular(&msg->transfers);
1488         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1489                 while (1) {
1490                         if (is_new_msg) {
1491                                 INIT_COMPLETION(tspi->xfer_completion);
1492                                 ret = tegra_spi_start_transfer_one(spi, xfer,
1493                                                 is_first_msg, single_xfer);
1494                                 if (ret < 0) {
1495                                         dev_err(tspi->dev,
1496                                                         "spi cannot start transfer,err %d\n",
1497                                                         ret);
1498                                         goto exit;
1499                                 }
1500                                 is_first_msg = false;
1501                                 is_new_msg = false;
1502                                 ret = tegra_spi_wait_on_message_xfer(tspi);
1503                                 if (ret)
1504                                         goto exit;
1505                                 ret = tegra_spi_handle_message(tspi, xfer);
1506                                 if (ret)
1507                                         goto exit;
1508                                 if (tspi->cur_pos == xfer->len) {
1509                                         is_new_msg = true;
1510                                         break;
1511                                 }
1512                         } else {
1513                                 ret = tegra_spi_wait_remain_message(tspi, xfer);
1514                                 if (ret)
1515                                         goto exit;
1516                                 ret = tegra_spi_handle_message(tspi, xfer);
1517                                 if (ret)
1518                                         goto exit;
1519                                 if (tspi->cur_pos == xfer->len) {
1520                                         is_new_msg = true;
1521                                         break;
1522                                 }
1523                         }
1524                 } /* End of while */
1525                 msg->actual_length += xfer->len;
1526                 if (xfer->cs_change && xfer->delay_usecs) {
1527                         tegra_spi_writel(tspi, tspi->def_command1_reg,
1528                                         SPI_COMMAND1);
1529
1530                         if (cdata && gpio_is_valid(cdata->cs_gpio))
1531                                 gpio_set_value(cdata->cs_gpio, gval);
1532
1533                         udelay(xfer->delay_usecs);
1534
1535                         if (cdata && gpio_is_valid(cdata->cs_gpio))
1536                                 gpio_set_value(cdata->cs_gpio, !gval);
1537                 }
1538         }
1539         ret = 0;
1540 exit:
1541         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1542         if (cdata && gpio_is_valid(cdata->cs_gpio))
1543                 gpio_set_value(cdata->cs_gpio, gval);
1544
1545         tegra_spi_runtime_put(tspi);
1546         msg->status = ret;
1547         spi_finalize_current_message(master);
1548         return ret;
1549 }
1550
1551 static void handle_cpu_based_err_xfer(struct tegra_spi_data *tspi)
1552 {
1553         unsigned long flags;
1554
1555         spin_lock_irqsave(&tspi->lock, flags);
1556         if (tspi->tx_status ||  tspi->rx_status) {
1557                 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1558                         tspi->status_reg);
1559
1560                 if (tspi->status_reg & SPI_TX_FIFO_UNF)
1561                         dev_err(tspi->dev, "CpuXfer: TX FIFO UNDERRUN ERROR\n");
1562
1563                 if (tspi->status_reg & SPI_TX_FIFO_OVF)
1564                         dev_err(tspi->dev, "CpuXfer: TX FIFO OVERFLOW ERROR\n");
1565
1566                 if (tspi->status_reg & SPI_RX_FIFO_UNF)
1567                         dev_err(tspi->dev, "CpuXfer: RX FIFO UNDERRUN ERROR\n");
1568
1569                 if (tspi->status_reg & SPI_RX_FIFO_OVF)
1570                         dev_err(tspi->dev, "CpuXfer: RX FIFO OVERFLOW ERROR\n");
1571
1572                 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1573                         tspi->command1_reg, tspi->dma_control_reg);
1574                 tegra_spi_dump_regs(tspi);
1575                 tegra_periph_reset_assert(tspi->clk);
1576                 udelay(2);
1577                 tegra_periph_reset_deassert(tspi->clk);
1578         }
1579         spin_unlock_irqrestore(&tspi->lock, flags);
1580 }
1581
1582 static void handle_dma_based_err_xfer(struct tegra_spi_data *tspi)
1583 {
1584         int err = 0;
1585         unsigned long flags;
1586
1587         spin_lock_irqsave(&tspi->lock, flags);
1588         /* Abort dmas if any error */
1589         if (tspi->cur_direction & DATA_DIR_TX) {
1590                 if (tspi->tx_status) {
1591                         dmaengine_terminate_all(tspi->tx_dma_chan);
1592                         err += 1;
1593                 }
1594         }
1595
1596         if (tspi->cur_direction & DATA_DIR_RX) {
1597                 if (tspi->rx_status) {
1598                         dmaengine_terminate_all(tspi->rx_dma_chan);
1599                         err += 2;
1600                 }
1601         }
1602
1603         if (err) {
1604                 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1605                         tspi->status_reg);
1606
1607                 if (tspi->status_reg & SPI_TX_FIFO_UNF)
1608                         dev_err(tspi->dev, "DmaXfer: TX FIFO UNDERRUN ERROR\n");
1609
1610                 if (tspi->status_reg & SPI_TX_FIFO_OVF)
1611                         dev_err(tspi->dev, "DmaXfer: TX FIFO OVERFLOW ERROR\n");
1612
1613                 if (tspi->status_reg & SPI_RX_FIFO_UNF)
1614                         dev_err(tspi->dev, "DmaXfer: RX FIFO UNDERRUN ERROR\n");
1615
1616                 if (tspi->status_reg & SPI_RX_FIFO_OVF)
1617                         dev_err(tspi->dev, "DmaXfer: RX FIFO OVERFLOW ERROR\n");
1618
1619                 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1620                         tspi->command1_reg, tspi->dma_control_reg);
1621                 tegra_spi_dump_regs(tspi);
1622                 tegra_periph_reset_assert(tspi->clk);
1623                 udelay(2);
1624                 tegra_periph_reset_deassert(tspi->clk);
1625         }
1626         spin_unlock_irqrestore(&tspi->lock, flags);
1627 }
1628
1629 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1630 {
1631         struct tegra_spi_data *tspi = context_data;
1632
1633         if (tspi->polling_mode)
1634                 dev_warn(tspi->dev, "interrupt raised in polling mode\n");
1635
1636         tegra_spi_clear_status(tspi);
1637         if (!tspi->transfer_in_progress) {
1638                 dev_err(tspi->dev, "spurious interrupt, status_reg = 0x%x\n",
1639                                 tspi->status_reg);
1640                 return IRQ_NONE;
1641         }
1642         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1643         if (tspi->cur_direction & SPI_TX_EN)
1644                 tspi->tx_status = tspi->status_reg &
1645                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1646
1647         if (tspi->cur_direction & SPI_RX_EN)
1648                 tspi->rx_status = tspi->status_reg &
1649                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1650
1651         if (!tspi->is_curr_dma_xfer)
1652                 handle_cpu_based_err_xfer(tspi);
1653         else
1654                 handle_dma_based_err_xfer(tspi);
1655
1656         tspi->transfer_in_progress = false;
1657         complete(&tspi->xfer_completion);
1658         return IRQ_HANDLED;
1659 }
1660
1661 static int tegra_spi_status_poll(struct tegra_spi_data *tspi)
1662 {
1663         unsigned int status;
1664         unsigned long timeout;
1665
1666         timeout = SPI_POLL_TIMEOUT;
1667         /*
1668          * Read register would take between 1~3us and 1us delay added in loop
1669          * Calculate timeout taking this into consideration
1670          */
1671         do {
1672                 status = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
1673                 if (status & SPI_RDY)
1674                         break;
1675                 timeout--;
1676                 udelay(1);
1677         } while (timeout);
1678
1679         if (!timeout) {
1680                 dev_err(tspi->dev, "transfer timeout (polling)\n");
1681                 return 0;
1682         }
1683
1684         tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1685         if (tspi->cur_direction & DATA_DIR_TX)
1686                 tspi->tx_status = tspi->status_reg &
1687                                         (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1688
1689         if (tspi->cur_direction & DATA_DIR_RX)
1690                 tspi->rx_status = tspi->status_reg &
1691                                         (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1692
1693         if (!(tspi->cur_direction & DATA_DIR_TX) &&
1694                         !(tspi->cur_direction & DATA_DIR_RX))
1695                 dev_err(tspi->dev, "spurious interrupt, status_reg = 0x%x\n",
1696                                 tspi->status_reg);
1697
1698         tegra_spi_clear_status(tspi);
1699
1700         if (!tspi->is_curr_dma_xfer)
1701                 handle_cpu_based_err_xfer(tspi);
1702         else
1703                 handle_dma_based_err_xfer(tspi);
1704
1705         return timeout;
1706 }
1707
1708 static struct tegra_spi_platform_data *tegra_spi_parse_dt(
1709                 struct platform_device *pdev)
1710 {
1711         struct tegra_spi_platform_data *pdata;
1712         const unsigned int *prop;
1713         struct device_node *np = pdev->dev.of_node;
1714         struct device_node *nc = NULL;
1715         struct device_node *found_nc = NULL;
1716         u32 pval;
1717         int len;
1718         int ret;
1719
1720         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1721         if (!pdata) {
1722                 dev_err(&pdev->dev, "Memory alloc for pdata failed\n");
1723                 return NULL;
1724         }
1725
1726         prop = of_get_property(np, "spi-max-frequency", NULL);
1727         if (prop)
1728                 pdata->spi_max_frequency = be32_to_cpup(prop);
1729
1730         if (of_find_property(np, "nvidia,clock-always-on", NULL))
1731                 pdata->is_clkon_always = true;
1732
1733         if (of_find_property(np, "nvidia,polling-mode", NULL))
1734                 pdata->is_polling_mode = true;
1735
1736         if (of_find_property(np, "nvidia,boost-reg-access", NULL))
1737                 pdata->boost_reg_access = true;
1738
1739         if (of_find_property(np, "nvidia,disable-runtime-pm", NULL))
1740                 pdata->runtime_pm = false;
1741         else
1742                 pdata->runtime_pm = true;
1743
1744         ret = of_property_read_u32(np, "nvidia,maximum-dma-buffer-size", &pval);
1745         if (!ret)
1746                 pdata->max_dma_buffer_size = pval;
1747
1748         /* when no client is defined, default chipselect is zero */
1749         pdata->def_chip_select = 0;
1750
1751         /*
1752          * Last child node or first node which has property as default-cs will
1753          * become the default.
1754          */
1755         for_each_available_child_of_node(np, nc) {
1756                 found_nc = nc;
1757                 ret = of_property_read_bool(nc, "nvidia,default-chipselect");
1758                 if (ret)
1759                         break;
1760         }
1761         if (found_nc) {
1762                 prop = of_get_property(found_nc, "reg", &len);
1763                 if (!prop || len < sizeof(*prop))
1764                         dev_err(&pdev->dev, "%s has no reg property\n",
1765                                         found_nc->full_name);
1766                 else
1767                         pdata->def_chip_select = be32_to_cpup(prop);
1768         }
1769
1770         return pdata;
1771 }
1772
1773 static struct tegra_spi_chip_data tegra114_spi_chip_data = {
1774         .intr_mask_reg = false,
1775         .set_rx_tap_delay = false,
1776 };
1777
1778 static struct tegra_spi_chip_data tegra124_spi_chip_data = {
1779         .intr_mask_reg = false,
1780         .set_rx_tap_delay = true,
1781 };
1782
1783 static struct tegra_spi_chip_data tegra210_spi_chip_data = {
1784         .intr_mask_reg = true,
1785         .set_rx_tap_delay = false,
1786 };
1787
1788 static struct of_device_id tegra_spi_of_match[] = {
1789         {
1790                 .compatible = "nvidia,tegra114-spi",
1791                 .data       = &tegra114_spi_chip_data,
1792         }, {
1793                 .compatible = "nvidia,tegra124-spi",
1794                 .data       = &tegra124_spi_chip_data,
1795         }, {
1796                 .compatible = "nvidia,tegra210-spi",
1797                 .data       = &tegra210_spi_chip_data,
1798         }, {
1799                 .compatible = "nvidia,tegra186-spi",
1800                 .data       = &tegra210_spi_chip_data,
1801         },
1802         {}
1803 };
1804 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1805
1806 static int tegra_spi_probe(struct platform_device *pdev)
1807 {
1808         struct spi_master       *master;
1809         struct tegra_spi_data   *tspi;
1810         struct resource         *r;
1811         struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1812         const struct of_device_id *match;
1813         const struct tegra_spi_chip_data *chip_data = &tegra114_spi_chip_data;
1814         int ret, spi_irq;
1815         int bus_num;
1816
1817         if (pdev->dev.of_node) {
1818                 bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1819                 if (bus_num < 0) {
1820                         dev_warn(&pdev->dev,
1821                                 "Dynamic bus number will be registerd\n");
1822                         bus_num = -1;
1823                 }
1824         } else {
1825                 bus_num = pdev->id;
1826         }
1827
1828         if (!pdata && pdev->dev.of_node)
1829                 pdata = tegra_spi_parse_dt(pdev);
1830
1831         if (!pdata) {
1832                 dev_err(&pdev->dev, "No platform data, exiting\n");
1833                 return -ENODEV;
1834         }
1835
1836         if (!pdata->spi_max_frequency)
1837                 pdata->spi_max_frequency = 25000000; /* 25MHz */
1838
1839         master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1840         if (!master) {
1841                 dev_err(&pdev->dev, "master allocation failed\n");
1842                 return -ENOMEM;
1843         }
1844
1845         /* the spi->mode bits understood by this driver: */
1846         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1847                 SPI_TX_DUAL | SPI_RX_DUAL;
1848         /* supported bpw 4-32 */
1849         master->bits_per_word_mask = (u32) ~(BIT(0)|BIT(1)|BIT(2));
1850         master->setup = tegra_spi_setup;
1851         master->transfer_one_message = tegra_spi_transfer_one_message;
1852         master->num_chipselect = MAX_CHIP_SELECT;
1853         master->bus_num = bus_num;
1854         master->spi_cs_low  = tegra_spi_cs_low;
1855
1856         dev_set_drvdata(&pdev->dev, master);
1857         tspi = spi_master_get_devdata(master);
1858         tspi->master = master;
1859         tspi->clock_always_on = pdata->is_clkon_always;
1860         tspi->polling_mode = pdata->is_polling_mode;
1861         tspi->boost_reg_access = pdata->boost_reg_access;
1862         tspi->runtime_pm = pdata->runtime_pm;
1863         if (!tspi->runtime_pm)
1864                 tspi->clock_always_on = true;
1865         tspi->def_chip_select = pdata->def_chip_select;
1866         tspi->dev = &pdev->dev;
1867
1868         if (pdev->dev.of_node) {
1869                 match = of_match_device(tegra_spi_of_match,
1870                                 &pdev->dev);
1871                 if (match)
1872                         chip_data = match->data;
1873         }
1874         tspi->chip_data = chip_data;
1875
1876         tspi->prod_list = tegra_prod_get(&pdev->dev, NULL);
1877         if (IS_ERR(tspi->prod_list)) {
1878                 dev_err(&pdev->dev, "Prod settings list not initialized\n");
1879                 tspi->prod_list = NULL;
1880         }
1881
1882         spin_lock_init(&tspi->lock);
1883
1884         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1885         if (!r) {
1886                 dev_err(&pdev->dev, "No IO memory resource\n");
1887                 ret = -ENODEV;
1888                 goto exit_free_master;
1889         }
1890         tspi->phys = r->start;
1891         tspi->base = devm_ioremap_resource(&pdev->dev, r);
1892         if (IS_ERR(tspi->base)) {
1893                 dev_err(&pdev->dev,
1894                         "Cannot request memregion/iomap dma address\n");
1895                 ret = PTR_ERR(tspi->base);
1896                 goto exit_free_master;
1897         }
1898
1899         spi_irq = platform_get_irq(pdev, 0);
1900         tspi->irq = spi_irq;
1901
1902         tspi->clk = devm_clk_get(&pdev->dev, "spi");
1903         if (IS_ERR(tspi->clk)) {
1904                 dev_err(&pdev->dev, "can not get clock\n");
1905                 ret = PTR_ERR(tspi->clk);
1906                 goto exit_free_master;
1907         }
1908
1909         tspi->pinctrl = devm_pinctrl_get(&pdev->dev);
1910         if (IS_ERR(tspi->pinctrl)) {
1911                 dev_info(&pdev->dev, "Pincontrol not found\n");
1912                 tspi->pinctrl = NULL;
1913         }
1914
1915         if (tspi->pinctrl) {
1916                 tspi->enable_interface = pinctrl_lookup_state(tspi->pinctrl,
1917                                                 "interface-enable");
1918                 if (IS_ERR(tspi->enable_interface)) {
1919                         dev_info(&pdev->dev, "Static pin configuration used\n");
1920                         tspi->enable_interface = NULL;
1921                 }
1922         }
1923
1924         tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1925         tspi->dma_buf_size = (pdata->max_dma_buffer_size) ?
1926                                 pdata->max_dma_buffer_size :
1927                                 DEFAULT_SPI_DMA_BUF_LEN;
1928         tspi->spi_max_frequency = pdata->spi_max_frequency;
1929         tspi->min_div = 0;
1930
1931         ret = tegra_spi_init_dma_param(tspi, true);
1932         if (ret < 0)
1933                 goto exit_free_master;
1934         ret = tegra_spi_init_dma_param(tspi, false);
1935         if (ret < 0)
1936                 goto exit_rx_dma_free;
1937         tspi->max_buf_size = tspi->dma_buf_size;
1938         init_completion(&tspi->tx_dma_complete);
1939         init_completion(&tspi->rx_dma_complete);
1940
1941         init_completion(&tspi->xfer_completion);
1942
1943         if (tspi->clock_always_on) {
1944                 ret = clk_prepare_enable(tspi->clk);
1945                 if (ret < 0) {
1946                         dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1947                         goto exit_deinit_dma;
1948                 }
1949         }
1950         if (tspi->runtime_pm) {
1951                 pm_runtime_enable(tspi->dev);
1952                 if (!pm_runtime_enabled(tspi->dev)) {
1953                         ret = tegra_spi_runtime_resume(tspi->dev);
1954                         if (ret)
1955                                 goto exit_pm_disable;
1956                 }
1957
1958                 /* set autosuspend delay for the adapter device */
1959                 pm_runtime_set_autosuspend_delay(tspi->dev,
1960                                                  SPI_AUTOSUSPEND_DELAY);
1961                 pm_runtime_use_autosuspend(tspi->dev);
1962         }
1963
1964         ret = tegra_spi_runtime_get(tspi);
1965         if (ret < 0) {
1966                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1967                 goto exit_pm_disable;
1968         }
1969
1970         tegra_periph_reset_assert(tspi->clk);
1971         udelay(2);
1972         tegra_periph_reset_deassert(tspi->clk);
1973
1974         tspi->def_command1_reg  = SPI_M_S | SPI_LSBYTE_FE;
1975         tspi->def_command1_reg |= SPI_CS_SEL(tspi->def_chip_select);
1976         tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1977         tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1978         tegra_spi_runtime_put(tspi);
1979
1980         ret = devm_request_irq(&pdev->dev, tspi->irq, tegra_spi_isr, 0,
1981                         dev_name(&pdev->dev), tspi);
1982         if (ret < 0) {
1983                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1984                                         tspi->irq);
1985                 goto exit_free_master;
1986         }
1987
1988         master->dev.of_node = pdev->dev.of_node;
1989         ret = spi_register_master(master);
1990         if (ret < 0) {
1991                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1992                 goto exit_pm_disable;
1993         }
1994
1995         if (tspi->enable_interface) {
1996                 ret = pinctrl_select_state(tspi->pinctrl,
1997                                 tspi->enable_interface);
1998                 if (ret < 0) {
1999                         dev_err(&pdev->dev, "Enable pin interface failed: %d\n",
2000                                 ret);
2001                         goto exit_master_unreg;
2002                 }
2003         }
2004
2005         return ret;
2006
2007 exit_master_unreg:
2008         spi_unregister_master(master);
2009
2010 exit_pm_disable:
2011         pm_runtime_disable(&pdev->dev);
2012         if (!pm_runtime_status_suspended(&pdev->dev))
2013                 tegra_spi_runtime_suspend(&pdev->dev);
2014         if (tspi->clock_always_on)
2015                 clk_disable_unprepare(tspi->clk);
2016 exit_deinit_dma:
2017         tegra_spi_deinit_dma_param(tspi, false);
2018 exit_rx_dma_free:
2019         tegra_spi_deinit_dma_param(tspi, true);
2020 exit_free_master:
2021         spi_master_put(master);
2022         return ret;
2023 }
2024
2025 static int tegra_spi_remove(struct platform_device *pdev)
2026 {
2027         struct spi_master *master = dev_get_drvdata(&pdev->dev);
2028         struct tegra_spi_data   *tspi = spi_master_get_devdata(master);
2029
2030         spi_unregister_master(master);
2031
2032         if (tspi->tx_dma_chan)
2033                 tegra_spi_deinit_dma_param(tspi, false);
2034
2035         if (tspi->rx_dma_chan)
2036                 tegra_spi_deinit_dma_param(tspi, true);
2037
2038         pm_runtime_disable(&pdev->dev);
2039         if (!pm_runtime_status_suspended(&pdev->dev))
2040                 tegra_spi_runtime_suspend(&pdev->dev);
2041
2042         if (tspi->clock_always_on)
2043                 clk_disable_unprepare(tspi->clk);
2044
2045         if (tspi->prod_list)
2046                 tegra_prod_release(&tspi->prod_list);
2047
2048         return 0;
2049 }
2050
2051 #ifdef CONFIG_PM_SLEEP
2052 static int tegra_spi_suspend(struct device *dev)
2053 {
2054         struct spi_master *master = dev_get_drvdata(dev);
2055         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
2056         int ret;
2057
2058         ret = spi_master_suspend(master);
2059
2060         if (tspi->clock_always_on)
2061                 clk_disable_unprepare(tspi->clk);
2062
2063         return ret;
2064 }
2065
2066 static int tegra_spi_resume(struct device *dev)
2067 {
2068         struct spi_master *master = dev_get_drvdata(dev);
2069         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
2070         unsigned long intr_mask;
2071         int ret;
2072
2073         if (tspi->clock_always_on) {
2074                 ret = clk_prepare_enable(tspi->clk);
2075                 if (ret < 0) {
2076                         dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
2077                         return ret;
2078                 }
2079         }
2080
2081         ret = tegra_spi_runtime_get(tspi);
2082         if (ret < 0) {
2083                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
2084                 return ret;
2085         }
2086         tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
2087         tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
2088         if (tspi->chip_data->intr_mask_reg) {
2089                 if ((tspi->cur_direction & DATA_DIR_TX) ||
2090                     (tspi->cur_direction & DATA_DIR_RX)) {
2091                         intr_mask = tegra_spi_readl(tspi, SPI_INTR_MASK);
2092                         if (!tspi->polling_mode)
2093                                 intr_mask &= ~(SPI_INTR_ALL_MASK);
2094                         else
2095                                 intr_mask |= SPI_INTR_ALL_MASK;
2096                         tegra_spi_writel(tspi, intr_mask, SPI_INTR_MASK);
2097                 }
2098         }
2099         tegra_spi_runtime_put(tspi);
2100
2101         return spi_master_resume(master);
2102 }
2103 #endif
2104
2105 static int tegra_spi_runtime_suspend(struct device *dev)
2106 {
2107         struct spi_master *master = dev_get_drvdata(dev);
2108         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
2109
2110         /* Flush all write which are in PPSB queue by reading back */
2111         tegra_spi_readl(tspi, SPI_COMMAND1);
2112
2113         clk_disable_unprepare(tspi->clk);
2114         return 0;
2115 }
2116
2117 static int tegra_spi_runtime_resume(struct device *dev)
2118 {
2119         struct spi_master *master = dev_get_drvdata(dev);
2120         struct tegra_spi_data *tspi = spi_master_get_devdata(master);
2121         int ret;
2122
2123         ret = clk_prepare_enable(tspi->clk);
2124         if (ret < 0) {
2125                 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
2126                 return ret;
2127         }
2128         return 0;
2129 }
2130
2131 static const struct dev_pm_ops tegra_spi_pm_ops = {
2132         SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
2133                 tegra_spi_runtime_resume, NULL)
2134         SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
2135 };
2136 static struct platform_driver tegra_spi_driver = {
2137         .driver = {
2138                 .name           = "spi-tegra114",
2139                 .owner          = THIS_MODULE,
2140                 .pm             = &tegra_spi_pm_ops,
2141                 .of_match_table = of_match_ptr(tegra_spi_of_match),
2142         },
2143         .probe =        tegra_spi_probe,
2144         .remove =       tegra_spi_remove,
2145 };
2146 module_platform_driver(tegra_spi_driver);
2147
2148 MODULE_ALIAS("platform:spi-tegra114");
2149 MODULE_DESCRIPTION("NVIDIA Tegra114/124 SPI Controller Driver");
2150 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
2151 MODULE_LICENSE("GPL v2");