arch/arm/mach-tegra/board-ardbeg.c

   1 /*
   2  * arch/arm/mach-tegra/board-ardbeg.c
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/i2c-hid.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/delay.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/gpio.h>
  33 #include <linux/input.h>
  34 #include <linux/platform_data/tegra_usb.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/rm31080a_ts.h>
  37 #include <linux/maxim_sti.h>
  38 #include <linux/memblock.h>
  39 #include <linux/spi/spi-tegra.h>
  40 #include <linux/nfc/pn544.h>
  41 #include <linux/rfkill-gpio.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/ti_wilink_st.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/smb349-charger.h>
  46 #include <linux/max17048_battery.h>
  47 #include <linux/leds.h>
  48 #include <linux/i2c/at24.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/i2c.h>
  51 #include <linux/i2c-tegra.h>
  52 #include <linux/platform_data/serial-tegra.h>
  53 #include <linux/edp.h>
  54 #include <linux/usb/tegra_usb_phy.h>
  55 #include <linux/mfd/palmas.h>
  56 #include <linux/clk/tegra.h>
  57 #include <media/tegra_dtv.h>
  58 #include <linux/clocksource.h>
  59 #include <linux/irqchip.h>
  60 #include <linux/irqchip/tegra.h>
  61 #include <linux/tegra-soc.h>
  62 #include <linux/tegra_fiq_debugger.h>
  63 #include <linux/platform_data/tegra_usb_modem_power.h>
  64 #include <linux/platform_data/tegra_ahci.h>
  65 #include <linux/irqchip/tegra.h>
  66 #include <sound/max98090.h>
  67
  68 #include <mach/irqs.h>
  69 #include <mach/pinmux.h>
  70 #include <mach/pinmux-t12.h>
  71 #include <mach/io_dpd.h>
  72 #include <mach/i2s.h>
  73 #include <mach/isomgr.h>
  74 #include <mach/tegra_asoc_pdata.h>
  75 #include <mach/dc.h>
  76 #include <mach/tegra_usb_pad_ctrl.h>
  77
  78 #include <asm/mach-types.h>
  79 #include <asm/mach/arch.h>
  80 #include <mach/gpio-tegra.h>
  81 #include <mach/xusb.h>
  82
  83 #include "board.h"
  84 #include "board-ardbeg.h"
  85 #include "board-common.h"
  86 #include "board-touch-raydium.h"
  87 #include "board-touch-maxim_sti.h"
  88 #include "clock.h"
  89 #include "common.h"
  90 #include "devices.h"
  91 #include "gpio-names.h"
  92 #include "iomap.h"
  93 #include "pm.h"
  94 #include "tegra-board-id.h"
  95 #include "tegra-of-dev-auxdata.h"
  96
  97 static struct board_info board_info, display_board_info;
  98
  99 static struct resource ardbeg_bluedroid_pm_resources[] = {
 100         [0] = {
 101                 .name   = "shutdown_gpio",
 102                 .start  = TEGRA_GPIO_PR1,
 103                 .end    = TEGRA_GPIO_PR1,
 104                 .flags  = IORESOURCE_IO,
 105         },
 106         [1] = {
 107                 .name = "host_wake",
 108                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 109         },
 110         [2] = {
 111                 .name = "gpio_ext_wake",
 112                 .start  = TEGRA_GPIO_PEE1,
 113                 .end    = TEGRA_GPIO_PEE1,
 114                 .flags  = IORESOURCE_IO,
 115         },
 116         [3] = {
 117                 .name = "gpio_host_wake",
 118                 .start  = TEGRA_GPIO_PU6,
 119                 .end    = TEGRA_GPIO_PU6,
 120                 .flags  = IORESOURCE_IO,
 121         },
 122         [4] = {
 123                 .name = "reset_gpio",
 124                 .start  = TEGRA_GPIO_PX1,
 125                 .end    = TEGRA_GPIO_PX1,
 126                 .flags  = IORESOURCE_IO,
 127         },
 128 };
 129
 130 static struct platform_device ardbeg_bluedroid_pm_device = {
 131         .name = "bluedroid_pm",
 132         .id             = 0,
 133         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
 134         .resource       = ardbeg_bluedroid_pm_resources,
 135 };
 136
 137 static noinline void __init ardbeg_setup_bluedroid_pm(void)
 138 {
 139         ardbeg_bluedroid_pm_resources[1].start =
 140                 ardbeg_bluedroid_pm_resources[1].end =
 141                                 gpio_to_irq(TEGRA_GPIO_PU6);
 142         platform_device_register(&ardbeg_bluedroid_pm_device);
 143 }
 144
 145 static struct i2c_board_info __initdata rt5639_board_info = {
 146         I2C_BOARD_INFO("rt5639", 0x1c),
 147 };
 148
 149 static struct max98090_eq_cfg max98090_eq_cfg[] = {
 150 };
 151
 152 static struct max98090_pdata norrin_max98090_pdata = {
 153         /* Equalizer Configuration */
 154         .eq_cfg = max98090_eq_cfg,
 155         .eq_cfgcnt = ARRAY_SIZE(max98090_eq_cfg),
 156
 157         /* Microphone Configuration */
 158         .digmic_left_mode = 1,
 159         .digmic_right_mode = 1,
 160 };
 161
 162 static struct i2c_board_info __initdata max98090_board_info = {
 163         I2C_BOARD_INFO("max98090", 0x10),
 164         .platform_data  = &norrin_max98090_pdata,
 165 };
 166
 167 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
 168         /* name         parent          rate            enabled */
 169         { "pll_m",      NULL,           0,              false},
 170         { "hda",        "pll_p",        108000000,      false},
 171         { "hda2codec_2x", "pll_p",      48000000,       false},
 172         { "pwm",        "pll_p",        48000000,       false},
 173         { "pll_a",      "pll_p_out1",   282240000,      false},
 174         { "i2s1",       "pll_a_out0",   0,              false},
 175         { "i2s3",       "pll_a_out0",   0,              false},
 176         { "i2s4",       "pll_a_out0",   0,              false},
 177         { "spdif_out",  "pll_a_out0",   0,              false},
 178         { "d_audio",    "pll_a_out0",   12288000,       false},
 179         { "dam0",       "clk_m",        12000000,       false},
 180         { "dam1",       "clk_m",        12000000,       false},
 181         { "dam2",       "clk_m",        12000000,       false},
 182         { "audio1",     "i2s1_sync",    0,              false},
 183         { "audio3",     "i2s3_sync",    0,              false},
 184         { "vi_sensor",  "pll_p",        150000000,      false},
 185         { "vi_sensor2", "pll_p",        150000000,      false},
 186         { "cilab",      "pll_p",        150000000,      false},
 187         { "cilcd",      "pll_p",        150000000,      false},
 188         { "cile",       "pll_p",        150000000,      false},
 189         { "i2c1",       "pll_p",        3200000,        false},
 190         { "i2c2",       "pll_p",        3200000,        false},
 191         { "i2c3",       "pll_p",        3200000,        false},
 192         { "i2c4",       "pll_p",        3200000,        false},
 193         { "i2c5",       "pll_p",        3200000,        false},
 194         { "sbc1",       "pll_p",        25000000,       false},
 195         { "sbc2",       "pll_p",        25000000,       false},
 196         { "sbc3",       "pll_p",        25000000,       false},
 197         { "sbc4",       "pll_p",        25000000,       false},
 198         { "sbc5",       "pll_p",        25000000,       false},
 199         { "sbc6",       "pll_p",        25000000,       false},
 200         { "uarta",      "pll_p",        408000000,      false},
 201         { "uartb",      "pll_p",        408000000,      false},
 202         { "uartc",      "pll_p",        408000000,      false},
 203         { "uartd",      "pll_p",        408000000,      false},
 204         { NULL,         NULL,           0,              0},
 205 };
 206
 207 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
 208         .hid_descriptor_address = 0x0,
 209 };
 210
 211 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
 212         I2C_BOARD_INFO("hid", 0x3B),
 213         .platform_data  = &i2c_keyboard_pdata,
 214 };
 215
 216 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
 217         .hid_descriptor_address = 0x20,
 218 };
 219
 220 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
 221         I2C_BOARD_INFO("hid", 0x2C),
 222         .platform_data  = &i2c_touchpad_pdata,
 223 };
 224
 225 static void ardbeg_i2c_init(void)
 226 {
 227         struct board_info board_info;
 228         tegra_get_board_info(&board_info);
 229
 230         if (board_info.board_id == BOARD_PM374) {
 231                 i2c_register_board_info(0, &max98090_board_info, 1);
 232         } else if (board_info.board_id != BOARD_PM359)
 233                 i2c_register_board_info(0, &rt5639_board_info, 1);
 234
 235         if (board_info.board_id == BOARD_PM359 ||
 236                 board_info.board_id == BOARD_PM358 ||
 237                 board_info.board_id == BOARD_PM363 ||
 238                 board_info.board_id == BOARD_PM374) {
 239                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
 240                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
 241
 242                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
 243                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
 244         }
 245 }
 246
 247 #ifndef CONFIG_USE_OF
 248 static struct platform_device *ardbeg_uart_devices[] __initdata = {
 249         &tegra_uarta_device,
 250         &tegra_uartb_device,
 251         &tegra_uartc_device,
 252 };
 253
 254 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
 255         .dma_req_selector = 8,
 256         .modem_interrupt = false,
 257 };
 258
 259 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
 260         .dma_req_selector = 9,
 261         .modem_interrupt = false,
 262 };
 263
 264 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
 265         .dma_req_selector = 10,
 266         .modem_interrupt = false,
 267 };
 268 #endif
 269
 270 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
 271         .dma_req_selector = 19,
 272         .modem_interrupt = false,
 273 };
 274
 275 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
 276         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 277         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 278         .gpio_spkr_en = -1,
 279         .gpio_int_mic_en = -1,
 280         .gpio_ext_mic_en = -1,
 281         .gpio_hp_mute = -1,
 282         .gpio_codec1 = -1,
 283         .gpio_codec2 = -1,
 284         .gpio_codec3 = -1,
 285         .i2s_param[HIFI_CODEC]       = {
 286                 .audio_port_id = 1,
 287                 .is_i2s_master = 1,
 288                 .i2s_mode = TEGRA_DAIFMT_I2S,
 289                 .sample_size    = 16,
 290                 .channels       = 2,
 291                 .bit_clk        = 1536000,
 292         },
 293         .i2s_param[BT_SCO] = {
 294                 .audio_port_id = 3,
 295                 .is_i2s_master = 1,
 296                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 297         },
 298         .i2s_param[BASEBAND]    = {
 299                 .audio_port_id  = 0,
 300                 .is_i2s_master  = 1,
 301                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 302                 .sample_size    = 16,
 303                 .rate           = 16000,
 304                 .channels       = 2,
 305                 .bit_clk        = 1024000,
 306         },
 307 };
 308
 309 static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
 310         .gpio_hp_det            = NORRIN_GPIO_HP_DET,
 311         .gpio_ext_mic_en        = TEGRA_GPIO_HP_DET,
 312         .gpio_hp_mute           = -1,
 313         .edp_support            = true,
 314         .edp_states             = {1080, 842, 0},
 315         .i2s_param[HIFI_CODEC]  = {
 316                 .audio_port_id  = 1,
 317                 .is_i2s_master  = 1,
 318                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 319                 .sample_size    = 16,
 320                 .channels       = 2,
 321                 .bit_clk        = 1536000,
 322         },
 323         .i2s_param[BT_SCO]      = {
 324                 .audio_port_id  = 3,
 325                 .is_i2s_master  = 1,
 326                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 327                 .sample_size    = 16,
 328                 .channels       = 1,
 329                 .bit_clk        = 512000,
 330         },
 331 };
 332
 333 static void ardbeg_audio_init(void)
 334 {
 335         struct board_info board_info;
 336         tegra_get_board_info(&board_info);
 337         if (board_info.board_id == BOARD_PM359 ||
 338                         board_info.board_id == BOARD_PM358 ||
 339                         board_info.board_id == BOARD_PM370 ||
 340                         board_info.board_id == BOARD_PM374 ||
 341                         board_info.board_id == BOARD_PM375 ||
 342                         board_info.board_id == BOARD_PM377 ||
 343                         board_info.board_id == BOARD_PM363) {
 344                 /*Laguna*/
 345                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
 346                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
 347                 if (board_info.board_id != BOARD_PM363)
 348                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
 349         } else {
 350                 /*Ardbeg*/
 351
 352                 if (board_info.board_id == BOARD_E1762 ||
 353                         board_info.board_id == BOARD_P1761 ||
 354                         board_info.board_id == BOARD_E1922) {
 355                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 356                                 TEGRA_GPIO_CDC_IRQ;
 357                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 358                 } else {
 359                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 360                                 TEGRA_GPIO_HP_DET;
 361                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
 362                 }
 363                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 364                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 365         }
 366
 367         if (board_info.board_id == BOARD_E1971) {
 368                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
 369                 ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
 370                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
 371                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
 372         }
 373
 374         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
 375         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
 376
 377         norrin_audio_pdata_max98090.codec_name = "max98090.0-0010";
 378         norrin_audio_pdata_max98090.codec_dai_name = "HiFi";
 379 }
 380
 381 static struct platform_device ardbeg_audio_device_rt5639 = {
 382         .name = "tegra-snd-rt5639",
 383         .id = 0,
 384         .dev = {
 385                 .platform_data = &ardbeg_audio_pdata_rt5639,
 386         },
 387 };
 388
 389 static struct platform_device norrin_audio_device_max98090 = {
 390         .name   = "tegra-snd-max98090",
 391         .id     = 0,
 392         .dev    = {
 393                 .platform_data = &norrin_audio_pdata_max98090,
 394         },
 395 };
 396
 397 static void __init ardbeg_uart_init(void)
 398 {
 399
 400 #ifndef CONFIG_USE_OF
 401         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
 402         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
 403         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
 404         platform_add_devices(ardbeg_uart_devices,
 405                         ARRAY_SIZE(ardbeg_uart_devices));
 406 #endif
 407         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 408         if (!is_tegra_debug_uartport_hs()) {
 409                 int debug_port_id = uart_console_debug_init(3);
 410                 if (debug_port_id < 0)
 411                         return;
 412
 413 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
 414                 tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
 415 #else
 416                 platform_device_register(uart_console_debug_device);
 417 #endif
 418         } else {
 419                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 420                 platform_device_register(&tegra_uartd_device);
 421         }
 422 }
 423
 424 static struct resource tegra_rtc_resources[] = {
 425         [0] = {
 426                 .start = TEGRA_RTC_BASE,
 427                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
 428                 .flags = IORESOURCE_MEM,
 429         },
 430         [1] = {
 431                 .start = INT_RTC,
 432                 .end = INT_RTC,
 433                 .flags = IORESOURCE_IRQ,
 434         },
 435 };
 436
 437 static struct platform_device tegra_rtc_device = {
 438         .name = "tegra_rtc",
 439         .id   = -1,
 440         .resource = tegra_rtc_resources,
 441         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
 442 };
 443
 444 static struct platform_device *ardbeg_devices[] __initdata = {
 445         &tegra_pmu_device,
 446         &tegra_rtc_device,
 447 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
 448         &tegratab_tegra_wakeup_monitor_device,
 449 #endif
 450         &tegra_udc_device,
 451 #if defined(CONFIG_TEGRA_WATCHDOG)
 452         &tegra_wdt0_device,
 453 #endif
 454 #if defined(CONFIG_TEGRA_AVP)
 455         &tegra_avp_device,
 456 #endif
 457 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
 458         &tegra12_se_device,
 459 #endif
 460         &tegra_ahub_device,
 461         &tegra_dam_device0,
 462         &tegra_dam_device1,
 463         &tegra_dam_device2,
 464         &tegra_i2s_device0,
 465         &tegra_i2s_device1,
 466         &tegra_i2s_device3,
 467         &tegra_i2s_device4,
 468         &tegra_spdif_device,
 469         &spdif_dit_device,
 470         &bluetooth_dit_device,
 471         &baseband_dit_device,
 472         &tegra_hda_device,
 473         &tegra_offload_device,
 474         &tegra30_avp_audio_device,
 475 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
 476         &tegra_aes_device,
 477 #endif
 478         &tegra_hier_ictlr_device,
 479 };
 480
 481 static struct tegra_usb_platform_data tegra_udc_pdata = {
 482         .port_otg = true,
 483         .has_hostpc = true,
 484         .unaligned_dma_buf_supported = false,
 485         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 486         .op_mode = TEGRA_USB_OPMODE_DEVICE,
 487         .u_data.dev = {
 488                 .vbus_pmu_irq = 0,
 489                 .vbus_gpio = -1,
 490                 .charging_supported = true,
 491                 .remote_wakeup_supported = false,
 492         },
 493         .u_cfg.utmi = {
 494                 .hssync_start_delay = 0,
 495                 .elastic_limit = 16,
 496                 .idle_wait_delay = 17,
 497                 .term_range_adj = 6,
 498                 .xcvr_setup = 8,
 499                 .xcvr_lsfslew = 2,
 500                 .xcvr_lsrslew = 2,
 501                 .xcvr_setup_offset = 0,
 502                 .xcvr_use_fuses = 1,
 503         },
 504 };
 505
 506 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
 507         .port_otg = true,
 508         .has_hostpc = true,
 509         .unaligned_dma_buf_supported = true,
 510         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 511         .op_mode = TEGRA_USB_OPMODE_HOST,
 512         .u_data.host = {
 513                 .vbus_gpio = -1,
 514                 .hot_plug = false,
 515                 .remote_wakeup_supported = true,
 516                 .power_off_on_suspend = true,
 517         },
 518         .u_cfg.utmi = {
 519                 .hssync_start_delay = 0,
 520                 .elastic_limit = 16,
 521                 .idle_wait_delay = 17,
 522                 .term_range_adj = 6,
 523                 .xcvr_setup = 15,
 524                 .xcvr_lsfslew = 0,
 525                 .xcvr_lsrslew = 3,
 526                 .xcvr_setup_offset = 0,
 527                 .xcvr_use_fuses = 1,
 528                 .vbus_oc_map = 0x4,
 529                 .xcvr_hsslew_lsb = 2,
 530         },
 531 };
 532
 533 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
 534         .port_otg = false,
 535         .has_hostpc = true,
 536         .unaligned_dma_buf_supported = true,
 537         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 538         .op_mode = TEGRA_USB_OPMODE_HOST,
 539         .u_data.host = {
 540                 .vbus_gpio = -1,
 541                 .hot_plug = false,
 542                 .remote_wakeup_supported = true,
 543                 .power_off_on_suspend = true,
 544         },
 545         .u_cfg.utmi = {
 546                 .hssync_start_delay = 0,
 547                 .elastic_limit = 16,
 548                 .idle_wait_delay = 17,
 549                 .term_range_adj = 6,
 550                 .xcvr_setup = 8,
 551                 .xcvr_lsfslew = 2,
 552                 .xcvr_lsrslew = 2,
 553                 .xcvr_setup_offset = 0,
 554                 .xcvr_use_fuses = 1,
 555                 .vbus_oc_map = 0x5,
 556         },
 557 };
 558
 559 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
 560         .port_otg = false,
 561         .has_hostpc = true,
 562         .unaligned_dma_buf_supported = true,
 563         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 564         .op_mode = TEGRA_USB_OPMODE_HOST,
 565         .u_data.host = {
 566                 .vbus_gpio = -1,
 567                 .hot_plug = false,
 568                 .remote_wakeup_supported = true,
 569                 .power_off_on_suspend = true,
 570         },
 571         .u_cfg.utmi = {
 572         .hssync_start_delay = 0,
 573                 .elastic_limit = 16,
 574                 .idle_wait_delay = 17,
 575                 .term_range_adj = 6,
 576                 .xcvr_setup = 8,
 577                 .xcvr_lsfslew = 2,
 578                 .xcvr_lsrslew = 2,
 579                 .xcvr_setup_offset = 0,
 580                 .xcvr_use_fuses = 1,
 581                 .vbus_oc_map = 0x5,
 582         },
 583 };
 584
 585 static struct gpio modem_gpios[] = { /* Bruce modem */
 586         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
 587         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
 588         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
 589 };
 590
 591 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
 592         .port_otg = false,
 593         .has_hostpc = true,
 594         .unaligned_dma_buf_supported = true,
 595         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 596         .op_mode = TEGRA_USB_OPMODE_HOST,
 597         .u_data.host = {
 598                 .vbus_gpio = -1,
 599                 .hot_plug = false,
 600                 .remote_wakeup_supported = true,
 601                 .power_off_on_suspend = true,
 602         },
 603 };
 604
 605 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
 606         .port_otg = false,
 607         .has_hostpc = true,
 608         .unaligned_dma_buf_supported = true,
 609         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 610         .op_mode        = TEGRA_USB_OPMODE_HOST,
 611         .u_data.host = {
 612                 .vbus_gpio = -1,
 613                 .hot_plug = false,
 614                 .remote_wakeup_supported = true,
 615                 .power_off_on_suspend = true,
 616         },
 617 };
 618
 619
 620 static struct tegra_usb_otg_data tegra_otg_pdata = {
 621         .ehci_device = &tegra_ehci1_device,
 622         .ehci_pdata = &tegra_ehci1_utmi_pdata,
 623 };
 624
 625 static void ardbeg_usb_init(void)
 626 {
 627         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 628         int modem_id = tegra_get_modem_id();
 629         struct board_info bi;
 630         tegra_get_pmu_board_info(&bi);
 631
 632         if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
 633                                         board_info.board_id == BOARD_E1784)
 634                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
 635
 636         if (board_info.board_id == BOARD_PM359 ||
 637                         board_info.board_id == BOARD_PM358 ||
 638                         board_info.board_id == BOARD_PM370 ||
 639                         board_info.board_id == BOARD_PM374 ||
 640                         board_info.board_id == BOARD_PM375 ||
 641                         board_info.board_id == BOARD_PM377 ||
 642                         board_info.board_id == BOARD_PM363) {
 643                 /* Laguna */
 644                 /* Host cable is detected through AMS PMU Interrupt */
 645                 if (board_info.major_revision >= 'A' &&
 646                         board_info.major_revision <= 'D' &&
 647                         board_info.board_id == BOARD_PM375) {
 648                         tegra_udc_pdata.id_det_type = TEGRA_USB_VIRTUAL_ID;
 649                         tegra_ehci1_utmi_pdata.id_det_type =
 650                                                 TEGRA_USB_VIRTUAL_ID;
 651                 } else {
 652                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 653                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 654                 }
 655                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
 656         } else {
 657                 /* Ardbeg and TN8 */
 658
 659                 /*
 660                  * TN8 supports vbus changing and it can handle
 661                  * vbus voltages larger then 5V.  Enable this.
 662                  */
 663                 if (board_info.board_id == BOARD_P1761 ||
 664                         board_info.board_id == BOARD_E1784 ||
 665                         board_info.board_id == BOARD_E1780) {
 666
 667                         /*
 668                          * Set the maximum voltage that can be supplied
 669                          * over USB vbus that the board supports if we use
 670                          * a quick charge 2 wall charger.
 671                          */
 672                         tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_9V;
 673                         tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1200;
 674
 675                         /* charger needs to be set to 2A - h/w will do 1.8A */
 676                         tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 2000;
 677                 }
 678
 679                 switch (bi.board_id) {
 680                 case BOARD_E1733:
 681                         /* Host cable is detected through PMU Interrupt */
 682                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 683                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 684                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 685                                                          "as3722-extcon";
 686                         break;
 687                 case BOARD_E1736:
 688                 case BOARD_E1769:
 689                 case BOARD_E1735:
 690                 case BOARD_E1936:
 691                 case BOARD_P1761:
 692                         /* Device cable is detected through PMU Interrupt */
 693                         tegra_udc_pdata.support_pmu_vbus = true;
 694                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
 695                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
 696                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
 697                                                          "palmas-extcon";
 698                         /* Host cable is detected through PMU Interrupt */
 699                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 700                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 701                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
 702                                                          "palmas-extcon";
 703                 }
 704
 705                 /* Enable Y-Cable support */
 706                 if (bi.board_id == BOARD_P1761)
 707                         tegra_ehci1_utmi_pdata.u_data.host.support_y_cable =
 708                                                         true;
 709         }
 710
 711         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
 712                 tegra_otg_pdata.is_xhci = false;
 713                 tegra_udc_pdata.u_data.dev.is_xhci = false;
 714         } else {
 715                 tegra_otg_pdata.is_xhci = true;
 716                 tegra_udc_pdata.u_data.dev.is_xhci = true;
 717         }
 718         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
 719         platform_device_register(&tegra_otg_device);
 720         /* Setup the udc platform data */
 721         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
 722
 723         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 724                 if (!modem_id) {
 725                         if ((bi.board_id != BOARD_P1761) &&
 726                             (bi.board_id != BOARD_E1922) &&
 727                             (bi.board_id != BOARD_E1784)) {
 728                                 tegra_ehci2_device.dev.platform_data =
 729                                         &tegra_ehci2_utmi_pdata;
 730                                 platform_device_register(&tegra_ehci2_device);
 731                         }
 732                 }
 733         }
 734
 735         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 736                 if ((bi.board_id != BOARD_P1761) &&
 737                     (bi.board_id != BOARD_E1922) &&
 738                     (bi.board_id != BOARD_E1784)) {
 739                         tegra_ehci3_device.dev.platform_data =
 740                                 &tegra_ehci3_utmi_pdata;
 741                         platform_device_register(&tegra_ehci3_device);
 742                 }
 743         }
 744
 745 }
 746
 747 static struct tegra_xusb_platform_data xusb_pdata = {
 748         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
 749                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
 750 };
 751
 752 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
 753 static void ardbeg_xusb_init(void)
 754 {
 755         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 756
 757         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
 758
 759         if (board_info.board_id == BOARD_PM359 ||
 760                         board_info.board_id == BOARD_PM358 ||
 761                         board_info.board_id == BOARD_PM374 ||
 762                         board_info.board_id == BOARD_PM370 ||
 763                         board_info.board_id == BOARD_PM363) {
 764                 if (board_info.board_id == BOARD_PM374 ||
 765                         board_info.board_id == BOARD_PM370)
 766                         pr_info("Norrin. 0x%x\n", board_info.board_id);
 767                 else
 768                         pr_info("Laguna. 0x%x\n", board_info.board_id);
 769
 770                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 771                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 772                                 TEGRA_XUSB_SS_P0);
 773
 774                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 775                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 776                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
 777
 778                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 779         } else if (board_info.board_id == BOARD_PM375) {
 780                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 781                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 782                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 783                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
 784                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
 785                 xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
 786         } else {
 787                 /* Ardbeg */
 788                 if (board_info.board_id == BOARD_E1781) {
 789                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
 790                         /* Shield ERS-S */
 791                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 792                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 793
 794                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 795                                 xusb_pdata.portmap &= ~(
 796                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
 797                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 798                 } else {
 799                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
 800                         /* Shield ERS */
 801                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 802                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 803                                         TEGRA_XUSB_SS_P0);
 804
 805                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 806                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 807                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 808                 }
 809                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 810         }
 811
 812         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
 813                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
 814
 815         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
 816                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
 817 }
 818 #endif
 819
 820 static int baseband_init(void)
 821 {
 822         int ret;
 823
 824         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
 825         if (ret) {
 826                 pr_warn("%s:gpio request failed\n", __func__);
 827                 return ret;
 828         }
 829
 830         /* enable pull-down for MDM_COLD_BOOT */
 831         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
 832                                     TEGRA_PUPD_PULL_DOWN);
 833
 834         /* Release modem reset to start boot */
 835         gpio_set_value(MDM_RST, 1);
 836
 837         /* export GPIO for user space access through sysfs */
 838         gpio_export(MDM_RST, false);
 839         gpio_export(MDM_SAR0, false);
 840
 841         return 0;
 842 }
 843
 844 static const struct tegra_modem_operations baseband_operations = {
 845         .init = baseband_init,
 846 };
 847
 848 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
 849         .ops = &baseband_operations,
 850         .regulator_name = "vdd_wwan_mdm",
 851         .wake_gpio = -1,
 852         .boot_gpio = MDM_COLDBOOT,
 853         .boot_irq_flags = IRQF_TRIGGER_RISING |
 854                                     IRQF_TRIGGER_FALLING |
 855                                     IRQF_ONESHOT,
 856         .autosuspend_delay = 2000,
 857         .short_autosuspend_delay = 50,
 858         .tegra_ehci_device = &tegra_ehci2_device,
 859         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
 860         .mdm_power_report_gpio = MDM_POWER_REPORT,
 861         .mdm_power_irq_flags = IRQF_TRIGGER_RISING |
 862                                 IRQF_TRIGGER_FALLING |
 863                                 IRQF_ONESHOT,
 864 };
 865
 866 static struct platform_device icera_bruce_device = {
 867         .name = "tegra_usb_modem_power",
 868         .id = -1,
 869         .dev = {
 870                 .platform_data = &baseband_pdata,
 871         },
 872 };
 873
 874 static void ardbeg_modem_init(void)
 875 {
 876         int modem_id = tegra_get_modem_id();
 877         struct board_info board_info;
 878         struct board_info pmu_board_info;
 879         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 880
 881         tegra_get_board_info(&board_info);
 882         tegra_get_pmu_board_info(&pmu_board_info);
 883         pr_info("%s: modem_id = %d\n", __func__, modem_id);
 884
 885         switch (modem_id) {
 886         case TEGRA_BB_BRUCE:
 887                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 888                         /* Set specific USB wake source for Ardbeg */
 889                         if (board_info.board_id == BOARD_E1780)
 890                                 tegra_set_wake_source(42, INT_USB2);
 891                         if (pmu_board_info.board_id == BOARD_E1736 ||
 892                                 pmu_board_info.board_id == BOARD_E1769 ||
 893                                 pmu_board_info.board_id == BOARD_E1936)
 894                                 baseband_pdata.regulator_name = NULL;
 895                         platform_device_register(&icera_bruce_device);
 896                 }
 897                 break;
 898         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
 899                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 900                         tegra_ehci2_device.dev.platform_data =
 901                                 &tegra_ehci2_hsic_smsc_hub_pdata;
 902                         /* Set specific USB wake source for Ardbeg */
 903                         if (board_info.board_id == BOARD_E1780)
 904                                 tegra_set_wake_source(42, INT_USB2);
 905                         platform_device_register(&tegra_ehci2_device);
 906                 } else
 907                         xusb_pdata.pretend_connect_0 = true;
 908                 break;
 909         default:
 910                 return;
 911         }
 912 }
 913
 914 #ifdef CONFIG_USE_OF
 915 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
 916         T124_SPI_OF_DEV_AUXDATA,
 917         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
 918                                 NULL),
 919         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
 920         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
 921                 NULL),
 922         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
 923                 "gk20a.0", NULL),
 924 #ifdef CONFIG_ARCH_TEGRA_VIC
 925         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
 926 #endif
 927         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
 928                 NULL),
 929         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
 930         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
 931         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
 932         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
 933         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
 934                                 NULL),
 935         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
 936                                 NULL),
 937         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
 938                                 NULL),
 939         T124_I2C_OF_DEV_AUXDATA,
 940         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
 941                                 &xusb_pdata),
 942         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
 943                 NULL),
 944         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
 945                 NULL),
 946         OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
 947                                 NULL),
 948         OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
 949         OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
 950                 NULL),
 951         OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
 952                 NULL),
 953         OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
 954                 NULL),
 955         OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
 956                                 NULL),
 957         OF_DEV_AUXDATA("nvidia,tegra114-ahci-sata", 0x70027000, "tegra-sata.0",
 958                 NULL),
 959         {}
 960 };
 961 #endif
 962
 963 struct maxim_sti_pdata maxim_sti_pdata = {
 964         .touch_fusion         = "/vendor/bin/touch_fusion",
 965         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 966         .fw_name              = "maxim_fp35.bin",
 967         .nl_family            = TF_FAMILY_NAME,
 968         .nl_mc_groups         = 5,
 969         .chip_access_method   = 2,
 970         .default_reset_state  = 0,
 971         .tx_buf_size          = 4100,
 972         .rx_buf_size          = 4100,
 973         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 974         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 975 };
 976
 977 struct maxim_sti_pdata maxim_sti_pdata_rd = {
 978         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
 979         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 980         .fw_name              = "maxim_fp35.bin",
 981         .nl_family            = TF_FAMILY_NAME,
 982         .nl_mc_groups         = 5,
 983         .chip_access_method   = 2,
 984         .default_reset_state  = 0,
 985         .tx_buf_size          = 4100,
 986         .rx_buf_size          = 4100,
 987         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 988         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 989 };
 990
 991 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
 992         .rx_clk_tap_delay = 0,
 993         .is_hw_based_cs = true,
 994         .tx_clk_tap_delay = 0,
 995 };
 996
 997 struct spi_board_info maxim_sti_spi_board = {
 998         .modalias = MAXIM_STI_NAME,
 999         .bus_num = TOUCH_SPI_ID,
1000         .chip_select = TOUCH_SPI_CS,
1001         .max_speed_hz = 12 * 1000 * 1000,
1002         .mode = SPI_MODE_0,
1003         .platform_data = &maxim_sti_pdata,
1004         .controller_data = &maxim_dev_cdata,
1005 };
1006
1007 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
1008         /* name         parent          rate            enabled */
1009         { "extern2",    "pll_p",        41000000,       false},
1010         { "clk_out_2",  "extern2",      40800000,       false},
1011         { NULL,         NULL,           0,              0},
1012 };
1013
1014 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
1015         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1016         .config = 0,
1017         .platform_id = RM_PLATFORM_A010,
1018         .name_of_clock = "clk_out_2",
1019         .name_of_clock_con = "extern2",
1020 };
1021
1022 static struct rm_spi_ts_platform_data rm31080ts_tn8_data = {
1023         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1024         .config = 0,
1025         .platform_id = RM_PLATFORM_T008,
1026         .name_of_clock = "clk_out_2",
1027         .name_of_clock_con = "extern2",
1028 };
1029
1030 static struct rm_spi_ts_platform_data rm31080ts_tn8_p1765_data = {
1031         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1032         .config = 0,
1033         .platform_id = RM_PLATFORM_T008_2,
1034         .name_of_clock = "clk_out_2",
1035         .name_of_clock_con = "extern2",
1036 };
1037
1038 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
1039         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1040         .config = 0,
1041         .platform_id = RM_PLATFORM_P140,
1042         .name_of_clock = "clk_out_2",
1043         .name_of_clock_con = "extern2",
1044 };
1045
1046 struct rm_spi_ts_platform_data rm31080ts_t132loki_data = {
1047         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1048         .config = 0,
1049         .platform_id = RM_PLATFORM_L005,
1050         .name_of_clock = "clk_out_2",
1051         .name_of_clock_con = "extern2",
1052 };
1053
1054 struct rm_spi_ts_platform_data rm31080ts_t132loki_data_jdi_5 = {
1055         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1056         .config = 0,
1057         .platform_id = RM_PLATFORM_L005,
1058         .name_of_clock = "clk_out_2",
1059         .name_of_clock_con = "extern2",
1060         .gpio_sensor_select0 = false,
1061         .gpio_sensor_select1 = true,
1062 };
1063 static struct tegra_spi_device_controller_data dev_cdata = {
1064         .rx_clk_tap_delay = 0,
1065         .tx_clk_tap_delay = 16,
1066 };
1067
1068 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1069         {
1070                 .modalias = "rm_ts_spidev",
1071                 .bus_num = TOUCH_SPI_ID,
1072                 .chip_select = TOUCH_SPI_CS,
1073                 .max_speed_hz = 12 * 1000 * 1000,
1074                 .mode = SPI_MODE_0,
1075                 .controller_data = &dev_cdata,
1076                 .platform_data = &rm31080ts_ardbeg_data,
1077         },
1078 };
1079
1080 static struct spi_board_info rm31080a_tn8_spi_board[1] = {
1081         {
1082                 .modalias = "rm_ts_spidev",
1083                 .bus_num = TOUCH_SPI_ID,
1084                 .chip_select = TOUCH_SPI_CS,
1085                 .max_speed_hz = 18 * 1000 * 1000,
1086                 .mode = SPI_MODE_0,
1087                 .controller_data = &dev_cdata,
1088                 .platform_data = &rm31080ts_tn8_data,
1089         },
1090 };
1091
1092 static struct spi_board_info rm31080a_tn8_p1765_spi_board[1] = {
1093         {
1094                 .modalias = "rm_ts_spidev",
1095                 .bus_num = TOUCH_SPI_ID,
1096                 .chip_select = TOUCH_SPI_CS,
1097                 .max_speed_hz = 18 * 1000 * 1000,
1098                 .mode = SPI_MODE_0,
1099                 .controller_data = &dev_cdata,
1100                 .platform_data = &rm31080ts_tn8_p1765_data,
1101         },
1102 };
1103
1104 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
1105         {
1106                 .modalias = "rm_ts_spidev",
1107                 .bus_num = NORRIN_TOUCH_SPI_ID,
1108                 .chip_select = NORRIN_TOUCH_SPI_CS,
1109                 .max_speed_hz = 12 * 1000 * 1000,
1110                 .mode = SPI_MODE_0,
1111                 .controller_data = &dev_cdata,
1112                 .platform_data = &rm31080ts_norrin_data,
1113         },
1114 };
1115
1116 static int __init ardbeg_touch_init(void)
1117 {
1118         tegra_get_board_info(&board_info);
1119
1120         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1121                 pr_info("%s init maxim touch\n", __func__);
1122 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1123         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1124                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1125                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1126                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1127 #endif
1128         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1129                 pr_info("%s init raydium touch\n", __func__);
1130                 tegra_clk_init_from_table(touch_clk_init_table);
1131                 if (board_info.board_id == BOARD_PM374) {
1132                         rm31080a_norrin_spi_board[0].irq =
1133                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1134                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1135                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1136                                         &rm31080ts_norrin_data,
1137                                         &rm31080a_norrin_spi_board[0],
1138                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1139                 } else if ((board_info.board_id == BOARD_P2530) ||
1140                         (board_info.board_id == BOARD_E2548)) {
1141                         if (board_info.sku == BOARD_SKU_FOSTER)
1142                                 return 0;
1143                         if (tegra_get_touch_panel_id() == TOUCHPANEL_LOKI_JDI5)
1144                                 rm31080a_ardbeg_spi_board[0].platform_data =
1145                                         &rm31080ts_t132loki_data_jdi_5;
1146                         else
1147                                 rm31080a_ardbeg_spi_board[0].platform_data =
1148                                         &rm31080ts_t132loki_data;
1149                         if (board_info.fab >= 0xa3) {
1150                                 rm31080ts_t132loki_data.name_of_clock = NULL;
1151                                 rm31080ts_t132loki_data.name_of_clock_con = NULL;
1152                         } else
1153                                 tegra_clk_init_from_table(touch_clk_init_table);
1154                                 rm31080a_ardbeg_spi_board[0].irq =
1155                                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1156                                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1157                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1158                                         &rm31080ts_t132loki_data,
1159                                         &rm31080a_ardbeg_spi_board[0],
1160                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1161                 } else if (board_info.board_id == BOARD_P1761) {
1162                         rm31080a_tn8_spi_board[0].irq =
1163                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1164                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1165                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1166                                 &rm31080ts_tn8_data,
1167                                 &rm31080a_tn8_spi_board[0],
1168                                 ARRAY_SIZE(rm31080a_tn8_spi_board));
1169                 } else if (board_info.board_id == BOARD_P1765) {
1170                         rm31080a_tn8_p1765_spi_board[0].irq =
1171                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1172                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1173                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1174                                 &rm31080ts_tn8_p1765_data,
1175                                 &rm31080a_tn8_p1765_spi_board[0],
1176                                 ARRAY_SIZE(rm31080a_tn8_p1765_spi_board));
1177                 } else {
1178                         rm31080a_ardbeg_spi_board[0].irq =
1179                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1180                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1181                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1182                                         &rm31080ts_ardbeg_data,
1183                                         &rm31080a_ardbeg_spi_board[0],
1184                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1185                 }
1186         }
1187         return 0;
1188 }
1189
1190 static void __init ardbeg_sysedp_init(void)
1191 {
1192         struct board_info bi;
1193
1194         tegra_get_board_info(&bi);
1195
1196         switch (bi.board_id) {
1197         case BOARD_E1780:
1198                 if (bi.sku == 1100) {
1199                         tn8_new_sysedp_init();
1200                 }
1201                 else
1202                         shield_new_sysedp_init();
1203                 break;
1204         case BOARD_E1971:
1205         case BOARD_E1922:
1206         case BOARD_E1784:
1207         case BOARD_P1761:
1208         case BOARD_P1765:
1209                 tn8_new_sysedp_init();
1210                 break;
1211         case BOARD_PM358:
1212         case BOARD_PM359:
1213         case BOARD_PM375:
1214         case BOARD_PM377:
1215         default:
1216                 break;
1217         }
1218 }
1219
1220 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1221 {
1222         struct board_info bi;
1223
1224         tegra_get_board_info(&bi);
1225
1226         switch (bi.board_id) {
1227         case BOARD_E1780:
1228                 if (bi.sku == 1100)
1229                         tn8_sysedp_dynamic_capping_init();
1230                 else
1231                         shield_sysedp_dynamic_capping_init();
1232                 break;
1233         case BOARD_E1971:
1234         case BOARD_E1922:
1235         case BOARD_E1784:
1236         case BOARD_P1761:
1237         case BOARD_P1765:
1238                 tn8_sysedp_dynamic_capping_init();
1239                 break;
1240         case BOARD_PM358:
1241         case BOARD_PM359:
1242         case BOARD_PM375:
1243         case BOARD_PM377:
1244         default:
1245                 break;
1246         }
1247 }
1248
1249 static void __init ardbeg_sysedp_batmon_init(void)
1250 {
1251         struct board_info bi;
1252
1253         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1254                 return;
1255
1256         tegra_get_board_info(&bi);
1257
1258         switch (bi.board_id) {
1259         case BOARD_E1780:
1260                 if (bi.sku != 1100)
1261                         shield_sysedp_batmon_init();
1262                 break;
1263         case BOARD_PM358:
1264         case BOARD_PM359:
1265         case BOARD_PM375:
1266         case BOARD_PM377:
1267         default:
1268                 break;
1269         }
1270 }
1271
1272
1273
1274 static void __init edp_init(void)
1275 {
1276         struct board_info bi;
1277
1278         tegra_get_board_info(&bi);
1279
1280         switch (bi.board_id) {
1281         case BOARD_E1780:
1282                 if (bi.sku == 1100)
1283                         tn8_edp_init();
1284                 else
1285                         ardbeg_edp_init();
1286                 break;
1287         case BOARD_P1761:
1288                         tn8_edp_init();
1289                         break;
1290         case BOARD_PM358:
1291         case BOARD_PM359:
1292         case BOARD_PM375:
1293         case BOARD_PM377:
1294                         laguna_edp_init();
1295                         break;
1296         case BOARD_P2530:
1297         case BOARD_E2548:
1298                         loki_edp_init();
1299                         break;
1300         default:
1301                         ardbeg_edp_init();
1302                         break;
1303         }
1304 }
1305
1306 static void __init tegra_ardbeg_early_init(void)
1307 {
1308         ardbeg_sysedp_init();
1309         tegra_clk_init_from_table(ardbeg_clk_init_table);
1310         tegra_clk_verify_parents();
1311         if (of_machine_is_compatible("nvidia,jetson-tk1"))
1312                 tegra_soc_device_init("jetson-tk1");
1313         else if (of_machine_is_compatible("nvidia,laguna"))
1314                 tegra_soc_device_init("laguna");
1315         else if (of_machine_is_compatible("nvidia,tn8"))
1316                 tegra_soc_device_init("tn8");
1317         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1318                 tegra_soc_device_init("ardbeg_sata");
1319         else if (of_machine_is_compatible("nvidia,norrin"))
1320                 tegra_soc_device_init("norrin");
1321         else if (of_machine_is_compatible("nvidia,bowmore"))
1322                 tegra_soc_device_init("bowmore");
1323         else if (of_machine_is_compatible("nvidia,t132loki"))
1324                 tegra_soc_device_init("t132loki");
1325         else
1326                 tegra_soc_device_init("ardbeg");
1327 }
1328
1329 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1330         .dma_req_selector = 11,
1331 };
1332
1333 static void __init ardbeg_dtv_init(void)
1334 {
1335         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1336         platform_device_register(&tegra_dtv_device);
1337 }
1338
1339 static struct tegra_io_dpd pexbias_io = {
1340         .name                   = "PEX_BIAS",
1341         .io_dpd_reg_index       = 0,
1342         .io_dpd_bit             = 4,
1343 };
1344 static struct tegra_io_dpd pexclk1_io = {
1345         .name                   = "PEX_CLK1",
1346         .io_dpd_reg_index       = 0,
1347         .io_dpd_bit             = 5,
1348 };
1349 static struct tegra_io_dpd pexclk2_io = {
1350         .name                   = "PEX_CLK2",
1351         .io_dpd_reg_index       = 0,
1352         .io_dpd_bit             = 6,
1353 };
1354
1355 static void __init tegra_ardbeg_late_init(void)
1356 {
1357         struct board_info board_info;
1358         tegra_get_board_info(&board_info);
1359         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1360                 board_info.board_id, board_info.sku,
1361                 board_info.fab, board_info.major_revision,
1362                 board_info.minor_revision);
1363
1364         if (board_info.board_id == BOARD_E2548 ||
1365                         board_info.board_id == BOARD_P2530)
1366                 loki_pinmux_init();
1367 #ifndef CONFIG_MACH_EXUMA
1368         ardbeg_display_init();
1369 #endif
1370         ardbeg_uart_init();
1371         ardbeg_usb_init();
1372         ardbeg_modem_init();
1373 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
1374         ardbeg_xusb_init();
1375 #endif
1376         ardbeg_i2c_init();
1377         ardbeg_audio_init();
1378         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1379         if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
1380                 platform_device_register(&norrin_audio_device_max98090);
1381         else if (board_info.board_id != BOARD_PM359)
1382                 platform_device_register(&ardbeg_audio_device_rt5639);
1383         tegra_io_dpd_init();
1384         if (board_info.board_id == BOARD_E2548 ||
1385                         board_info.board_id == BOARD_P2530)
1386                 loki_sdhci_init();
1387         else
1388                 ardbeg_sdhci_init();
1389
1390         if (board_info.board_id == BOARD_PM359 ||
1391                         board_info.board_id == BOARD_PM358 ||
1392                         board_info.board_id == BOARD_PM370 ||
1393                         board_info.board_id == BOARD_PM375 ||
1394                         board_info.board_id == BOARD_PM377 ||
1395                         board_info.board_id == BOARD_PM363)
1396                 laguna_regulator_init();
1397         else if (board_info.board_id == BOARD_PM374)
1398                 norrin_regulator_init();
1399         else if (board_info.board_id == BOARD_E2548 ||
1400                         board_info.board_id == BOARD_P2530)
1401                 loki_regulator_init();
1402         else
1403                 ardbeg_regulator_init();
1404         ardbeg_dtv_init();
1405         ardbeg_suspend_init();
1406
1407         if ((board_info.board_id == BOARD_PM374) ||
1408                 (board_info.board_id == BOARD_E1971) ||
1409                 (board_info.board_id == BOARD_E1973))
1410                 norrin_emc_init();
1411         else if (board_info.board_id == BOARD_E2548 ||
1412                         board_info.board_id == BOARD_P2530)
1413                 loki_emc_init();
1414         else
1415                 ardbeg_emc_init();
1416
1417         edp_init();
1418         isomgr_init();
1419         ardbeg_touch_init();
1420         if (board_info.board_id == BOARD_E2548 ||
1421                         board_info.board_id == BOARD_P2530)
1422                 loki_panel_init();
1423         else
1424                 ardbeg_panel_init();
1425
1426                 /* put PEX pads into DPD mode to save additional power */
1427                 tegra_io_dpd_enable(&pexbias_io);
1428                 tegra_io_dpd_enable(&pexclk1_io);
1429                 tegra_io_dpd_enable(&pexclk2_io);
1430
1431         if (board_info.board_id == BOARD_E2548 ||
1432                         board_info.board_id == BOARD_P2530)
1433                 loki_kbc_init();
1434
1435 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1436         tegra_wdt_recovery_init();
1437 #endif
1438
1439
1440         if (board_info.board_id == BOARD_PM374 ||
1441                 board_info.board_id == BOARD_PM359 ||
1442                 board_info.board_id == BOARD_PM358 ||
1443                 board_info.board_id == BOARD_PM370 ||
1444                 board_info.board_id == BOARD_PM375 ||
1445                 board_info.board_id == BOARD_PM377 ||
1446                 board_info.board_id == BOARD_PM363) {
1447                 ardbeg_sensors_init();
1448                 norrin_soctherm_init();
1449         }       else if (board_info.board_id == BOARD_E2548 ||
1450                         board_info.board_id == BOARD_P2530) {
1451                 loki_sensors_init();
1452                 loki_fan_init();
1453                 loki_soctherm_init();
1454         }       else {
1455                 ardbeg_sensors_init();
1456                 ardbeg_soctherm_init();
1457         }
1458
1459         ardbeg_setup_bluedroid_pm();
1460         ardbeg_sysedp_dynamic_capping_init();
1461         ardbeg_sysedp_batmon_init();
1462 }
1463
1464 static void __init tegra_ardbeg_init_early(void)
1465 {
1466         tegra_get_board_info(&board_info);
1467         if (board_info.board_id == BOARD_E2548 ||
1468                         board_info.board_id == BOARD_P2530)
1469                 loki_rail_alignment_init();
1470         else
1471                 ardbeg_rail_alignment_init();
1472         tegra12x_init_early();
1473 }
1474
1475 static void __init tegra_ardbeg_dt_init(void)
1476 {
1477         tegra_get_board_info(&board_info);
1478         tegra_get_display_board_info(&display_board_info);
1479
1480         tegra_ardbeg_early_init();
1481 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1482         carveout_linear_set(&tegra_generic_cma_dev);
1483         carveout_linear_set(&tegra_vpr_cma_dev);
1484 #endif
1485 #ifdef CONFIG_USE_OF
1486         ardbeg_camera_auxdata(ardbeg_auxdata_lookup);
1487         of_platform_populate(NULL,
1488                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1489                 &platform_bus);
1490 #endif
1491         tegra_get_board_info(&board_info);
1492         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1493                 board_info.board_id, board_info.sku,
1494                 board_info.fab, board_info.major_revision,
1495                 board_info.minor_revision);
1496
1497         tegra_ardbeg_late_init();
1498 }
1499
1500 static void __init tegra_ardbeg_reserve(void)
1501 {
1502 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1503         ulong tmp;
1504 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1505
1506 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1507                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1508         ulong carveout_size = 0;
1509         ulong fb2_size = SZ_16M;
1510 #else
1511         ulong carveout_size = SZ_1G;
1512         ulong fb2_size = SZ_4M;
1513 #endif
1514         ulong fb1_size = SZ_16M + SZ_2M;
1515         ulong vpr_size = 186 * SZ_1M;
1516
1517 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
1518         /* support FBcon on 4K monitors */
1519         fb2_size = SZ_64M + SZ_8M;      /* 4096*2160*4*2 = 70778880 bytes */
1520 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
1521
1522 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1523         tmp = fb1_size;
1524         fb1_size = fb2_size;
1525         fb2_size = tmp;
1526 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1527
1528         tegra_reserve4(carveout_size, fb1_size, fb2_size, vpr_size);
1529 }
1530
1531 static const char * const ardbeg_dt_board_compat[] = {
1532         "nvidia,ardbeg",
1533         NULL
1534 };
1535
1536 static const char * const laguna_dt_board_compat[] = {
1537         "nvidia,laguna",
1538         NULL
1539 };
1540
1541 static const char * const tn8_dt_board_compat[] = {
1542         "nvidia,tn8",
1543         NULL
1544 };
1545
1546 static const char * const ardbeg_sata_dt_board_compat[] = {
1547         "nvidia,ardbeg_sata",
1548         NULL
1549 };
1550
1551 static const char * const norrin_dt_board_compat[] = {
1552         "nvidia,norrin",
1553         NULL
1554 };
1555
1556 static const char * const bowmore_dt_board_compat[] = {
1557         "nvidia,bowmore",
1558         NULL
1559 };
1560
1561 static const char * const loki_dt_board_compat[] = {
1562         "nvidia,t132loki",
1563         NULL
1564 };
1565
1566 static const char * const jetson_dt_board_compat[] = {
1567         "nvidia,jetson-tk1",
1568         NULL
1569 };
1570
1571 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1572 DT_MACHINE_START(LOKI, "t132loki")
1573         .atag_offset    = 0x100,
1574         .smp            = smp_ops(tegra_smp_ops),
1575         .map_io         = tegra_map_common_io,
1576         .reserve        = tegra_ardbeg_reserve,
1577         .init_early     = tegra_ardbeg_init_early,
1578         .init_irq       = irqchip_init,
1579         .init_time      = clocksource_of_init,
1580         .init_machine   = tegra_ardbeg_dt_init,
1581         .restart        = tegra_assert_system_reset,
1582         .dt_compat      = loki_dt_board_compat,
1583         .init_late      = tegra_init_late
1584 MACHINE_END
1585 #endif
1586
1587 DT_MACHINE_START(LAGUNA, "laguna")
1588         .atag_offset    = 0x100,
1589         .smp            = smp_ops(tegra_smp_ops),
1590         .map_io         = tegra_map_common_io,
1591         .reserve        = tegra_ardbeg_reserve,
1592         .init_early     = tegra_ardbeg_init_early,
1593         .init_irq       = irqchip_init,
1594         .init_time      = clocksource_of_init,
1595         .init_machine   = tegra_ardbeg_dt_init,
1596         .restart        = tegra_assert_system_reset,
1597         .dt_compat      = laguna_dt_board_compat,
1598         .init_late      = tegra_init_late
1599 MACHINE_END
1600
1601 DT_MACHINE_START(TN8, "tn8")
1602         .atag_offset    = 0x100,
1603         .smp            = smp_ops(tegra_smp_ops),
1604         .map_io         = tegra_map_common_io,
1605         .reserve        = tegra_ardbeg_reserve,
1606         .init_early     = tegra_ardbeg_init_early,
1607         .init_irq       = irqchip_init,
1608         .init_time      = clocksource_of_init,
1609         .init_machine   = tegra_ardbeg_dt_init,
1610         .restart        = tegra_assert_system_reset,
1611         .dt_compat      = tn8_dt_board_compat,
1612         .init_late      = tegra_init_late
1613 MACHINE_END
1614
1615 DT_MACHINE_START(NORRIN, "norrin")
1616         .atag_offset    = 0x100,
1617         .smp            = smp_ops(tegra_smp_ops),
1618         .map_io         = tegra_map_common_io,
1619         .reserve        = tegra_ardbeg_reserve,
1620         .init_early     = tegra_ardbeg_init_early,
1621         .init_irq       = irqchip_init,
1622         .init_time      = clocksource_of_init,
1623         .init_machine   = tegra_ardbeg_dt_init,
1624         .restart        = tegra_assert_system_reset,
1625         .dt_compat      = norrin_dt_board_compat,
1626         .init_late      = tegra_init_late
1627 MACHINE_END
1628
1629 DT_MACHINE_START(BOWMORE, "bowmore")
1630         .atag_offset    = 0x100,
1631         .smp            = smp_ops(tegra_smp_ops),
1632         .map_io         = tegra_map_common_io,
1633         .reserve        = tegra_ardbeg_reserve,
1634         .init_early     = tegra_ardbeg_init_early,
1635         .init_irq       = irqchip_init,
1636         .init_time      = clocksource_of_init,
1637         .init_machine   = tegra_ardbeg_dt_init,
1638         .restart        = tegra_assert_system_reset,
1639         .dt_compat      = bowmore_dt_board_compat,
1640         .init_late      = tegra_init_late
1641 MACHINE_END
1642
1643 DT_MACHINE_START(ARDBEG, "ardbeg")
1644         .atag_offset    = 0x100,
1645         .smp            = smp_ops(tegra_smp_ops),
1646         .map_io         = tegra_map_common_io,
1647         .reserve        = tegra_ardbeg_reserve,
1648         .init_early     = tegra_ardbeg_init_early,
1649         .init_irq       = irqchip_init,
1650         .init_time      = clocksource_of_init,
1651         .init_machine   = tegra_ardbeg_dt_init,
1652         .restart        = tegra_assert_system_reset,
1653         .dt_compat      = ardbeg_dt_board_compat,
1654         .init_late      = tegra_init_late
1655 MACHINE_END
1656
1657 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1658         .atag_offset    = 0x100,
1659         .smp            = smp_ops(tegra_smp_ops),
1660         .map_io         = tegra_map_common_io,
1661         .reserve        = tegra_ardbeg_reserve,
1662         .init_early     = tegra_ardbeg_init_early,
1663         .init_irq       = irqchip_init,
1664         .init_time      = clocksource_of_init,
1665         .init_machine   = tegra_ardbeg_dt_init,
1666         .restart        = tegra_assert_system_reset,
1667         .dt_compat      = ardbeg_sata_dt_board_compat,
1668         .init_late      = tegra_init_late
1669
1670 MACHINE_END
1671
1672 DT_MACHINE_START(JETSON_TK1, "jetson-tk1")
1673         .atag_offset    = 0x100,
1674         .smp            = smp_ops(tegra_smp_ops),
1675         .map_io         = tegra_map_common_io,
1676         .reserve        = tegra_ardbeg_reserve,
1677         .init_early     = tegra_ardbeg_init_early,
1678         .init_irq       = irqchip_init,
1679         .init_time      = clocksource_of_init,
1680         .init_machine   = tegra_ardbeg_dt_init,
1681         .restart        = tegra_assert_system_reset,
1682         .dt_compat      = jetson_dt_board_compat,
1683         .init_late      = tegra_init_late
1684 MACHINE_END