drivers/iio/imu/nvi_mpu/nvi_mpu.c

   1 /* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   2  *
   3  * This software is licensed under the terms of the GNU General Public
   4  * License version 2, as published by the Free Software Foundation, and
   5  * may be copied, distributed, and modified under those terms.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include "nvi.h"
  16
  17 enum inv_filter_e {
  18         INV_FILTER_256HZ_NOLPF2 = 0,
  19         INV_FILTER_188HZ,
  20         INV_FILTER_98HZ,
  21         INV_FILTER_42HZ,
  22         INV_FILTER_20HZ,
  23         INV_FILTER_10HZ,
  24         INV_FILTER_5HZ,
  25         INV_FILTER_2100HZ_NOLPF,
  26         NUM_FILTER
  27 };
  28
  29 #define MPU_MEM_OTP_BANK_0              (16)
  30
  31 /* produces an unique identifier for each device based on the
  32    combination of product version and product revision */
  33 struct prod_rev_map_t {
  34         u16 mpl_product_key;
  35         u8 silicon_rev;
  36         u16 gyro_trim;
  37         u16 accel_trim;
  38 };
  39
  40 /* registers */
  41 #define REG_XA_OFFS_L_TC                (0x07)
  42 #define REG_PRODUCT_ID                  (0x0C)
  43 #define REG_ST_GCT_X                    (0x0D)
  44
  45 /* data definitions */
  46 #define BYTES_PER_SENSOR         6
  47 #define INV_MPU_SAMPLE_RATE_CHANGE_STABLE 50
  48
  49 /* data header defines */
  50 #define MPU6XXX_MAX_MPU_MEM      (256 * 12)
  51
  52 #define ST_THRESHOLD_MULTIPLIER  10
  53 #define ST_MAX_SAMPLES           500
  54 #define ST_MAX_THRESHOLD         100
  55
  56 #define MEM_ADDR_PROD_REV        0x6
  57 #define SOFT_PROD_VER_BYTES      5
  58
  59 /* init parameters */
  60 #define MPL_PROD_KEY(ver, rev)  (ver * 100 + rev)
  61 #define NUM_OF_PROD_REVS (ARRAY_SIZE(prod_rev_map))
  62 /*---- MPU6050 Silicon Revisions ----*/
  63 #define MPU_SILICON_REV_A2                    1       /* MPU6050A2 Device */
  64 #define MPU_SILICON_REV_B1                    2       /* MPU6050B1 Device */
  65
  66 #define BIT_PRFTCH_EN                         0x40
  67 #define BIT_CFG_USER_BANK                     0x20
  68
  69 #define DEFAULT_ACCEL_TRIM                    16384
  70 #define DEFAULT_GYRO_TRIM                     131
  71
  72 /*--- Test parameters defaults --- */
  73 #define DEF_OLDEST_SUPP_PROD_REV        8
  74 #define DEF_OLDEST_SUPP_SW_REV          2
  75
  76 /* sample rate */
  77 #define DEF_SELFTEST_SAMPLE_RATE        0
  78 /* full scale setting dps */
  79 #define DEF_SELFTEST_GYRO_FS            (0 << 3)
  80 #define DEF_SELFTEST_ACCEL_FS           (2 << 3)
  81 #define DEF_SELFTEST_GYRO_SENS          (32768 / 250)
  82 /* wait time before collecting data */
  83 #define DEF_GYRO_WAIT_TIME              10
  84 #define DEF_ST_STABLE_TIME              20
  85 #define DEF_GYRO_SCALE                  131
  86 #define DEF_ST_PRECISION                1000
  87 #define DEF_ST_ACCEL_FS_MG              8000UL
  88 #define DEF_ST_SCALE                    (1L << 15)
  89 #define DEF_ST_TRY_TIMES                2
  90 #define DEF_ST_ACCEL_RESULT_SHIFT       1
  91 #define DEF_ST_ABS_THRESH               20
  92 #define DEF_ST_TOR                      2
  93
  94 #define X                               0
  95 #define Y                               1
  96 #define Z                               2
  97 /*---- MPU6050 notable product revisions ----*/
  98 #define MPU_PRODUCT_KEY_B1_E1_5         105
  99 /* accelerometer Hw self test min and max bias shift (mg) */
 100 #define DEF_ACCEL_ST_SHIFT_MIN          300
 101 #define DEF_ACCEL_ST_SHIFT_MAX          950
 102
 103 #define DEF_ACCEL_ST_SHIFT_DELTA        500
 104 #define DEF_GYRO_CT_SHIFT_DELTA         500
 105 /* gyroscope Coriolis self test min and max bias shift (dps) */
 106 #define DEF_GYRO_CT_SHIFT_MIN           10
 107 #define DEF_GYRO_CT_SHIFT_MAX           105
 108
 109 /*---- MPU6500 Self Test Pass/Fail Criteria ----*/
 110 /* Gyro Offset Max Value (dps) */
 111 #define DEF_GYRO_OFFSET_MAX             20
 112 /* Gyro Self Test Absolute Limits ST_AL (dps) */
 113 #define DEF_GYRO_ST_AL                  60
 114 /* Accel Self Test Absolute Limits ST_AL (mg) */
 115 #define DEF_ACCEL_ST_AL_MIN             225
 116 #define DEF_ACCEL_ST_AL_MAX             675
 117 #define DEF_6500_ACCEL_ST_SHIFT_DELTA   500
 118 #define DEF_6500_GYRO_CT_SHIFT_DELTA    500
 119 #define DEF_ST_MPU6500_ACCEL_LPF        2
 120 #define DEF_ST_6500_ACCEL_FS_MG         2000UL
 121 #define DEF_SELFTEST_6500_ACCEL_FS      (0 << 3)
 122
 123 /* Note: The ST_AL values are only used when ST_OTP = 0,
 124  * i.e no factory self test values for reference
 125  */
 126
 127 /* NOTE: product entries are in chronological order */
 128 static const struct prod_rev_map_t prod_rev_map[] = {
 129         /* prod_ver = 0 */
 130         {MPL_PROD_KEY(0,   1), MPU_SILICON_REV_A2, 131, 16384},
 131         {MPL_PROD_KEY(0,   2), MPU_SILICON_REV_A2, 131, 16384},
 132         {MPL_PROD_KEY(0,   3), MPU_SILICON_REV_A2, 131, 16384},
 133         {MPL_PROD_KEY(0,   4), MPU_SILICON_REV_A2, 131, 16384},
 134         {MPL_PROD_KEY(0,   5), MPU_SILICON_REV_A2, 131, 16384},
 135         {MPL_PROD_KEY(0,   6), MPU_SILICON_REV_A2, 131, 16384},
 136         /* prod_ver = 1 */
 137         {MPL_PROD_KEY(0,   7), MPU_SILICON_REV_A2, 131, 16384},
 138         {MPL_PROD_KEY(0,   8), MPU_SILICON_REV_A2, 131, 16384},
 139         {MPL_PROD_KEY(0,   9), MPU_SILICON_REV_A2, 131, 16384},
 140         {MPL_PROD_KEY(0,  10), MPU_SILICON_REV_A2, 131, 16384},
 141         {MPL_PROD_KEY(0,  11), MPU_SILICON_REV_A2, 131, 16384},
 142         {MPL_PROD_KEY(0,  12), MPU_SILICON_REV_A2, 131, 16384},
 143         {MPL_PROD_KEY(0,  13), MPU_SILICON_REV_A2, 131, 16384},
 144         {MPL_PROD_KEY(0,  14), MPU_SILICON_REV_A2, 131, 16384},
 145         {MPL_PROD_KEY(0,  15), MPU_SILICON_REV_A2, 131, 16384},
 146         {MPL_PROD_KEY(0,  27), MPU_SILICON_REV_A2, 131, 16384},
 147         /* prod_ver = 1 */
 148         {MPL_PROD_KEY(1,  16), MPU_SILICON_REV_B1, 131, 16384},
 149         {MPL_PROD_KEY(1,  17), MPU_SILICON_REV_B1, 131, 16384},
 150         {MPL_PROD_KEY(1,  18), MPU_SILICON_REV_B1, 131, 16384},
 151         {MPL_PROD_KEY(1,  19), MPU_SILICON_REV_B1, 131, 16384},
 152         {MPL_PROD_KEY(1,  20), MPU_SILICON_REV_B1, 131, 16384},
 153         {MPL_PROD_KEY(1,  28), MPU_SILICON_REV_B1, 131, 16384},
 154         {MPL_PROD_KEY(1,   1), MPU_SILICON_REV_B1, 131, 16384},
 155         {MPL_PROD_KEY(1,   2), MPU_SILICON_REV_B1, 131, 16384},
 156         {MPL_PROD_KEY(1,   3), MPU_SILICON_REV_B1, 131, 16384},
 157         {MPL_PROD_KEY(1,   4), MPU_SILICON_REV_B1, 131, 16384},
 158         {MPL_PROD_KEY(1,   5), MPU_SILICON_REV_B1, 131, 16384},
 159         {MPL_PROD_KEY(1,   6), MPU_SILICON_REV_B1, 131, 16384},
 160         /* prod_ver = 2 */
 161         {MPL_PROD_KEY(2,   7), MPU_SILICON_REV_B1, 131, 16384},
 162         {MPL_PROD_KEY(2,   8), MPU_SILICON_REV_B1, 131, 16384},
 163         {MPL_PROD_KEY(2,   9), MPU_SILICON_REV_B1, 131, 16384},
 164         {MPL_PROD_KEY(2,  10), MPU_SILICON_REV_B1, 131, 16384},
 165         {MPL_PROD_KEY(2,  11), MPU_SILICON_REV_B1, 131, 16384},
 166         {MPL_PROD_KEY(2,  12), MPU_SILICON_REV_B1, 131, 16384},
 167         {MPL_PROD_KEY(2,  29), MPU_SILICON_REV_B1, 131, 16384},
 168         /* prod_ver = 3 */
 169         {MPL_PROD_KEY(3,  30), MPU_SILICON_REV_B1, 131, 16384},
 170         /* prod_ver = 4 */
 171         {MPL_PROD_KEY(4,  31), MPU_SILICON_REV_B1, 131,  8192},
 172         {MPL_PROD_KEY(4,   1), MPU_SILICON_REV_B1, 131,  8192},
 173         {MPL_PROD_KEY(4,   3), MPU_SILICON_REV_B1, 131,  8192},
 174         /* prod_ver = 5 */
 175         {MPL_PROD_KEY(5,   3), MPU_SILICON_REV_B1, 131, 16384},
 176         /* prod_ver = 6 */
 177         {MPL_PROD_KEY(6,  19), MPU_SILICON_REV_B1, 131, 16384},
 178         /* prod_ver = 7 */
 179         {MPL_PROD_KEY(7,  19), MPU_SILICON_REV_B1, 131, 16384},
 180         /* prod_ver = 8 */
 181         {MPL_PROD_KEY(8,  19), MPU_SILICON_REV_B1, 131, 16384},
 182         /* prod_ver = 9 */
 183         {MPL_PROD_KEY(9,  19), MPU_SILICON_REV_B1, 131, 16384},
 184         /* prod_ver = 10 */
 185         {MPL_PROD_KEY(10, 19), MPU_SILICON_REV_B1, 131, 16384}
 186 };
 187
 188 /*
 189 *   List of product software revisions
 190 *
 191 *   NOTE :
 192 *   software revision 0 falls back to the old detection method
 193 *   based off the product version and product revision per the
 194 *   table above
 195 */
 196 static const struct prod_rev_map_t sw_rev_map[] = {
 197         {0,                  0,   0,     0},
 198         {1, MPU_SILICON_REV_B1, 131,  8192},    /* rev C */
 199         {2, MPU_SILICON_REV_B1, 131, 16384}     /* rev D */
 200 };
 201
 202 static const u16 mpu_6500_st_tb[256] = {
 203         2620, 2646, 2672, 2699, 2726, 2753, 2781, 2808,
 204         2837, 2865, 2894, 2923, 2952, 2981, 3011, 3041,
 205         3072, 3102, 3133, 3165, 3196, 3228, 3261, 3293,
 206         3326, 3359, 3393, 3427, 3461, 3496, 3531, 3566,
 207         3602, 3638, 3674, 3711, 3748, 3786, 3823, 3862,
 208         3900, 3939, 3979, 4019, 4059, 4099, 4140, 4182,
 209         4224, 4266, 4308, 4352, 4395, 4439, 4483, 4528,
 210         4574, 4619, 4665, 4712, 4759, 4807, 4855, 4903,
 211         4953, 5002, 5052, 5103, 5154, 5205, 5257, 5310,
 212         5363, 5417, 5471, 5525, 5581, 5636, 5693, 5750,
 213         5807, 5865, 5924, 5983, 6043, 6104, 6165, 6226,
 214         6289, 6351, 6415, 6479, 6544, 6609, 6675, 6742,
 215         6810, 6878, 6946, 7016, 7086, 7157, 7229, 7301,
 216         7374, 7448, 7522, 7597, 7673, 7750, 7828, 7906,
 217         7985, 8065, 8145, 8227, 8309, 8392, 8476, 8561,
 218         8647, 8733, 8820, 8909, 8998, 9088, 9178, 9270,
 219         9363, 9457, 9551, 9647, 9743, 9841, 9939, 10038,
 220         10139, 10240, 10343, 10446, 10550, 10656, 10763, 10870,
 221         10979, 11089, 11200, 11312, 11425, 11539, 11654, 11771,
 222         11889, 12008, 12128, 12249, 12371, 12495, 12620, 12746,
 223         12874, 13002, 13132, 13264, 13396, 13530, 13666, 13802,
 224         13940, 14080, 14221, 14363, 14506, 14652, 14798, 14946,
 225         15096, 15247, 15399, 15553, 15709, 15866, 16024, 16184,
 226         16346, 16510, 16675, 16842, 17010, 17180, 17352, 17526,
 227         17701, 17878, 18057, 18237, 18420, 18604, 18790, 18978,
 228         19167, 19359, 19553, 19748, 19946, 20145, 20347, 20550,
 229         20756, 20963, 21173, 21385, 21598, 21814, 22033, 22253,
 230         22475, 22700, 22927, 23156, 23388, 23622, 23858, 24097,
 231         24338, 24581, 24827, 25075, 25326, 25579, 25835, 26093,
 232         26354, 26618, 26884, 27153, 27424, 27699, 27976, 28255,
 233         28538, 28823, 29112, 29403, 29697, 29994, 30294, 30597,
 234         30903, 31212, 31524, 31839, 32157, 32479, 32804
 235 };
 236
 237 static const int accel_st_tb[31] = {
 238         340, 351, 363, 375, 388, 401, 414, 428,
 239         443, 458, 473, 489, 506, 523, 541, 559,
 240         578, 597, 617, 638, 660, 682, 705, 729,
 241         753, 779, 805, 832, 860, 889, 919
 242 };
 243
 244 static const int gyro_6050_st_tb[31] = {
 245         3275, 3425, 3583, 3748, 3920, 4100, 4289, 4486,
 246         4693, 4909, 5134, 5371, 5618, 5876, 6146, 6429,
 247         6725, 7034, 7358, 7696, 8050, 8421, 8808, 9213,
 248         9637, 10080, 10544, 11029, 11537, 12067, 12622
 249 };
 250
 251
 252 /**
 253  *  index_of_key()- Inverse lookup of the index of an MPL product key .
 254  *  @key: the MPL product indentifier also referred to as 'key'.
 255  */
 256 static short index_of_key(u16 key)
 257 {
 258         int i;
 259
 260         for (i = 0; i < NUM_OF_PROD_REVS; i++)
 261                 if (prod_rev_map[i].mpl_product_key == key)
 262                         return (short)i;
 263         return -EINVAL;
 264 }
 265
 266 int inv_init_6050(struct nvi_state *st)
 267 {
 268         int ret;
 269         u8 prod_ver = 0x00, prod_rev = 0x00;
 270         struct prod_rev_map_t *p_rev;
 271         u8 bank = (BIT_PRFTCH_EN | BIT_CFG_USER_BANK | MPU_MEM_OTP_BANK_0);
 272         u16 mem_addr = ((bank << 8) | MEM_ADDR_PROD_REV);
 273         u16 key;
 274         u8 regs[5];
 275         u16 sw_rev;
 276         short index;
 277         struct inv_chip_info_s *chip_info = &st->chip_info;
 278
 279         st->snsr[DEV_ACC].matrix = true;
 280         st->snsr[DEV_GYR].matrix = true;
 281         if (st->snsr[DEV_ACC].cfg.thresh_hi > 0)
 282                 st->en_msk |= (1 << EN_LP);
 283         else
 284                 st->en_msk &= ~(1 << EN_LP);
 285         ret = nvi_i2c_r(st, 0, REG_PRODUCT_ID, 1, &prod_ver);
 286         if (ret)
 287                 return ret;
 288
 289         prod_ver &= 0xf;
 290         /*memory read need more time after power up */
 291         msleep(POWER_UP_TIME);
 292         ret = nvi_mem_rd(st, mem_addr, 1, &prod_rev);
 293         if (ret)
 294                 return ret;
 295
 296         prod_rev >>= 2;
 297         /* clean the prefetch and cfg user bank bits */
 298         ret = nvi_i2c_wr(st, &st->hal->reg->mem_bank, 0, __func__);
 299         if (ret)
 300                 return ret;
 301
 302         /* get the software-product version, read from XA_OFFS_L */
 303         ret = nvi_i2c_r(st, 0 , REG_XA_OFFS_L_TC, SOFT_PROD_VER_BYTES, regs);
 304         if (ret)
 305                 return ret;
 306
 307         sw_rev = (regs[4] & 0x01) << 2 |        /* 0x0b, bit 0 */
 308                  (regs[2] & 0x01) << 1 |        /* 0x09, bit 0 */
 309                  (regs[0] & 0x01);              /* 0x07, bit 0 */
 310         /* if 0, use the product key to determine the type of part */
 311         if (sw_rev == 0) {
 312                 key = MPL_PROD_KEY(prod_ver, prod_rev);
 313                 if (key == 0)
 314                         return -EINVAL;
 315
 316                 index = index_of_key(key);
 317                 if (index < 0 || index >= NUM_OF_PROD_REVS)
 318                         return -EINVAL;
 319
 320                 /* check MPL is compiled for this device */
 321                 if (prod_rev_map[index].silicon_rev != MPU_SILICON_REV_B1)
 322                         return -EINVAL;
 323
 324                 p_rev = (struct prod_rev_map_t *)&prod_rev_map[index];
 325         /* if valid, use the software product key */
 326         } else if (sw_rev < ARRAY_SIZE(sw_rev_map)) {
 327                 p_rev = (struct prod_rev_map_t *)&sw_rev_map[sw_rev];
 328         } else {
 329                 return -EINVAL;
 330         }
 331
 332         chip_info->product_id = prod_ver;
 333         chip_info->product_revision = prod_rev;
 334         chip_info->silicon_revision = p_rev->silicon_rev;
 335         chip_info->software_revision = sw_rev;
 336         chip_info->gyro_sens_trim = p_rev->gyro_trim;
 337         chip_info->accel_sens_trim = p_rev->accel_trim;
 338         if (chip_info->accel_sens_trim == 0)
 339                 chip_info->accel_sens_trim = DEFAULT_ACCEL_TRIM;
 340         chip_info->multi = DEFAULT_ACCEL_TRIM / chip_info->accel_sens_trim;
 341         if (chip_info->multi != 1)
 342                 pr_info("multi is %d\n", chip_info->multi);
 343         return ret;
 344 }
 345
 346 static int nvi_init_6500(struct nvi_state *st)
 347 {
 348         st->snsr[DEV_ACC].matrix = true;
 349         st->snsr[DEV_GYR].matrix = true;
 350         if (st->snsr[DEV_ACC].cfg.thresh_hi > 0)
 351                 st->en_msk |= (1 << EN_LP);
 352         else
 353                 st->en_msk &= ~(1 << EN_LP);
 354         return 0;
 355 }
 356
 357 static int inv_reset_offset_reg(struct nvi_state *st, bool en)
 358 {
 359         int i, ret;
 360         s16 gyro[AXIS_N], accel[AXIS_N];
 361
 362         if (en) {
 363                 for (i = 0; i < AXIS_N; i++) {
 364                         gyro[i] = st->rom_offset[DEV_GYR][i];
 365                         accel[i] = st->rom_offset[DEV_ACC][i];
 366                 }
 367         } else {
 368                 for (i = 0; i < AXIS_N; i++) {
 369                         gyro[i] = st->rom_offset[DEV_GYR][i] +
 370                                                    st->dev_offset[DEV_GYR][i];
 371                         accel[i] = st->rom_offset[DEV_ACC][i] +
 372                                             (st->dev_offset[DEV_ACC][i] << 1);
 373                 }
 374         }
 375         for (i = 0; i < AXIS_N; i++) {
 376                 ret = nvi_wr_gyro_offset(st, i, (u16)gyro[i]);
 377                 if (ret)
 378                         return ret;
 379
 380                 ret = nvi_wr_accel_offset(st, i, (u16)accel[i]);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  *  inv_mpu_recover_setting() recover the old settings after everything is done
 390  */
 391 static void inv_mpu_recover_setting(struct nvi_state *st)
 392 {
 393         inv_reset_offset_reg(st, false);
 394 }
 395
 396 /**
 397  *  read_accel_hw_self_test_prod_shift()- read the accelerometer hardware
 398  *                                         self-test bias shift calculated
 399  *                                         during final production test and
 400  *                                         stored in chip non-volatile memory.
 401  *  @st:  main data structure.
 402  *  @st_prod:   A pointer to an array of 3 elements to hold the values
 403  *              for production hardware self-test bias shifts returned to the
 404  *              user.
 405  *  @accel_sens: accel sensitivity.
 406  */
 407 static int read_accel_hw_self_test_prod_shift(struct nvi_state *st,
 408                                               int *st_prod, int *accel_sens)
 409 {
 410         u8 regs[4];
 411         u8 shift_code[3];
 412         int ret, i;
 413
 414         for (i = 0; i < 3; i++)
 415                 st_prod[i] = 0;
 416         ret = nvi_i2c_r(st, 0, REG_ST_GCT_X, ARRAY_SIZE(regs), regs);
 417         if (ret)
 418                 return ret;
 419
 420         if ((!regs[0]) && (!regs[1]) && (!regs[2]) && (!regs[3]))
 421                 return -EINVAL;
 422
 423         shift_code[X] = ((regs[0] & 0xE0) >> 3) | ((regs[3] & 0x30) >> 4);
 424         shift_code[Y] = ((regs[1] & 0xE0) >> 3) | ((regs[3] & 0x0C) >> 2);
 425         shift_code[Z] = ((regs[2] & 0xE0) >> 3) |  (regs[3] & 0x03);
 426         for (i = 0; i < 3; i++)
 427                 if (shift_code[i])
 428                         st_prod[i] = accel_sens[i] *
 429                                      accel_st_tb[shift_code[i] - 1];
 430
 431         return 0;
 432 }
 433
 434 /**
 435 * inv_check_accel_self_test()- check accel self test. this function returns
 436 *                              zero as success. A non-zero return value
 437 *                              indicates failure in self test.
 438 *  @*st: main data structure.
 439 *  @*reg_avg: average value of normal test.
 440 *  @*st_avg:  average value of self test
 441 */
 442 static int inv_check_accel_self_test(struct nvi_state *st,
 443                                      int *reg_avg, int *st_avg)
 444 {
 445         int gravity, j, ret_val;
 446         int tmp;
 447         int st_shift_prod[AXIS_N], st_shift_cust[AXIS_N];
 448         int st_shift_ratio[AXIS_N];
 449         int accel_sens[AXIS_N];
 450
 451         if (st->chip_info.software_revision < DEF_OLDEST_SUPP_SW_REV &&
 452             st->chip_info.product_revision < DEF_OLDEST_SUPP_PROD_REV)
 453                 return 0;
 454
 455         ret_val = 0;
 456         tmp = DEF_ST_SCALE * DEF_ST_PRECISION / DEF_ST_ACCEL_FS_MG;
 457         for (j = 0; j < 3; j++)
 458                 accel_sens[j] = tmp;
 459
 460         if (MPL_PROD_KEY(st->chip_info.product_id,
 461                          st->chip_info.product_revision) ==
 462                                                      MPU_PRODUCT_KEY_B1_E1_5) {
 463                 /* half sensitivity Z accelerometer parts */
 464                 accel_sens[Z] /= 2;
 465         } else {
 466                 /* half sensitivity X, Y, Z accelerometer parts */
 467                 accel_sens[X] /= st->chip_info.multi;
 468                 accel_sens[Y] /= st->chip_info.multi;
 469                 accel_sens[Z] /= st->chip_info.multi;
 470         }
 471         gravity = accel_sens[Z];
 472         ret_val = read_accel_hw_self_test_prod_shift(st, st_shift_prod,
 473                                                         accel_sens);
 474         if (ret_val)
 475                 return ret_val;
 476
 477         for (j = 0; j < 3; j++) {
 478                 st_shift_cust[j] = abs(reg_avg[j] - st_avg[j]);
 479                 if (st_shift_prod[j]) {
 480                         tmp = st_shift_prod[j] / DEF_ST_PRECISION;
 481                         st_shift_ratio[j] = abs(st_shift_cust[j] / tmp
 482                                 - DEF_ST_PRECISION);
 483                         if (st_shift_ratio[j] > DEF_ACCEL_ST_SHIFT_DELTA)
 484                                 ret_val = 1;
 485                 } else {
 486                         if (st_shift_cust[j] <
 487                                 DEF_ACCEL_ST_SHIFT_MIN * gravity)
 488                                 ret_val = 1;
 489                         if (st_shift_cust[j] >
 490                                 DEF_ACCEL_ST_SHIFT_MAX * gravity)
 491                                 ret_val = 1;
 492                 }
 493         }
 494
 495         return ret_val;
 496 }
 497
 498 /**
 499 * inv_check_6050_gyro_self_test() - check 6050 gyro self test. this function
 500 *                                   returns zero as success. A non-zero return
 501 *                                   value indicates failure in self test.
 502 *  @*st: main data structure.
 503 *  @*reg_avg: average value of normal test.
 504 *  @*st_avg:  average value of self test
 505 */
 506 static int inv_check_6050_gyro_self_test(struct nvi_state *st,
 507                                          int *reg_avg, int *st_avg)
 508 {
 509         int ret;
 510         int ret_val;
 511         int st_shift_prod[3], st_shift_cust[3], st_shift_ratio[3], i;
 512         u8 regs[3];
 513
 514         if (st->chip_info.software_revision < DEF_OLDEST_SUPP_SW_REV &&
 515             st->chip_info.product_revision < DEF_OLDEST_SUPP_PROD_REV)
 516                 return 0;
 517
 518         ret_val = 0;
 519         ret = nvi_i2c_r(st, 0, REG_ST_GCT_X, 3, regs);
 520         if (ret)
 521                 return ret;
 522         regs[X] &= 0x1f;
 523         regs[Y] &= 0x1f;
 524         regs[Z] &= 0x1f;
 525         for (i = 0; i < 3; i++) {
 526                 if (regs[i] != 0)
 527                         st_shift_prod[i] = gyro_6050_st_tb[regs[i] - 1];
 528                 else
 529                         st_shift_prod[i] = 0;
 530         }
 531         st_shift_prod[1] = -st_shift_prod[1];
 532
 533         for (i = 0; i < 3; i++) {
 534                 st_shift_cust[i] =  st_avg[i] - reg_avg[i];
 535                 if (st_shift_prod[i]) {
 536                         st_shift_ratio[i] = abs(st_shift_cust[i] /
 537                                 st_shift_prod[i] - DEF_ST_PRECISION);
 538                         if (st_shift_ratio[i] > DEF_GYRO_CT_SHIFT_DELTA)
 539                                 ret_val = 1;
 540                 } else {
 541                         if (st_shift_cust[i] < DEF_ST_PRECISION *
 542                                 DEF_GYRO_CT_SHIFT_MIN * DEF_SELFTEST_GYRO_SENS)
 543                                 ret_val = 1;
 544                         if (st_shift_cust[i] > DEF_ST_PRECISION *
 545                                 DEF_GYRO_CT_SHIFT_MAX * DEF_SELFTEST_GYRO_SENS)
 546                                 ret_val = 1;
 547                 }
 548         }
 549         /* check for absolute value passing criterion. Using DEF_ST_TOR
 550          * for certain degree of tolerance */
 551         for (i = 0; i < 3; i++)
 552                 if (abs(reg_avg[i]) > DEF_ST_TOR * DEF_ST_ABS_THRESH *
 553                     DEF_ST_PRECISION * DEF_GYRO_SCALE)
 554                         ret_val = 1;
 555
 556         return ret_val;
 557 }
 558
 559 /**
 560 * inv_check_6500_gyro_self_test() - check 6500 gyro self test. this function
 561 *                                   returns zero as success. A non-zero return
 562 *                                   value indicates failure in self test.
 563 *  @*st: main data structure.
 564 *  @*reg_avg: average value of normal test.
 565 *  @*st_avg:  average value of self test
 566 */
 567 static int inv_check_6500_gyro_self_test(struct nvi_state *st,
 568                                          int *reg_avg, int *st_avg)
 569 {
 570         u8 regs[AXIS_N];
 571         int ret_val, ret, axis;
 572         int otp_value_zero = 0;
 573         int st_shift_prod[3], st_shift_cust[3], i;
 574
 575         ret_val = 0;
 576         ret = 0;
 577         for (axis = 0; axis < AXIS_N; axis++)
 578                 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_g[axis],
 579                                      &regs[axis]);
 580         if (ret)
 581                 return ret;
 582         pr_debug("%s self_test gyro shift_code - %02x %02x %02x\n",
 583                  st->snsr[DEV_GYR].cfg.part, regs[0], regs[1], regs[2]);
 584
 585         for (i = 0; i < 3; i++) {
 586                 if (regs[i] != 0) {
 587                         st_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1];
 588                 } else {
 589                         st_shift_prod[i] = 0;
 590                         otp_value_zero = 1;
 591                 }
 592         }
 593         pr_debug("%s self_test gyro st_shift_prod - %+d %+d %+d\n",
 594                  st->snsr[DEV_GYR].cfg.part, st_shift_prod[0],
 595                  st_shift_prod[1], st_shift_prod[2]);
 596
 597         for (i = 0; i < 3; i++) {
 598                 st_shift_cust[i] = st_avg[i] - reg_avg[i];
 599                 if (!otp_value_zero) {
 600                         /* Self Test Pass/Fail Criteria A */
 601                         if (st_shift_cust[i] < DEF_6500_GYRO_CT_SHIFT_DELTA
 602                                                 * st_shift_prod[i])
 603                                         ret_val = 1;
 604                 } else {
 605                         /* Self Test Pass/Fail Criteria B */
 606                         if (st_shift_cust[i] < DEF_GYRO_ST_AL *
 607                                                 DEF_SELFTEST_GYRO_SENS *
 608                                                 DEF_ST_PRECISION)
 609                                 ret_val = 1;
 610                 }
 611         }
 612         pr_debug("%s self_test gyro st_shift_cust - %+d %+d %+d\n",
 613                  st->snsr[DEV_GYR].cfg.part, st_shift_cust[0],
 614                  st_shift_cust[1], st_shift_cust[2]);
 615
 616         if (ret_val == 0) {
 617                 /* Self Test Pass/Fail Criteria C */
 618                 for (i = 0; i < 3; i++)
 619                         if (abs(reg_avg[i]) > DEF_GYRO_OFFSET_MAX *
 620                                                 DEF_SELFTEST_GYRO_SENS *
 621                                                 DEF_ST_PRECISION)
 622                                 ret_val = 1;
 623         }
 624
 625         return ret_val;
 626 }
 627
 628 /**
 629 * inv_check_6500_accel_self_test() - check 6500 accel self test. this function
 630 *                                   returns zero as success. A non-zero return
 631 *                                   value indicates failure in self test.
 632 *  @*st: main data structure.
 633 *  @*reg_avg: average value of normal test.
 634 *  @*st_avg:  average value of self test
 635 */
 636 static int inv_check_6500_accel_self_test(struct nvi_state *st,
 637                                                 int *reg_avg, int *st_avg) {
 638         int ret_val, ret, axis;
 639         int st_shift_prod[3], st_shift_cust[3], st_shift_ratio[3], i;
 640         u8 regs[AXIS_N];
 641         int otp_value_zero = 0;
 642
 643 #define ACCEL_ST_AL_MIN ((DEF_ACCEL_ST_AL_MIN * DEF_ST_SCALE \
 644                                  / DEF_ST_6500_ACCEL_FS_MG) * DEF_ST_PRECISION)
 645 #define ACCEL_ST_AL_MAX ((DEF_ACCEL_ST_AL_MAX * DEF_ST_SCALE \
 646                                  / DEF_ST_6500_ACCEL_FS_MG) * DEF_ST_PRECISION)
 647
 648         ret_val = 0;
 649         ret = 0;
 650         for (axis = 0; axis < AXIS_N; axis++)
 651                 ret |= nvi_i2c_rd(st, &st->hal->reg->self_test_a[axis],
 652                                      &regs[axis]);
 653         if (ret)
 654                 return ret;
 655         pr_debug("%s self_test accel shift_code - %02x %02x %02x\n",
 656                  st->snsr[DEV_ACC].cfg.part, regs[0], regs[1], regs[2]);
 657
 658         for (i = 0; i < 3; i++) {
 659                 if (regs[i] != 0) {
 660                         st_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1];
 661                 } else {
 662                         st_shift_prod[i] = 0;
 663                         otp_value_zero = 1;
 664                 }
 665         }
 666         pr_debug("%s self_test accel st_shift_prod - %+d %+d %+d\n",
 667                  st->snsr[DEV_ACC].cfg.part, st_shift_prod[0],
 668                  st_shift_prod[1], st_shift_prod[2]);
 669
 670         if (!otp_value_zero) {
 671                 /* Self Test Pass/Fail Criteria A */
 672                 for (i = 0; i < 3; i++) {
 673                         st_shift_cust[i] = st_avg[i] - reg_avg[i];
 674                         st_shift_ratio[i] = abs(st_shift_cust[i] /
 675                                         st_shift_prod[i] - DEF_ST_PRECISION);
 676                         if (st_shift_ratio[i] > DEF_6500_ACCEL_ST_SHIFT_DELTA)
 677                                 ret_val = 1;
 678                 }
 679         } else {
 680                 /* Self Test Pass/Fail Criteria B */
 681                 for (i = 0; i < 3; i++) {
 682                         st_shift_cust[i] = abs(st_avg[i] - reg_avg[i]);
 683                         if (st_shift_cust[i] < ACCEL_ST_AL_MIN ||
 684                                         st_shift_cust[i] > ACCEL_ST_AL_MAX)
 685                                 ret_val = 1;
 686                 }
 687         }
 688         pr_debug("%s self_test accel st_shift_cust - %+d %+d %+d\n",
 689                  st->snsr[DEV_ACC].cfg.part, st_shift_cust[0],
 690                  st_shift_cust[1], st_shift_cust[2]);
 691
 692         return ret_val;
 693 }
 694
 695 /*
 696  *  inv_mpu_do_test() - do the actual test of self testing
 697  */
 698 static int inv_mpu_do_test(struct nvi_state *st, int self_test_flag,
 699                            int *gyro_result, int *accel_result)
 700 {
 701         int ret, i, j, packet_size;
 702         u8 data[BYTES_PER_SENSOR * 2], d, lpf;
 703         u16 fifo_en;
 704         short vals[3];
 705         int fifo_count, packet_count, ind, s;
 706
 707         packet_size = BYTES_PER_SENSOR * 2;
 708         ret = nvi_int_able(st, __func__, false);
 709         if (ret)
 710                 return ret;
 711         /* disable the sensor output to FIFO */
 712         /* disable fifo reading */
 713         ret = nvi_user_ctrl_en(st, __func__, false, false, false, false);
 714         if (ret)
 715                 return ret;
 716         /* clear FIFO */
 717         ret = nvi_i2c_wr_rc(st, &st->hal->reg->user_ctrl, BIT_FIFO_RST,
 718                             __func__, &st->rc.user_ctrl);
 719         if (ret)
 720                 return ret;
 721         /* setup parameters */
 722         ret = nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1, INV_FILTER_98HZ,
 723                             __func__, &st->rc.gyro_config1);
 724         if (ret < 0)
 725                 return ret;
 726
 727         ret = nvi_i2c_wr_rc(st, &st->hal->reg->smplrt[0],
 728                             DEF_SELFTEST_SAMPLE_RATE,
 729                             __func__, (u8 *)&st->rc.smplrt[0]);
 730         if (ret)
 731                 return ret;
 732         /* wait for the sampling rate change to stabilize */
 733         mdelay(INV_MPU_SAMPLE_RATE_CHANGE_STABLE);
 734         if (st->hal == &nvi_hal_6050) {
 735                 d = DEF_SELFTEST_ACCEL_FS;
 736                 lpf = 0;
 737         } else {
 738                 d = DEF_SELFTEST_6500_ACCEL_FS;
 739                 lpf = DEF_ST_MPU6500_ACCEL_LPF;
 740         }
 741         ret = nvi_i2c_wr_rc(st, &st->hal->reg->accel_config, d | self_test_flag,
 742                             __func__, &st->rc.accel_config);
 743         if (ret < 0)
 744                 return ret;
 745
 746         ret = nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2,
 747                                self_test_flag | DEF_SELFTEST_GYRO_FS,
 748                                __func__, &st->rc.gyro_config1);
 749         if (ret < 0)
 750                 return ret;
 751
 752         /* wait for the output to get stable */
 753         if (self_test_flag)
 754                 msleep(DEF_ST_STABLE_TIME);
 755
 756         /* enable FIFO reading */
 757         ret = nvi_i2c_wr_rc(st, &st->hal->reg->user_ctrl, BIT_FIFO_EN,
 758                             __func__, &st->rc.user_ctrl);
 759         if (ret)
 760                 return ret;
 761         /* enable sensor output to FIFO */
 762         fifo_en = (st->hal->dev[DEV_ACC]->fifo_en_msk |
 763                    st->hal->dev[DEV_GYR]->fifo_en_msk);
 764         for (i = 0; i < AXIS_N; i++) {
 765                 gyro_result[i] = 0;
 766                 accel_result[i] = 0;
 767         }
 768         s = 0;
 769         while (s < ST_MAX_SAMPLES) {
 770                 /* enable sensor output to FIFO */
 771                 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, fifo_en,
 772                                        __func__, (u8 *)&st->rc.fifo_en, false);
 773                 if (ret)
 774                         return ret;
 775                 mdelay(DEF_GYRO_WAIT_TIME);
 776                 ret = nvi_i2c_write_rc(st, &st->hal->reg->fifo_en, 0,
 777                                        __func__, (u8 *)&st->rc.fifo_en, false);
 778                 if (ret)
 779                         return ret;
 780
 781                 ret = nvi_i2c_rd(st, &st->hal->reg->fifo_count_h, data);
 782                 if (ret)
 783                         return ret;
 784                 fifo_count = be16_to_cpup((__be16 *)(&data[0]));
 785                 pr_debug("%s self_test fifo_count - %d\n",
 786                          st->snsr[0].cfg.part, fifo_count);
 787                 packet_count = fifo_count / packet_size;
 788                 i = 0;
 789                 while ((i < packet_count) && (s < ST_MAX_SAMPLES)) {
 790                         ret = nvi_i2c_r(st, st->hal->reg->fifo_rw.bank,
 791                                         st->hal->reg->fifo_rw.reg,
 792                                         packet_size, data);
 793                         if (ret)
 794                                 return ret;
 795                         ind = 0;
 796                         for (j = 0; j < AXIS_N; j++) {
 797                                 vals[j] = (short)be16_to_cpup(
 798                                     (__be16 *)(&data[ind + 2 * j]));
 799                                 accel_result[j] += vals[j];
 800                         }
 801                         ind += BYTES_PER_SENSOR;
 802                         pr_debug(
 803                             "%s self_test accel data - %d %+d %+d %+d",
 804                                  st->snsr[DEV_ACC].cfg.part,
 805                                  s, vals[0], vals[1], vals[2]);
 806
 807                         for (j = 0; j < AXIS_N; j++) {
 808                                 vals[j] = (short)be16_to_cpup(
 809                                         (__be16 *)(&data[ind + 2 * j]));
 810                                 gyro_result[j] += vals[j];
 811                         }
 812                         pr_debug("%s self_test gyro data - %d %+d %+d %+d",
 813                                  st->snsr[DEV_GYR].cfg.part,
 814                                  s, vals[0], vals[1], vals[2]);
 815
 816                         s++;
 817                         i++;
 818                 }
 819         }
 820
 821         for (j = 0; j < AXIS_N; j++) {
 822                 accel_result[j] = accel_result[j] / s;
 823                 accel_result[j] *= DEF_ST_PRECISION;
 824         }
 825         for (j = 0; j < AXIS_N; j++) {
 826                 gyro_result[j] = gyro_result[j] / s;
 827                 gyro_result[j] *= DEF_ST_PRECISION;
 828         }
 829
 830         return 0;
 831 }
 832
 833 /*
 834  *  inv_mpu_self_test() - main function to do hardware self test
 835  */
 836 static int inv_mpu_self_test(struct nvi_state *st,
 837                              int *gyro_bias_st, int *gyro_bias,
 838                              int *accel_bias_st, int *accel_bias)
 839 {
 840         int ret;
 841         int test_times;
 842         int i;
 843         char accel_result;
 844         char gyro_result;
 845
 846         ret = nvi_pm_wr(st, __func__, INV_CLK_PLL, 0, 0);
 847         if (ret)
 848                 return ret;
 849         ret = inv_reset_offset_reg(st, true);
 850         if (ret)
 851                 return ret;
 852         accel_result = 0;
 853         gyro_result = 0;
 854         test_times = DEF_ST_TRY_TIMES;
 855         while (test_times > 0) {
 856                 ret = inv_mpu_do_test(st, 0, gyro_bias,
 857                                          accel_bias);
 858                 if (ret == -EAGAIN)
 859                         test_times--;
 860                 else
 861                         test_times = 0;
 862         }
 863         if (ret)
 864                 goto test_fail;
 865         pr_debug("%s self_test accel bias_regular - %+d %+d %+d\n",
 866                  st->snsr[DEV_ACC].cfg.part, accel_bias[0],
 867                  accel_bias[1], accel_bias[2]);
 868         pr_debug("%s self_test gyro bias_regular - %+d %+d %+d\n",
 869                  st->snsr[DEV_GYR].cfg.part, gyro_bias[0],
 870                  gyro_bias[1], gyro_bias[2]);
 871
 872         for (i = 0; i < AXIS_N; i++) {
 873                 st->bias[DEV_GYR][i] = gyro_bias[i];
 874                 st->bias[DEV_ACC][i] = accel_bias[i];
 875         }
 876
 877         test_times = DEF_ST_TRY_TIMES;
 878         while (test_times > 0) {
 879                 ret = inv_mpu_do_test(st, BITS_SELF_TEST_EN, gyro_bias_st,
 880                                          accel_bias_st);
 881                 if (ret == -EAGAIN)
 882                         test_times--;
 883                 else
 884                         break;
 885         }
 886         if (ret)
 887                 goto test_fail;
 888         pr_debug("%s self_test accel bias_st - %+d %+d %+d\n",
 889                  st->snsr[DEV_ACC].cfg.part, accel_bias_st[0],
 890                  accel_bias_st[1], accel_bias_st[2]);
 891         pr_debug("%s self_test gyro bias_st - %+d %+d %+d\n",
 892                  st->snsr[DEV_GYR].cfg.part, gyro_bias_st[0],
 893                  gyro_bias_st[1], gyro_bias_st[2]);
 894
 895 test_fail:
 896         inv_mpu_recover_setting(st);
 897         return (accel_result << DEF_ST_ACCEL_RESULT_SHIFT) | gyro_result;
 898 }
 899
 900 static int nvi_st_acc_6050(struct nvi_state *st)
 901 {
 902         int gyro_bias_st[AXIS_N];
 903         int gyro_bias[AXIS_N];
 904         int accel_bias_st[AXIS_N];
 905         int accel_bias[AXIS_N];
 906         int ret;
 907
 908         ret = inv_mpu_self_test(st, gyro_bias_st, gyro_bias,
 909                                 accel_bias_st, accel_bias);
 910         return !inv_check_accel_self_test(st, accel_bias, accel_bias_st);
 911 }
 912
 913 static int nvi_st_gyr_6050(struct nvi_state *st)
 914 {
 915         int gyro_bias_st[AXIS_N];
 916         int gyro_bias[AXIS_N];
 917         int accel_bias_st[AXIS_N];
 918         int accel_bias[AXIS_N];
 919         int ret;
 920
 921         ret = inv_mpu_self_test(st, gyro_bias_st, gyro_bias,
 922                                 accel_bias_st, accel_bias);
 923         return !inv_check_6050_gyro_self_test(st, gyro_bias, gyro_bias_st);
 924 }
 925
 926 static int nvi_st_acc_6500(struct nvi_state *st)
 927 {
 928         int gyro_bias_st[AXIS_N];
 929         int gyro_bias[AXIS_N];
 930         int accel_bias_st[AXIS_N];
 931         int accel_bias[AXIS_N];
 932         int ret;
 933
 934         ret = inv_mpu_self_test(st, gyro_bias_st, gyro_bias,
 935                                 accel_bias_st, accel_bias);
 936         return !inv_check_6500_accel_self_test(st, accel_bias, accel_bias_st);
 937 }
 938
 939 static int nvi_st_gyr_6500(struct nvi_state *st)
 940 {
 941         int gyro_bias_st[AXIS_N];
 942         int gyro_bias[AXIS_N];
 943         int accel_bias_st[AXIS_N];
 944         int accel_bias[AXIS_N];
 945         int ret;
 946
 947         ret = inv_mpu_self_test(st, gyro_bias_st, gyro_bias,
 948                                 accel_bias_st, accel_bias);
 949         return !inv_check_6500_gyro_self_test(st, gyro_bias, gyro_bias_st);
 950 }
 951
 952 static int nvi_wr_pwr_mgmt_1_war(struct nvi_state *st)
 953 {
 954         u8 val;
 955         int i;
 956         int ret;
 957
 958         for (i = 0; i < (POWER_UP_TIME / REG_UP_TIME); i++) {
 959                 ret = nvi_i2c_wr(st, &st->hal->reg->pm1, 0, NULL);
 960                 mdelay(REG_UP_TIME);
 961                 val = -1;
 962                 ret = nvi_i2c_rd(st, &st->hal->reg->pm1, &val);
 963                 if ((!ret) && (val == st->hal->reg->pm1.dflt))
 964                         break;
 965         }
 966         st->rc.pm1 = val;
 967         return ret;
 968 }
 969
 970 static int nvi_pm_6050(struct nvi_state *st, u8 pm1, u8 pm2, u8 lp)
 971 {
 972         bool rc_dis;
 973         int ret;
 974
 975         rc_dis = st->rc_dis;
 976         st->rc_dis = true;
 977         nvi_wr_pwr_mgmt_1_war(st);
 978         pm2 |= lp << 6;
 979         ret = nvi_i2c_wr_rc(st, &st->hal->reg->pm2, pm2,
 980                             __func__, &st->rc.pm2);
 981         if (!ret)
 982                 st->rc.lp_config = lp;
 983         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm1, pm1,
 984                              __func__, &st->rc.pm1);
 985         st->rc_dis = rc_dis;
 986         return ret;
 987 }
 988
 989 static int nvi_pm_6500(struct nvi_state *st, u8 pm1, u8 pm2, u8 lp)
 990 {
 991         int ret = 0;
 992
 993         /* must be on internal clock before gyro enable/disable in pm2 */
 994         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm1, 0,
 995                              __func__, &st->rc.pm1);
 996         if (pm1 & BIT_CYCLE) {
 997                 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->lp_config, lp,
 998                                      __func__, &st->rc.lp_config);
 999                 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
1000                                      BIT_FIFO_SIZE_1K | BIT_ACCEL_FCHOCIE_B,
1001                                      __func__, &st->rc.accel_config2);
1002         }
1003         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm2, pm2,
1004                              __func__, &st->rc.pm2);
1005         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->pm1, pm1,
1006                              __func__, &st->rc.pm1);
1007         if (!(pm1 & BIT_CYCLE))
1008                 ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2,
1009                                      BIT_FIFO_SIZE_1K,
1010                                      __func__, &st->rc.accel_config2);
1011         return ret;
1012 }
1013
1014 static int nvi_en_acc_mpu(struct nvi_state *st)
1015 {
1016         u8 val;
1017         int ret = 0;
1018
1019         st->snsr[DEV_ACC].buf_n = 6;
1020         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config2, 0,
1021                              __func__, &st->rc.accel_config2);
1022         val = (st->snsr[DEV_ACC].usr_cfg << 1) | 0x01;
1023         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->accel_config, val,
1024                              __func__, &st->rc.accel_config);
1025         return ret;
1026 }
1027
1028 static int nvi_en_gyr_mpu(struct nvi_state *st)
1029 {
1030         u8 val = st->snsr[DEV_GYR].usr_cfg << 3;
1031
1032         st->snsr[DEV_GYR].buf_n = 6;
1033         return nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config2, val,
1034                              __func__, &st->rc.gyro_config2);
1035 }
1036
1037 struct nvi_fn nvi_fn_6050 = {
1038         .pm                             = nvi_pm_6050,
1039         .init                           = inv_init_6050, /* INV crappy code */
1040         .st_acc                         = nvi_st_acc_6050,
1041         .st_gyr                         = nvi_st_gyr_6050,
1042         .en_acc                         = nvi_en_acc_mpu,
1043         .en_gyr                         = nvi_en_gyr_mpu,
1044 };
1045
1046 struct nvi_fn nvi_fn_6500 = {
1047         .pm                             = nvi_pm_6500,
1048         .init                           = nvi_init_6500,
1049         .st_acc                         = nvi_st_acc_6500,
1050         .st_gyr                         = nvi_st_gyr_6500,
1051         .en_acc                         = nvi_en_acc_mpu,
1052         .en_gyr                         = nvi_en_gyr_mpu,
1053 };
1054
1055
1056 static const unsigned int nvi_lpf_us_tbl[] = {
1057         0, /* WAR: disabled 3906, 256Hz */
1058         5319,   /* 188Hz */
1059         10204,  /* 98Hz */
1060         23810,  /* 42Hz */
1061         50000,  /* 20Hz */
1062         100000, /* 10Hz */
1063         /* 200000, 5Hz */
1064 };
1065
1066 static int nvi_src(struct nvi_state *st)
1067 {
1068         u8 lpf;
1069         u16 rate;
1070         unsigned int us;
1071         int ret;
1072
1073         us = st->src[SRC_MPU].period_us_req;
1074         /* calculate rate */
1075         rate = us / 1000 - 1;
1076         st->src[SRC_MPU].period_us_src = us;
1077         ret = nvi_i2c_wr_rc(st, &st->hal->reg->smplrt[SRC_MPU], rate,
1078                             __func__, (u8 *)&st->rc.smplrt[SRC_MPU]);
1079         /* calculate LPF */
1080         lpf = 0;
1081         us <<= 1;
1082         for (lpf = 0; lpf < ARRAY_SIZE(nvi_lpf_us_tbl); lpf++) {
1083                 if (us < nvi_lpf_us_tbl[lpf])
1084                         break;
1085         }
1086         ret |= nvi_i2c_wr_rc(st, &st->hal->reg->gyro_config1, lpf,
1087                              __func__, &st->rc.gyro_config1);
1088         ret |= nvi_aux_delay(st, __func__);
1089         if (st->sts & (NVS_STS_SPEW_MSG | NVI_DBG_SPEW_MSG))
1090                 dev_info(&st->i2c->dev, "%s src[SRC_MPU]: period=%u err=%d\n",
1091                          __func__, st->src[SRC_MPU].period_us_req, ret);
1092         return ret;
1093 }
1094
1095 static const unsigned long nvi_lp_dly_us_tbl_6050[] = {
1096         800000, /* 800ms */
1097         200000, /* 200ms */
1098         50000,  /* 50ms */
1099         /* 25000, 25ms */
1100 };
1101
1102 static const struct nvi_hal_src src[] = {
1103         {
1104                 .dev_msk                = ((1 << DEV_ACC) | (1 << DEV_GYR) |
1105                                            (1 << DEV_AUX)),
1106                 .period_us_min          = 10000,
1107                 .period_us_max          = 256000,
1108                 .fn_period              = nvi_src,
1109         },
1110 };
1111
1112 static struct nvi_rr nvi_rr_acc[] = {
1113         /* all accelerometer values are in g's  fval = NVS_FLOAT_NANO */
1114         {
1115                 .max_range              = {
1116                         .ival           = 19,
1117                         .fval           = 613300000,
1118                 },
1119                 .resolution             = {
1120                         .ival           = 0,
1121                         .fval           = 598550,
1122                 },
1123         },
1124         {
1125                 .max_range              = {
1126                         .ival           = 39,
1127                         .fval           = 226600000,
1128                 },
1129                 .resolution             = {
1130                         .ival           = 0,
1131                         .fval           = 1197101,
1132                 },
1133         },
1134         {
1135                 .max_range              = {
1136                         .ival           = 78,
1137                         .fval           = 453200000,
1138                 },
1139                 .resolution             = {
1140                         .ival           = 0,
1141                         .fval           = 2394202,
1142                 },
1143         },
1144         {
1145                 .max_range              = {
1146                         .ival           = 156,
1147                         .fval           = 906400000,
1148                 },
1149                 .resolution             = {
1150                         .ival           = 0,
1151                         .fval           = 4788403,
1152                 },
1153         },
1154 };
1155
1156 static struct nvi_rr nvi_rr_gyr[] = {
1157         /* rad / sec  fval = NVS_FLOAT_NANO */
1158         {
1159                 .max_range              = {
1160                         .ival           = 4,
1161                         .fval           = 363323130,
1162                 },
1163                 .resolution             = {
1164                         .ival           = 0,
1165                         .fval           = 133231,
1166                 },
1167         },
1168         {
1169                 .max_range              = {
1170                         .ival           = 8,
1171                         .fval           = 726646260,
1172                 },
1173                 .resolution             = {
1174                         .ival           = 0,
1175                         .fval           = 266462,
1176                 },
1177         },
1178         {
1179                 .max_range              = {
1180                         .ival           = 17,
1181                         .fval           = 453292520,
1182                 },
1183                 .resolution             = {
1184                         .ival           = 0,
1185                         .fval           = 532113,
1186                 },
1187         },
1188         {
1189                 .max_range              = {
1190                         .ival           = 34,
1191                         .fval           = 906585040,
1192                 },
1193                 .resolution             = {
1194                         .ival           = 0,
1195                         .fval           = 1064225,
1196                 },
1197         },
1198 };
1199
1200 static struct nvi_rr nvi_rr_tmp[] = {
1201         {
1202                 .max_range              = {
1203                         .ival           = 125,
1204                         .fval           = 0,
1205                 },
1206                 .resolution             = {
1207                         .ival           = 1,
1208                         .fval           = 0,
1209                 },
1210         },
1211 };
1212
1213 static struct nvi_rr nvi_rr_dmp[] = {
1214         {
1215                 .max_range              = {
1216                         .ival           = 1,
1217                         .fval           = 0,
1218                 },
1219                 .resolution             = {
1220                         .ival           = 1,
1221                         .fval           = 0,
1222                 },
1223         },
1224 };
1225
1226 static const struct nvi_hal_dev nvi_hal_acc_6050 = {
1227         .version                        = 3,
1228         .src                            = SRC_MPU,
1229         .rr_0n                          = ARRAY_SIZE(nvi_rr_acc) - 1,
1230         .rr                             = nvi_rr_acc,
1231         .milliamp                       = {
1232                 .ival                   = 0,
1233                 .fval                   = 500000000, /* NVS_FLOAT_NANO */
1234         },
1235         .fifo_en_msk                    = 0x08,
1236         .fifo_data_n                    = 6,
1237 };
1238
1239 static const struct nvi_hal_dev nvi_hal_gyr = {
1240         .version                        = 3,
1241         .src                            = SRC_MPU,
1242         .rr_0n                          = ARRAY_SIZE(nvi_rr_gyr) - 1,
1243         .rr                             = nvi_rr_gyr,
1244         .milliamp                       = {
1245                 .ival                   = 3,
1246                 .fval                   = 700000000, /* NVS_FLOAT_NANO */
1247         },
1248         .fifo_en_msk                    = 0x70,
1249         .fifo_data_n                    = 6,
1250 };
1251
1252 static const struct nvi_hal_dev nvi_hal_tmp_6050 = {
1253         .version                        = 2,
1254         .src                            = -1,
1255         .rr_0n                          = ARRAY_SIZE(nvi_rr_tmp) - 1,
1256         .rr                             = nvi_rr_tmp,
1257         .scale                          = {
1258                 .ival                   = 0,
1259                 .fval                   = 315806400, /* NVS_FLOAT_NANO */
1260         },
1261         .offset                         = {
1262                 .ival                   = 0,
1263                 .fval                   = 239418400, /* NVS_FLOAT_NANO */
1264         },
1265         .milliamp                       = {
1266                 .ival                   = 3,
1267                 .fval                   = 700000000, /* NVS_FLOAT_NANO */
1268         },
1269 };
1270
1271 static const struct nvi_hal_dev nvi_hal_aux = {
1272         .version                        = 0,
1273         .src                            = SRC_MPU,
1274 };
1275
1276 static const struct nvi_hal_dev nvi_hal_dmp = {
1277         .version                        = 1,
1278         .src                            = -1,
1279         .rr_0n                          = ARRAY_SIZE(nvi_rr_dmp) - 1,
1280         .rr                             = nvi_rr_dmp,
1281         .milliamp                       = {
1282                 .ival                   = 0,
1283                 .fval                   = 500000, /* NVS_FLOAT_MICRO */
1284         },
1285 };
1286
1287 static const struct nvi_hal_reg nvi_hal_reg_6050 = {
1288         .self_test_g[AXIS_X]            = {
1289                 .reg                    = 0x00,
1290         },
1291         .self_test_g[AXIS_Y]            = {
1292                 .reg                    = 0x01,
1293         },
1294         .self_test_g[AXIS_Z]            = {
1295                 .reg                    = 0x02,
1296         },
1297         .self_test_a[AXIS_X]    = {
1298                 .reg                    = 0x0D,
1299         },
1300         .self_test_a[AXIS_Y]    = {
1301                 .reg                    = 0x0E,
1302         },
1303         .self_test_a[AXIS_Z]    = {
1304                 .reg                    = 0x0F,
1305         },
1306         .a_offset_h[AXIS_X]             = {
1307                 .reg                    = 0x06,
1308                 .len                    = 2,
1309         },
1310         .a_offset_h[AXIS_Y]             = {
1311                 .reg                    = 0x08,
1312                 .len                    = 2,
1313         },
1314         .a_offset_h[AXIS_Z]             = {
1315                 .reg                    = 0x0A,
1316                 .len                    = 2,
1317         },
1318         .g_offset_h[AXIS_X]             = {
1319                 .reg                    = 0x13,
1320                 .len                    = 2,
1321         },
1322         .g_offset_h[AXIS_Y]             = {
1323                 .reg                    = 0x15,
1324                 .len                    = 2,
1325         },
1326         .g_offset_h[AXIS_Z]             = {
1327                 .reg                    = 0x17,
1328                 .len                    = 2,
1329         },
1330         .smplrt[0]                      = {
1331                 .reg                    = 0x19,
1332         },
1333         .gyro_config1                   = {
1334                 .reg                    = 0x1A,
1335         },
1336         .gyro_config2                   = {
1337                 .reg                    = 0x1B,
1338         },
1339         .accel_config                   = {
1340                 .reg                    = 0x1C,
1341         },
1342         .accel_config2                  = {
1343                 .reg                    = 0x1D,
1344         },
1345         .lp_config                      = {
1346                 .reg                    = 0x1E,
1347         },
1348         .int_pin_cfg                    = {
1349                 .reg                    = 0x37,
1350         },
1351         .int_enable                     = {
1352                 .reg                    = 0x38,
1353         },
1354         .int_dmp                        = {
1355                 .reg                    = 0x39,
1356         },
1357         .int_status                     = {
1358                 .reg                    = 0x3A,
1359         },
1360         .out_h[DEV_ACC]         = {
1361                 .reg                    = 0x3B,
1362         },
1363         .out_h[DEV_GYR]         = {
1364                 .reg                    = 0x43,
1365         },
1366         .out_h[DEV_TMP]         = {
1367                 .reg                    = 0x41,
1368         },
1369         .ext_sens_data_00               = {
1370                 .reg                    = 0x49,
1371         },
1372         .signal_path_reset              = {
1373                 .reg                    = 0x68,
1374         },
1375         .user_ctrl                      = {
1376                 .reg                    = 0x6A,
1377         },
1378         .pm1                            = {
1379                 .reg                    = 0x6B,
1380         },
1381         .pm2                            = {
1382                 .reg                    = 0x6C,
1383         },
1384         .mem_bank                       = {
1385                 .reg                    = 0x6D,
1386         },
1387         .mem_addr                       = {
1388                 .reg                    = 0x6E,
1389         },
1390         .mem_rw                         = {
1391                 .reg                    = 0x6F,
1392         },
1393         .fw_start                       = {
1394                 .reg                    = 0x70,
1395                 .len                    = 2,
1396         },
1397         .fifo_en                        = {
1398                 .reg                    = 0x23,
1399         },
1400         .fifo_count_h                   = {
1401                 .reg                    = 0x72,
1402                 .len                    = 2,
1403         },
1404         .fifo_rw                        = {
1405                 .reg                    = 0x74,
1406         },
1407         .who_am_i                       = {
1408                 .reg                    = 0x75,
1409         },
1410         .i2c_mst_status                 = {
1411                 .reg                    = 0x36,
1412         },
1413         .i2c_mst_ctrl                   = {
1414                 .reg                    = 0x24,
1415         },
1416         .i2c_mst_delay_ctrl             = {
1417                 .reg                    = 0x67,
1418         },
1419         .i2c_slv_addr[0]                = {
1420                 .reg                    = 0x25,
1421         },
1422         .i2c_slv_addr[1]                = {
1423                 .reg                    = 0x28,
1424         },
1425         .i2c_slv_addr[2]                = {
1426                 .reg                    = 0x2B,
1427         },
1428         .i2c_slv_addr[3]                = {
1429                 .reg                    = 0x2E,
1430         },
1431         .i2c_slv_addr[4]                = {
1432                 .reg                    = 0x31,
1433         },
1434         .i2c_slv_reg[0]                 = {
1435                 .reg                    = 0x26,
1436         },
1437         .i2c_slv_reg[1]                 = {
1438                 .reg                    = 0x29,
1439         },
1440         .i2c_slv_reg[2]                 = {
1441                 .reg                    = 0x2C,
1442         },
1443         .i2c_slv_reg[3]                 = {
1444                 .reg                    = 0x2F,
1445         },
1446         .i2c_slv_reg[4]                 = {
1447                 .reg                    = 0x32,
1448         },
1449         .i2c_slv_ctrl[0]                = {
1450                 .reg                    = 0x27,
1451         },
1452         .i2c_slv_ctrl[1]                = {
1453                 .reg                    = 0x2A,
1454         },
1455         .i2c_slv_ctrl[2]                = {
1456                 .reg                    = 0x2D,
1457         },
1458         .i2c_slv_ctrl[3]                = {
1459                 .reg                    = 0x30,
1460         },
1461         .i2c_slv4_ctrl                  = {
1462                 .reg                    = 0x34,
1463         },
1464         .i2c_slv_do[0]                  = {
1465                 .reg                    = 0x63,
1466         },
1467         .i2c_slv_do[1]                  = {
1468                 .reg                    = 0x64,
1469         },
1470         .i2c_slv_do[2]                  = {
1471                 .reg                    = 0x65,
1472         },
1473         .i2c_slv_do[3]                  = {
1474                 .reg                    = 0x66,
1475         },
1476         .i2c_slv_do[4]                  = {
1477                 .reg                    = 0x33,
1478         },
1479         .i2c_slv4_di                    = {
1480                 .reg                    = 0x35,
1481         },
1482 };
1483
1484 static const struct nvi_hal_bit nvi_hal_bit_6050 = {
1485         .dmp_int_sm                     = 2,
1486         .dmp_int_stp                    = 3,
1487         .int_i2c_mst                    = 0,
1488         .int_dmp                        = 1,
1489         .int_pll_rdy                    = 7,
1490         .int_wom                        = 6,
1491         .int_wof                        = 3,
1492         .int_data_rdy_0                 = 0,
1493         .int_data_rdy_1                 = 0,
1494         .int_data_rdy_2                 = 0,
1495         .int_data_rdy_3                 = 0,
1496         .int_fifo_ovrflw_0              = 4,
1497         .int_fifo_ovrflw_1              = 4,
1498         .int_fifo_ovrflw_2              = 4,
1499         .int_fifo_ovrflw_3              = 4,
1500         .int_fifo_wm_0                  = 6,
1501         .int_fifo_wm_1                  = 6,
1502         .int_fifo_wm_2                  = 6,
1503         .int_fifo_wm_3                  = 6,
1504         .slv_fifo_en[0]                 = 0,
1505         .slv_fifo_en[1]                 = 1,
1506         .slv_fifo_en[2]                 = 2,
1507         .slv_fifo_en[3]                 = 13,
1508 };
1509
1510 const struct nvi_hal nvi_hal_6050 = {
1511         .regs_n                         = 118,
1512         .reg_bank_n                     = 1,
1513         .src                            = src,
1514         .src_n                          = ARRAY_SIZE(src),
1515         .lp_tbl                         = nvi_lp_dly_us_tbl_6050,
1516         .lp_tbl_n                       = ARRAY_SIZE(nvi_lp_dly_us_tbl_6050),
1517         .dev[DEV_ACC]                   = &nvi_hal_acc_6050,
1518         .dev[DEV_GYR]                   = &nvi_hal_gyr,
1519         .dev[DEV_TMP]                   = &nvi_hal_tmp_6050,
1520         .dev[DEV_SM]                    = &nvi_hal_dmp,
1521         .dev[DEV_STP]                   = &nvi_hal_dmp,
1522         .dev[DEV_QTN]                   = &nvi_hal_dmp,
1523         .dev[DEV_GMR]                   = &nvi_hal_dmp,
1524         .dev[DEV_GYU]                   = &nvi_hal_gyr,
1525         .dev[DEV_AUX]                   = &nvi_hal_aux,
1526         .reg                            = &nvi_hal_reg_6050,
1527         .bit                            = &nvi_hal_bit_6050,
1528         .fn                             = &nvi_fn_6050,
1529 };
1530 EXPORT_SYMBOL(nvi_hal_6050);
1531
1532 static const unsigned long nvi_lp_dly_us_tbl_6500[] = {
1533         4096000,/* 4096ms */
1534         2048000,/* 2048ms */
1535         1024000,/* 1024ms */
1536         512000, /* 512ms */
1537         256000, /* 256ms */
1538         128000, /* 128ms */
1539         64000,  /* 64ms */
1540         32000,  /* 32ms */
1541         16000,  /* 16ms */
1542         8000,   /* 8ms */
1543         4000,   /* 4ms */
1544         /* 2000, 2ms */
1545 };
1546
1547 static const struct nvi_hal_dev nvi_hal_acc_6500 = {
1548         .version                        = 3,
1549         .src                            = SRC_MPU,
1550         .rr_0n                          = ARRAY_SIZE(nvi_rr_acc) - 1,
1551         .rr                             = nvi_rr_acc,
1552         .milliamp                       = {
1553                 .ival                   = 0,
1554                 .fval                   = 500000000, /* NVS_FLOAT_NANO */
1555         },
1556         .fifo_en_msk                    = 0x08,
1557         .fifo_data_n                    = 6,
1558 };
1559
1560 static const struct nvi_hal_dev nvi_hal_tmp_6500 = {
1561         .version                        = 2,
1562         .src                            = -1,
1563         .rr_0n                          = ARRAY_SIZE(nvi_rr_tmp) - 1,
1564         .rr                             = nvi_rr_tmp,
1565         .scale                          = {
1566                 .ival                   = 0,
1567                 .fval                   = 334082700, /* NVS_FLOAT_NANO */
1568         },
1569         .offset                         = {
1570                 .ival                   = 0,
1571                 .fval                   = 137625600, /* NVS_FLOAT_NANO */
1572         },
1573         .milliamp                       = {
1574                 .ival                   = 3,
1575                 .fval                   = 700000000, /* NVS_FLOAT_NANO */
1576         },
1577 };
1578
1579 static const struct nvi_hal_reg nvi_hal_reg_6500 = {
1580         .self_test_g[AXIS_X]            = {
1581                 .reg                    = 0x00,
1582         },
1583         .self_test_g[AXIS_Y]            = {
1584                 .reg                    = 0x01,
1585         },
1586         .self_test_g[AXIS_Z]            = {
1587                 .reg                    = 0x02,
1588         },
1589         .self_test_a[AXIS_X]    = {
1590                 .reg                    = 0x0D,
1591         },
1592         .self_test_a[AXIS_Y]    = {
1593                 .reg                    = 0x0E,
1594         },
1595         .self_test_a[AXIS_Z]    = {
1596                 .reg                    = 0x0F,
1597         },
1598         .a_offset_h[AXIS_X]             = {
1599                 .reg                    = 0x77,
1600                 .len                    = 2,
1601         },
1602         .a_offset_h[AXIS_Y]             = {
1603                 .reg                    = 0x7A,
1604                 .len                    = 2,
1605         },
1606         .a_offset_h[AXIS_Z]             = {
1607                 .reg                    = 0x7D,
1608                 .len                    = 2,
1609         },
1610         .g_offset_h[AXIS_X]             = {
1611                 .reg                    = 0x13,
1612                 .len                    = 2,
1613         },
1614         .g_offset_h[AXIS_Y]             = {
1615                 .reg                    = 0x15,
1616                 .len                    = 2,
1617         },
1618         .g_offset_h[AXIS_Z]             = {
1619                 .reg                    = 0x17,
1620                 .len                    = 2,
1621         },
1622         .smplrt[SRC_MPU]                = {
1623                 .reg                    = 0x19,
1624         },
1625         .gyro_config1                   = {
1626                 .reg                    = 0x1A,
1627         },
1628         .gyro_config2                   = {
1629                 .reg                    = 0x1B,
1630         },
1631         .accel_config                   = {
1632                 .reg                    = 0x1C,
1633         },
1634         .accel_config2                  = {
1635                 .reg                    = 0x1D,
1636         },
1637         .lp_config                      = {
1638                 .reg                    = 0x1E,
1639         },
1640         .int_pin_cfg                    = {
1641                 .reg                    = 0x37,
1642         },
1643         .int_enable                     = {
1644                 .reg                    = 0x38,
1645         },
1646         .int_dmp                        = {
1647                 .reg                    = 0x39,
1648         },
1649         .int_status                     = {
1650                 .reg                    = 0x3A,
1651         },
1652         .out_h[DEV_ACC]         = {
1653                 .reg                    = 0x3B,
1654         },
1655         .out_h[DEV_GYR]         = {
1656                 .reg                    = 0x43,
1657         },
1658         .out_h[DEV_TMP]         = {
1659                 .reg                    = 0x41,
1660         },
1661         .ext_sens_data_00               = {
1662                 .reg                    = 0x49,
1663         },
1664         .signal_path_reset              = {
1665                 .reg                    = 0x68,
1666         },
1667         .user_ctrl                      = {
1668                 .reg                    = 0x6A,
1669         },
1670         .pm1                            = {
1671                 .reg                    = 0x6B,
1672         },
1673         .pm2                            = {
1674                 .reg                    = 0x6C,
1675         },
1676         .mem_bank                       = {
1677                 .reg                    = 0x6D,
1678         },
1679         .mem_addr                       = {
1680                 .reg                    = 0x6E,
1681         },
1682         .mem_rw                         = {
1683                 .reg                    = 0x6F,
1684         },
1685         .fw_start                       = {
1686                 .reg                    = 0x70,
1687                 .len                    = 2,
1688         },
1689         .fifo_en                        = {
1690                 .reg                    = 0x23,
1691         },
1692         .fifo_count_h                   = {
1693                 .reg                    = 0x72,
1694                 .len                    = 2,
1695         },
1696         .fifo_rw                        = {
1697                 .reg                    = 0x74,
1698         },
1699         .who_am_i                       = {
1700                 .reg                    = 0x75,
1701         },
1702         .i2c_mst_status                 = {
1703                 .reg                    = 0x36,
1704         },
1705         .i2c_mst_ctrl                   = {
1706                 .reg                    = 0x24,
1707         },
1708         .i2c_mst_delay_ctrl             = {
1709                 .reg                    = 0x67,
1710         },
1711         .i2c_slv_addr[0]                = {
1712                 .reg                    = 0x25,
1713         },
1714         .i2c_slv_addr[1]                = {
1715                 .reg                    = 0x28,
1716         },
1717         .i2c_slv_addr[2]                = {
1718                 .reg                    = 0x2B,
1719         },
1720         .i2c_slv_addr[3]                = {
1721                 .reg                    = 0x2E,
1722         },
1723         .i2c_slv_addr[4]                = {
1724                 .reg                    = 0x31,
1725         },
1726         .i2c_slv_reg[0]                 = {
1727                 .reg                    = 0x26,
1728         },
1729         .i2c_slv_reg[1]                 = {
1730                 .reg                    = 0x29,
1731         },
1732         .i2c_slv_reg[2]                 = {
1733                 .reg                    = 0x2C,
1734         },
1735         .i2c_slv_reg[3]                 = {
1736                 .reg                    = 0x2F,
1737         },
1738         .i2c_slv_reg[4]                 = {
1739                 .reg                    = 0x32,
1740         },
1741         .i2c_slv_ctrl[0]                = {
1742                 .reg                    = 0x27,
1743         },
1744         .i2c_slv_ctrl[1]                = {
1745                 .reg                    = 0x2A,
1746         },
1747         .i2c_slv_ctrl[2]                = {
1748                 .reg                    = 0x2D,
1749         },
1750         .i2c_slv_ctrl[3]                = {
1751                 .reg                    = 0x30,
1752         },
1753         .i2c_slv4_ctrl                  = {
1754                 .reg                    = 0x34,
1755         },
1756         .i2c_slv_do[0]                  = {
1757                 .reg                    = 0x63,
1758         },
1759         .i2c_slv_do[1]                  = {
1760                 .reg                    = 0x64,
1761         },
1762         .i2c_slv_do[2]                  = {
1763                 .reg                    = 0x65,
1764         },
1765         .i2c_slv_do[3]                  = {
1766                 .reg                    = 0x66,
1767         },
1768         .i2c_slv_do[4]                  = {
1769                 .reg                    = 0x33,
1770         },
1771         .i2c_slv4_di                    = {
1772                 .reg                    = 0x35,
1773         },
1774 };
1775
1776 const struct nvi_hal nvi_hal_6500 = {
1777         .regs_n                         = 128,
1778         .reg_bank_n                     = 1,
1779         .src                            = src,
1780         .src_n                          = ARRAY_SIZE(src),
1781         .lp_tbl                         = nvi_lp_dly_us_tbl_6500,
1782         .lp_tbl_n                       = ARRAY_SIZE(nvi_lp_dly_us_tbl_6500),
1783         .dev[DEV_ACC]                   = &nvi_hal_acc_6500,
1784         .dev[DEV_GYR]                   = &nvi_hal_gyr,
1785         .dev[DEV_TMP]                   = &nvi_hal_tmp_6500,
1786         .dev[DEV_SM]                    = &nvi_hal_dmp,
1787         .dev[DEV_STP]                   = &nvi_hal_dmp,
1788         .dev[DEV_QTN]                   = &nvi_hal_dmp,
1789         .dev[DEV_GMR]                   = &nvi_hal_dmp,
1790         .dev[DEV_GYU]                   = &nvi_hal_gyr,
1791         .dev[DEV_AUX]                   = &nvi_hal_aux,
1792         .reg                            = &nvi_hal_reg_6500,
1793         .bit                            = &nvi_hal_bit_6050,
1794         .fn                             = &nvi_fn_6500,
1795 };
1796 EXPORT_SYMBOL(nvi_hal_6500);
1797
1798 const struct nvi_hal nvi_hal_6515 = {
1799         .regs_n                         = 128,
1800         .reg_bank_n                     = 1,
1801         .src                            = src,
1802         .src_n                          = ARRAY_SIZE(src),
1803         .lp_tbl                         = nvi_lp_dly_us_tbl_6500,
1804         .lp_tbl_n                       = ARRAY_SIZE(nvi_lp_dly_us_tbl_6500),
1805         .dev[DEV_ACC]                   = &nvi_hal_acc_6500,
1806         .dev[DEV_GYR]                   = &nvi_hal_gyr,
1807         .dev[DEV_TMP]                   = &nvi_hal_tmp_6500,
1808         .dev[DEV_SM]                    = &nvi_hal_dmp,
1809         .dev[DEV_STP]                   = &nvi_hal_dmp,
1810         .dev[DEV_QTN]                   = &nvi_hal_dmp,
1811         .dev[DEV_GMR]                   = &nvi_hal_dmp,
1812         .dev[DEV_GYU]                   = &nvi_hal_gyr,
1813         .dev[DEV_AUX]                   = &nvi_hal_aux,
1814         .reg                            = &nvi_hal_reg_6500,
1815         .bit                            = &nvi_hal_bit_6050,
1816         .fn                             = &nvi_fn_6500,
1817         .dmp                            = &nvi_dmp_mpu,
1818 };
1819 EXPORT_SYMBOL(nvi_hal_6515);
1820