2 * arch/arm/mach-tegra/tegra12_clocks.c
4 * Copyright (C) 2011-2014 NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/platform_device.h>
32 #include <linux/tegra-soc.h>
33 #include <linux/tegra-fuse.h>
35 #include <asm/clkdev.h>
46 #include "tegra12_emc.h"
47 #include "tegra_cl_dvfs.h"
48 #include "cpu-tegra.h"
49 #include "tegra11_soctherm.h"
51 #define RST_DEVICES_L 0x004
52 #define RST_DEVICES_H 0x008
53 #define RST_DEVICES_U 0x00C
54 #define RST_DEVICES_V 0x358
55 #define RST_DEVICES_W 0x35C
56 #define RST_DEVICES_X 0x28C
57 #define RST_DEVICES_SET_L 0x300
58 #define RST_DEVICES_CLR_L 0x304
59 #define RST_DEVICES_SET_V 0x430
60 #define RST_DEVICES_CLR_V 0x434
61 #define RST_DEVICES_SET_X 0x290
62 #define RST_DEVICES_CLR_X 0x294
63 #define RST_DEVICES_NUM 6
65 #define CLK_OUT_ENB_L 0x010
66 #define CLK_OUT_ENB_H 0x014
67 #define CLK_OUT_ENB_U 0x018
68 #define CLK_OUT_ENB_V 0x360
69 #define CLK_OUT_ENB_W 0x364
70 #define CLK_OUT_ENB_X 0x280
71 #define CLK_OUT_ENB_SET_L 0x320
72 #define CLK_OUT_ENB_CLR_L 0x324
73 #define CLK_OUT_ENB_SET_V 0x440
74 #define CLK_OUT_ENB_CLR_V 0x444
75 #define CLK_OUT_ENB_SET_X 0x284
76 #define CLK_OUT_ENB_CLR_X 0x288
77 #define CLK_OUT_ENB_NUM 6
79 #define CLK_OUT_ENB_L_RESET_MASK 0xfcd7dff1
80 #define CLK_OUT_ENB_H_RESET_MASK 0xefddfff7
81 #define CLK_OUT_ENB_U_RESET_MASK 0xfbfefbfa
82 #define CLK_OUT_ENB_V_RESET_MASK 0xffc1fffb
83 #define CLK_OUT_ENB_W_RESET_MASK 0x3f7fbfff
84 #define CLK_OUT_ENB_X_RESET_MASK 0x00170979
86 #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) /* Reserved on Tegra11 */
87 #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
89 #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
90 #define PERIPH_CLK_TO_RST_REG(c) \
91 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, RST_DEVICES_X, 4)
92 #define PERIPH_CLK_TO_RST_SET_REG(c) \
93 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, \
95 #define PERIPH_CLK_TO_RST_CLR_REG(c) \
96 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, \
99 #define PERIPH_CLK_TO_ENB_REG(c) \
100 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, CLK_OUT_ENB_X, 4)
101 #define PERIPH_CLK_TO_ENB_SET_REG(c) \
102 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, \
103 CLK_OUT_ENB_SET_X, 8)
104 #define PERIPH_CLK_TO_ENB_CLR_REG(c) \
105 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, \
106 CLK_OUT_ENB_CLR_X, 8)
108 #define IS_PERIPH_IN_RESET(c) \
109 (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
111 #define CLK_MASK_ARM 0x44
112 #define MISC_CLK_ENB 0x48
114 #define OSC_CTRL 0x50
115 #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
116 #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
117 #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
118 #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
119 #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
120 #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
121 #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
122 #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
123 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
125 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
126 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
127 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
128 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
130 #define PERIPH_CLK_SOURCE_I2S1 0x100
131 #define PERIPH_CLK_SOURCE_EMC 0x19c
132 #define PERIPH_CLK_SOURCE_EMC_MC_SAME (1<<16)
134 #define PERIPH_CLK_SOURCE_LA 0x1f8
135 #define PERIPH_CLK_SOURCE_NUM1 \
136 ((PERIPH_CLK_SOURCE_LA - PERIPH_CLK_SOURCE_I2S1) / 4)
138 #define PERIPH_CLK_SOURCE_MSELECT 0x3b4
139 #define PERIPH_CLK_SOURCE_SE 0x42c
140 #define PERIPH_CLK_SOURCE_NUM2 \
141 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_MSELECT) / 4 + 1)
143 #define AUDIO_DLY_CLK 0x49c
144 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
145 #define PERIPH_CLK_SOURCE_NUM3 \
146 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
148 #define SPARE_REG 0x55c
149 #define SPARE_REG_CLK_M_DIVISOR_SHIFT 2
150 #define SPARE_REG_CLK_M_DIVISOR_MASK (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT)
152 #define PERIPH_CLK_SOURCE_XUSB_HOST 0x600
153 #define PERIPH_CLK_SOURCE_VIC 0x678
154 #define PERIPH_CLK_SOURCE_NUM4 \
155 ((PERIPH_CLK_SOURCE_VIC - PERIPH_CLK_SOURCE_XUSB_HOST) / 4 + 1)
157 #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
158 PERIPH_CLK_SOURCE_NUM2 + \
159 PERIPH_CLK_SOURCE_NUM3 + \
160 PERIPH_CLK_SOURCE_NUM4)
162 #define CPU_SOFTRST_CTRL 0x380
163 #define CPU_SOFTRST_CTRL1 0x384
164 #define CPU_SOFTRST_CTRL2 0x388
166 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
167 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
168 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
169 #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
170 #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
171 #define PERIPH_CLK_UART_DIV_ENB (1<<24)
172 #define PERIPH_CLK_VI_SEL_EX_SHIFT 24
173 #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
174 #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
175 #define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
177 #define AUDIO_SYNC_SOURCE_MASK 0x0F
178 #define AUDIO_SYNC_DISABLE_BIT 0x10
179 #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
181 #define PERIPH_CLK_SOR_CLK_SEL_SHIFT 14
182 #define PERIPH_CLK_SOR_CLK_SEL_MASK (0x3<<PERIPH_CLK_SOR_CLK_SEL_SHIFT)
186 #define PLL_BASE_BYPASS (1<<31)
187 #define PLL_BASE_ENABLE (1<<30)
188 #define PLL_BASE_REF_ENABLE (1<<29)
189 #define PLL_BASE_OVERRIDE (1<<28)
190 #define PLL_BASE_LOCK (1<<27)
191 #define PLL_BASE_DIVP_MASK (0x7<<20)
192 #define PLL_BASE_DIVP_SHIFT 20
193 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
194 #define PLL_BASE_DIVN_SHIFT 8
195 #define PLL_BASE_DIVM_MASK (0x1F)
196 #define PLL_BASE_DIVM_SHIFT 0
198 #define PLL_BASE_PARSE(pll, cfg, b) \
200 (cfg).m = ((b) & pll##_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; \
201 (cfg).n = ((b) & pll##_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; \
202 (cfg).p = ((b) & pll##_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT; \
205 #define PLL_OUT_RATIO_MASK (0xFF<<8)
206 #define PLL_OUT_RATIO_SHIFT 8
207 #define PLL_OUT_OVERRIDE (1<<2)
208 #define PLL_OUT_CLKEN (1<<1)
209 #define PLL_OUT_RESET_DISABLE (1<<0)
211 #define PLL_MISC(c) \
212 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
213 #define PLL_MISCN(c, n) \
214 ((c)->u.pll.misc1 + ((n) - 1) * PLL_MISC(c))
215 #define PLL_MISC_LOCK_ENABLE(c) \
216 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
218 #define PLL_MISC_DCCON_SHIFT 20
219 #define PLL_MISC_CPCON_SHIFT 8
220 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
221 #define PLL_MISC_LFCON_SHIFT 4
222 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
223 #define PLL_MISC_VCOCON_SHIFT 0
224 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
226 #define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
229 #define PLLU_BASE_OVERRIDE (1<<24)
230 #define PLLU_BASE_POST_DIV (1<<20)
233 #define PLLD_BASE_DIVN_MASK (0x7FF<<8)
234 #define PLLD_BASE_CSI_CLKENABLE (1<<26)
235 #define PLLD_BASE_DSI_MUX_SHIFT 25
236 #define PLLD_BASE_DSI_MUX_MASK (1<<PLLD_BASE_DSI_MUX_SHIFT)
237 #define PLLD_BASE_CSI_CLKSOURCE (1<<23)
239 #define PLLD_MISC_DSI_CLKENABLE (1<<30)
240 #define PLLD_MISC_DIV_RST (1<<23)
241 #define PLLD_MISC_DCCON_SHIFT 12
243 #define PLLDU_LFCON 2
245 /* PLLC2 and PLLC3 (PLLCX) */
246 #define PLLCX_USE_DYN_RAMP 0
247 #define PLLCX_BASE_PHASE_LOCK (1<<26)
248 #define PLLCX_BASE_DIVP_MASK (0x7<<PLL_BASE_DIVP_SHIFT)
249 #define PLLCX_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
250 #define PLLCX_BASE_DIVM_MASK (0x3<<PLL_BASE_DIVM_SHIFT)
251 #define PLLCX_PDIV_MAX ((PLLCX_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT))
252 #define PLLCX_IS_DYN(new_p, old_p) (((new_p) <= 8) && ((old_p) <= 8))
254 #define PLLCX_MISC_STROBE (1<<31)
255 #define PLLCX_MISC_RESET (1<<30)
256 #define PLLCX_MISC_SDM_DIV_SHIFT 28
257 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
258 #define PLLCX_MISC_FILT_DIV_SHIFT 26
259 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
260 #define PLLCX_MISC_ALPHA_SHIFT 18
261 #define PLLCX_MISC_ALPHA_MASK (0xFF << PLLCX_MISC_ALPHA_SHIFT)
262 #define PLLCX_MISC_KB_SHIFT 9
263 #define PLLCX_MISC_KB_MASK (0x1FF << PLLCX_MISC_KB_SHIFT)
264 #define PLLCX_MISC_KA_SHIFT 2
265 #define PLLCX_MISC_KA_MASK (0x7F << PLLCX_MISC_KA_SHIFT)
266 #define PLLCX_MISC_VCO_GAIN_SHIFT 0
267 #define PLLCX_MISC_VCO_GAIN_MASK (0x3 << PLLCX_MISC_VCO_GAIN_SHIFT)
269 #define PLLCX_MISC_KOEF_LOW_RANGE \
270 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x23 << PLLCX_MISC_KB_SHIFT))
272 #define PLLCX_MISC_DIV_LOW_RANGE \
273 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
274 #define PLLCX_MISC_DIV_HIGH_RANGE \
275 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
276 #define PLLCX_FD_ULCK_FRM_SHIFT 12
277 #define PLLCX_FD_ULCK_FRM_MASK (0x3 << PLLCX_FD_ULCK_FRM_SHIFT)
278 #define PLLCX_FD_LCK_FRM_SHIFT 8
279 #define PLLCX_FD_LCK_FRM_MASK (0x3 << PLLCX_FD_LCK_FRM_SHIFT)
280 #define PLLCX_PD_ULCK_FRM_SHIFT 28
281 #define PLLCX_PD_ULCK_FRM_MASK (0x3 << PLLCX_PD_ULCK_FRM_SHIFT)
282 #define PLLCX_PD_LCK_FRM_SHIFT 24
283 #define PLLCX_PD_LCK_FRM_MASK (0x3 << PLLCX_PD_LCK_FRM_SHIFT)
284 #define PLLCX_PD_OUT_HYST_SHIFT 20
285 #define PLLCX_PD_OUT_HYST_MASK (0x3 << PLLCX_PD_OUT_HYST_SHIFT)
286 #define PLLCX_PD_IN_HYST_SHIFT 16
287 #define PLLCX_PD_IN_HYST_MASK (0x3 << PLLCX_PD_IN_HYST_SHIFT)
289 #define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
290 PLLCX_MISC_KOEF_LOW_RANGE | \
291 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
292 PLLCX_MISC_DIV_LOW_RANGE | \
294 #define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
295 #define PLLCX_MISC2_DEFAULT_VALUE ((0x2 << PLLCX_PD_ULCK_FRM_SHIFT) | \
296 (0x1 << PLLCX_PD_LCK_FRM_SHIFT) | \
297 (0x3 << PLLCX_PD_OUT_HYST_SHIFT) | \
298 (0x1 << PLLCX_PD_IN_HYST_SHIFT) | \
299 (0x2 << PLLCX_FD_ULCK_FRM_SHIFT) | \
300 (0x2 << PLLCX_FD_LCK_FRM_SHIFT))
301 #define PLLCX_MISC3_DEFAULT_VALUE 0x200
303 #define PLLCX_MISC1_IDDQ (0x1 << 27)
305 /* PLLX and PLLC (PLLXC)*/
306 #define PLLXC_USE_DYN_RAMP 0
307 #define PLLXC_BASE_DIVP_MASK (0xF<<PLL_BASE_DIVP_SHIFT)
308 #define PLLXC_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
309 #define PLLXC_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
311 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w,
312 and s/w usage is limited to 5 */
313 #define PLLXC_PDIV_MAX 14
314 #define PLLXC_SW_PDIV_MAX 5
317 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
318 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
319 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
320 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
321 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
322 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
323 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
324 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
325 #define PLLX_MISC2_CLAMP_NDIV (0x1 << 1)
326 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
328 #define PLLX_MISC3_IDDQ (0x1 << 3)
330 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
331 #define PLLX_HW_CTRL_CFG 0x548
333 #define PLLX_HW_CTRL_CFG 0x14
336 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
339 #define PLLC_BASE_LOCK_OVERRIDE (1<<28)
341 #define PLLC_MISC_IDDQ (0x1 << 26)
342 #define PLLC_MISC_LOCK_ENABLE (0x1 << 24)
344 #define PLLC_MISC1_CLAMP_NDIV (0x1 << 26)
345 #define PLLC_MISC1_EN_DYNRAMP (0x1 << 25)
346 #define PLLC_MISC1_DYNRAMP_STEPA_SHIFT 17
347 #define PLLC_MISC1_DYNRAMP_STEPA_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPA_SHIFT)
348 #define PLLC_MISC1_DYNRAMP_STEPB_SHIFT 9
349 #define PLLC_MISC1_DYNRAMP_STEPB_MASK (0xFF << PLLC_MISC1_DYNRAMP_STEPB_SHIFT)
350 #define PLLC_MISC1_NDIV_NEW_SHIFT 1
351 #define PLLC_MISC1_NDIV_NEW_MASK (0xFF << PLLC_MISC1_NDIV_NEW_SHIFT)
352 #define PLLC_MISC1_DYNRAMP_DONE (0x1 << 0)
355 #define PLLM_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT)
356 #define PLLM_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
357 #define PLLM_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
359 /* PLLM has 4-bit PDIV, but entry 15 is not allowed in h/w,
360 and s/w usage is limited to 5 */
361 #define PLLM_PDIV_MAX 14
362 #define PLLM_SW_PDIV_MAX 5
364 #define PLLM_MISC_FSM_SW_OVERRIDE (0x1 << 10)
365 #define PLLM_MISC_IDDQ (0x1 << 5)
366 #define PLLM_MISC_LOCK_DISABLE (0x1 << 4)
367 #define PLLM_MISC_LOCK_OVERRIDE (0x1 << 3)
369 #define PMC_PLLP_WB0_OVERRIDE 0xf8
370 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
371 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11)
373 /* M, N layout for PLLM override and base registers are the same */
374 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
376 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
377 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT 27
378 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK (0xF << 27)
381 #define PLLSS_CFG(c) ((c)->u.pll.misc1 + 0)
382 #define PLLSS_CTRL1(c) ((c)->u.pll.misc1 + 4)
383 #define PLLSS_CTRL2(c) ((c)->u.pll.misc1 + 8)
385 #define PLLSS_BASE_DIVP_MASK (0xF << PLL_BASE_DIVP_SHIFT)
386 #define PLLSS_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
387 #define PLLSS_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
388 #define PLLSS_BASE_SOURCE_SHIFT 25
389 #define PLLSS_BASE_SOURCE_MASK (3 << PLLSS_BASE_SOURCE_SHIFT)
391 /* PLLSS has 4-bit PDIV, but entry 15 is not allowed in h/w,
392 and s/w usage is limited to 5 */
393 #define PLLSS_PDIV_MAX 14
394 #define PLLSS_SW_PDIV_MAX 5
396 #define PLLSS_MISC_LOCK_ENABLE (0x1 << 30)
397 #define PLLSS_MISC_KCP_SHIFT 25
398 #define PLLSS_MISC_KCP_MASK (0x3 << PLLSS_MISC_KCP_SHIFT)
399 #define PLLSS_MISC_KVCO_SHIFT 24
400 #define PLLSS_MISC_KVCO_MASK (0x1 << PLLSS_MISC_KVCO_SHIFT)
401 #define PLLSS_MISC_SETUP_SHIFT 0
402 #define PLLSS_MISC_SETUP_MASK (0xFFFFFF << PLLSS_MISC_SETUP_SHIFT)
403 #define PLLSS_BASE_LOCK_OVERRIDE (0x1 << 24)
404 #define PLLSS_BASE_LOCK (0x1 << 27)
405 #define PLLSS_BASE_IDDQ (0x1 << 19)
407 #define PLLSS_MISC_DEFAULT_VALUE ( \
408 (PLLSS_MISC_KVCO << PLLSS_MISC_KVCO_SHIFT) | \
409 (PLLSS_MISC_SETUP << PLLSS_MISC_SETUP_SHIFT))
410 #define PLLSS_CFG_DEFAULT_VALUE ( \
411 (PLLSS_EN_SDM << 31) | \
412 (PLLSS_EN_SSC << 30) | \
413 (PLLSS_EN_DITHER2 << 29) | \
414 (PLLSS_EN_DITHER << 28) | \
415 (PLLSS_SDM_RESET << 27) | \
417 #define PLLSS_CTRL1_DEFAULT_VALUE \
418 ((PLLSS_SDM_SSC_MAX << 16) | (PLLSS_SDM_SSC_MIN << 0))
419 #define PLLSS_CTRL2_DEFAULT_VALUE \
420 ((PLLSS_SDM_SSC_STEP << 16) | (PLLSS_SDM_DIN << 0))
422 /* PLLSS configuration */
423 #define PLLSS_MISC_KVCO 0
424 #define PLLSS_MISC_SETUP 0
425 #define PLLSS_EN_SDM 0
426 #define PLLSS_EN_SSC 0
427 #define PLLSS_EN_DITHER2 0
428 #define PLLSS_EN_DITHER 1
429 #define PLLSS_SDM_RESET 0
430 #define PLLSS_CLAMP 0
431 #define PLLSS_SDM_SSC_MAX 0
432 #define PLLSS_SDM_SSC_MIN 0
433 #define PLLSS_SDM_SSC_STEP 0
434 #define PLLSS_SDM_DIN 0
436 /* PLLDP SS parameters */
437 #define PLLDP_SS_CTRL1_0_DEFAULT_VALUE 0xF000E5EC
438 #define PLLDP_SS_CTRL2_0_DEFAULT_VALUE 0x101BF000
439 #define PLLDP_SS_CFG_0_DEFAULT_VALUE 0xC0000000
443 #define PLLRE_BASE_DIVP_SHIFT 16
444 #define PLLRE_BASE_DIVP_MASK (0xF << PLLRE_BASE_DIVP_SHIFT)
445 #define PLLRE_BASE_DIVN_MASK (0xFF << PLL_BASE_DIVN_SHIFT)
446 #define PLLRE_BASE_DIVM_MASK (0xFF << PLL_BASE_DIVM_SHIFT)
448 /* PLLRE has 4-bit PDIV, but entry 15 is not allowed in h/w,
449 and s/w usage is limited to 5 */
450 #define PLLRE_PDIV_MAX 14
451 #define PLLRE_SW_PDIV_MAX 5
453 #define PLLRE_MISC_LOCK_ENABLE (0x1 << 30)
454 #define PLLRE_MISC_LOCK_OVERRIDE (0x1 << 29)
455 #define PLLRE_MISC_LOCK (0x1 << 24)
456 #define PLLRE_MISC_IDDQ (0x1 << 16)
458 #define OUT_OF_TABLE_CPCON 0x8
460 #define SUPER_CLK_MUX 0x00
461 #define SUPER_STATE_SHIFT 28
462 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
463 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
464 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
465 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
466 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
467 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
468 #define SUPER_LP_DIV2_BYPASS (0x1 << 16)
469 #define SUPER_SOURCE_MASK 0xF
470 #define SUPER_FIQ_SOURCE_SHIFT 12
471 #define SUPER_IRQ_SOURCE_SHIFT 8
472 #define SUPER_RUN_SOURCE_SHIFT 4
473 #define SUPER_IDLE_SOURCE_SHIFT 0
475 #define SUPER_CLK_DIVIDER 0x04
476 #define SUPER_CLOCK_DIV_U71_SHIFT 16
477 #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
479 #define CLK13_SOURCE_SHIFT 28
480 #define CLK13_SOURCE_MASK 0xF
482 #define BUS_CLK_DISABLE (1<<3)
483 #define BUS_CLK_DIV_MASK 0x3
486 #define PMC_CTRL_BLINK_ENB (1 << 7)
488 #define PMC_DPD_PADS_ORIDE 0x1c
489 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
491 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
492 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
493 #define PMC_BLINK_TIMER_ENB (1 << 15)
494 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
495 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
497 #define UTMIP_PLL_CFG2 0x488
498 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
499 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
500 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
501 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
502 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
503 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
504 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
505 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
506 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
507 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
509 #define UTMIP_PLL_CFG1 0x484
510 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
511 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
512 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
513 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
514 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
515 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
516 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
519 #define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
520 #define PLLE_BASE_DIVCML_SHIFT 24
521 #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
523 #define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
524 #define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
526 /* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
527 #define PLLE_CMLDIV_MAX 14
528 #define PLLE_MISC_READY (1<<15)
529 #define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
530 #define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
531 #define PLLE_MISC_LOCK (1<<11)
532 #define PLLE_MISC_LOCK_ENABLE (1<<9)
533 #define PLLE_MISC_PLLE_PTS (1<<8)
534 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
535 #define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
536 #define PLLE_MISC_VREG_CTRL_SHIFT 2
537 #define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
539 #define PLLE_SS_CTRL 0x68
540 #define PLLE_SS_INCINTRV_SHIFT 24
541 #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
542 #define PLLE_SS_INC_SHIFT 16
543 #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
544 #define PLLE_SS_CNTL_INVERT (0x1 << 15)
545 #define PLLE_SS_CNTL_CENTER (0x1 << 14)
546 #define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
547 #define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
548 #define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
549 #define PLLE_SS_MAX_SHIFT 0
550 #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
551 #define PLLE_SS_COEFFICIENTS_MASK \
552 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
553 #define PLLE_SS_COEFFICIENTS_VAL \
554 ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
555 (0x25<<PLLE_SS_MAX_SHIFT))
556 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
557 PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
559 #define PLLE_AUX 0x48c
560 #define PLLE_AUX_PLLRE_SEL (1<<28)
561 #define PLLE_AUX_SEQ_STATE_SHIFT 26
562 #define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
563 #define PLLE_AUX_SEQ_START_STATE (1<<25)
564 #define PLLE_AUX_SEQ_ENABLE (1<<24)
565 #define PLLE_AUX_SS_SWCTL (1<<6)
566 #define PLLE_AUX_ENABLE_SWCTL (1<<4)
567 #define PLLE_AUX_USE_LOCKDET (1<<3)
568 #define PLLE_AUX_PLLP_SEL (1<<2)
570 #define PLLE_AUX_CML_SATA_ENABLE (1<<1)
571 #define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
573 /* USB PLLs PD HW controls */
574 #define XUSBIO_PLL_CFG0 0x51c
575 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
576 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
577 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
578 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
579 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
581 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
582 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
583 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
584 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
585 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
586 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
587 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
588 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
589 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
591 #define PLLU_HW_PWRDN_CFG0 0x530
592 #define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
593 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
594 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
595 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
596 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
598 #define USB_PLLS_SEQ_START_STATE (1<<25)
599 #define USB_PLLS_SEQ_ENABLE (1<<24)
600 #define USB_PLLS_USE_LOCKDET (1<<6)
601 #define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
603 /* XUSB PLL PAD controls */
604 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0 0x40
605 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD (1<<3)
606 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ (1<<0)
610 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
611 #define DFLL_BASE 0x2f4
613 #define DFLL_BASE 0x80
615 #define DFLL_BASE_RESET (1<<0)
617 #define LVL2_CLK_GATE_OVRE 0x554
619 #define ROUND_DIVIDER_UP 0
620 #define ROUND_DIVIDER_DOWN 1
621 #define DIVIDER_1_5_ALLOWED 0
623 /* Tegra CPU clock and reset control regs */
624 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
625 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
626 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
627 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
628 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
630 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
631 #define CPU_RESET(cpu) (0x111001ul << (cpu))
633 /* PLLP default fixed rate in h/w controlled mode */
634 #define PLLP_DEFAULT_FIXED_RATE 408000000
636 /* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
637 #define USE_PLLE_INPUT_PLLRE 0
639 static bool tegra12_is_dyn_ramp(struct clk *c,
640 unsigned long rate, bool from_vco_min);
641 static void tegra12_pllp_init_dependencies(unsigned long pllp_rate);
642 static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
643 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap);
644 static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
645 unsigned long rate, unsigned long ceiling);
647 static bool tegra12_periph_is_special_reset(struct clk *c);
648 static void tegra12_dfll_cpu_late_init(struct clk *c);
650 static bool detach_shared_bus;
651 module_param(detach_shared_bus, bool, 0644);
653 /* Defines default range for dynamic frequency lock loop (DFLL)
654 to be used as CPU clock source:
655 "0" - DFLL is not used,
656 "1" - DFLL is used as a source for all CPU rates
657 "2" - DFLL is used only for high rates above crossover with PLL dvfs curve
662 * Structure defining the fields for USB UTMI clocks Parameters.
664 struct utmi_clk_param
666 /* Oscillator Frequency in KHz */
668 /* UTMIP PLL Enable Delay Count */
669 u8 enable_delay_count;
670 /* UTMIP PLL Stable count */
672 /* UTMIP PLL Active delay count */
673 u8 active_delay_count;
674 /* UTMIP PLL Xtal frequency count */
678 static const struct utmi_clk_param utmi_parameters[] =
680 /* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
681 {13000000, 0x02, 0x33, 0x05, 0x7F},
682 {19200000, 0x03, 0x4B, 0x06, 0xBB},
683 {12000000, 0x02, 0x2F, 0x04, 0x76},
684 {26000000, 0x04, 0x66, 0x09, 0xFE},
685 {16800000, 0x03, 0x41, 0x0A, 0xA4},
688 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
689 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
690 static void __iomem *reg_clk13_base = IO_ADDRESS(TEGRA_CLK13_RESET_BASE);
692 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
693 static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
694 static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
696 #define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
697 #define MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE (0x1 << 1)
698 #define MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE (0x1 << 2)
699 #define MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE (0x1 << 3)
702 * Some peripheral clocks share an enable bit, so refcount the enable bits
703 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
706 static DEFINE_SPINLOCK(periph_refcount_lock);
707 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
709 #define clk_writel(value, reg) \
710 __raw_writel(value, reg_clk_base + (reg))
711 #define clk_readl(reg) \
712 __raw_readl(reg_clk_base + (reg))
713 #define pmc_writel(value, reg) \
714 __raw_writel(value, reg_pmc_base + (reg))
715 #define pmc_readl(reg) \
716 readl(reg_pmc_base + (reg))
717 #define xusb_padctl_writel(value, reg) \
718 __raw_writel(value, reg_xusb_padctl_base + (reg))
719 #define xusb_padctl_readl(reg) \
720 readl(reg_xusb_padctl_base + (reg))
722 static inline void clk_writel_delay(u32 value, u32 reg)
724 __raw_writel((value), reg_clk_base + (reg));
725 __raw_readl(reg_clk_base + (reg));
730 static inline void pll_writel_delay(u32 value, u32 reg)
732 __raw_writel((value), reg_clk_base + (reg));
733 __raw_readl(reg_clk_base + (reg));
738 /* Overloading clk_writelx macro based on the TEGRA_13x_SOC define */
739 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
741 #define clk_writelx(value, reg) \
742 __raw_writel(value, reg_clk_base + (reg))
743 #define clk_readlx(reg) \
744 __raw_readl(reg_clk_base + (reg))
748 #define clk_writelx(value, reg) \
749 __raw_writel(value, reg_clk13_base + (reg))
750 #define clk_readlx(reg) \
751 __raw_readl(reg_clk13_base + (reg))
755 static inline void clk_writelx_delay(u32 value, u32 reg)
757 clk_writelx(value, reg);
763 static inline void pll_writelx_delay(u32 value, u32 reg)
765 clk_writelx(value, reg);
771 static inline int clk_set_div(struct clk *c, u32 n)
773 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
776 static inline u32 periph_clk_to_reg(
777 struct clk *c, u32 reg_L, u32 reg_V, u32 reg_X, int offs)
779 u32 reg = c->u.periph.clk_num / 32;
780 BUG_ON(reg >= RST_DEVICES_NUM);
782 reg = reg_L + (reg * offs);
784 reg = reg_V + ((reg - 3) * offs);
790 static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
792 u32 flags, u32 round_mode)
794 s64 divider_ux1 = parent_rate;
798 if (!(flags & DIV_U71_INT))
800 if (round_mode == ROUND_DIVIDER_UP)
801 divider_ux1 += rate - 1;
802 do_div(divider_ux1, rate);
803 if (flags & DIV_U71_INT)
806 if (divider_ux1 - 2 < 0)
809 if (divider_ux1 - 2 > max_x)
812 #if !DIVIDER_1_5_ALLOWED
813 if (divider_ux1 == 3)
814 divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
816 return divider_ux1 - 2;
819 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
820 u32 flags, u32 round_mode)
822 return clk_div_x1_get_divider(parent_rate, rate, 0xFF,
826 static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate,
827 u32 flags, u32 round_mode)
829 return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF,
833 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
837 divider_u16 = parent_rate;
840 divider_u16 += rate - 1;
841 do_div(divider_u16, rate);
843 if (divider_u16 - 1 < 0)
846 if (divider_u16 - 1 > 0xFFFF)
849 return divider_u16 - 1;
852 static long fixed_src_bus_round_updown(struct clk *c, struct clk *src,
853 u32 flags, unsigned long rate, bool up)
856 unsigned long source_rate, round_rate;
858 source_rate = clk_get_rate(src);
860 divider = clk_div71_get_divider(source_rate, rate + (up ? -1 : 1),
861 flags, up ? ROUND_DIVIDER_DOWN : ROUND_DIVIDER_UP);
865 round_rate = source_rate * 2 / (divider + 2);
867 if (round_rate > c->max_rate) {
868 divider += flags & DIV_U71_INT ? 2 : 1;
869 #if !DIVIDER_1_5_ALLOWED
870 divider = max(2, divider);
872 round_rate = source_rate * 2 / (divider + 2);
877 static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
879 return a->u.shared_bus_user.client->max_rate * a->div <
880 b->u.shared_bus_user.client->max_rate * b->div;
883 static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
885 return a->u.shared_bus_user.rate * a->div <
886 b->u.shared_bus_user.rate * b->div;
889 /* clk_m functions */
890 static unsigned long tegra12_clk_m_autodetect_rate(struct clk *c)
892 u32 osc_ctrl = clk_readl(OSC_CTRL);
893 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
894 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
896 u32 spare = clk_readl(SPARE_REG);
897 u32 divisor = (spare & SPARE_REG_CLK_M_DIVISOR_MASK)
898 >> SPARE_REG_CLK_M_DIVISOR_SHIFT;
899 u32 spare_update = spare & ~SPARE_REG_CLK_M_DIVISOR_MASK;
901 c->rate = tegra_clk_measure_input_freq();
904 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
905 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
906 BUG_ON(divisor != 0);
909 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
910 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
911 BUG_ON(divisor != 0);
914 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
915 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
916 BUG_ON(divisor != 0);
919 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
920 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
921 BUG_ON(divisor != 0);
924 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
925 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
926 BUG_ON(divisor != 0);
929 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
930 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
931 BUG_ON(divisor != 1);
932 spare_update |= (1 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
935 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
936 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
937 BUG_ON(divisor != 3);
938 spare_update |= (3 << SPARE_REG_CLK_M_DIVISOR_SHIFT);
940 case 115200: /* fake 13M for QT */
941 case 230400: /* fake 13M for QT */
942 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
944 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
945 BUG_ON(divisor != 0);
948 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
952 clk_writel(auto_clock_control, OSC_CTRL);
953 clk_writel(spare_update, SPARE_REG);
958 static void tegra12_clk_m_init(struct clk *c)
960 pr_debug("%s on clock %s\n", __func__, c->name);
961 tegra12_clk_m_autodetect_rate(c);
964 static int tegra12_clk_m_enable(struct clk *c)
966 pr_debug("%s on clock %s\n", __func__, c->name);
970 static void tegra12_clk_m_disable(struct clk *c)
972 pr_debug("%s on clock %s\n", __func__, c->name);
973 WARN(1, "Attempting to disable main SoC clock\n");
976 static struct clk_ops tegra_clk_m_ops = {
977 .init = tegra12_clk_m_init,
978 .enable = tegra12_clk_m_enable,
979 .disable = tegra12_clk_m_disable,
982 static struct clk_ops tegra_clk_m_div_ops = {
983 .enable = tegra12_clk_m_enable,
986 /* PLL reference divider functions */
987 static void tegra12_pll_ref_init(struct clk *c)
989 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
990 pr_debug("%s on clock %s\n", __func__, c->name);
992 switch (pll_ref_div) {
993 case OSC_CTRL_PLL_REF_DIV_1:
996 case OSC_CTRL_PLL_REF_DIV_2:
999 case OSC_CTRL_PLL_REF_DIV_4:
1003 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
1010 static struct clk_ops tegra_pll_ref_ops = {
1011 .init = tegra12_pll_ref_init,
1012 .enable = tegra12_clk_m_enable,
1013 .disable = tegra12_clk_m_disable,
1016 /* super clock functions */
1017 /* "super clocks" on tegra12x have two-stage muxes, fractional 7.1 divider and
1018 * clock skipping super divider. We will ignore the clock skipping divider,
1019 * since we can't lower the voltage when using the clock skip, but we can if
1020 * we lower the PLL frequency. Note that skipping divider can and will be used
1021 * by thermal control h/w for automatic throttling. There is also a 7.1 divider
1022 * that most CPU super-clock inputs can be routed through. We will not use it
1023 * as well (keep default 1:1 state), to avoid high jitter on PLLX and DFLL path
1024 * and possible concurrency access issues with thermal h/w (7.1 divider setting
1025 * share register with clock skipping divider)
1027 static void tegra12_super_clk_init(struct clk *c)
1032 const struct clk_mux_sel *sel;
1033 val = clk_readl(c->reg + SUPER_CLK_MUX);
1035 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
1036 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
1037 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
1038 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
1039 source = (val >> shift) & SUPER_SOURCE_MASK;
1042 * Enforce PLLX DIV2 bypass setting as early as possible. It is always
1043 * safe to do for both cclk_lp and cclk_g when booting on G CPU. (In
1044 * case of booting on LP CPU, cclk_lp will be updated during the cpu
1045 * rate change after boot, and cclk_g after the cluster switch.)
1047 if ((c->flags & DIV_U71) && (!is_lp_cluster())) {
1048 val |= SUPER_LP_DIV2_BYPASS;
1049 clk_writel_delay(val, c->reg);
1052 for (sel = c->inputs; sel->input != NULL; sel++) {
1053 if (sel->value == source)
1056 BUG_ON(sel->input == NULL);
1057 c->parent = sel->input;
1059 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
1060 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
1061 (val & SUPER_LP_DIV2_BYPASS))
1062 c->parent = c->parent->parent;
1064 /* Update parent in case when LP CPU PLLX DIV2 bypassed */
1065 if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
1066 (val & SUPER_LP_DIV2_BYPASS))
1067 c->parent = c->parent->parent;
1069 if (c->flags & DIV_U71) {
1074 * Make sure 7.1 divider is 1:1; clear h/w skipper control -
1075 * it will be enabled by soctherm later
1077 val = clk_readl(c->reg + SUPER_CLK_DIVIDER);
1078 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
1080 clk_writel(val, c->reg + SUPER_CLK_DIVIDER);
1083 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
1086 static int tegra12_super_clk_enable(struct clk *c)
1091 static void tegra12_super_clk_disable(struct clk *c)
1093 /* since tegra12 has 2 CPU super clocks - low power lp-mode clock and
1094 geared up g-mode super clock - mode switch may request to disable
1095 either of them; accept request with no affect on h/w */
1098 static int tegra12_super_clk_set_parent(struct clk *c, struct clk *p)
1101 const struct clk_mux_sel *sel;
1104 val = clk_readl(c->reg + SUPER_CLK_MUX);
1105 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
1106 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
1107 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
1108 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
1109 for (sel = c->inputs; sel->input != NULL; sel++) {
1110 if (sel->input == p) {
1111 /* For LP mode super-clock switch between PLLX direct
1112 and divided-by-2 outputs is allowed only when other
1113 than PLLX clock source is current parent */
1114 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
1115 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
1116 if (c->parent->flags & PLLX)
1118 val ^= SUPER_LP_DIV2_BYPASS;
1119 clk_writel_delay(val, c->reg);
1121 val &= ~(SUPER_SOURCE_MASK << shift);
1122 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
1124 if (c->flags & DIV_U71) {
1125 /* Make sure 7.1 divider is 1:1 */
1126 u32 div = clk_readl(c->reg + SUPER_CLK_DIVIDER);
1127 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
1133 clk_writel_delay(val, c->reg);
1135 if (c->refcnt && c->parent)
1136 clk_disable(c->parent);
1146 * Do not use super clocks "skippers", since dividing using a clock skipper
1147 * does not allow the voltage to be scaled down. Instead adjust the rate of
1148 * the parent clock. This requires that the parent of a super clock have no
1149 * other children, otherwise the rate will change underneath the other
1152 static int tegra12_super_clk_set_rate(struct clk *c, unsigned long rate)
1154 /* In tegra12_cpu_clk_set_plls() and tegra12_sbus_cmplx_set_rate()
1155 * this call is skipped by directly setting rate of source plls. If we
1156 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
1157 * skipper control, not only this function, but cpu and sbus set_rate
1158 * APIs should be changed accordingly.
1160 return clk_set_rate(c->parent, rate);
1163 #ifdef CONFIG_PM_SLEEP
1164 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
1165 static void tegra12_super_clk_resume(struct clk *c, struct clk *backup,
1169 const struct clk_mux_sel *sel;
1172 /* For sclk and cclk_g super clock just restore saved value */
1173 if (!(c->flags & DIV_2)) {
1174 clk_writel_delay(setting, c->reg);
1179 * For cclk_lp supper clock: switch to backup (= not PLLX) source,
1180 * safely restore PLLX DIV2 bypass, and only then restore full
1183 val = clk_readl(c->reg);
1184 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
1185 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
1186 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
1187 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
1188 for (sel = c->inputs; sel->input != NULL; sel++) {
1189 if (sel->input == backup) {
1190 val &= ~(SUPER_SOURCE_MASK << shift);
1191 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
1193 BUG_ON(backup->flags & PLLX);
1194 clk_writel_delay(val, c->reg);
1196 val &= ~SUPER_LP_DIV2_BYPASS;
1197 val |= (setting & SUPER_LP_DIV2_BYPASS);
1198 clk_writel_delay(val, c->reg);
1199 clk_writel_delay(setting, c->reg);
1208 static struct clk_ops tegra_super_ops = {
1209 .init = tegra12_super_clk_init,
1210 .enable = tegra12_super_clk_enable,
1211 .disable = tegra12_super_clk_disable,
1212 .set_parent = tegra12_super_clk_set_parent,
1213 .set_rate = tegra12_super_clk_set_rate,
1216 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1217 static void tegra13_super_cclk_init(struct clk *c)
1222 const struct clk_mux_sel *sel;
1223 val = clk_readlx(c->reg + SUPER_CLK_MUX);
1226 shift = CLK13_SOURCE_SHIFT;
1227 source = (val >> shift) & CLK13_SOURCE_MASK;
1229 for (sel = c->inputs; sel->input != NULL; sel++) {
1230 if (sel->value == source)
1233 BUG_ON(sel->input == NULL);
1234 c->parent = sel->input;
1236 if (c->flags & DIV_U71) {
1241 * Make sure 7.1 divider is 1:1; clear h/w skipper control -
1242 * it will be enabled by soctherm later
1244 val = clk_readlx(c->reg + SUPER_CLK_DIVIDER);
1245 BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK);
1247 clk_writelx(val, c->reg + SUPER_CLK_DIVIDER);
1250 clk_writelx(0, c->reg + SUPER_CLK_DIVIDER);
1253 static int tegra13_super_cclk_enable(struct clk *c)
1258 static void tegra13_super_cclk_disable(struct clk *c)
1260 /* since tegra13 has 1 CPU super clocks that is never disabled
1261 by clock framework accept request with no affect on h/w */
1264 static int tegra13_super_cclk_set_parent(struct clk *c, struct clk *p)
1267 const struct clk_mux_sel *sel;
1270 val = clk_readlx(c->reg);
1271 shift = CLK13_SOURCE_SHIFT;
1272 for (sel = c->inputs; sel->input != NULL; sel++) {
1273 if (sel->input == p) {
1274 val &= ~(CLK13_SOURCE_MASK << shift);
1275 val |= (sel->value & CLK13_SOURCE_MASK) << shift;
1277 if (c->flags & DIV_U71) {
1278 /* Make sure 7.1 divider is 1:1 */
1279 u32 div = clk_readlx(c->reg + SUPER_CLK_DIVIDER);
1280 BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK);
1286 clk_writelx_delay(val, c->reg);
1288 if (c->refcnt && c->parent)
1289 clk_disable(c->parent);
1299 * Do not use super clocks "skippers", since dividing using a clock skipper
1300 * does not allow the voltage to be scaled down. Instead adjust the rate of
1301 * the parent clock. This requires that the parent of a super clock have no
1302 * other children, otherwise the rate will change underneath the other
1305 static int tegra13_super_cclk_set_rate(struct clk *c, unsigned long rate)
1307 /* In tegra12_cpu_clk_set_plls() op (shared with tegra13 as well)
1308 * this call is skipped by directly setting rate of source plls. If we
1309 * ever use 7.1 divider at other than 1:1 setting, or exercise s/w
1310 * skipper control, not only this function, but cpu and sbus set_rate
1311 * APIs should be changed accordingly.
1313 return clk_set_rate(c->parent, rate);
1316 static struct clk_ops tegra13_super_cclk_ops = {
1317 .init = tegra13_super_cclk_init,
1318 .enable = tegra13_super_cclk_enable,
1319 .disable = tegra13_super_cclk_disable,
1320 .set_parent = tegra13_super_cclk_set_parent,
1321 .set_rate = tegra13_super_cclk_set_rate,
1325 /* virtual cpu clock functions */
1326 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
1327 To change the frequency of these clocks, the parent pll may need to be
1328 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
1329 and then the clock moved back to the pll. To hide this sequence, a virtual
1332 static void tegra12_cpu_clk_init(struct clk *c)
1334 c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF;
1337 static int tegra12_cpu_clk_enable(struct clk *c)
1342 static void tegra12_cpu_clk_disable(struct clk *c)
1345 * tegra12 has 2 virtual CPU clocks - low power lp-mode clock
1346 * and geared up g-mode clock - mode switch may request to disable
1347 * either of them; tegra13 that shares CPU ops with tegra12 has
1348 * only one virtual CPU that is never disabled; in any case accept
1349 * request with no affect on h/w/
1353 static int tegra12_cpu_clk_set_plls(struct clk *c, unsigned long rate,
1354 unsigned long old_rate)
1357 bool on_main = false;
1358 unsigned long backup_rate, main_rate;
1359 unsigned long vco_min = c->u.cpu.main->u.pll.vco_min;
1362 * Take an extra reference to the main pll so it doesn't turn off when
1363 * we move the cpu off of it. If possible, use main pll dynamic ramp
1364 * to reach target rate in one shot. Otherwise, use dynamic ramp to
1365 * lower current rate to pll VCO minimum level before switching to
1368 if (c->parent->parent == c->u.cpu.main) {
1369 bool dramp = (rate > c->u.cpu.backup_rate) &&
1370 tegra12_is_dyn_ramp(c->u.cpu.main, rate, false);
1371 clk_enable(c->u.cpu.main);
1375 ((old_rate > vco_min) &&
1376 tegra12_is_dyn_ramp(c->u.cpu.main, vco_min, false))) {
1377 main_rate = dramp ? rate : vco_min;
1378 ret = clk_set_rate(c->u.cpu.main, main_rate);
1380 pr_err("Failed to set cpu rate %lu on source"
1381 " %s\n", main_rate, c->u.cpu.main->name);
1386 } else if (old_rate > vco_min) {
1387 #if PLLXC_USE_DYN_RAMP
1388 pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
1389 c->u.cpu.main->name, old_rate, vco_min);
1394 /* Switch to back-up source, and stay on it if target rate is below
1396 if (c->parent->parent != c->u.cpu.backup) {
1397 ret = clk_set_parent(c->parent, c->u.cpu.backup);
1399 pr_err("Failed to switch cpu to %s\n",
1400 c->u.cpu.backup->name);
1405 backup_rate = min(rate, c->u.cpu.backup_rate);
1406 if (backup_rate != clk_get_rate_locked(c)) {
1407 ret = clk_set_rate(c->u.cpu.backup, backup_rate);
1409 pr_err("Failed to set cpu rate %lu on backup source\n",
1414 if (rate == backup_rate)
1417 /* Switch from backup source to main at rate not exceeding pll VCO
1418 minimum. Use dynamic ramp to reach target rate if it is above VCO
1421 if (rate > vco_min) {
1422 if (tegra12_is_dyn_ramp(c->u.cpu.main, rate, true))
1423 main_rate = vco_min;
1424 #if PLLXC_USE_DYN_RAMP
1426 pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
1427 c->u.cpu.main->name, vco_min, rate);
1431 ret = clk_set_rate(c->u.cpu.main, main_rate);
1433 pr_err("Failed to set cpu rate %lu on source"
1434 " %s\n", main_rate, c->u.cpu.main->name);
1437 ret = clk_set_parent(c->parent, c->u.cpu.main);
1439 pr_err("Failed to switch cpu to %s\n", c->u.cpu.main->name);
1442 if (rate != main_rate) {
1443 ret = clk_set_rate(c->u.cpu.main, rate);
1445 pr_err("Failed to set cpu rate %lu on source"
1446 " %s\n", rate, c->u.cpu.main->name);
1453 clk_disable(c->u.cpu.main);
1458 static int tegra12_cpu_clk_dfll_on(struct clk *c, unsigned long rate,
1459 unsigned long old_rate)
1462 struct clk *dfll = c->u.cpu.dynamic;
1463 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1465 /* dfll rate request */
1466 ret = clk_set_rate(dfll, rate);
1468 pr_err("Failed to set cpu rate %lu on source"
1469 " %s\n", rate, dfll->name);
1473 /* 1st time - switch to dfll */
1474 if (c->parent->parent != dfll) {
1475 if (max(old_rate, rate) < dfll_rate_min) {
1476 /* set interim cpu dvfs rate at dfll_rate_min to
1477 prevent voltage drop below dfll Vmin */
1478 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1480 pr_err("Failed to set cpu dvfs rate %lu\n",
1486 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1487 ret = clk_set_parent(c->parent, dfll);
1489 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1490 pr_err("Failed to switch cpu to %s\n", dfll->name);
1493 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1494 WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
1496 /* prevent legacy dvfs voltage scaling */
1497 tegra_dvfs_dfll_mode_set(c->dvfs, rate);
1498 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1503 static int tegra12_cpu_clk_dfll_off(struct clk *c, unsigned long rate,
1504 unsigned long old_rate)
1508 struct clk *dfll = c->u.cpu.dynamic;
1509 unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
1511 rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
1512 pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
1513 dfll_rate_min = max(rate, dfll_rate_min);
1515 /* set target rate last time in dfll mode */
1516 if (old_rate != dfll_rate_min) {
1517 ret = tegra_dvfs_set_rate(c, dfll_rate_min);
1519 ret = clk_set_rate(dfll, dfll_rate_min);
1522 pr_err("Failed to set cpu rate %lu on source %s\n",
1523 dfll_rate_min, dfll->name);
1528 /* unlock dfll - release volatge rail control */
1529 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1530 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1532 pr_err("Failed to unlock %s\n", dfll->name);
1536 /* restore legacy dvfs operations and set appropriate voltage */
1537 ret = tegra_dvfs_dfll_mode_clear(c->dvfs, dfll_rate_min);
1539 pr_err("Failed to set cpu rail for rate %lu\n", rate);
1543 /* set pll to target rate and return to pll source */
1544 ret = clk_set_rate(pll, rate);
1546 pr_err("Failed to set cpu rate %lu on source"
1547 " %s\n", rate, pll->name);
1550 ret = clk_set_parent(c->parent, pll);
1552 pr_err("Failed to switch cpu to %s\n", pll->name);
1556 /* If going up, adjust voltage here (down path is taken care of by the
1557 framework after set rate exit) */
1558 if (old_rate <= rate)
1559 tegra_dvfs_set_rate(c, rate);
1561 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1565 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1566 tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
1567 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1571 static int tegra12_cpu_clk_set_rate(struct clk *c, unsigned long rate)
1573 unsigned long old_rate = clk_get_rate_locked(c);
1574 bool has_dfll = c->u.cpu.dynamic &&
1575 (c->u.cpu.dynamic->state != UNINITIALIZED);
1576 bool is_dfll = c->parent->parent == c->u.cpu.dynamic;
1578 /* On SILICON allow CPU rate change only if cpu regulator is connected.
1579 Ignore regulator connection on FPGA and SIMULATION platforms. */
1580 if (c->dvfs && tegra_platform_is_silicon()) {
1581 if (!c->dvfs->dvfs_rail)
1583 else if ((!c->dvfs->dvfs_rail->reg) && (old_rate < rate) &&
1584 (c->boot_rate < rate)) {
1585 WARN(1, "Increasing CPU rate while regulator is not"
1586 " ready is not allowed\n");
1590 if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
1591 if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
1592 return tegra12_cpu_clk_dfll_on(c, rate, old_rate);
1594 return tegra12_cpu_clk_dfll_off(c, rate, old_rate);
1596 return tegra12_cpu_clk_set_plls(c, rate, old_rate);
1599 static long tegra12_cpu_clk_round_rate(struct clk *c, unsigned long rate)
1601 unsigned long max_rate = c->max_rate;
1603 /* Remove dfll boost to maximum rate when running on PLL */
1604 if (c->dvfs && !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
1605 max_rate -= c->dvfs->dfll_data.max_rate_boost;
1607 if (rate > max_rate)
1609 else if (rate < c->min_rate)
1614 static struct clk_ops tegra_cpu_ops = {
1615 .init = tegra12_cpu_clk_init,
1616 .enable = tegra12_cpu_clk_enable,
1617 .disable = tegra12_cpu_clk_disable,
1618 .set_rate = tegra12_cpu_clk_set_rate,
1619 .round_rate = tegra12_cpu_clk_round_rate,
1623 static void tegra12_cpu_cmplx_clk_init(struct clk *c)
1625 int i = !!is_lp_cluster();
1627 BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G);
1628 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
1629 BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP);
1631 c->parent = c->inputs[i].input;
1634 /* cpu complex clock provides second level vitualization (on top of
1635 cpu virtual cpu rate control) in order to hide the CPU mode switch
1637 #if PARAMETERIZE_CLUSTER_SWITCH
1638 static unsigned int switch_delay;
1639 static unsigned int switch_flags;
1640 static DEFINE_SPINLOCK(parameters_lock);
1642 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags)
1644 spin_lock(¶meters_lock);
1646 switch_flags = flags;
1647 spin_unlock(¶meters_lock);
1651 static int tegra12_cpu_cmplx_clk_enable(struct clk *c)
1656 static void tegra12_cpu_cmplx_clk_disable(struct clk *c)
1658 pr_debug("%s on clock %s\n", __func__, c->name);
1660 /* oops - don't disable the CPU complex clock! */
1664 static int tegra12_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate)
1666 unsigned long flags;
1668 struct clk *parent = c->parent;
1670 if (!parent->ops || !parent->ops->set_rate)
1673 clk_lock_save(parent, &flags);
1675 ret = clk_set_rate_locked(parent, rate);
1677 clk_unlock_restore(parent, &flags);
1682 static int tegra12_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
1685 unsigned int flags, delay;
1686 const struct clk_mux_sel *sel;
1687 unsigned long rate = clk_get_rate(c->parent);
1688 struct clk *dfll = c->parent->u.cpu.dynamic ? : p->u.cpu.dynamic;
1689 struct clk *p_source_old = NULL;
1690 struct clk *p_source;
1692 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1693 BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G));
1695 for (sel = c->inputs; sel->input != NULL; sel++) {
1696 if (sel->input == p)
1702 #if PARAMETERIZE_CLUSTER_SWITCH
1703 spin_lock(¶meters_lock);
1704 flags = switch_flags;
1705 delay = switch_delay;
1707 spin_unlock(¶meters_lock);
1710 /* over/under-clocking after switch - allow, but update rate */
1711 if ((rate > p->max_rate) || (rate < p->min_rate)) {
1712 rate = rate > p->max_rate ? p->max_rate : p->min_rate;
1713 ret = clk_set_rate(c->parent, rate);
1715 pr_err("%s: Failed to set rate %lu for %s\n",
1716 __func__, rate, p->name);
1723 if (rate > p->max_rate) { /* over-clocking - no switch */
1724 pr_warn("%s: No %s mode switch to %s at rate %lu\n",
1725 __func__, c->name, p->name, rate);
1728 flags = TEGRA_POWER_CLUSTER_IMMEDIATE;
1729 flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT;
1732 flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
1733 TEGRA_POWER_CLUSTER_G;
1735 if (p == c->parent) {
1736 if (flags & TEGRA_POWER_CLUSTER_FORCE) {
1737 /* Allow parameterized switch to the same mode */
1738 ret = tegra_cluster_control(delay, flags);
1740 pr_err("%s: Failed to force %s mode to %s\n",
1741 __func__, c->name, p->name);
1744 return 0; /* already switched - exit */
1747 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, true);
1748 if (c->parent->parent->parent == dfll) {
1749 /* G (DFLL selected as clock source) => LP switch:
1750 * turn DFLL into open loop mode ("release" VDD_CPU rail)
1751 * select target p_source for LP, and get its rate ready
1753 ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
1757 p_source = rate <= p->u.cpu.backup_rate ?
1758 p->u.cpu.backup : p->u.cpu.main;
1759 ret = clk_set_rate(p_source, rate);
1762 } else if ((p->parent->parent == dfll) ||
1763 (p->dvfs && tegra_dvfs_is_dfll_range(p->dvfs, rate))) {
1764 /* LP => G (DFLL selected as clock source) switch:
1765 * set DFLL rate ready (DFLL is still disabled)
1766 * (set target p_source as dfll, G source is already selected)
1769 ret = clk_set_rate(dfll,
1770 tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail) ? rate :
1771 max(rate, p->dvfs->dfll_data.use_dfll_rate_min));
1775 ret = tegra_dvfs_rail_dfll_mode_set_cold(tegra_cpu_rail, dfll);
1780 /* DFLL is not selected on either side of the switch:
1781 * set target p_source equal to current clock source
1783 p_source = c->parent->parent->parent;
1785 /* Switch new parent to target clock source if necessary */
1786 if (p->parent->parent != p_source) {
1787 clk_enable(p->parent->parent);
1788 clk_enable(p->parent);
1789 p_source_old = p->parent->parent;
1790 ret = clk_set_parent(p->parent, p_source);
1792 pr_err("%s: Failed to set parent %s for %s\n",
1793 __func__, p_source->name, p->name);
1798 /* Enabling new parent scales new mode voltage rail in advanvce
1799 before the switch happens (if p_source is DFLL: open loop mode) */
1803 /* switch CPU mode */
1804 ret = tegra_cluster_control(delay, flags);
1808 pr_err("%s: Failed to switch %s mode to %s\n",
1809 __func__, c->name, p->name);
1814 * Lock DFLL now (resume closed loop VDD_CPU control).
1815 * G CPU operations are resumed on DFLL if it was the last G CPU
1816 * clock source, or if resume rate is in DFLL usage range in case
1817 * when auto-switch between PLL and DFLL is enabled.
1819 if (p_source == dfll) {
1820 if (tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail)) {
1821 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1823 clk_set_rate(dfll, rate);
1824 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1825 tegra_dvfs_dfll_mode_set(p->dvfs, rate);
1829 /* Disabling old parent scales old mode voltage rail */
1831 clk_disable(c->parent);
1833 clk_disable(p->parent);
1834 clk_disable(p_source_old);
1839 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1843 /* Re-lock DFLL if necessary after aborted switch */
1844 if (c->parent->parent->parent == dfll) {
1845 clk_set_rate(dfll, rate);
1846 tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
1849 clk_disable(p->parent);
1850 clk_disable(p_source_old);
1852 tegra_dvfs_rail_mode_updating(tegra_cpu_rail, false);
1854 pr_err("%s: aborted switch from %s to %s\n",
1855 __func__, c->parent->name, p->name);
1859 static long tegra12_cpu_cmplx_round_rate(struct clk *c,
1862 return clk_round_rate(c->parent, rate);
1865 static struct clk_ops tegra_cpu_cmplx_ops = {
1866 .init = tegra12_cpu_cmplx_clk_init,
1867 .enable = tegra12_cpu_cmplx_clk_enable,
1868 .disable = tegra12_cpu_cmplx_clk_disable,
1869 .set_rate = tegra12_cpu_cmplx_clk_set_rate,
1870 .set_parent = tegra12_cpu_cmplx_clk_set_parent,
1871 .round_rate = tegra12_cpu_cmplx_round_rate,
1874 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
1875 * reset the COP block (i.e. AVP) */
1876 static void tegra12_cop_clk_reset(struct clk *c, bool assert)
1878 unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L;
1880 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
1881 clk_writel(1 << 1, reg);
1884 static struct clk_ops tegra_cop_ops = {
1885 .reset = tegra12_cop_clk_reset,
1888 /* bus clock functions */
1889 static DEFINE_SPINLOCK(bus_clk_lock);
1891 static int bus_set_div(struct clk *c, int div)
1894 unsigned long flags;
1896 if (!div || (div > (BUS_CLK_DIV_MASK + 1)))
1899 spin_lock_irqsave(&bus_clk_lock, flags);
1900 val = clk_readl(c->reg);
1901 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
1902 val |= (div - 1) << c->reg_shift;
1903 clk_writel(val, c->reg);
1905 spin_unlock_irqrestore(&bus_clk_lock, flags);
1910 static void tegra12_bus_clk_init(struct clk *c)
1912 u32 val = clk_readl(c->reg);
1913 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
1914 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
1918 static int tegra12_bus_clk_enable(struct clk *c)
1920 u32 val = clk_readl(c->reg);
1921 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
1922 clk_writel(val, c->reg);
1926 static void tegra12_bus_clk_disable(struct clk *c)
1928 u32 val = clk_readl(c->reg);
1929 val |= BUS_CLK_DISABLE << c->reg_shift;
1930 clk_writel(val, c->reg);
1933 static int tegra12_bus_clk_set_rate(struct clk *c, unsigned long rate)
1935 unsigned long parent_rate = clk_get_rate(c->parent);
1938 if (tegra_platform_is_qt())
1940 for (i = 1; i <= 4; i++) {
1941 if (rate >= parent_rate / i)
1942 return bus_set_div(c, i);
1947 static struct clk_ops tegra_bus_ops = {
1948 .init = tegra12_bus_clk_init,
1949 .enable = tegra12_bus_clk_enable,
1950 .disable = tegra12_bus_clk_disable,
1951 .set_rate = tegra12_bus_clk_set_rate,
1954 /* Virtual system bus complex clock is used to hide the sequence of
1955 changing sclk/hclk/pclk parents and dividers to configure requested
1956 sclk target rate. */
1957 static void tegra12_sbus_cmplx_init(struct clk *c)
1961 c->max_rate = c->parent->max_rate;
1962 c->min_rate = c->parent->min_rate;
1964 /* Threshold must be an exact proper factor of low range parent,
1965 and both low/high range parents have 7.1 fractional dividers */
1966 rate = clk_get_rate(c->u.system.sclk_low->parent);
1967 if (tegra_platform_is_qt())
1969 if (c->u.system.threshold) {
1970 BUG_ON(c->u.system.threshold > rate) ;
1971 BUG_ON((rate % c->u.system.threshold) != 0);
1973 BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71));
1974 BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71));
1977 /* This special sbus round function is implemented because:
1979 * (a) sbus complex clock source is selected automatically based on rate
1981 * (b) since sbus is a shared bus, and its frequency is set to the highest
1982 * enabled shared_bus_user clock, the target rate should be rounded up divider
1983 * ladder (if max limit allows it) - for pll_div and peripheral_div common is
1984 * rounding down - special case again.
1986 * Note that final rate is trimmed (not rounded up) to avoid spiraling up in
1987 * recursive calls. Lost 1Hz is added in tegra12_sbus_cmplx_set_rate before
1988 * actually setting divider rate.
1990 static long tegra12_sbus_cmplx_round_updown(struct clk *c, unsigned long rate,
1993 unsigned long round_rate;
1994 struct clk *new_parent;
1996 rate = max(rate, c->min_rate);
1998 new_parent = (rate <= c->u.system.threshold) ?
1999 c->u.system.sclk_low : c->u.system.sclk_high;
2001 round_rate = fixed_src_bus_round_updown(
2002 c, new_parent->parent, new_parent->flags, rate, up);
2004 if (new_parent == c->u.system.sclk_high) {
2005 /* Prevent oscillation across threshold */
2006 if (round_rate <= c->u.system.threshold)
2007 round_rate = c->u.system.threshold;
2012 static long tegra12_sbus_cmplx_round_rate(struct clk *c, unsigned long rate)
2014 return tegra12_sbus_cmplx_round_updown(c, rate, true);
2018 * FIXME: This limitation may have been relaxed on Tegra12.
2019 * This issue has to be visited again once the new limitation is clarified.
2021 * Limitations on SCLK/HCLK/PCLK dividers:
2022 * (A) H/w limitation:
2023 * if SCLK >= 60MHz, SCLK:PCLK >= 2
2024 * (B) S/w policy limitation, in addition to (A):
2025 * if any APB bus shared user request is enabled, HCLK:PCLK >= 2
2026 * Reason for (B): assuming APB bus shared user has requested X < 60MHz,
2027 * HCLK = PCLK = X, and new AHB user is coming on-line requesting Y >= 60MHz,
2028 * we can consider 2 paths depending on order of changing HCLK rate and
2030 * (i) HCLK:PCLK = X:X => Y:Y* => Y:Y/2, (*) violates rule (A)
2031 * (ii) HCLK:PCLK = X:X => X:X/2* => Y:Y/2, (*) under-clocks APB user
2032 * In this case we can not guarantee safe transition from HCLK:PCLK = 1:1
2033 * below 60MHz to HCLK rate above 60MHz without under-clocking APB user.
2034 * Hence, policy (B).
2036 * Note: when there are no request from APB users, path (ii) can be used to
2037 * increase HCLK above 60MHz, and HCLK:PCLK = 1:1 is allowed.
2040 #define SCLK_PCLK_UNITY_RATIO_RATE_MAX 60000000
2041 #define BUS_AHB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
2042 #define BUS_APB_DIV_MAX (BUS_CLK_DIV_MASK + 1UL)
2044 static int tegra12_sbus_cmplx_set_rate(struct clk *c, unsigned long rate)
2047 struct clk *new_parent;
2050 * Configure SCLK/HCLK/PCLK guranteed safe combination:
2051 * - select the appropriate sclk parent
2052 * - keep hclk at the same rate as sclk
2053 * - set pclk at 1:2 rate of hclk
2055 bus_set_div(c->u.system.pclk, 2);
2056 bus_set_div(c->u.system.hclk, 1);
2057 c->child_bus->child_bus->div = 2;
2058 c->child_bus->div = 1;
2060 if (rate == clk_get_rate_locked(c))
2063 new_parent = (rate <= c->u.system.threshold) ?
2064 c->u.system.sclk_low : c->u.system.sclk_high;
2066 ret = clk_set_rate(new_parent, rate + 1);
2068 pr_err("Failed to set sclk source %s to %lu\n",
2069 new_parent->name, rate);
2073 if (new_parent != clk_get_parent(c->parent)) {
2074 ret = clk_set_parent(c->parent, new_parent);
2076 pr_err("Failed to switch sclk source to %s\n",
2085 static int tegra12_clk_sbus_update(struct clk *bus)
2089 unsigned long s_rate, h_rate, p_rate, ceiling;
2090 struct clk *ahb, *apb;
2092 if (detach_shared_bus)
2095 s_rate = tegra12_clk_shared_bus_update(bus, &ahb, &apb, &ceiling);
2096 if (bus->override_rate)
2097 return clk_set_rate_locked(bus, s_rate);
2099 ahb = bus->child_bus;
2100 apb = ahb->child_bus;
2101 h_rate = ahb->u.shared_bus_user.rate;
2102 p_rate = apb->u.shared_bus_user.rate;
2103 p_requested = apb->refcnt > 1;
2105 /* Propagate ratio requirements up from PCLK to SCLK */
2107 h_rate = max(h_rate, p_rate * 2);
2108 s_rate = max(s_rate, h_rate);
2109 if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
2110 s_rate = max(s_rate, p_rate * 2);
2112 /* Propagate cap requirements down from SCLK to PCLK */
2113 s_rate = tegra12_clk_cap_shared_bus(bus, s_rate, ceiling);
2114 if (s_rate >= SCLK_PCLK_UNITY_RATIO_RATE_MAX)
2115 p_rate = min(p_rate, s_rate / 2);
2116 h_rate = min(h_rate, s_rate);
2118 p_rate = min(p_rate, h_rate / 2);
2121 /* Set new sclk rate in safe 1:1:2, rounded "up" configuration */
2122 ret = clk_set_rate_locked(bus, s_rate);
2126 /* Finally settle new bus divider values */
2127 s_rate = clk_get_rate_locked(bus);
2128 div = min(s_rate / h_rate, BUS_AHB_DIV_MAX);
2130 bus_set_div(bus->u.system.hclk, div);
2134 h_rate = clk_get_rate(bus->u.system.hclk);
2135 div = min(h_rate / p_rate, BUS_APB_DIV_MAX);
2137 bus_set_div(bus->u.system.pclk, div);
2144 static struct clk_ops tegra_sbus_cmplx_ops = {
2145 .init = tegra12_sbus_cmplx_init,
2146 .set_rate = tegra12_sbus_cmplx_set_rate,
2147 .round_rate = tegra12_sbus_cmplx_round_rate,
2148 .round_rate_updown = tegra12_sbus_cmplx_round_updown,
2149 .shared_bus_update = tegra12_clk_sbus_update,
2152 /* Blink output functions */
2154 static void tegra12_blink_clk_init(struct clk *c)
2158 val = pmc_readl(PMC_CTRL);
2159 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
2161 val = pmc_readl(c->reg);
2163 if (val & PMC_BLINK_TIMER_ENB) {
2164 unsigned int on_off;
2166 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
2167 PMC_BLINK_TIMER_DATA_ON_MASK;
2168 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
2169 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
2171 /* each tick in the blink timer is 4 32KHz clocks */
2172 c->div = on_off * 4;
2178 static int tegra12_blink_clk_enable(struct clk *c)
2182 val = pmc_readl(PMC_DPD_PADS_ORIDE);
2183 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
2185 val = pmc_readl(PMC_CTRL);
2186 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
2187 pmc_readl(PMC_CTRL);
2192 static void tegra12_blink_clk_disable(struct clk *c)
2196 val = pmc_readl(PMC_CTRL);
2197 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
2199 val = pmc_readl(PMC_DPD_PADS_ORIDE);
2200 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
2201 pmc_readl(PMC_DPD_PADS_ORIDE);
2204 static int tegra12_blink_clk_set_rate(struct clk *c, unsigned long rate)
2206 unsigned long parent_rate = clk_get_rate(c->parent);
2207 if (rate >= parent_rate) {
2209 pmc_writel(0, c->reg);
2211 unsigned int on_off;
2214 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
2215 c->div = on_off * 8;
2217 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
2218 PMC_BLINK_TIMER_DATA_ON_SHIFT;
2219 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
2220 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
2222 val |= PMC_BLINK_TIMER_ENB;
2223 pmc_writel(val, c->reg);
2230 static struct clk_ops tegra_blink_clk_ops = {
2231 .init = &tegra12_blink_clk_init,
2232 .enable = &tegra12_blink_clk_enable,
2233 .disable = &tegra12_blink_clk_disable,
2234 .set_rate = &tegra12_blink_clk_set_rate,
2238 static int tegra12_pll_clk_wait_for_lock(
2239 struct clk *c, u32 lock_reg, u32 lock_bits)
2241 #if USE_PLL_LOCK_BITS
2245 for (i = 0; i < (c->u.pll.lock_delay / PLL_PRE_LOCK_DELAY + 1); i++) {
2246 udelay(PLL_PRE_LOCK_DELAY);
2247 if (c->flags & PLLX)
2248 val = clk_readlx(lock_reg);
2250 val = clk_readl(lock_reg);
2252 if ((val & lock_bits) == lock_bits) {
2253 udelay(PLL_POST_LOCK_DELAY);
2258 /* PLLCX lock bits may fluctuate after the lock - do detailed reporting
2259 at debug level (phase lock bit happens to uniquely identify PLLCX) */
2260 if (lock_bits & PLLCX_BASE_PHASE_LOCK) {
2261 pr_debug("Timed out waiting %s locks: %s %s not set\n", c->name,
2262 val & PLL_BASE_LOCK ? "" : "frequency_lock",
2263 val & PLLCX_BASE_PHASE_LOCK ? "" : "phase_lock");
2264 pr_debug("base = 0x%x\n", val);
2265 if (c->flags & PLLX) {
2266 pr_debug("misc = 0x%x\n", clk_readlx(c->reg + PLL_MISC(c)));
2267 pr_debug("misc1 = 0x%x\n", clk_readlx(c->reg + PLL_MISCN(c, 1)));
2268 pr_debug("misc2 = 0x%x\n", clk_readlx(c->reg + PLL_MISCN(c, 2)));
2269 pr_debug("misc3 = 0x%x\n", clk_readlx(c->reg + PLL_MISCN(c, 3)));
2271 pr_debug("misc = 0x%x\n", clk_readl(c->reg + PLL_MISC(c)));
2272 pr_debug("misc1 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 1)));
2273 pr_debug("misc2 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 2)));
2274 pr_debug("misc3 = 0x%x\n", clk_readl(c->reg + PLL_MISCN(c, 3)));
2278 pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
2279 c->name, lock_reg, val);
2283 udelay(c->u.pll.lock_delay);
2287 static void usb_plls_hw_control_enable(u32 reg)
2289 u32 val = clk_readl(reg);
2290 val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
2291 val &= ~USB_PLLS_ENABLE_SWCTL;
2292 val |= USB_PLLS_SEQ_START_STATE;
2293 pll_writel_delay(val, reg);
2295 val |= USB_PLLS_SEQ_ENABLE;
2296 pll_writel_delay(val, reg);
2299 static void tegra12_utmi_param_configure(struct clk *c)
2303 unsigned long main_rate =
2304 clk_get_rate(c->parent->parent);
2306 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2307 if (main_rate == utmi_parameters[i].osc_frequency) {
2312 if (i >= ARRAY_SIZE(utmi_parameters)) {
2313 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
2317 reg = clk_readl(UTMIP_PLL_CFG2);
2319 /* Program UTMIP PLL stable and active counts */
2320 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2321 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2322 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
2323 utmi_parameters[i].stable_count);
2325 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2327 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
2328 utmi_parameters[i].active_delay_count);
2330 /* Remove power downs from UTMIP PLL control bits */
2331 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2332 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2333 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
2334 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2335 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2336 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2337 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
2338 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2340 clk_writel(reg, UTMIP_PLL_CFG2);
2342 /* Program UTMIP PLL delay and oscillator frequency counts */
2343 reg = clk_readl(UTMIP_PLL_CFG1);
2344 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2346 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
2347 utmi_parameters[i].enable_delay_count);
2349 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2350 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
2351 utmi_parameters[i].xtal_freq_count);
2353 /* Remove power downs from UTMIP PLL control bits */
2354 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2355 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
2356 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
2357 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2358 clk_writel(reg, UTMIP_PLL_CFG1);
2360 /* Setup HW control of UTMIPLL */
2361 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2362 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2363 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2364 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
2365 clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
2367 reg = clk_readl(UTMIP_PLL_CFG1);
2368 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2369 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2370 pll_writel_delay(reg, UTMIP_PLL_CFG1);
2372 /* Setup SW override of UTMIPLL assuming USB2.0
2373 ports are assigned to USB2 */
2374 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2375 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
2376 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2377 pll_writel_delay(reg, UTMIPLL_HW_PWRDN_CFG0);
2379 /* Enable HW control UTMIPLL */
2380 reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
2381 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2382 pll_writel_delay(reg, UTMIPLL_HW_PWRDN_CFG0);
2385 static void tegra12_pll_clk_init(struct clk *c)
2387 u32 val = clk_readl(c->reg + PLL_BASE);
2388 u32 divn_mask = c->flags & PLLD ?
2389 PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
2391 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2393 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
2394 const struct clk_pll_freq_table *sel;
2395 unsigned long input_rate = clk_get_rate(c->parent);
2396 c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
2398 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2399 if (sel->input_rate == input_rate &&
2400 sel->output_rate == c->u.pll.fixed_rate) {
2402 c->div = sel->m * sel->p;
2406 pr_err("Clock %s has unknown fixed frequency\n", c->name);
2408 } else if (val & PLL_BASE_BYPASS) {
2412 c->mul = (val & divn_mask) >> PLL_BASE_DIVN_SHIFT;
2413 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
2414 if (c->flags & PLLU)
2415 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
2417 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
2418 PLL_BASE_DIVP_SHIFT));
2421 if (c->flags & PLL_FIXED) {
2422 c->u.pll.fixed_rate = clk_get_rate_locked(c);
2425 if (c->flags & PLLU) {
2426 /* Configure UTMI PLL power management */
2427 tegra12_utmi_param_configure(c);
2429 /* Put PLLU under h/w control */
2430 usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
2432 val = clk_readl(c->reg + PLL_BASE);
2433 val &= ~PLLU_BASE_OVERRIDE;
2434 pll_writel_delay(val, c->reg + PLL_BASE);
2436 /* Set XUSB PLL pad pwr override and iddq */
2437 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
2438 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
2439 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
2440 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
2441 xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
2445 static int tegra12_pll_clk_enable(struct clk *c)
2448 pr_debug("%s on clock %s\n", __func__, c->name);
2450 #if USE_PLL_LOCK_BITS
2451 /* toggle lock enable bit to reset lock detection circuit (couple
2452 register reads provide enough duration for reset pulse) */
2453 val = clk_readl(c->reg + PLL_MISC(c));
2454 val &= ~PLL_MISC_LOCK_ENABLE(c);
2455 clk_writel(val, c->reg + PLL_MISC(c));
2456 val = clk_readl(c->reg + PLL_MISC(c));
2457 val = clk_readl(c->reg + PLL_MISC(c));
2458 val |= PLL_MISC_LOCK_ENABLE(c);
2459 clk_writel(val, c->reg + PLL_MISC(c));
2461 val = clk_readl(c->reg + PLL_BASE);
2462 val &= ~PLL_BASE_BYPASS;
2463 val |= PLL_BASE_ENABLE;
2464 clk_writel(val, c->reg + PLL_BASE);
2466 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
2471 static void tegra12_pll_clk_disable(struct clk *c)
2474 pr_debug("%s on clock %s\n", __func__, c->name);
2476 val = clk_readl(c->reg);
2477 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2478 if (tegra_platform_is_qt())
2480 clk_writel(val, c->reg);
2483 /* Special comparison frequency selection for PLLD at 12MHz refrence rate */
2484 unsigned long get_pll_cfreq_special(struct clk *c, unsigned long input_rate,
2485 unsigned long rate, unsigned long *vco)
2487 if (!(c->flags & PLLD) || (input_rate != 12000000))
2490 *vco = c->u.pll.vco_min;
2492 if (rate <= 250000000)
2494 else if (rate <= 500000000)
2500 /* Common comparison frequency selection */
2501 unsigned long get_pll_cfreq_common(struct clk *c, unsigned long input_rate,
2502 unsigned long rate, unsigned long *vco)
2504 unsigned long cfreq = 0;
2506 switch (input_rate) {
2509 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
2512 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
2516 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
2519 if (c->parent->flags & DIV_U71_FIXED) {
2520 /* PLLP_OUT1 rate is not in PLLA table */
2521 pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
2522 __func__, c->name, input_rate, rate);
2523 cfreq = input_rate/(input_rate/1000000);
2526 pr_err("%s: Unexpected reference rate %lu\n",
2527 __func__, input_rate);
2531 /* Raise VCO to guarantee 0.5% accuracy, and vco min boundary */
2532 *vco = max(200 * cfreq, c->u.pll.vco_min);
2536 static u8 get_pll_cpcon(struct clk *c, u16 n)
2538 if (c->flags & PLLD) {
2550 return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
2553 static int tegra12_pll_clk_set_rate(struct clk *c, unsigned long rate)
2555 u32 val, p_div, old_base;
2556 unsigned long input_rate;
2557 const struct clk_pll_freq_table *sel;
2558 struct clk_pll_freq_table cfg;
2559 u32 divn_mask = c->flags & PLLD ?
2560 PLLD_BASE_DIVN_MASK : PLL_BASE_DIVN_MASK;
2562 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
2564 if (tegra_platform_is_qt())
2566 if (c->flags & PLL_FIXED) {
2568 if (rate != c->u.pll.fixed_rate) {
2569 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
2570 __func__, c->name, c->u.pll.fixed_rate, rate);
2577 input_rate = clk_get_rate(c->parent);
2579 /* Check if the target rate is tabulated */
2580 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2581 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2582 if (c->flags & PLLU) {
2583 BUG_ON(sel->p < 1 || sel->p > 2);
2585 p_div = PLLU_BASE_POST_DIV;
2588 for (val = sel->p; val > 1; val >>= 1, p_div++);
2589 p_div <<= PLL_BASE_DIVP_SHIFT;
2595 /* Configure out-of-table rate */
2596 if (sel->input_rate == 0) {
2597 unsigned long cfreq, vco;
2598 BUG_ON(c->flags & PLLU);
2601 /* If available, use pll specific algorithm to select comparison
2602 frequency, and vco target */
2603 cfreq = get_pll_cfreq_special(c, input_rate, rate, &vco);
2605 cfreq = get_pll_cfreq_common(c, input_rate, rate, &vco);
2607 for (cfg.output_rate = rate; cfg.output_rate < vco; p_div++)
2608 cfg.output_rate <<= 1;
2610 cfg.p = 0x1 << p_div;
2611 cfg.m = input_rate / cfreq;
2612 cfg.n = cfg.output_rate / cfreq;
2613 cfg.cpcon = get_pll_cpcon(c, cfg.n);
2615 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
2616 (cfg.n > (divn_mask >> PLL_BASE_DIVN_SHIFT)) ||
2617 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
2618 (cfg.output_rate > c->u.pll.vco_max)) {
2619 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2620 __func__, c->name, rate);
2623 p_div <<= PLL_BASE_DIVP_SHIFT;
2627 c->div = sel->m * sel->p;
2629 old_base = val = clk_readl(c->reg + PLL_BASE);
2630 val &= ~(PLL_BASE_DIVM_MASK | divn_mask |
2631 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
2632 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
2633 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
2634 if (val == old_base)
2637 if (c->state == ON) {
2638 tegra12_pll_clk_disable(c);
2639 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2641 clk_writel(val, c->reg + PLL_BASE);
2643 if (c->flags & PLL_HAS_CPCON) {
2644 val = clk_readl(c->reg + PLL_MISC(c));
2645 val &= ~PLL_MISC_CPCON_MASK;
2646 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
2647 if (c->flags & (PLLU | PLLD)) {
2648 val &= ~PLL_MISC_LFCON_MASK;
2649 val |= PLLDU_LFCON << PLL_MISC_LFCON_SHIFT;
2651 clk_writel(val, c->reg + PLL_MISC(c));
2655 tegra12_pll_clk_enable(c);
2660 static struct clk_ops tegra_pll_ops = {
2661 .init = tegra12_pll_clk_init,
2662 .enable = tegra12_pll_clk_enable,
2663 .disable = tegra12_pll_clk_disable,
2664 .set_rate = tegra12_pll_clk_set_rate,
2667 static void tegra12_pllp_clk_init(struct clk *c)
2669 tegra12_pll_clk_init(c);
2670 tegra12_pllp_init_dependencies(c->u.pll.fixed_rate);
2673 #ifdef CONFIG_PM_SLEEP
2674 static void tegra12_pllp_clk_resume(struct clk *c)
2676 unsigned long rate = c->u.pll.fixed_rate;
2677 tegra12_pll_clk_init(c);
2678 BUG_ON(rate != c->u.pll.fixed_rate);
2682 static struct clk_ops tegra_pllp_ops = {
2683 .init = tegra12_pllp_clk_init,
2684 .enable = tegra12_pll_clk_enable,
2685 .disable = tegra12_pll_clk_disable,
2686 .set_rate = tegra12_pll_clk_set_rate,
2690 tegra12_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
2696 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
2697 mask = PLLD_BASE_CSI_CLKENABLE | PLLD_BASE_CSI_CLKSOURCE;
2698 reg = c->reg + PLL_BASE;
2700 case TEGRA_CLK_MIPI_CSI_OUT_ENB:
2701 mask = PLLD_BASE_CSI_CLKENABLE;
2702 clear = PLLD_BASE_CSI_CLKSOURCE;
2703 reg = c->reg + PLL_BASE;
2705 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
2706 mask = PLLD_MISC_DSI_CLKENABLE;
2707 reg = c->reg + PLL_MISC(c);
2709 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
2710 mask = PLLD_BASE_DSI_MUX_MASK;
2711 reg = c->reg + PLL_BASE;
2717 val = clk_readl(reg);
2723 clk_writel(val, reg);
2727 static struct clk_ops tegra_plld_ops = {
2728 .init = tegra12_pll_clk_init,
2729 .enable = tegra12_pll_clk_enable,
2730 .disable = tegra12_pll_clk_disable,
2731 .set_rate = tegra12_pll_clk_set_rate,
2732 .clk_cfg_ex = tegra12_plld_clk_cfg_ex,
2736 * Dynamic ramp PLLs:
2737 * PLLC2 and PLLC3 (PLLCX)
2738 * PLLX and PLLC (PLLXC)
2740 * When scaling PLLC and PLLX, dynamic ramp is allowed for any transition that
2741 * changes NDIV only. As a matter of policy we will make sure that switching
2742 * between output rates above VCO minimum is always dynamic. The pre-requisite
2743 * for the above guarantee is the following configuration convention:
2744 * - pll configured with fixed MDIV
2745 * - when output rate is above VCO minimum PDIV = 0 (p-value = 1)
2746 * Switching between output rates below VCO minimum may or may not be dynamic,
2747 * and switching across VCO minimum is never dynamic.
2749 * PLLC2 and PLLC3 in addition to dynamic ramp mechanism have also glitchless
2750 * output dividers. However dynamic ramp without overshoot is guaranteed only
2751 * when output divisor is less or equal 8.
2753 * Of course, dynamic ramp is applied provided PLL is already enabled.
2757 * Common configuration policy for dynamic ramp PLLs:
2758 * - always set fixed M-value based on the reference rate
2759 * - always set P-value value 1:1 for output rates above VCO minimum, and
2760 * choose minimum necessary P-value for output rates below VCO minimum
2761 * - calculate N-value based on selected M and P
2763 static int pll_dyn_ramp_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2764 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2771 p = DIV_ROUND_UP(c->u.pll.vco_min, rate);
2772 p = c->u.pll.round_p_to_pdiv(p, pdiv);
2773 if (IS_ERR_VALUE(p))
2776 cfg->m = PLL_FIXED_MDIV(c, input_rate);
2778 cfg->output_rate = rate * cfg->p;
2779 if (cfg->output_rate > c->u.pll.vco_max)
2780 cfg->output_rate = c->u.pll.vco_max;
2781 cfg->n = cfg->output_rate * cfg->m / input_rate;
2783 /* can use PLLCX N-divider field layout for all dynamic ramp PLLs */
2784 if (cfg->n > (PLLCX_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT))
2790 static int pll_dyn_ramp_find_cfg(struct clk *c, struct clk_pll_freq_table *cfg,
2791 unsigned long rate, unsigned long input_rate, u32 *pdiv)
2793 const struct clk_pll_freq_table *sel;
2795 /* Check if the target rate is tabulated */
2796 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
2797 if (sel->input_rate == input_rate && sel->output_rate == rate) {
2798 u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
2799 BUG_ON(IS_ERR_VALUE(p));
2800 BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
2806 /* Configure out-of-table rate */
2807 if (pll_dyn_ramp_cfg(c, cfg, rate, input_rate, pdiv)) {
2808 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
2809 __func__, c->name, rate);
2815 static inline void pll_do_iddq(struct clk *c, u32 offs, u32 iddq_bit, bool set)
2818 if (c->flags & PLLX)
2819 val = clk_readlx(c->reg + offs);
2821 val = clk_readl(c->reg + offs);
2828 if (c->flags & PLLX)
2829 clk_writelx_delay(val, c->reg + offs);
2831 clk_writel_delay(val, c->reg + offs);
2835 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
2836 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
2837 /* p: */ 1, 2, 3, 4, 6, 8, 12, 16 };
2839 static u32 pllcx_round_p_to_pdiv(u32 p, u32 *pdiv)
2844 for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
2845 /* Do not use DIV3 p values - mapped to even PDIV */
2846 if (i && ((i & 0x1) == 0))
2849 if (p <= pllcx_p[i]) {
2859 static void pllcx_update_dynamic_koef(struct clk *c, unsigned long input_rate,
2862 u32 val, n_threshold;
2864 switch (input_rate) {
2879 pr_err("%s: Unexpected reference rate %lu\n",
2880 __func__, input_rate);
2885 val = clk_readl(c->reg + PLL_MISC(c));
2886 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
2887 val |= n <= n_threshold ?
2888 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
2889 clk_writel(val, c->reg + PLL_MISC(c));
2892 static void pllcx_strobe(struct clk *c)
2894 u32 reg = c->reg + PLL_MISC(c);
2895 u32 val = clk_readl(reg);
2897 val |= PLLCX_MISC_STROBE;
2898 pll_writel_delay(val, reg);
2900 val &= ~PLLCX_MISC_STROBE;
2901 clk_writel(val, reg);
2904 static void pllcx_set_defaults(struct clk *c, unsigned long input_rate, u32 n)
2906 u32 misc1val = PLLCX_MISC1_DEFAULT_VALUE;
2909 misc1val |= PLLCX_MISC1_IDDQ;
2910 clk_writel(PLLCX_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
2911 clk_writel(misc1val, c->reg + PLL_MISCN(c, 1));
2912 clk_writel(PLLCX_MISC2_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 2));
2913 clk_writel(PLLCX_MISC3_DEFAULT_VALUE, c->reg + PLL_MISCN(c, 3));
2915 pllcx_update_dynamic_koef(c, input_rate, n);
2918 static void tegra12_pllcx_clk_init(struct clk *c)
2920 unsigned long input_rate = clk_get_rate(c->parent);
2923 /* clip vco_min to exact multiple of input rate to avoid crossover
2926 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
2927 c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllcx_p[PLLCX_PDIV_MAX]);
2929 val = clk_readl(c->reg + PLL_BASE);
2930 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
2933 * PLLCX is not a boot PLL, it should be left disabled by boot-loader,
2934 * and no enabled module clocks should use it as a source during clock
2937 BUG_ON(c->state == ON && !tegra_platform_is_linsim() &&
2938 !is_tegra_hypervisor_mode());
2940 * Most of PLLCX register fields are shadowed, and can not be read
2941 * directly from PLL h/w. Hence, actual PLLCX boot state is unknown.
2942 * Initialize PLL to default state: disabled, reset; shadow registers
2943 * loaded with default parameters; dividers are preset for half of
2944 * minimum VCO rate (the latter assured that shadowed divider settings
2945 * are within supported range).
2947 m = PLL_FIXED_MDIV(c, input_rate);
2948 n = m * c->u.pll.vco_min / input_rate;
2950 val = (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
2951 (1 << PLL_BASE_DIVP_SHIFT);
2952 clk_writel(val, c->reg + PLL_BASE); /* PLL disabled */
2954 pllcx_set_defaults(c, input_rate, n);
2960 static int tegra12_pllcx_clk_enable(struct clk *c)
2963 pr_debug("%s on clock %s\n", __func__, c->name);
2965 pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, false);
2967 val = clk_readl(c->reg + PLL_BASE);
2968 val &= ~PLL_BASE_BYPASS;
2969 val |= PLL_BASE_ENABLE;
2970 pll_writel_delay(val, c->reg + PLL_BASE);
2972 val = clk_readl(c->reg + PLL_MISC(c));
2973 val &= ~PLLCX_MISC_RESET;
2974 pll_writel_delay(val, c->reg + PLL_MISC(c));
2977 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
2978 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
2982 static void tegra12_pllcx_clk_disable(struct clk *c)
2985 pr_debug("%s on clock %s\n", __func__, c->name);
2987 val = clk_readl(c->reg);
2988 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
2989 clk_writel(val, c->reg);
2991 val = clk_readl(c->reg + PLL_MISC(c));
2992 val |= PLLCX_MISC_RESET;
2993 pll_writel_delay(val, c->reg + PLL_MISC(c));
2995 pll_do_iddq(c, PLL_MISCN(c, 1), PLLCX_MISC1_IDDQ, true);
2998 static int tegra12_pllcx_clk_set_rate(struct clk *c, unsigned long rate)
3001 unsigned long input_rate;
3002 struct clk_pll_freq_table cfg, old_cfg;
3003 const struct clk_pll_freq_table *sel = &cfg;
3005 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3006 if (tegra_platform_is_qt())
3009 input_rate = clk_get_rate(c->parent);
3011 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3015 c->div = sel->m * sel->p;
3017 val = clk_readl(c->reg + PLL_BASE);
3018 PLL_BASE_PARSE(PLLCX, old_cfg, val);
3019 old_cfg.p = pllcx_p[old_cfg.p];
3021 BUG_ON(old_cfg.m != sel->m);
3022 if ((sel->n == old_cfg.n) && (sel->p == old_cfg.p))
3025 #if PLLCX_USE_DYN_RAMP
3026 if (c->state == ON && ((sel->n == old_cfg.n) ||
3027 PLLCX_IS_DYN(sel->p, old_cfg.p))) {
3029 * Dynamic ramp if PLL is enabled, and M divider is unchanged:
3030 * - Change P divider 1st if intermediate rate is below either
3032 * - Change N divider with DFS strobe - target rate is either
3033 * final new rate or below old rate
3034 * - If divider has been changed, exit without waiting for lock.
3035 * Otherwise, wait for lock and change divider.
3037 if (sel->p > old_cfg.p) {
3038 val &= ~PLLCX_BASE_DIVP_MASK;
3039 val |= pdiv << PLL_BASE_DIVP_SHIFT;
3040 clk_writel(val, c->reg + PLL_BASE);
3043 if (sel->n != old_cfg.n) {
3044 pllcx_update_dynamic_koef(c, input_rate, sel->n);
3045 val &= ~PLLCX_BASE_DIVN_MASK;
3046 val |= sel->n << PLL_BASE_DIVN_SHIFT;
3047 pll_writel_delay(val, c->reg + PLL_BASE);
3050 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
3051 PLL_BASE_LOCK | PLLCX_BASE_PHASE_LOCK);
3054 if (sel->p < old_cfg.p) {
3055 val &= ~PLLCX_BASE_DIVP_MASK;
3056 val |= pdiv << PLL_BASE_DIVP_SHIFT;
3057 clk_writel(val, c->reg + PLL_BASE);
3063 val &= ~(PLLCX_BASE_DIVN_MASK | PLLCX_BASE_DIVP_MASK);
3064 val |= (sel->n << PLL_BASE_DIVN_SHIFT) |
3065 (pdiv << PLL_BASE_DIVP_SHIFT);
3067 if (c->state == ON) {
3068 tegra12_pllcx_clk_disable(c);
3069 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
3071 pllcx_update_dynamic_koef(c, input_rate, sel->n);
3072 clk_writel(val, c->reg + PLL_BASE);
3074 tegra12_pllcx_clk_enable(c);
3079 #ifdef CONFIG_PM_SLEEP
3080 static void tegra12_pllcx_clk_resume_enable(struct clk *c)
3082 unsigned long rate = clk_get_rate_all_locked(c->parent);
3083 u32 val = clk_readl(c->reg + PLL_BASE);
3084 enum clk_state state = c->state;
3086 if (val & PLL_BASE_ENABLE)
3087 return; /* already resumed */
3089 /* Restore input divider */
3090 val &= ~PLLCX_BASE_DIVM_MASK;
3091 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
3092 clk_writel(val, c->reg + PLL_BASE);
3094 /* temporarily sync h/w and s/w states, final sync happens
3095 in tegra_clk_resume later */
3097 pllcx_set_defaults(c, rate, c->mul);
3099 rate = clk_get_rate_all_locked(c);
3100 tegra12_pllcx_clk_set_rate(c, rate);
3101 tegra12_pllcx_clk_enable(c);
3106 static struct clk_ops tegra_pllcx_ops = {
3107 .init = tegra12_pllcx_clk_init,
3108 .enable = tegra12_pllcx_clk_enable,
3109 .disable = tegra12_pllcx_clk_disable,
3110 .set_rate = tegra12_pllcx_clk_set_rate,
3114 /* non-monotonic mapping below is not a typo */
3115 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
3116 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3117 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3119 static u32 pllxc_round_p_to_pdiv(u32 p, u32 *pdiv)
3121 if (!p || (p > PLLXC_SW_PDIV_MAX + 1))
3129 static void pllxc_get_dyn_steps(struct clk *c, unsigned long input_rate,
3130 u32 *step_a, u32 *step_b)
3132 switch (input_rate) {
3148 pr_err("%s: Unexpected reference rate %lu\n",
3149 __func__, input_rate);
3154 static void pllx_set_defaults(struct clk *c, unsigned long input_rate)
3159 /* Only s/w dyn ramp control is supported */
3160 val = clk_readlx(PLLX_HW_CTRL_CFG);
3161 BUG_ON(!(val & PLLX_HW_CTRL_CFG_SWCTRL) && !tegra_platform_is_linsim());
3163 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
3164 val = step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
3165 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
3167 /* Get ready dyn ramp state machine, disable lock override */
3168 clk_writelx(val, c->reg + PLL_MISCN(c, 2));
3170 /* Enable outputs to CPUs and configure lock */
3172 #if USE_PLL_LOCK_BITS
3173 val |= PLL_MISC_LOCK_ENABLE(c);
3175 clk_writelx(val, c->reg + PLL_MISC(c));
3177 /* Check/set IDDQ */
3178 val = clk_readlx(c->reg + PLL_MISCN(c, 3));
3179 if (c->state == ON) {
3180 BUG_ON(val & PLLX_MISC3_IDDQ && !tegra_platform_is_linsim());
3182 val |= PLLX_MISC3_IDDQ;
3183 clk_writelx(val, c->reg + PLL_MISCN(c, 3));
3187 static void pllc_set_defaults(struct clk *c, unsigned long input_rate)
3192 /* Get ready dyn ramp state machine */
3193 pllxc_get_dyn_steps(c, input_rate, &step_a, &step_b);
3194 val = step_a << PLLC_MISC1_DYNRAMP_STEPA_SHIFT;
3195 val |= step_b << PLLC_MISC1_DYNRAMP_STEPB_SHIFT;
3196 clk_writel(val, c->reg + PLL_MISCN(c, 1));
3198 /* Configure lock and check/set IDDQ */
3199 val = clk_readl(c->reg + PLL_BASE);
3200 val &= ~PLLC_BASE_LOCK_OVERRIDE;
3201 clk_writel(val, c->reg + PLL_BASE);
3203 val = clk_readl(c->reg + PLL_MISC(c));
3204 #if USE_PLL_LOCK_BITS
3205 val |= PLLC_MISC_LOCK_ENABLE;
3207 val &= ~PLLC_MISC_LOCK_ENABLE;
3209 clk_writel(val, c->reg + PLL_MISC(c));
3211 if (c->state == ON) {
3212 BUG_ON(val & PLLC_MISC_IDDQ && !tegra_platform_is_linsim());
3214 val |= PLLC_MISC_IDDQ;
3215 clk_writel(val, c->reg + PLL_MISC(c));
3219 static void tegra12_pllxc_clk_init(struct clk *c)
3221 unsigned long input_rate = clk_get_rate(c->parent);
3224 /* clip vco_min to exact multiple of input rate to avoid crossover
3227 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3229 DIV_ROUND_UP(c->u.pll.vco_min, pllxc_p[PLLXC_SW_PDIV_MAX]);
3231 if (c->flags & PLLX)
3232 val = clk_readlx(c->reg + PLL_BASE);
3234 val = clk_readl(c->reg + PLL_BASE);
3236 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3238 m = (val & PLLXC_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3239 p = (val & PLLXC_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3240 BUG_ON(p > PLLXC_PDIV_MAX);
3244 c->mul = (val & PLLXC_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3246 if (c->flags & PLLX)
3247 pllx_set_defaults(c, input_rate);
3249 pllc_set_defaults(c, input_rate);
3252 static int tegra12_pllxc_clk_enable(struct clk *c)
3255 pr_debug("%s on clock %s\n", __func__, c->name);
3257 if (c->flags & PLLX) {
3258 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, false);
3259 val = clk_readlx(c->reg + PLL_BASE);
3260 val |= PLL_BASE_ENABLE;
3261 clk_writelx(val, c->reg + PLL_BASE);
3263 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, false);
3264 val = clk_readl(c->reg + PLL_BASE);
3265 val |= PLL_BASE_ENABLE;
3266 clk_writel(val, c->reg + PLL_BASE);
3269 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
3274 static void tegra12_pllxc_clk_disable(struct clk *c)
3277 pr_debug("%s on clock %s\n", __func__, c->name);
3279 if (c->flags & PLLX) {
3280 val = clk_readlx(c->reg + PLL_BASE);
3281 val &= ~PLL_BASE_ENABLE;
3282 clk_writelx(val, c->reg + PLL_BASE);
3284 val = clk_readl(c->reg + PLL_BASE);
3285 val &= ~PLL_BASE_ENABLE;
3286 clk_writel(val, c->reg + PLL_BASE);
3289 if (c->flags & PLLX)
3290 pll_do_iddq(c, PLL_MISCN(c, 3), PLLX_MISC3_IDDQ, true);
3292 pll_do_iddq(c, PLL_MISC(c), PLLC_MISC_IDDQ, true);
3296 #define PLLXC_DYN_RAMP(pll_misc, reg) \
3298 u32 misc = clk_readl((reg)); \
3300 misc &= ~pll_misc##_NDIV_NEW_MASK; \
3301 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
3302 pll_writel_delay(misc, (reg)); \
3304 misc |= pll_misc##_EN_DYNRAMP; \
3305 clk_writel(misc, (reg)); \
3306 tegra12_pll_clk_wait_for_lock(c, (reg), \
3307 pll_misc##_DYNRAMP_DONE); \
3309 val &= ~PLLXC_BASE_DIVN_MASK; \
3310 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
3311 pll_writel_delay(val, c->reg + PLL_BASE); \
3313 misc &= ~pll_misc##_EN_DYNRAMP; \
3314 pll_writel_delay(misc, (reg)); \
3317 #define PLLX_DYN_RAMP(pll_misc, reg) \
3319 u32 misc = clk_readlx((reg)); \
3321 misc &= ~pll_misc##_NDIV_NEW_MASK; \
3322 misc |= sel->n << pll_misc##_NDIV_NEW_SHIFT; \
3323 pll_writelx_delay(misc, (reg)); \
3325 misc |= pll_misc##_EN_DYNRAMP; \
3326 clk_writelx(misc, (reg)); \
3327 tegra12_pll_clk_wait_for_lock(c, (reg), \
3328 pll_misc##_DYNRAMP_DONE); \
3330 val &= ~PLLXC_BASE_DIVN_MASK; \
3331 val |= sel->n << PLL_BASE_DIVN_SHIFT; \
3332 pll_writelx_delay(val, c->reg + PLL_BASE); \
3334 misc &= ~pll_misc##_EN_DYNRAMP; \
3335 pll_writelx_delay(misc, (reg)); \
3338 static int tegra12_pllxc_clk_set_rate(struct clk *c, unsigned long rate)
3341 unsigned long input_rate;
3342 struct clk_pll_freq_table cfg, old_cfg;
3343 const struct clk_pll_freq_table *sel = &cfg;
3345 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3346 if (tegra_platform_is_qt())
3349 input_rate = clk_get_rate(c->parent);
3351 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3355 c->div = sel->m * sel->p;
3357 if (c->flags & PLLX)
3358 val = clk_readlx(c->reg + PLL_BASE);
3360 val = clk_readl(c->reg + PLL_BASE);
3362 PLL_BASE_PARSE(PLLXC, old_cfg, val);
3363 old_cfg.p = pllxc_p[old_cfg.p];
3365 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
3366 (sel->p == old_cfg.p))
3369 #if PLLXC_USE_DYN_RAMP
3371 * Dynamic ramp can be used if M, P dividers are unchanged
3372 * (coveres superset of conventional dynamic ramps)
3374 if ((c->state == ON) && (sel->m == old_cfg.m) &&
3375 (sel->p == old_cfg.p)) {
3377 if (c->flags & PLLX) {
3378 u32 reg = c->reg + PLL_MISCN(c, 2);
3379 PLLX_DYN_RAMP(PLLX_MISC2, reg);
3381 u32 reg = c->reg + PLL_MISCN(c, 1);
3382 PLLXC_DYN_RAMP(PLLC_MISC1, reg);
3388 if (c->state == ON) {
3389 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3390 val &= ~PLL_BASE_ENABLE;
3391 if (c->flags & PLLX)
3392 pll_writelx_delay(val, c->reg + PLL_BASE);
3394 pll_writel_delay(val, c->reg + PLL_BASE);
3397 val &= ~(PLLXC_BASE_DIVM_MASK |
3398 PLLXC_BASE_DIVN_MASK | PLLXC_BASE_DIVP_MASK);
3399 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3400 (sel->n << PLL_BASE_DIVN_SHIFT) | (pdiv << PLL_BASE_DIVP_SHIFT);
3401 if (c->flags & PLLX)
3402 clk_writelx(val, c->reg + PLL_BASE);
3404 clk_writel(val, c->reg + PLL_BASE);
3406 if (c->state == ON) {
3407 val |= PLL_BASE_ENABLE;
3408 if (c->flags & PLLX)
3409 clk_writelx(val, c->reg + PLL_BASE);
3411 clk_writel(val, c->reg + PLL_BASE);
3412 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE,
3418 #ifdef CONFIG_PM_SLEEP
3419 static void tegra12_pllxc_clk_resume_enable(struct clk *c)
3421 unsigned long rate = clk_get_rate_all_locked(c->parent);
3422 enum clk_state state = c->state;
3424 if (c->flags & PLLX) {
3425 if (clk_readlx(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
3426 return; /* already resumed */
3428 if (clk_readl(c->reg + PLL_BASE) & PLL_BASE_ENABLE)
3429 return; /* already resumed */
3432 /* temporarily sync h/w and s/w states, final sync happens
3433 in tegra_clk_resume later */
3435 if (c->flags & PLLX)
3436 pllx_set_defaults(c, rate);
3438 pllc_set_defaults(c, rate);
3440 rate = clk_get_rate_all_locked(c);
3441 tegra12_pllxc_clk_set_rate(c, rate);
3442 tegra12_pllxc_clk_enable(c);
3447 static struct clk_ops tegra_pllxc_ops = {
3448 .init = tegra12_pllxc_clk_init,
3449 .enable = tegra12_pllxc_clk_enable,
3450 .disable = tegra12_pllxc_clk_disable,
3451 .set_rate = tegra12_pllxc_clk_set_rate,
3455 /* FIXME: pllm suspend/resume */
3457 /* non-monotonic mapping below is not a typo */
3458 static u8 pllm_p[PLLM_PDIV_MAX + 1] = {
3459 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3460 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3462 static u32 pllm_round_p_to_pdiv(u32 p, u32 *pdiv)
3464 if (!p || (p > PLLM_SW_PDIV_MAX + 1))
3472 static void pllm_set_defaults(struct clk *c, unsigned long input_rate)
3474 u32 val = clk_readl(c->reg + PLL_MISC(c));
3476 val &= ~PLLM_MISC_LOCK_OVERRIDE;
3477 #if USE_PLL_LOCK_BITS
3478 val &= ~PLLM_MISC_LOCK_DISABLE;
3480 val |= PLLM_MISC_LOCK_DISABLE;
3484 val |= PLLM_MISC_IDDQ;
3486 BUG_ON(val & PLLM_MISC_IDDQ && !tegra_platform_is_linsim());
3488 clk_writel(val, c->reg + PLL_MISC(c));
3491 static void tegra12_pllm_clk_init(struct clk *c)
3493 unsigned long input_rate = clk_get_rate(c->parent);
3496 /* clip vco_min to exact multiple of input rate to avoid crossover
3499 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3501 DIV_ROUND_UP(c->u.pll.vco_min, pllm_p[PLLM_SW_PDIV_MAX]);
3503 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3504 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3505 c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF;
3507 /* Tegra12 has bad default value of PMC_PLLM_WB0_OVERRIDE.
3508 * If bootloader does not initialize PLLM, kernel has to
3509 * initialize the register with sane value. */
3510 if (c->state == OFF) {
3511 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3512 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3513 if (m != PLL_FIXED_MDIV(c, input_rate)) {
3514 /* Copy DIVM and DIVN from PLLM_BASE */
3515 pr_info("%s: Fixing DIVM and DIVN\n", __func__);
3516 val = clk_readl(c->reg + PLL_BASE);
3517 val &= (PLLM_BASE_DIVM_MASK
3518 | PLLM_BASE_DIVN_MASK);
3519 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
3523 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3524 p = (val & PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) >>
3525 PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
3527 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3529 val = clk_readl(c->reg + PLL_BASE);
3530 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3531 p = (val & PLLM_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3534 m = (val & PLLM_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3535 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate)
3536 && tegra_platform_is_silicon());
3537 c->div = m * pllm_p[p];
3538 c->mul = (val & PLLM_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3540 pllm_set_defaults(c, input_rate);
3543 static int tegra12_pllm_clk_enable(struct clk *c)
3546 pr_debug("%s on clock %s\n", __func__, c->name);
3548 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, false);
3550 /* Just enable both base and override - one would work */
3551 val = clk_readl(c->reg + PLL_BASE);
3552 val |= PLL_BASE_ENABLE;
3553 clk_writel(val, c->reg + PLL_BASE);
3555 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3556 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3557 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3558 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3560 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
3564 static void tegra12_pllm_clk_disable(struct clk *c)
3567 pr_debug("%s on clock %s\n", __func__, c->name);
3569 /* Just disable both base and override - one would work */
3570 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3571 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
3572 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
3573 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3575 val = clk_readl(c->reg + PLL_BASE);
3576 val &= ~PLL_BASE_ENABLE;
3577 clk_writel(val, c->reg + PLL_BASE);
3579 pll_do_iddq(c, PLL_MISC(c), PLLM_MISC_IDDQ, true);
3582 static int tegra12_pllm_clk_set_rate(struct clk *c, unsigned long rate)
3585 unsigned long input_rate;
3586 struct clk_pll_freq_table cfg;
3587 const struct clk_pll_freq_table *sel = &cfg;
3589 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3591 if (c->state == ON) {
3592 if (rate != clk_get_rate_locked(c)) {
3593 pr_err("%s: Can not change memory %s rate in flight\n",
3600 input_rate = clk_get_rate(c->parent);
3602 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3606 c->div = sel->m * sel->p;
3608 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
3609 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
3610 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE_2);
3611 val &= ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK;
3612 val |= pdiv << PMC_PLLM_WB0_OVERRIDE_2_DIVP_SHIFT;
3613 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE_2);
3615 val = pmc_readl(PMC_PLLM_WB0_OVERRIDE);
3616 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK);
3617 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3618 (sel->n << PLL_BASE_DIVN_SHIFT);
3619 pmc_writel(val, PMC_PLLM_WB0_OVERRIDE);
3621 val = clk_readl(c->reg + PLL_BASE);
3622 val &= ~(PLLM_BASE_DIVM_MASK | PLLM_BASE_DIVN_MASK |
3623 PLLM_BASE_DIVP_MASK);
3624 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
3625 (sel->n << PLL_BASE_DIVN_SHIFT) |
3626 (pdiv << PLL_BASE_DIVP_SHIFT);
3627 clk_writel(val, c->reg + PLL_BASE);
3633 static struct clk_ops tegra_pllm_ops = {
3634 .init = tegra12_pllm_clk_init,
3635 .enable = tegra12_pllm_clk_enable,
3636 .disable = tegra12_pllm_clk_disable,
3637 .set_rate = tegra12_pllm_clk_set_rate,
3641 static u8 pllss_p[PLLSS_PDIV_MAX + 1] = {
3642 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3643 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3645 static u32 pllss_round_p_to_pdiv(u32 p, u32 *pdiv)
3647 if (!p || (p > PLLSS_SW_PDIV_MAX + 1))
3655 static void pllss_set_defaults(struct clk *c, unsigned long input_rate)
3659 clk_writel(PLLSS_MISC_DEFAULT_VALUE, c->reg + PLL_MISC(c));
3661 if (strcmp(c->name, "pll_dp") == 0) {
3662 clk_writel(PLLDP_SS_CFG_0_DEFAULT_VALUE, c->reg + PLLSS_CFG(c));
3663 clk_writel(PLLDP_SS_CTRL1_0_DEFAULT_VALUE, c->reg + PLLSS_CTRL1(c));
3664 clk_writel(PLLDP_SS_CTRL2_0_DEFAULT_VALUE, c->reg + PLLSS_CTRL2(c));
3666 clk_writel(PLLSS_CFG_DEFAULT_VALUE, c->reg + PLLSS_CFG(c));
3667 clk_writel(PLLSS_CTRL1_DEFAULT_VALUE, c->reg + PLLSS_CTRL1(c));
3668 clk_writel(PLLSS_CTRL2_DEFAULT_VALUE, c->reg + PLLSS_CTRL2(c));
3670 val = clk_readl(c->reg + PLL_MISC(c));
3671 val &= ~(PLLSS_MISC_KCP_MASK);
3672 val |= (c->u.pll.cpcon_default << PLLSS_MISC_KCP_SHIFT);
3673 #if USE_PLL_LOCK_BITS
3674 val |= PLLSS_MISC_LOCK_ENABLE;
3676 val &= ~PLLSS_MISC_LOCK_ENABLE;
3678 clk_writel(val, c->reg + PLL_MISC(c));
3680 val = clk_readl(c->reg + PLL_BASE);
3682 val |= PLLSS_BASE_IDDQ;
3684 BUG_ON(val & PLLSS_BASE_IDDQ && !tegra_platform_is_linsim());
3685 val &= ~PLLSS_BASE_LOCK_OVERRIDE;
3686 clk_writel(val, c->reg + PLL_BASE);
3689 static void tegra12_pllss_clk_init(struct clk *c)
3691 unsigned long input_rate;
3692 u32 m, n, p_div, val;
3694 val = clk_readl(c->reg + PLL_BASE);
3695 BUG_ON(((val & PLLSS_BASE_SOURCE_MASK)
3696 >> PLLSS_BASE_SOURCE_SHIFT) != 0);
3698 input_rate = clk_get_rate(c->parent);
3700 /* clip vco_min to exact multiple of input rate to avoid crossover
3703 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3705 DIV_ROUND_UP(c->u.pll.vco_min, pllss_p[PLLSS_SW_PDIV_MAX]);
3707 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3709 if (c->state == OFF){
3710 /* Reset default value of those PLLs are not safe.
3711 For example, they cause problem in LP0 resume.
3712 Replace them here with the safe value. */
3713 m = PLL_FIXED_MDIV(c, input_rate);
3714 n = c->u.pll.vco_min / input_rate * m;
3715 p_div = PLLSS_SW_PDIV_MAX;
3716 val &= ~PLLSS_BASE_DIVM_MASK;
3717 val &= ~PLLSS_BASE_DIVN_MASK;
3718 val &= ~PLLSS_BASE_DIVP_MASK;
3719 val |= m << PLL_BASE_DIVM_SHIFT;
3720 val |= n << PLL_BASE_DIVN_SHIFT;
3721 val |= p_div << PLL_BASE_DIVP_SHIFT;
3722 clk_writel(val, c->reg + PLL_BASE);
3724 pllss_set_defaults(c, input_rate);
3726 pr_info("%s was initialized by BootLoader\n", c->name);
3728 m = (val & PLLSS_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3729 n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3730 p_div = (val & PLLSS_BASE_DIVP_MASK) >> PLL_BASE_DIVP_SHIFT;
3732 c->div = m * pllss_p[p_div];
3735 pr_debug("%s: val=%08x m=%d n=%d p_div=%d input_rate=%lu\n",
3736 c->name, val, m, n, p_div, input_rate);
3740 static int tegra12_pllss_clk_enable(struct clk *c)
3743 pr_debug("%s on clock %s\n", __func__, c->name);
3745 pll_do_iddq(c, PLL_BASE, PLLSS_BASE_IDDQ, false);
3747 val = clk_readl(c->reg + PLL_BASE);
3748 val |= PLL_BASE_ENABLE;
3749 clk_writel(val, c->reg + PLL_BASE);
3751 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLLSS_BASE_LOCK);
3755 static void tegra12_pllss_clk_disable(struct clk *c)
3758 pr_debug("%s on clock %s\n", __func__, c->name);
3760 val = clk_readl(c->reg + PLL_BASE);
3761 val &= ~PLL_BASE_ENABLE;
3762 clk_writel(val, c->reg + PLL_BASE);
3764 pll_do_iddq(c, PLL_BASE, PLLSS_BASE_IDDQ, true);
3767 static int tegra12_pllss_clk_set_rate(struct clk *c, unsigned long rate)
3769 u32 val, pdiv, old_base;
3770 unsigned long input_rate;
3771 struct clk_pll_freq_table cfg, old_cfg;
3772 const struct clk_pll_freq_table *sel = &cfg;
3774 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3775 if (tegra_platform_is_qt())
3778 input_rate = clk_get_rate(c->parent);
3780 if (pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, &pdiv))
3784 c->div = sel->m * sel->p;
3786 val = clk_readl(c->reg + PLL_BASE);
3787 PLL_BASE_PARSE(PLLSS, old_cfg, val);
3788 old_cfg.p = pllss_p[old_cfg.p];
3790 if ((sel->m == old_cfg.m) && (sel->n == old_cfg.n) &&
3791 (sel->p == old_cfg.p))
3794 val = old_base = clk_readl(c->reg + PLL_BASE);
3795 val &= ~(PLLSS_BASE_DIVM_MASK
3796 | PLLSS_BASE_DIVN_MASK | PLLSS_BASE_DIVP_MASK);
3797 val |= (sel->m << PLL_BASE_DIVM_SHIFT)
3798 | (sel->n << PLL_BASE_DIVN_SHIFT)
3799 | (pdiv << PLL_BASE_DIVP_SHIFT);
3801 if (val == old_base)
3804 if (c->state == ON) {
3805 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3806 val &= ~PLL_BASE_ENABLE;
3807 old_base &= ~PLL_BASE_ENABLE;
3808 pll_writel_delay(old_base, c->reg + PLL_BASE);
3811 clk_writel(val, c->reg + PLL_BASE);
3813 if (c->state == ON) {
3814 val |= PLL_BASE_ENABLE;
3815 clk_writel(val, c->reg + PLL_BASE);
3816 tegra12_pll_clk_wait_for_lock(
3817 c, c->reg + PLL_BASE, PLLSS_BASE_LOCK);
3822 #ifdef CONFIG_PM_SLEEP
3823 static void tegra12_pllss_clk_resume_enable(struct clk *c)
3825 unsigned long rate = clk_get_rate_all_locked(c->parent);
3826 u32 val = clk_readl(c->reg + PLL_BASE);
3827 enum clk_state state = c->state;
3829 if (val & PLL_BASE_ENABLE)
3830 return; /* already resumed */
3832 /* Restore input divider */
3833 val &= ~PLLSS_BASE_DIVM_MASK;
3834 val |= PLL_FIXED_MDIV(c, rate) << PLL_BASE_DIVM_SHIFT;
3835 clk_writel(val, c->reg + PLL_BASE);
3837 /* temporarily sync h/w and s/w states, final sync happens
3838 in tegra_clk_resume later */
3840 pllss_set_defaults(c, rate);
3842 rate = clk_get_rate_all_locked(c);
3843 tegra12_pllss_clk_set_rate(c, rate);
3844 tegra12_pllss_clk_enable(c);
3849 static struct clk_ops tegra_pllss_ops = {
3850 .init = tegra12_pllss_clk_init,
3851 .enable = tegra12_pllss_clk_enable,
3852 .disable = tegra12_pllss_clk_disable,
3853 .set_rate = tegra12_pllss_clk_set_rate,
3854 /* s/w policy, no set_parent, always use tegra_pll_ref */
3857 /* non-monotonic mapping below is not a typo */
3858 static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
3859 /* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
3860 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
3862 static u32 pllre_round_p_to_pdiv(u32 p, u32 *pdiv)
3864 if (!p || (p > PLLRE_SW_PDIV_MAX + 1))
3872 static void pllre_set_defaults(struct clk *c, unsigned long input_rate)
3874 u32 val = clk_readl(c->reg + PLL_MISC(c));
3876 val &= ~PLLRE_MISC_LOCK_OVERRIDE;
3877 #if USE_PLL_LOCK_BITS
3878 val |= PLLRE_MISC_LOCK_ENABLE;
3880 val &= ~PLLRE_MISC_LOCK_ENABLE;
3884 val |= PLLRE_MISC_IDDQ;
3886 BUG_ON(val & PLLRE_MISC_IDDQ && !tegra_platform_is_linsim());
3888 clk_writel(val, c->reg + PLL_MISC(c));
3891 static void tegra12_pllre_clk_init(struct clk *c)
3893 unsigned long input_rate = clk_get_rate(c->parent);
3896 /* clip vco_min to exact multiple of input rate to avoid crossover
3899 DIV_ROUND_UP(c->u.pll.vco_min, input_rate) * input_rate;
3900 c->min_rate = c->u.pll.vco_min;
3902 val = clk_readl(c->reg + PLL_BASE);
3903 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
3906 /* overwrite h/w por state with min setting */
3907 m = PLL_FIXED_MDIV(c, input_rate);
3908 val = (m << PLL_BASE_DIVM_SHIFT) |
3909 (c->min_rate / input_rate << PLL_BASE_DIVN_SHIFT);
3910 clk_writel(val, c->reg + PLL_BASE);
3913 m = (val & PLLRE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
3914 BUG_ON(m != PLL_FIXED_MDIV(c, input_rate));
3917 c->mul = (val & PLLRE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
3919 pllre_set_defaults(c, input_rate);
3922 static int tegra12_pllre_clk_enable(struct clk *c)
3925 pr_debug("%s on clock %s\n", __func__, c->name);
3927 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, false);
3929 val = clk_readl(c->reg + PLL_BASE);
3930 val |= PLL_BASE_ENABLE;
3931 clk_writel(val, c->reg + PLL_BASE);
3933 tegra12_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3937 static void tegra12_pllre_clk_disable(struct clk *c)
3940 pr_debug("%s on clock %s\n", __func__, c->name);
3942 val = clk_readl(c->reg + PLL_BASE);
3943 val &= ~PLL_BASE_ENABLE;
3944 clk_writel(val, c->reg + PLL_BASE);
3946 pll_do_iddq(c, PLL_MISC(c), PLLRE_MISC_IDDQ, true);
3949 static int tegra12_pllre_clk_set_rate(struct clk *c, unsigned long rate)
3952 unsigned long input_rate;
3953 struct clk_pll_freq_table cfg;
3955 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
3957 if (rate < c->min_rate) {
3958 pr_err("%s: Failed to set %s rate %lu\n",
3959 __func__, c->name, rate);
3963 input_rate = clk_get_rate(c->parent);
3964 cfg.m = PLL_FIXED_MDIV(c, input_rate);
3965 cfg.n = rate * cfg.m / input_rate;
3970 val = old_base = clk_readl(c->reg + PLL_BASE);
3971 val &= ~(PLLRE_BASE_DIVM_MASK | PLLRE_BASE_DIVN_MASK);
3972 val |= (cfg.m << PLL_BASE_DIVM_SHIFT) | (cfg.n << PLL_BASE_DIVN_SHIFT);
3973 if (val == old_base)
3976 if (c->state == ON) {
3977 /* Use "ENABLE" pulse without placing PLL into IDDQ */
3978 val &= ~PLL_BASE_ENABLE;
3979 old_base &= ~PLL_BASE_ENABLE;
3980 pll_writel_delay(old_base, c->reg + PLL_BASE);
3983 clk_writel(val, c->reg + PLL_BASE);
3985 if (c->state == ON) {
3986 val |= PLL_BASE_ENABLE;
3987 clk_writel(val, c->reg + PLL_BASE);
3988 tegra12_pll_clk_wait_for_lock(
3989 c, c->reg + PLL_MISC(c), PLLRE_MISC_LOCK);
3994 static struct clk_ops tegra_pllre_ops = {
3995 .init = tegra12_pllre_clk_init,
3996 .enable = tegra12_pllre_clk_enable,
3997 .disable = tegra12_pllre_clk_disable,
3998 .set_rate = tegra12_pllre_clk_set_rate,
4001 static void tegra12_pllre_out_clk_init(struct clk *c)
4005 val = clk_readl(c->reg);
4006 p = (val & PLLRE_BASE_DIVP_MASK) >> PLLRE_BASE_DIVP_SHIFT;
4007 BUG_ON(p > PLLRE_PDIV_MAX);
4012 c->state = c->parent->state;
4015 static int tegra12_pllre_out_clk_enable(struct clk *c)
4020 static void tegra12_pllre_out_clk_disable(struct clk *c)
4024 static int tegra12_pllre_out_clk_set_rate(struct clk *c, unsigned long rate)
4027 unsigned long input_rate, flags;
4029 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4031 clk_lock_save(c->parent, &flags);
4032 input_rate = clk_get_rate_locked(c->parent);
4034 p = DIV_ROUND_UP(input_rate, rate);
4035 p = c->parent->u.pll.round_p_to_pdiv(p, &pdiv);
4036 if (IS_ERR_VALUE(p)) {
4037 pr_err("%s: Failed to set %s rate %lu\n",
4038 __func__, c->name, rate);
4039 clk_unlock_restore(c->parent, &flags);
4044 val = clk_readl(c->reg);
4045 val &= ~PLLRE_BASE_DIVP_MASK;
4046 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
4047 clk_writel(val, c->reg);
4049 clk_unlock_restore(c->parent, &flags);
4053 static struct clk_ops tegra_pllre_out_ops = {
4054 .init = tegra12_pllre_out_clk_init,
4055 .enable = tegra12_pllre_out_clk_enable,
4056 .disable = tegra12_pllre_out_clk_disable,
4057 .set_rate = tegra12_pllre_out_clk_set_rate,
4060 #ifdef CONFIG_PM_SLEEP
4061 /* Resume both pllre_vco and pllre_out */
4062 static void tegra12_pllre_clk_resume_enable(struct clk *c)
4065 u32 val = clk_readl(c->reg + PLL_BASE);
4066 unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
4067 enum clk_state state = c->parent->state;
4069 if (val & PLL_BASE_ENABLE)
4070 return; /* already resumed */
4072 /* temporarily sync h/w and s/w states, final sync happens
4073 in tegra_clk_resume later */
4074 c->parent->state = OFF;
4075 pllre_set_defaults(c->parent, rate);
4077 /* restore PLLRE VCO feedback loop (m, n) */
4078 rate = clk_get_rate_all_locked(c->parent);
4079 tegra12_pllre_clk_set_rate(c->parent, rate);
4081 /* restore PLLRE post-divider */
4082 c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
4083 val = clk_readl(c->reg);
4084 val &= ~PLLRE_BASE_DIVP_MASK;
4085 val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
4086 clk_writel(val, c->reg);
4088 tegra12_pllre_clk_enable(c->parent);
4089 c->parent->state = state;
4093 /* non-monotonic mapping below is not a typo */
4094 static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
4095 /* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
4096 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
4098 static inline void select_pll_e_input(u32 aux_reg)
4100 #if USE_PLLE_INPUT_PLLRE
4101 aux_reg |= PLLE_AUX_PLLRE_SEL;
4103 aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
4105 clk_writel(aux_reg, PLLE_AUX);
4108 static void tegra12_plle_clk_init(struct clk *c)
4111 struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
4112 struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
4113 struct clk *pllp = tegra_get_clock_by_name("pllp");
4114 #if USE_PLLE_INPUT_PLLRE
4115 struct clk *ref = re_vco;
4117 struct clk *ref = pll_ref;
4120 val = clk_readl(c->reg + PLL_BASE);
4121 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
4122 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
4123 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
4124 p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
4125 c->div *= plle_p[p];
4127 val = clk_readl(PLLE_AUX);
4128 c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
4129 (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
4130 if (c->parent != ref) {
4131 if (c->state == ON) {
4132 WARN(1, "%s: pll_e is left enabled with %s input\n",
4133 __func__, c->parent->name);
4136 select_pll_e_input(val);
4141 static void tegra12_plle_clk_disable(struct clk *c)
4144 pr_debug("%s on clock %s\n", __func__, c->name);
4146 /* FIXME: do we need to restore other s/w controls ? */
4147 val = clk_readl(c->reg + PLL_BASE);
4148 val &= ~PLL_BASE_ENABLE;
4149 clk_writel(val, c->reg + PLL_BASE);
4151 val = clk_readl(c->reg + PLL_MISC(c));
4152 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
4153 pll_writel_delay(val, c->reg + PLL_MISC(c));
4155 /* Set XUSB PLL pad pwr override and iddq */
4156 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4157 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
4158 val |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
4159 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4160 xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4163 static int tegra12_plle_clk_enable(struct clk *c)
4166 const struct clk_pll_freq_table *sel;
4167 unsigned long rate = c->u.pll.fixed_rate;
4168 unsigned long input_rate = clk_get_rate(c->parent);
4170 if (c->state == ON) {
4171 /* BL left plle enabled - don't change configuartion */
4172 pr_warn("%s: pll_e is already enabled\n", __func__);
4176 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
4177 if (sel->input_rate == input_rate && sel->output_rate == rate)
4181 if (sel->input_rate == 0) {
4182 pr_err("%s: %s input rate %lu is out-of-table\n",
4183 __func__, c->name, input_rate);
4187 /* setup locking configuration, s/w control of IDDQ and enable modes,
4188 take pll out of IDDQ via s/w control, setup VREG */
4189 val = clk_readl(c->reg + PLL_BASE);
4190 val &= ~PLLE_BASE_LOCK_OVERRIDE;
4191 clk_writel(val, c->reg + PLL_BASE);
4193 val = clk_readl(c->reg + PLL_MISC(c));
4194 val |= PLLE_MISC_LOCK_ENABLE;
4195 val |= PLLE_MISC_IDDQ_SW_CTRL;
4196 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
4197 val |= PLLE_MISC_PLLE_PTS;
4198 clk_writel(val, c->reg + PLL_MISC(c));
4201 /* configure dividers, disable SS */
4202 val = clk_readl(PLLE_SS_CTRL);
4203 val |= PLLE_SS_DISABLE;
4204 clk_writel(val, PLLE_SS_CTRL);
4206 val = clk_readl(c->reg + PLL_BASE);
4207 val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
4208 PLLE_BASE_DIVCML_MASK);
4209 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
4210 (sel->n << PLL_BASE_DIVN_SHIFT) |
4211 (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
4212 pll_writel_delay(val, c->reg + PLL_BASE);
4214 c->div = sel->m * sel->p;
4216 /* enable and lock pll */
4217 val |= PLL_BASE_ENABLE;
4218 clk_writel(val, c->reg + PLL_BASE);
4219 tegra12_pll_clk_wait_for_lock(
4220 c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
4222 val = clk_readl(PLLE_SS_CTRL);
4223 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
4224 val &= ~PLLE_SS_COEFFICIENTS_MASK;
4225 val |= PLLE_SS_COEFFICIENTS_VAL;
4226 clk_writel(val, PLLE_SS_CTRL);
4227 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
4228 pll_writel_delay(val, PLLE_SS_CTRL);
4229 val &= ~PLLE_SS_CNTL_INTERP_RESET;
4230 pll_writel_delay(val, PLLE_SS_CTRL);
4233 /* switch pll under h/w control */
4234 val = clk_readl(c->reg + PLL_MISC(c));
4235 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
4236 clk_writel(val, c->reg + PLL_MISC(c));
4238 val = clk_readl(PLLE_AUX);
4239 val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
4240 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
4241 pll_writel_delay(val, PLLE_AUX);
4242 val |= PLLE_AUX_SEQ_ENABLE;
4243 pll_writel_delay(val, PLLE_AUX);
4246 /* clear XUSB PLL pad pwr override and iddq */
4247 val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4248 val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_PWR_OVRD;
4249 val &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0_PLL_IDDQ;
4250 xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4251 xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL_P0_CTL1_0);
4253 /* enable hw control of xusb brick pll */
4254 usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
4259 #ifdef CONFIG_PM_SLEEP
4260 static void tegra12_plle_clk_resume(struct clk *c)
4262 u32 val = clk_readl(c->reg + PLL_BASE);
4263 if (val & PLL_BASE_ENABLE)
4264 return; /* already resumed */
4266 /* Restore parent */
4267 val = clk_readl(PLLE_AUX);
4268 select_pll_e_input(val);
4272 static struct clk_ops tegra_plle_ops = {
4273 .init = tegra12_plle_clk_init,
4274 .enable = tegra12_plle_clk_enable,
4275 .disable = tegra12_plle_clk_disable,
4279 * Tegra12 includes dynamic frequency lock loop (DFLL) with automatic voltage
4280 * control as possible CPU clock source. It is included in the Tegra12 clock
4281 * tree as "complex PLL" with standard Tegra clock framework APIs. However,
4282 * DFLL locking logic h/w access APIs are separated in the tegra_cl_dvfs.c
4283 * module. Hence, DFLL operations, with the exception of initialization, are
4284 * basically cl-dvfs wrappers.
4287 /* DFLL operations */
4288 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
4289 static void tune_cpu_trimmers(bool trim_high)
4291 tegra_soctherm_adjust_cpu_zone(trim_high);
4295 static void __init tegra12_dfll_clk_init(struct clk *c)
4297 c->ops->init = tegra12_dfll_cpu_late_init;
4300 static int tegra12_dfll_clk_enable(struct clk *c)
4302 return tegra_cl_dvfs_enable(c->u.dfll.cl_dvfs);
4305 static void tegra12_dfll_clk_disable(struct clk *c)
4307 tegra_cl_dvfs_disable(c->u.dfll.cl_dvfs);
4310 static int tegra12_dfll_clk_set_rate(struct clk *c, unsigned long rate)
4312 int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate);
4315 c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs);
4320 static void tegra12_dfll_clk_reset(struct clk *c, bool assert)
4322 u32 val = assert ? DFLL_BASE_RESET : 0;
4323 clk_writelx_delay(val, c->reg);
4327 tegra12_dfll_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
4329 if (p == TEGRA_CLK_DFLL_LOCK)
4330 return setting ? tegra_cl_dvfs_lock(c->u.dfll.cl_dvfs) :
4331 tegra_cl_dvfs_unlock(c->u.dfll.cl_dvfs);
4335 #ifdef CONFIG_PM_SLEEP
4336 static void tegra12_dfll_clk_resume(struct clk *c)
4338 if (!(clk_readlx(c->reg) & DFLL_BASE_RESET))
4339 return; /* already resumed */
4341 if (c->state != UNINITIALIZED) {
4342 tegra_periph_reset_deassert(c);
4343 tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
4348 static struct clk_ops tegra_dfll_ops = {
4349 .init = tegra12_dfll_clk_init,
4350 .enable = tegra12_dfll_clk_enable,
4351 .disable = tegra12_dfll_clk_disable,
4352 .set_rate = tegra12_dfll_clk_set_rate,
4353 .reset = tegra12_dfll_clk_reset,
4354 .clk_cfg_ex = tegra12_dfll_clk_cfg_ex,
4357 /* DFLL sysfs interface */
4358 static int tegra12_use_dfll_cb(const char *arg, const struct kernel_param *kp)
4361 unsigned long c_flags, p_flags;
4362 unsigned int old_use_dfll;
4363 struct clk *c = tegra_get_clock_by_name("cpu");
4364 struct clk *dfll = tegra_get_clock_by_name("dfll_cpu");
4366 if (!c->parent || !c->parent->dvfs || !dfll)
4369 ret = tegra_cpu_reg_mode_force_normal(true);
4371 pr_err("%s: Failed to force regulator normal mode\n", __func__);
4375 clk_lock_save(c, &c_flags);
4376 if (dfll->state == UNINITIALIZED) {
4377 pr_err("%s: DFLL is not initialized\n", __func__);
4378 clk_unlock_restore(c, &c_flags);
4379 tegra_cpu_reg_mode_force_normal(false);
4382 if (c->parent->u.cpu.mode == MODE_LP) {
4383 pr_err("%s: DFLL is not used on LP CPU\n", __func__);
4384 clk_unlock_restore(c, &c_flags);
4385 tegra_cpu_reg_mode_force_normal(false);
4389 clk_lock_save(c->parent, &p_flags);
4390 old_use_dfll = use_dfll;
4391 param_set_int(arg, kp);
4393 if (use_dfll != old_use_dfll) {
4394 ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
4396 use_dfll = old_use_dfll;
4398 ret = clk_set_rate_locked(c->parent,
4399 clk_get_rate_locked(c->parent));
4401 use_dfll = old_use_dfll;
4402 tegra_dvfs_set_dfll_range(
4403 c->parent->dvfs, use_dfll);
4407 clk_unlock_restore(c->parent, &p_flags);
4408 clk_unlock_restore(c, &c_flags);
4409 tegra_update_cpu_edp_limits();
4413 static struct kernel_param_ops tegra12_use_dfll_ops = {
4414 .set = tegra12_use_dfll_cb,
4415 .get = param_get_int,
4417 module_param_cb(use_dfll, &tegra12_use_dfll_ops, &use_dfll, 0644);
4420 /* Clock divider ops (non-atomic shared register access) */
4421 static DEFINE_SPINLOCK(pll_div_lock);
4423 static int tegra12_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
4424 static void tegra12_pll_div_clk_init(struct clk *c)
4426 if (c->flags & DIV_U71) {
4428 if (c->parent->state == OFF)
4431 val = clk_readl(c->reg);
4432 val >>= c->reg_shift;
4433 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
4434 if (!(val & PLL_OUT_RESET_DISABLE))
4437 if (c->u.pll_div.default_rate) {
4438 int ret = tegra12_pll_div_clk_set_rate(
4439 c, c->u.pll_div.default_rate);
4443 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
4444 c->div = (divu71 + 2);
4446 } else if (c->flags & DIV_2) {
4448 if (c->flags & (PLLD | PLLX)) {
4454 } else if (c->flags & PLLU) {
4455 u32 val = clk_readl(c->reg);
4456 c->state = val & (0x1 << c->reg_shift) ? ON : OFF;
4464 static int tegra12_pll_div_clk_enable(struct clk *c)
4468 unsigned long flags;
4470 pr_debug("%s: %s\n", __func__, c->name);
4471 if (c->flags & DIV_U71) {
4472 spin_lock_irqsave(&pll_div_lock, flags);
4473 val = clk_readl(c->reg);
4474 new_val = val >> c->reg_shift;
4477 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
4479 val &= ~(0xFFFF << c->reg_shift);
4480 val |= new_val << c->reg_shift;
4481 clk_writel_delay(val, c->reg);
4482 spin_unlock_irqrestore(&pll_div_lock, flags);
4484 } else if (c->flags & DIV_2) {
4486 } else if (c->flags & PLLU) {
4487 clk_lock_save(c->parent, &flags);
4488 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
4489 clk_writel_delay(val, c->reg);
4490 clk_unlock_restore(c->parent, &flags);
4496 static void tegra12_pll_div_clk_disable(struct clk *c)
4500 unsigned long flags;
4502 pr_debug("%s: %s\n", __func__, c->name);
4503 if (c->flags & DIV_U71) {
4504 spin_lock_irqsave(&pll_div_lock, flags);
4505 val = clk_readl(c->reg);
4506 new_val = val >> c->reg_shift;
4509 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
4511 val &= ~(0xFFFF << c->reg_shift);
4512 val |= new_val << c->reg_shift;
4513 clk_writel_delay(val, c->reg);
4514 spin_unlock_irqrestore(&pll_div_lock, flags);
4515 } else if (c->flags & PLLU) {
4516 clk_lock_save(c->parent, &flags);
4517 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
4518 clk_writel_delay(val, c->reg);
4519 clk_unlock_restore(c->parent, &flags);
4523 static int tegra12_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
4528 unsigned long parent_rate = clk_get_rate(c->parent);
4529 unsigned long flags;
4531 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4532 if (tegra_platform_is_qt())
4534 if (c->flags & DIV_U71) {
4535 divider_u71 = clk_div71_get_divider(
4536 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4537 if (divider_u71 >= 0) {
4538 spin_lock_irqsave(&pll_div_lock, flags);
4539 val = clk_readl(c->reg);
4540 new_val = val >> c->reg_shift;
4542 if (c->flags & DIV_U71_FIXED)
4543 new_val |= PLL_OUT_OVERRIDE;
4544 new_val &= ~PLL_OUT_RATIO_MASK;
4545 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
4547 val &= ~(0xFFFF << c->reg_shift);
4548 val |= new_val << c->reg_shift;
4549 clk_writel_delay(val, c->reg);
4550 c->div = divider_u71 + 2;
4552 spin_unlock_irqrestore(&pll_div_lock, flags);
4555 } else if (c->flags & DIV_2)
4556 return clk_set_rate(c->parent, rate * 2);
4561 static long tegra12_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
4564 unsigned long parent_rate = clk_get_rate(c->parent);
4565 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4567 if (c->flags & DIV_U71) {
4568 divider = clk_div71_get_divider(
4569 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4572 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4573 } else if (c->flags & DIV_2)
4574 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
4580 static struct clk_ops tegra_pll_div_ops = {
4581 .init = tegra12_pll_div_clk_init,
4582 .enable = tegra12_pll_div_clk_enable,
4583 .disable = tegra12_pll_div_clk_disable,
4584 .set_rate = tegra12_pll_div_clk_set_rate,
4585 .round_rate = tegra12_pll_div_clk_round_rate,
4588 /* Periph clk ops */
4589 static inline u32 periph_clk_source_mask(struct clk *c)
4591 if (c->u.periph.src_mask)
4592 return c->u.periph.src_mask;
4593 else if (c->flags & MUX_PWM)
4595 else if (c->flags & MUX_CLK_OUT)
4596 return 3 << (c->u.periph.clk_num + 4);
4597 else if (c->flags & PLLD)
4598 return PLLD_BASE_DSI_MUX_MASK;
4603 static inline u32 periph_clk_source_shift(struct clk *c)
4605 if (c->u.periph.src_shift)
4606 return c->u.periph.src_shift;
4607 else if (c->flags & MUX_PWM)
4609 else if (c->flags & MUX_CLK_OUT)
4610 return c->u.periph.clk_num + 4;
4611 else if (c->flags & PLLD)
4612 return PLLD_BASE_DSI_MUX_SHIFT;
4617 static void tegra12_periph_clk_init(struct clk *c)
4619 u32 val = clk_readl(c->reg);
4620 const struct clk_mux_sel *mux = 0;
4621 const struct clk_mux_sel *sel;
4622 if (c->flags & MUX) {
4623 for (sel = c->inputs; sel->input != NULL; sel++) {
4624 if (((val & periph_clk_source_mask(c)) >>
4625 periph_clk_source_shift(c)) == sel->value)
4630 c->parent = mux->input;
4632 if (c->flags & PLLU) {
4633 /* for xusb_hs clock enforce SS div2 source */
4634 val &= ~periph_clk_source_mask(c);
4635 clk_writel_delay(val, c->reg);
4637 c->parent = c->inputs[0].input;
4640 /* if peripheral is left under reset - enforce safe rate */
4642 if (c->flags & PERIPH_NO_RESET) {
4643 if (tegra12_periph_is_special_reset(c)) {
4644 tegra_periph_clk_safe_rate_init(c);
4645 val = clk_readl(c->reg);
4647 } else if (IS_PERIPH_IN_RESET(c)) {
4648 tegra_periph_clk_safe_rate_init(c);
4649 val = clk_readl(c->reg);
4652 if (c->flags & DIV_U71) {
4653 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
4654 if (c->flags & DIV_U71_IDLE) {
4655 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
4656 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
4657 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
4658 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
4659 clk_writel(val, c->reg);
4661 c->div = divu71 + 2;
4663 } else if (c->flags & DIV_U151) {
4664 u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
4665 if ((c->flags & DIV_U151_UART) &&
4666 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
4669 c->div = divu151 + 2;
4671 } else if (c->flags & DIV_U16) {
4672 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
4673 c->div = divu16 + 1;
4680 if (c->flags & PERIPH_NO_ENB) {
4681 c->state = c->parent->state;
4687 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
4689 if (!(c->flags & PERIPH_NO_RESET))
4690 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
4694 static int tegra12_periph_clk_enable(struct clk *c)
4696 unsigned long flags;
4697 pr_debug("%s on clock %s\n", __func__, c->name);
4699 if (c->flags & PERIPH_NO_ENB)
4702 spin_lock_irqsave(&periph_refcount_lock, flags);
4704 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
4705 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) {
4706 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4710 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
4711 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) {
4712 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) {
4713 udelay(RESET_PROPAGATION_DELAY);
4714 clk_writel_delay(PERIPH_CLK_TO_BIT(c),
4715 PERIPH_CLK_TO_RST_CLR_REG(c));
4718 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4722 static void tegra12_periph_clk_disable(struct clk *c)
4724 unsigned long val, flags;
4725 pr_debug("%s on clock %s\n", __func__, c->name);
4727 if (c->flags & PERIPH_NO_ENB)
4730 spin_lock_irqsave(&periph_refcount_lock, flags);
4733 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
4735 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
4736 /* If peripheral is in the APB bus then read the APB bus to
4737 * flush the write operation in apb bus. This will avoid the
4738 * peripheral access after disabling clock*/
4739 if (c->flags & PERIPH_ON_APB)
4740 val = tegra_read_chipid();
4743 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
4745 spin_unlock_irqrestore(&periph_refcount_lock, flags);
4748 static void tegra12_periph_clk_reset(struct clk *c, bool assert)
4751 pr_debug("%s %s on clock %s\n", __func__,
4752 assert ? "assert" : "deassert", c->name);
4754 if (c->flags & PERIPH_NO_ENB)
4757 if (!(c->flags & PERIPH_NO_RESET)) {
4759 /* If peripheral is in the APB bus then read the APB
4760 * bus to flush the write operation in apb bus. This
4761 * will avoid the peripheral access after disabling
4763 if (c->flags & PERIPH_ON_APB)
4764 val = tegra_read_chipid();
4766 clk_writel_delay(PERIPH_CLK_TO_BIT(c),
4767 PERIPH_CLK_TO_RST_SET_REG(c));
4769 clk_writel_delay(PERIPH_CLK_TO_BIT(c),
4770 PERIPH_CLK_TO_RST_CLR_REG(c));
4774 static int tegra12_periph_clk_set_parent(struct clk *c, struct clk *p)
4777 const struct clk_mux_sel *sel;
4778 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
4780 if (!(c->flags & MUX))
4781 return (p == c->parent) ? 0 : (-EINVAL);
4783 for (sel = c->inputs; sel->input != NULL; sel++) {
4784 if (sel->input == p) {
4785 val = clk_readl(c->reg);
4786 val &= ~periph_clk_source_mask(c);
4787 val |= (sel->value << periph_clk_source_shift(c));
4792 clk_writel_delay(val, c->reg);
4794 if (c->refcnt && c->parent)
4795 clk_disable(c->parent);
4805 static int tegra12_periph_clk_set_rate(struct clk *c, unsigned long rate)
4809 unsigned long parent_rate = clk_get_rate(c->parent);
4811 if (tegra_platform_is_qt())
4813 if (c->flags & DIV_U71) {
4814 divider = clk_div71_get_divider(
4815 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4817 val = clk_readl(c->reg);
4818 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
4820 clk_writel_delay(val, c->reg);
4821 c->div = divider + 2;
4825 } else if (c->flags & DIV_U151) {
4826 divider = clk_div151_get_divider(
4827 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4829 val = clk_readl(c->reg);
4830 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4832 if (c->flags & DIV_U151_UART) {
4834 val |= PERIPH_CLK_UART_DIV_ENB;
4836 val &= ~PERIPH_CLK_UART_DIV_ENB;
4838 clk_writel_delay(val, c->reg);
4839 c->div = divider + 2;
4843 } else if (c->flags & DIV_U16) {
4844 divider = clk_div16_get_divider(parent_rate, rate);
4846 val = clk_readl(c->reg);
4847 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
4849 clk_writel_delay(val, c->reg);
4850 c->div = divider + 1;
4854 } else if (parent_rate <= rate) {
4862 static long tegra12_periph_clk_round_rate(struct clk *c,
4866 unsigned long parent_rate = clk_get_rate(c->parent);
4867 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
4869 if (c->flags & DIV_U71) {
4870 divider = clk_div71_get_divider(
4871 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4875 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4876 } else if (c->flags & DIV_U151) {
4877 divider = clk_div151_get_divider(
4878 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
4882 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
4883 } else if (c->flags & DIV_U16) {
4884 divider = clk_div16_get_divider(parent_rate, rate);
4887 return DIV_ROUND_UP(parent_rate, divider + 1);
4892 static struct clk_ops tegra_periph_clk_ops = {
4893 .init = &tegra12_periph_clk_init,
4894 .enable = &tegra12_periph_clk_enable,
4895 .disable = &tegra12_periph_clk_disable,
4896 .set_parent = &tegra12_periph_clk_set_parent,
4897 .set_rate = &tegra12_periph_clk_set_rate,
4898 .round_rate = &tegra12_periph_clk_round_rate,
4899 .reset = &tegra12_periph_clk_reset,
4902 /* 1x shared bus ops */
4903 static long _1x_round_updown(struct clk *c, struct clk *src,
4904 unsigned long rate, bool up)
4906 return fixed_src_bus_round_updown(c, src, c->flags, rate, up);
4909 static long tegra12_1xbus_round_updown(struct clk *c, unsigned long rate,
4912 unsigned long pll_low_rate, pll_high_rate;
4914 rate = max(rate, c->min_rate);
4916 pll_low_rate = _1x_round_updown(c, c->u.periph.pll_low, rate, up);
4917 if (rate <= c->u.periph.threshold) {
4918 c->u.periph.pll_selected = c->u.periph.pll_low;
4919 return pll_low_rate;
4922 pll_high_rate = _1x_round_updown(c, c->u.periph.pll_high, rate, up);
4923 if (pll_high_rate <= c->u.periph.threshold) {
4924 c->u.periph.pll_selected = c->u.periph.pll_low;
4925 return pll_low_rate; /* prevent oscillation across threshold */
4929 /* rounding up: both plls may hit max, and round down */
4930 if (pll_high_rate < rate) {
4931 if (pll_low_rate < pll_high_rate) {
4932 c->u.periph.pll_selected = c->u.periph.pll_high;
4933 return pll_high_rate;
4936 if ((pll_low_rate < rate) ||
4937 (pll_low_rate > pll_high_rate)) {
4938 c->u.periph.pll_selected = c->u.periph.pll_high;
4939 return pll_high_rate;
4942 } else if (pll_low_rate < pll_high_rate) {
4943 /* rounding down: to get here both plls able to round down */
4944 c->u.periph.pll_selected = c->u.periph.pll_high;
4945 return pll_high_rate;
4947 c->u.periph.pll_selected = c->u.periph.pll_low;
4948 return pll_low_rate;
4951 static long tegra12_1xbus_round_rate(struct clk *c, unsigned long rate)
4953 return tegra12_1xbus_round_updown(c, rate, true);
4956 static int tegra12_1xbus_set_rate(struct clk *c, unsigned long rate)
4958 /* Compensate rate truncating during rounding */
4959 return tegra12_periph_clk_set_rate(c, rate + 1);
4962 static int tegra12_clk_1xbus_update(struct clk *c)
4965 struct clk *new_parent;
4966 unsigned long rate, old_rate;
4968 if (detach_shared_bus)
4971 rate = tegra12_clk_shared_bus_update(c, NULL, NULL, NULL);
4973 old_rate = clk_get_rate_locked(c);
4974 pr_debug("\n1xbus %s: rate %lu on parent %s: new request %lu\n",
4975 c->name, old_rate, c->parent->name, rate);
4976 if (rate == old_rate)
4979 if (!c->u.periph.min_div_low || !c->u.periph.min_div_high) {
4980 unsigned long r, m = c->max_rate;
4981 r = clk_get_rate(c->u.periph.pll_low);
4982 c->u.periph.min_div_low = DIV_ROUND_UP(r, m) * c->mul;
4983 r = clk_get_rate(c->u.periph.pll_high);
4984 c->u.periph.min_div_high = DIV_ROUND_UP(r, m) * c->mul;
4987 new_parent = c->u.periph.pll_selected;
4990 * The transition procedure below is guaranteed to switch to the target
4991 * parent/rate without violation of max clock limits. It would attempt
4992 * to switch without dip in bus rate if it is possible, but this cannot
4993 * be guaranteed (example: switch from 408 MHz : 1 to 624 MHz : 2 with
4994 * maximum bus limit 408 MHz will be executed as 408 => 204 => 312 MHz,
4995 * and there is no way to avoid rate dip in this case).
4997 if (new_parent != c->parent) {
4998 int interim_div = 0;
4999 /* Switching to pll_high may over-clock bus if current divider
5000 is too small - increase divider to safe value */
5001 if ((new_parent == c->u.periph.pll_high) &&
5002 (c->div < c->u.periph.min_div_high))
5003 interim_div = c->u.periph.min_div_high;
5005 /* Switching to pll_low may dip down rate if current divider
5006 is too big - decrease divider as much as we can */
5007 if ((new_parent == c->u.periph.pll_low) &&
5008 (c->div > c->u.periph.min_div_low) &&
5009 (c->div > c->u.periph.min_div_high))
5010 interim_div = c->u.periph.min_div_low;
5013 u64 interim_rate = old_rate * c->div;
5014 do_div(interim_rate, interim_div);
5015 ret = clk_set_rate_locked(c, interim_rate);
5017 pr_err("Failed to set %s rate to %lu\n",
5018 c->name, (unsigned long)interim_rate);
5021 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
5022 clk_get_rate_locked(c), c->parent->name);
5025 ret = clk_set_parent_locked(c, new_parent);
5027 pr_err("Failed to set %s parent %s\n",
5028 c->name, new_parent->name);
5032 old_rate = clk_get_rate_locked(c);
5033 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
5034 old_rate, c->parent->name);
5035 if (rate == old_rate)
5039 ret = clk_set_rate_locked(c, rate);
5041 pr_err("Failed to set %s rate to %lu\n", c->name, rate);
5044 pr_debug("1xbus %s: rate %lu on parent %s\n", c->name,
5045 clk_get_rate_locked(c), c->parent->name);
5050 static struct clk_ops tegra_1xbus_clk_ops = {
5051 .init = &tegra12_periph_clk_init,
5052 .enable = &tegra12_periph_clk_enable,
5053 .disable = &tegra12_periph_clk_disable,
5054 .set_parent = &tegra12_periph_clk_set_parent,
5055 .set_rate = &tegra12_1xbus_set_rate,
5056 .round_rate = &tegra12_1xbus_round_rate,
5057 .round_rate_updown = &tegra12_1xbus_round_updown,
5058 .reset = &tegra12_periph_clk_reset,
5059 .shared_bus_update = &tegra12_clk_1xbus_update,
5062 /* msenc clock propagation WAR for bug 1005168 */
5063 static int tegra12_msenc_clk_enable(struct clk *c)
5065 int ret = tegra12_periph_clk_enable(c);
5069 clk_writel(0, LVL2_CLK_GATE_OVRE);
5070 clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
5072 clk_writel(0, LVL2_CLK_GATE_OVRE);
5076 static struct clk_ops tegra_msenc_clk_ops = {
5077 .init = &tegra12_periph_clk_init,
5078 .enable = &tegra12_msenc_clk_enable,
5079 .disable = &tegra12_periph_clk_disable,
5080 .set_parent = &tegra12_periph_clk_set_parent,
5081 .set_rate = &tegra12_periph_clk_set_rate,
5082 .round_rate = &tegra12_periph_clk_round_rate,
5083 .reset = &tegra12_periph_clk_reset,
5085 /* Periph extended clock configuration ops */
5087 tegra12_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
5089 if (p == TEGRA_CLK_VI_INP_SEL) {
5090 u32 val = clk_readl(c->reg);
5091 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
5092 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
5093 PERIPH_CLK_VI_SEL_EX_MASK;
5094 clk_writel(val, c->reg);
5100 static struct clk_ops tegra_vi_clk_ops = {
5101 .init = &tegra12_periph_clk_init,
5102 .enable = &tegra12_periph_clk_enable,
5103 .disable = &tegra12_periph_clk_disable,
5104 .set_parent = &tegra12_periph_clk_set_parent,
5105 .set_rate = &tegra12_periph_clk_set_rate,
5106 .round_rate = &tegra12_periph_clk_round_rate,
5107 .clk_cfg_ex = &tegra12_vi_clk_cfg_ex,
5108 .reset = &tegra12_periph_clk_reset,
5112 tegra12_sor_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
5114 if (p == TEGRA_CLK_SOR_CLK_SEL) {
5115 u32 val = clk_readl(c->reg);
5116 val &= ~PERIPH_CLK_SOR_CLK_SEL_MASK;
5117 val |= (setting << PERIPH_CLK_SOR_CLK_SEL_SHIFT) &
5118 PERIPH_CLK_SOR_CLK_SEL_MASK;
5119 clk_writel(val, c->reg);
5125 static struct clk_ops tegra_sor_clk_ops = {
5126 .init = &tegra12_periph_clk_init,
5127 .enable = &tegra12_periph_clk_enable,
5128 .disable = &tegra12_periph_clk_disable,
5129 .set_parent = &tegra12_periph_clk_set_parent,
5130 .set_rate = &tegra12_periph_clk_set_rate,
5131 .round_rate = &tegra12_periph_clk_round_rate,
5132 .clk_cfg_ex = &tegra12_sor_clk_cfg_ex,
5133 .reset = &tegra12_periph_clk_reset,
5137 tegra12_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
5139 if (p == TEGRA_CLK_DTV_INVERT) {
5140 u32 val = clk_readl(c->reg);
5142 val |= PERIPH_CLK_DTV_POLARITY_INV;
5144 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
5145 clk_writel(val, c->reg);
5151 static struct clk_ops tegra_dtv_clk_ops = {
5152 .init = &tegra12_periph_clk_init,
5153 .enable = &tegra12_periph_clk_enable,
5154 .disable = &tegra12_periph_clk_disable,
5155 .set_parent = &tegra12_periph_clk_set_parent,
5156 .set_rate = &tegra12_periph_clk_set_rate,
5157 .round_rate = &tegra12_periph_clk_round_rate,
5158 .clk_cfg_ex = &tegra12_dtv_clk_cfg_ex,
5159 .reset = &tegra12_periph_clk_reset,
5162 static struct clk_ops tegra_dsi_clk_ops = {
5163 .init = &tegra12_periph_clk_init,
5164 .enable = &tegra12_periph_clk_enable,
5165 .disable = &tegra12_periph_clk_disable,
5166 .set_rate = &tegra12_periph_clk_set_rate,
5167 .round_rate = &tegra12_periph_clk_round_rate,
5168 .reset = &tegra12_periph_clk_reset,
5171 /* pciex clock support only reset function */
5172 static void tegra12_pciex_clk_init(struct clk *c)
5174 c->state = c->parent->state;
5177 static int tegra12_pciex_clk_enable(struct clk *c)
5182 static void tegra12_pciex_clk_disable(struct clk *c)
5186 static int tegra12_pciex_clk_set_rate(struct clk *c, unsigned long rate)
5188 unsigned long parent_rate = clk_get_rate(c->parent);
5191 * the only supported pcie configurations:
5192 * Gen1: plle = 100MHz, link at 250MHz
5193 * Gen2: plle = 100MHz, link at 500MHz
5195 if (parent_rate == 100000000) {
5196 if (rate == 500000000) {
5200 } else if (rate == 250000000) {
5209 static struct clk_ops tegra_pciex_clk_ops = {
5210 .init = tegra12_pciex_clk_init,
5211 .enable = tegra12_pciex_clk_enable,
5212 .disable = tegra12_pciex_clk_disable,
5213 .set_rate = tegra12_pciex_clk_set_rate,
5214 .reset = tegra12_periph_clk_reset,
5217 /* Output clock ops */
5219 static DEFINE_SPINLOCK(clk_out_lock);
5221 static void tegra12_clk_out_init(struct clk *c)
5223 const struct clk_mux_sel *mux = 0;
5224 const struct clk_mux_sel *sel;
5225 u32 val = pmc_readl(c->reg);
5227 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
5231 for (sel = c->inputs; sel->input != NULL; sel++) {
5232 if (((val & periph_clk_source_mask(c)) >>
5233 periph_clk_source_shift(c)) == sel->value)
5237 c->parent = mux->input;
5240 static int tegra12_clk_out_enable(struct clk *c)
5243 unsigned long flags;
5245 pr_debug("%s on clock %s\n", __func__, c->name);
5247 spin_lock_irqsave(&clk_out_lock, flags);
5248 val = pmc_readl(c->reg);
5249 val |= (0x1 << c->u.periph.clk_num);
5250 pmc_writel(val, c->reg);
5252 spin_unlock_irqrestore(&clk_out_lock, flags);
5257 static void tegra12_clk_out_disable(struct clk *c)
5260 unsigned long flags;
5262 pr_debug("%s on clock %s\n", __func__, c->name);
5264 spin_lock_irqsave(&clk_out_lock, flags);
5265 val = pmc_readl(c->reg);
5266 val &= ~(0x1 << c->u.periph.clk_num);
5267 pmc_writel(val, c->reg);
5269 spin_unlock_irqrestore(&clk_out_lock, flags);
5272 static int tegra12_clk_out_set_parent(struct clk *c, struct clk *p)
5275 unsigned long flags;
5276 const struct clk_mux_sel *sel;
5278 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
5280 for (sel = c->inputs; sel->input != NULL; sel++) {
5281 if (sel->input == p) {
5285 spin_lock_irqsave(&clk_out_lock, flags);
5286 val = pmc_readl(c->reg);
5287 val &= ~periph_clk_source_mask(c);
5288 val |= (sel->value << periph_clk_source_shift(c));
5289 pmc_writel(val, c->reg);
5291 spin_unlock_irqrestore(&clk_out_lock, flags);
5293 if (c->refcnt && c->parent)
5294 clk_disable(c->parent);
5303 static struct clk_ops tegra_clk_out_ops = {
5304 .init = &tegra12_clk_out_init,
5305 .enable = &tegra12_clk_out_enable,
5306 .disable = &tegra12_clk_out_disable,
5307 .set_parent = &tegra12_clk_out_set_parent,
5311 /* External memory controller clock ops */
5312 static void tegra12_emc_clk_init(struct clk *c)
5314 tegra12_periph_clk_init(c);
5315 tegra_emc_dram_type_init(c);
5318 static long tegra12_emc_clk_round_updown(struct clk *c, unsigned long rate,
5321 unsigned long new_rate = max(rate, c->min_rate);
5323 new_rate = tegra_emc_round_rate_updown(new_rate, up);
5324 if (IS_ERR_VALUE(new_rate))
5325 new_rate = c->max_rate;
5330 static long tegra12_emc_clk_round_rate(struct clk *c, unsigned long rate)
5332 return tegra12_emc_clk_round_updown(c, rate, true);
5335 static int tegra12_emc_clk_set_rate(struct clk *c, unsigned long rate)
5341 if (tegra_platform_is_qt())
5343 /* The tegra12x memory controller has an interlock with the clock
5344 * block that allows memory shadowed registers to be updated,
5345 * and then transfer them to the main registers at the same
5346 * time as the clock update without glitches. During clock change
5347 * operation both clock parent and divider may change simultaneously
5348 * to achieve requested rate. */
5349 p = tegra_emc_predict_parent(rate, &div_value);
5350 div_value += 2; /* emc has fractional DIV_U71 divider */
5351 if (IS_ERR_OR_NULL(p)) {
5352 pr_err("%s: Failed to predict emc parent for rate %lu\n",
5357 if (p == c->parent) {
5358 if (div_value == c->div)
5360 } else if (c->refcnt)
5363 ret = tegra_emc_set_rate(rate);
5367 if (p != c->parent) {
5368 if(c->refcnt && c->parent)
5369 clk_disable(c->parent);
5377 static int tegra12_clk_emc_bus_update(struct clk *bus)
5379 struct clk *p = NULL;
5380 unsigned long rate, old_rate, parent_rate, backup_rate;
5382 if (detach_shared_bus)
5385 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
5387 old_rate = clk_get_rate_locked(bus);
5388 if (rate == old_rate)
5391 if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
5392 if (bus->parent == p) {
5393 /* need backup to re-lock current parent */
5395 if (IS_ERR_VALUE(backup_rate)) {
5396 pr_err("%s: No backup for %s rate %lu\n",
5397 __func__, bus->name, rate);
5401 /* set volatge for backup rate if going up */
5402 if (backup_rate > old_rate) {
5403 ret = tegra_dvfs_set_rate(bus, backup_rate);
5405 pr_err("%s: dvfs failed on %s rate %lu\n",
5406 __func__, bus->name, backup_rate);
5411 trace_clock_set_rate(bus->name, backup_rate, 0);
5412 ret = bus->ops->set_rate(bus, backup_rate);
5414 pr_err("%s: Failed to backup %s for rate %lu\n",
5415 __func__, bus->name, rate);
5418 clk_rate_change_notify(bus, backup_rate);
5421 pr_err("%s: %s has other than emc child\n",
5426 if (clk_set_rate(p, parent_rate)) {
5427 pr_err("%s: Failed to set %s rate %lu\n",
5428 __func__, p->name, parent_rate);
5433 return clk_set_rate_locked(bus, rate);
5436 static struct clk_ops tegra_emc_clk_ops = {
5437 .init = &tegra12_emc_clk_init,
5438 .enable = &tegra12_periph_clk_enable,
5439 .disable = &tegra12_periph_clk_disable,
5440 .set_rate = &tegra12_emc_clk_set_rate,
5441 .round_rate = &tegra12_emc_clk_round_rate,
5442 .round_rate_updown = &tegra12_emc_clk_round_updown,
5443 .reset = &tegra12_periph_clk_reset,
5444 .shared_bus_update = &tegra12_clk_emc_bus_update,
5447 void tegra_mc_divider_update(struct clk *emc)
5449 emc->child_bus->div = (clk_readl(emc->reg) &
5450 PERIPH_CLK_SOURCE_EMC_MC_SAME) ? 1 : 2;
5453 static void tegra12_mc_clk_init(struct clk *c)
5456 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
5459 c->parent->child_bus = c;
5460 tegra_mc_divider_update(c->parent);
5464 static struct clk_ops tegra_mc_clk_ops = {
5465 .init = &tegra12_mc_clk_init,
5466 .enable = &tegra12_periph_clk_enable,
5467 .disable = &tegra12_periph_clk_disable,
5470 /* Clock doubler ops (non-atomic shared register access) */
5471 static DEFINE_SPINLOCK(doubler_lock);
5473 static void tegra12_clk_double_init(struct clk *c)
5475 u32 val = clk_readl(c->reg);
5476 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
5479 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
5483 static int tegra12_clk_double_set_rate(struct clk *c, unsigned long rate)
5486 unsigned long parent_rate = clk_get_rate(c->parent);
5487 unsigned long flags;
5489 if (rate == parent_rate) {
5490 spin_lock_irqsave(&doubler_lock, flags);
5491 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
5492 clk_writel(val, c->reg);
5495 spin_unlock_irqrestore(&doubler_lock, flags);
5497 } else if (rate == 2 * parent_rate) {
5498 spin_lock_irqsave(&doubler_lock, flags);
5499 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
5500 clk_writel(val, c->reg);
5503 spin_unlock_irqrestore(&doubler_lock, flags);
5509 static struct clk_ops tegra_clk_double_ops = {
5510 .init = &tegra12_clk_double_init,
5511 .enable = &tegra12_periph_clk_enable,
5512 .disable = &tegra12_periph_clk_disable,
5513 .set_rate = &tegra12_clk_double_set_rate,
5516 /* Audio sync clock ops */
5517 static int tegra12_sync_source_set_rate(struct clk *c, unsigned long rate)
5523 static struct clk_ops tegra_sync_source_ops = {
5524 .set_rate = &tegra12_sync_source_set_rate,
5527 static void tegra12_audio_sync_clk_init(struct clk *c)
5530 const struct clk_mux_sel *sel;
5531 u32 val = clk_readl(c->reg);
5532 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
5533 source = val & AUDIO_SYNC_SOURCE_MASK;
5534 for (sel = c->inputs; sel->input != NULL; sel++)
5535 if (sel->value == source)
5537 BUG_ON(sel->input == NULL);
5538 c->parent = sel->input;
5541 static int tegra12_audio_sync_clk_enable(struct clk *c)
5543 u32 val = clk_readl(c->reg);
5544 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
5548 static void tegra12_audio_sync_clk_disable(struct clk *c)
5550 u32 val = clk_readl(c->reg);
5551 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
5554 static int tegra12_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
5557 const struct clk_mux_sel *sel;
5558 for (sel = c->inputs; sel->input != NULL; sel++) {
5559 if (sel->input == p) {
5560 val = clk_readl(c->reg);
5561 val &= ~AUDIO_SYNC_SOURCE_MASK;
5567 clk_writel(val, c->reg);
5569 if (c->refcnt && c->parent)
5570 clk_disable(c->parent);
5580 static struct clk_ops tegra_audio_sync_clk_ops = {
5581 .init = tegra12_audio_sync_clk_init,
5582 .enable = tegra12_audio_sync_clk_enable,
5583 .disable = tegra12_audio_sync_clk_disable,
5584 .set_parent = tegra12_audio_sync_clk_set_parent,
5587 /* cml0 (pcie), and cml1 (sata) clock ops */
5588 static void tegra12_cml_clk_init(struct clk *c)
5590 u32 val = clk_readl(c->reg);
5591 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
5594 static int tegra12_cml_clk_enable(struct clk *c)
5596 u32 val = clk_readl(c->reg);
5597 val |= (0x1 << c->u.periph.clk_num);
5598 clk_writel(val, c->reg);
5602 static void tegra12_cml_clk_disable(struct clk *c)
5604 u32 val = clk_readl(c->reg);
5605 val &= ~(0x1 << c->u.periph.clk_num);
5606 clk_writel(val, c->reg);
5609 static struct clk_ops tegra_cml_clk_ops = {
5610 .init = &tegra12_cml_clk_init,
5611 .enable = &tegra12_cml_clk_enable,
5612 .disable = &tegra12_cml_clk_disable,
5618 * Some clocks require dynamic re-locking of source PLL in order to
5619 * achieve frequency scaling granularity that matches characterized
5620 * core voltage steps. The cbus clock creates a shared bus that
5621 * provides a virtual root for such clocks to hide and synchronize
5622 * parent PLL re-locking as well as backup operations.
5625 static void tegra12_clk_cbus_init(struct clk *c)
5631 static int tegra12_clk_cbus_enable(struct clk *c)
5636 static long tegra12_clk_cbus_round_updown(struct clk *c, unsigned long rate,
5640 const int *millivolts;
5644 c->min_rate = c->parent->min_rate;
5645 rate = max(rate, c->min_rate);
5649 /* update min now, since no dvfs table was available during init
5650 (skip placeholder entries set to 1 kHz) */
5652 for (i = 0; i < c->dvfs->num_freqs; i++) {
5653 if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) {
5654 c->min_rate = c->dvfs->freqs[i];
5658 BUG_ON(!c->min_rate);
5660 rate = max(rate, c->min_rate);
5662 millivolts = tegra_dvfs_get_millivolts_pll(c->dvfs);
5663 for (i = 0; ; i++) {
5664 unsigned long f = c->dvfs->freqs[i];
5665 int mv = millivolts[i];
5666 if ((f >= rate) || (mv >= c->dvfs->max_millivolts) ||
5667 ((i + 1) >= c->dvfs->num_freqs)) {
5668 if (!up && i && (f > rate))
5673 return c->dvfs->freqs[i];
5676 static long tegra12_clk_cbus_round_rate(struct clk *c, unsigned long rate)
5678 return tegra12_clk_cbus_round_updown(c, rate, true);
5681 static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort)
5685 /* set new divider if it is bigger than the current one */
5686 if (c->div < c->mul * div) {
5687 ret = clk_set_div(c, div);
5689 pr_err("%s: failed to set %s clock divider %u: %d\n",
5690 __func__, c->name, div, ret);
5696 if (c->parent != p) {
5697 ret = clk_set_parent(c, p);
5699 pr_err("%s: failed to set %s clock parent %s: %d\n",
5700 __func__, c->name, p->name, ret);
5706 /* set new divider if it is smaller than the current one */
5707 if (c->div > c->mul * div) {
5708 ret = clk_set_div(c, div);
5710 pr_err("%s: failed to set %s clock divider %u: %d\n",
5711 __func__, c->name, div, ret);
5717 static int cbus_backup(struct clk *c)
5722 list_for_each_entry(user, &c->shared_bus_list,
5723 u.shared_bus_user.node) {
5724 struct clk *client = user->u.shared_bus_user.client;
5725 if (client && (client->state == ON) &&
5726 (client->parent == c->parent)) {
5727 ret = cbus_switch_one(client,
5728 c->shared_bus_backup.input,
5729 c->shared_bus_backup.value *
5738 static int cbus_dvfs_set_rate(struct clk *c, unsigned long rate)
5743 list_for_each_entry(user, &c->shared_bus_list,
5744 u.shared_bus_user.node) {
5745 struct clk *client = user->u.shared_bus_user.client;
5746 if (client && client->refcnt && (client->parent == c->parent)) {
5747 ret = tegra_dvfs_set_rate(c, rate);
5755 static void cbus_restore(struct clk *c)
5759 list_for_each_entry(user, &c->shared_bus_list,
5760 u.shared_bus_user.node) {
5761 if (user->u.shared_bus_user.client)
5762 cbus_switch_one(user->u.shared_bus_user.client,
5763 c->parent, c->div * user->div, false);
5767 static int get_next_backup_div(struct clk *c, unsigned long rate)
5770 unsigned long backup_rate = clk_get_rate(c->shared_bus_backup.input);
5772 rate = max(rate, clk_get_rate_locked(c));
5773 rate = rate - (rate >> 2); /* 25% margin for backup rate */
5774 if ((u64)rate * div < backup_rate)
5775 div = DIV_ROUND_UP(backup_rate, rate);
5781 static int tegra12_clk_cbus_set_rate(struct clk *c, unsigned long rate)
5788 if (tegra_platform_is_qt())
5790 ret = clk_enable(c->parent);
5792 pr_err("%s: failed to enable %s clock: %d\n",
5793 __func__, c->name, ret);
5797 dramp = tegra12_is_dyn_ramp(c->parent, rate * c->div, false);
5799 c->shared_bus_backup.value = get_next_backup_div(c, rate);
5800 ret = cbus_backup(c);
5805 ret = clk_set_rate(c->parent, rate * c->div);
5807 pr_err("%s: failed to set %s clock rate %lu: %d\n",
5808 __func__, c->name, rate, ret);
5812 /* Safe voltage setting is taken care of by cbus clock dvfs; the call
5813 * below only records requirements for each enabled client.
5816 ret = cbus_dvfs_set_rate(c, rate);
5821 clk_disable(c->parent);
5825 static inline void cbus_move_enabled_user(
5826 struct clk *user, struct clk *dst, struct clk *src)
5829 list_move_tail(&user->u.shared_bus_user.node, &dst->shared_bus_list);
5831 clk_reparent(user, dst);
5834 #ifdef CONFIG_TEGRA_DYNAMIC_CBUS
5835 static int tegra12_clk_cbus_update(struct clk *bus)
5838 struct clk *slow = NULL;
5839 struct clk *top = NULL;
5841 unsigned long old_rate;
5842 unsigned long ceiling;
5844 if (detach_shared_bus)
5847 rate = tegra12_clk_shared_bus_update(bus, &top, &slow, &ceiling);
5849 /* use dvfs table of the slowest enabled client as cbus dvfs table */
5850 if (bus->dvfs && slow && (slow != bus->u.cbus.slow_user)) {
5852 unsigned long *dest = &bus->dvfs->freqs[0];
5853 unsigned long *src =
5854 &slow->u.shared_bus_user.client->dvfs->freqs[0];
5856 for (i = 0; i < bus->dvfs->num_freqs; i++)
5857 dest[i] = src[i] * slow->div;
5859 memcpy(dest, src, sizeof(*dest) * bus->dvfs->num_freqs);
5862 /* update bus state variables and rate */
5863 bus->u.cbus.slow_user = slow;
5864 bus->u.cbus.top_user = top;
5866 rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
5867 mv = tegra_dvfs_predict_millivolts(bus, rate);
5868 if (IS_ERR_VALUE(mv))
5872 mv -= bus->dvfs->cur_millivolts;
5873 if (bus->refcnt && (mv > 0)) {
5874 ret = tegra_dvfs_set_rate(bus, rate);
5880 old_rate = clk_get_rate_locked(bus);
5881 if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
5882 ret = bus->ops->set_rate(bus, rate);
5888 if (bus->refcnt && (mv <= 0)) {
5889 ret = tegra_dvfs_set_rate(bus, rate);
5895 clk_rate_change_notify(bus, rate);
5899 static int tegra12_clk_cbus_update(struct clk *bus)
5901 unsigned long rate, old_rate;
5903 if (detach_shared_bus)
5906 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
5908 old_rate = clk_get_rate_locked(bus);
5909 if (rate == old_rate)
5912 return clk_set_rate_locked(bus, rate);
5916 static int tegra12_clk_cbus_migrate_users(struct clk *user)
5918 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
5919 struct clk *src_bus, *dst_bus, *top_user, *c;
5920 struct list_head *pos, *n;
5922 if (!user->u.shared_bus_user.client || !user->inputs)
5925 /* Dual cbus on Tegra12 */
5926 src_bus = user->inputs[0].input;
5927 dst_bus = user->inputs[1].input;
5929 if (!src_bus->u.cbus.top_user && !dst_bus->u.cbus.top_user)
5932 /* Make sure top user on the source bus is requesting highest rate */
5933 if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
5934 bus_user_request_is_lower(src_bus->u.cbus.top_user,
5935 dst_bus->u.cbus.top_user)))
5936 swap(src_bus, dst_bus);
5938 /* If top user is the slow one on its own (source) bus, do nothing */
5939 top_user = src_bus->u.cbus.top_user;
5940 BUG_ON(!top_user->u.shared_bus_user.client);
5941 if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
5944 /* If source bus top user is slower than all users on destination bus,
5945 move top user; otherwise move all users slower than the top one */
5946 if (!dst_bus->u.cbus.slow_user ||
5947 !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
5948 cbus_move_enabled_user(top_user, dst_bus, src_bus);
5950 list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
5951 c = list_entry(pos, struct clk, u.shared_bus_user.node);
5952 if (c->u.shared_bus_user.enabled &&
5953 c->u.shared_bus_user.client &&
5954 bus_user_is_slower(c, top_user))
5955 cbus_move_enabled_user(c, dst_bus, src_bus);
5959 /* Update destination bus 1st (move clients), then source */
5960 tegra_clk_shared_bus_update(dst_bus);
5961 tegra_clk_shared_bus_update(src_bus);
5966 static struct clk_ops tegra_clk_cbus_ops = {
5967 .init = tegra12_clk_cbus_init,
5968 .enable = tegra12_clk_cbus_enable,
5969 .set_rate = tegra12_clk_cbus_set_rate,
5970 .round_rate = tegra12_clk_cbus_round_rate,
5971 .round_rate_updown = tegra12_clk_cbus_round_updown,
5972 .shared_bus_update = tegra12_clk_cbus_update,
5975 /* shared bus ops */
5977 * Some clocks may have multiple downstream users that need to request a
5978 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
5979 * clock to each user. The frequency of the bus is set to the highest
5980 * enabled shared_bus_user clock, with a minimum value set by the
5983 * Optionally shared bus may support users migration. Since shared bus and
5984 * its * children (users) have reversed rate relations: user rates determine
5985 * bus rate, * switching user from one parent/bus to another may change rates
5986 * of both parents. Therefore we need a cross-bus lock on top of individual
5987 * user and bus locks. For now, limit bus switch support to cbus only if
5988 * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
5991 static unsigned long tegra12_clk_shared_bus_update(struct clk *bus,
5992 struct clk **bus_top, struct clk **bus_slow, unsigned long *rate_cap)
5995 struct clk *slow = NULL;
5996 struct clk *top = NULL;
5998 unsigned long override_rate = 0;
5999 unsigned long top_rate = 0;
6000 unsigned long rate = bus->min_rate;
6001 unsigned long bw = 0;
6002 unsigned long iso_bw = 0;
6003 unsigned long ceiling = bus->max_rate;
6004 unsigned long ceiling_but_iso = bus->max_rate;
6005 u32 usage_flags = 0;
6006 bool rate_set = false;
6008 list_for_each_entry(c, &bus->shared_bus_list,
6009 u.shared_bus_user.node) {
6010 bool cap_user = (c->u.shared_bus_user.mode == SHARED_CEILING) ||
6011 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO);
6013 * Ignore requests from disabled floor and bw users, and from
6014 * auto-users riding the bus. Always honor ceiling users, even
6015 * if they are disabled - we do not want to keep enabled parent
6016 * bus just because ceiling is set. Ignore SCLK/AHB/APB dividers
6017 * to propagate flat max request.
6019 if (c->u.shared_bus_user.enabled || cap_user) {
6020 unsigned long request_rate = c->u.shared_bus_user.rate;
6021 if (!(c->flags & DIV_BUS))
6022 request_rate *= c->div ? : 1;
6023 usage_flags |= c->u.shared_bus_user.usage_flag;
6025 if (!(c->flags & BUS_RATE_LIMIT))
6028 switch (c->u.shared_bus_user.mode) {
6030 iso_bw += request_rate;
6031 if (iso_bw > bus->max_rate)
6032 iso_bw = bus->max_rate;
6036 if (bw > bus->max_rate)
6039 case SHARED_CEILING_BUT_ISO:
6041 min(request_rate, ceiling_but_iso);
6043 case SHARED_CEILING:
6044 ceiling = min(request_rate, ceiling);
6046 case SHARED_OVERRIDE:
6047 if (override_rate == 0)
6048 override_rate = request_rate;
6054 rate = max(request_rate, rate);
6055 if (c->u.shared_bus_user.client
6057 if (top_rate < request_rate) {
6058 top_rate = request_rate;
6060 } else if ((top_rate == request_rate) &&
6061 bus_user_is_slower(c, top)) {
6066 if (c->u.shared_bus_user.client &&
6067 (!slow || bus_user_is_slower(c, slow)))
6072 if (bus->flags & PERIPH_EMC_ENB) {
6073 unsigned long iso_bw_min;
6074 bw = tegra_emc_apply_efficiency(
6075 bw, iso_bw, bus->max_rate, usage_flags, &iso_bw_min);
6076 if (bus->ops && bus->ops->round_rate)
6077 iso_bw_min = bus->ops->round_rate(bus, iso_bw_min);
6078 ceiling_but_iso = max(ceiling_but_iso, iso_bw_min);
6081 rate = override_rate ? : max(rate, bw);
6082 ceiling = min(ceiling, ceiling_but_iso);
6083 ceiling = override_rate ? bus->max_rate : ceiling;
6084 bus->override_rate = override_rate;
6086 if (bus_top && bus_slow && rate_cap) {
6087 /* If dynamic bus dvfs table, let the caller to complete
6088 rounding and aggregation */
6091 *rate_cap = ceiling;
6094 * If satic bus dvfs table, complete rounding and aggregation.
6095 * In case when no user requested bus rate, and bus retention
6096 * is enabled, don't scale down - keep current rate.
6098 if (!rate_set && (bus->shared_bus_flags & SHARED_BUS_RETENTION))
6099 rate = clk_get_rate_locked(bus);
6100 rate = tegra12_clk_cap_shared_bus(bus, rate, ceiling);
6106 static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
6107 unsigned long rate, unsigned long ceiling)
6109 if (bus->ops && bus->ops->round_rate_updown)
6110 ceiling = bus->ops->round_rate_updown(bus, ceiling, false);
6112 rate = min(rate, ceiling);
6114 if (bus->ops && bus->ops->round_rate)
6115 rate = bus->ops->round_rate(bus, rate);
6120 static int tegra_clk_shared_bus_migrate_users(struct clk *user)
6122 if (detach_shared_bus)
6125 /* Only cbus migration is supported */
6126 if (user->flags & PERIPH_ON_CBUS)
6127 return tegra12_clk_cbus_migrate_users(user);
6131 static void tegra_clk_shared_bus_user_init(struct clk *c)
6133 c->max_rate = c->parent->max_rate;
6134 c->u.shared_bus_user.rate = c->parent->max_rate;
6138 if ((c->u.shared_bus_user.mode == SHARED_CEILING) ||
6139 (c->u.shared_bus_user.mode == SHARED_CEILING_BUT_ISO)) {
6144 if (c->u.shared_bus_user.client_id) {
6145 struct clk *client =
6146 tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
6148 pr_err("%s: could not find clk %s\n", __func__,
6149 c->u.shared_bus_user.client_id);
6153 if ((client->state == ON) && !(client->flags & PERIPH_NO_ENB))
6154 pr_info("%s: %s client %s left ON\n", __func__,
6155 c->parent->name, client->name);
6157 c->u.shared_bus_user.client = client;
6158 c->u.shared_bus_user.client->flags |=
6159 c->parent->flags & PERIPH_ON_CBUS;
6160 c->flags |= c->parent->flags & PERIPH_ON_CBUS;
6161 c->div = c->u.shared_bus_user.client_div ? : 1;
6165 list_add_tail(&c->u.shared_bus_user.node,
6166 &c->parent->shared_bus_list);
6169 static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
6172 const struct clk_mux_sel *sel;
6174 if (detach_shared_bus)
6180 if (!(c->inputs && c->cross_clk_mutex && clk_cansleep(c)))
6183 for (sel = c->inputs; sel->input != NULL; sel++) {
6184 if (sel->input == p)
6193 list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
6194 ret = tegra_clk_shared_bus_update(p);
6196 list_move_tail(&c->u.shared_bus_user.node,
6197 &c->parent->shared_bus_list);
6198 tegra_clk_shared_bus_update(c->parent);
6203 tegra_clk_shared_bus_update(c->parent);
6206 clk_disable(c->parent);
6213 static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
6217 c->u.shared_bus_user.rate = rate;
6218 ret = tegra_clk_shared_bus_update(c->parent);
6220 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
6221 tegra_clk_shared_bus_migrate_users(c);
6226 static long tegra_clk_shared_bus_user_round_rate(
6227 struct clk *c, unsigned long rate)
6230 * Defer rounding requests until aggregated. BW users must not be
6231 * rounded at all, others just clipped to bus range (some clients
6232 * may use round api to find limits). Ignore SCLK/AHB and AHB/APB
6233 * dividers to keep flat bus requests propagation.
6235 if ((c->u.shared_bus_user.mode != SHARED_BW) &&
6236 (c->u.shared_bus_user.mode != SHARED_ISO_BW)) {
6237 if (!(c->flags & DIV_BUS) && (c->div > 1))
6240 if (rate > c->parent->max_rate)
6241 rate = c->parent->max_rate;
6242 else if (rate < c->parent->min_rate)
6243 rate = c->parent->min_rate;
6245 if (!(c->flags & DIV_BUS) && (c->div > 1))
6251 static int tegra_clk_shared_bus_user_enable(struct clk *c)
6255 c->u.shared_bus_user.enabled = true;
6256 ret = tegra_clk_shared_bus_update(c->parent);
6257 if (!ret && c->u.shared_bus_user.client)
6258 ret = clk_enable(c->u.shared_bus_user.client);
6260 if (!ret && c->cross_clk_mutex && clk_cansleep(c))
6261 tegra_clk_shared_bus_migrate_users(c);
6266 static void tegra_clk_shared_bus_user_disable(struct clk *c)
6268 if (c->u.shared_bus_user.client)
6269 clk_disable(c->u.shared_bus_user.client);
6270 c->u.shared_bus_user.enabled = false;
6271 tegra_clk_shared_bus_update(c->parent);
6273 if (c->cross_clk_mutex && clk_cansleep(c))
6274 tegra_clk_shared_bus_migrate_users(c);
6277 static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
6279 if (c->u.shared_bus_user.client) {
6280 if (c->u.shared_bus_user.client->ops &&
6281 c->u.shared_bus_user.client->ops->reset)
6282 c->u.shared_bus_user.client->ops->reset(
6283 c->u.shared_bus_user.client, assert);
6287 static struct clk_ops tegra_clk_shared_bus_user_ops = {
6288 .init = tegra_clk_shared_bus_user_init,
6289 .enable = tegra_clk_shared_bus_user_enable,
6290 .disable = tegra_clk_shared_bus_user_disable,
6291 .set_parent = tegra_clk_shared_bus_user_set_parent,
6292 .set_rate = tegra_clk_shared_bus_user_set_rate,
6293 .round_rate = tegra_clk_shared_bus_user_round_rate,
6294 .reset = tegra_clk_shared_bus_user_reset,
6297 /* shared bus connector ops (user/bus connector to cascade shared buses) */
6298 static int tegra12_clk_shared_connector_update(struct clk *bus)
6300 unsigned long rate, old_rate;
6302 if (detach_shared_bus)
6305 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
6307 old_rate = clk_get_rate_locked(bus);
6308 if (rate == old_rate)
6311 return clk_set_rate_locked(bus, rate);
6314 static struct clk_ops tegra_clk_shared_connector_ops = {
6315 .init = tegra_clk_shared_bus_user_init,
6316 .enable = tegra_clk_shared_bus_user_enable,
6317 .disable = tegra_clk_shared_bus_user_disable,
6318 .set_parent = tegra_clk_shared_bus_user_set_parent,
6319 .set_rate = tegra_clk_shared_bus_user_set_rate,
6320 .round_rate = tegra_clk_shared_bus_user_round_rate,
6321 .reset = tegra_clk_shared_bus_user_reset,
6322 .shared_bus_update = tegra12_clk_shared_connector_update,
6325 /* coupled gate ops */
6327 * Some clocks may have common enable/disable control, but run at different
6328 * rates, and have different dvfs tables. Coupled gate clock synchronize
6329 * enable/disable operations for such clocks.
6332 static int tegra12_clk_coupled_gate_enable(struct clk *c)
6335 const struct clk_mux_sel *sel;
6338 pr_debug("%s on clock %s\n", __func__, c->name);
6340 for (sel = c->inputs; sel->input != NULL; sel++) {
6341 if (sel->input == c->parent)
6344 ret = clk_enable(sel->input);
6346 while (sel != c->inputs) {
6348 if (sel->input == c->parent)
6350 clk_disable(sel->input);
6356 return tegra12_periph_clk_enable(c);
6359 static void tegra12_clk_coupled_gate_disable(struct clk *c)
6361 const struct clk_mux_sel *sel;
6364 pr_debug("%s on clock %s\n", __func__, c->name);
6366 tegra12_periph_clk_disable(c);
6368 if (!c->refcnt) /* happens only on boot clean-up: don't propagate */
6371 for (sel = c->inputs; sel->input != NULL; sel++) {
6372 if (sel->input == c->parent)
6375 if (sel->input->set) /* enforce coupling after boot only */
6376 clk_disable(sel->input);
6380 static struct clk_ops tegra_clk_coupled_gate_ops = {
6381 .init = tegra12_periph_clk_init,
6382 .enable = tegra12_clk_coupled_gate_enable,
6383 .disable = tegra12_clk_coupled_gate_disable,
6384 .reset = &tegra12_periph_clk_reset,
6389 * AHB and APB shared bus operations
6390 * APB shared bus is a user of AHB shared bus
6391 * AHB shared bus is a user of SCLK complex shared bus
6392 * SCLK/AHB and AHB/APB dividers can be dynamically changed. When AHB and APB
6393 * users requests are propagated to SBUS target rate, current values of the
6394 * dividers are ignored, and flat maximum request is selected as SCLK bus final
6395 * target. Then the dividers will be re-evaluated, based on AHB and APB targets.
6396 * Both AHB and APB buses are always enabled.
6398 static void tegra12_clk_ahb_apb_init(struct clk *c, struct clk *bus_clk)
6400 tegra_clk_shared_bus_user_init(c);
6401 c->max_rate = bus_clk->max_rate;
6402 c->min_rate = bus_clk->min_rate;
6403 c->mul = bus_clk->mul;
6404 c->div = bus_clk->div;
6406 c->u.shared_bus_user.rate = clk_get_rate(bus_clk);
6407 c->u.shared_bus_user.enabled = true;
6408 c->parent->child_bus = c;
6411 static void tegra12_clk_ahb_init(struct clk *c)
6413 struct clk *bus_clk = c->parent->u.system.hclk;
6414 tegra12_clk_ahb_apb_init(c, bus_clk);
6417 static void tegra12_clk_apb_init(struct clk *c)
6419 struct clk *bus_clk = c->parent->parent->u.system.pclk;
6420 tegra12_clk_ahb_apb_init(c, bus_clk);
6423 static int tegra12_clk_ahb_apb_update(struct clk *bus)
6427 if (detach_shared_bus)
6430 rate = tegra12_clk_shared_bus_update(bus, NULL, NULL, NULL);
6431 return clk_set_rate_locked(bus, rate);
6434 static struct clk_ops tegra_clk_ahb_ops = {
6435 .init = tegra12_clk_ahb_init,
6436 .set_rate = tegra_clk_shared_bus_user_set_rate,
6437 .round_rate = tegra_clk_shared_bus_user_round_rate,
6438 .shared_bus_update = tegra12_clk_ahb_apb_update,
6441 static struct clk_ops tegra_clk_apb_ops = {
6442 .init = tegra12_clk_apb_init,
6443 .set_rate = tegra_clk_shared_bus_user_set_rate,
6444 .round_rate = tegra_clk_shared_bus_user_round_rate,
6445 .shared_bus_update = tegra12_clk_ahb_apb_update,
6448 /* Clock definitions */
6449 static struct clk tegra_clk_32k = {
6456 static struct clk tegra_clk_m = {
6458 .flags = ENABLE_ON_INIT,
6459 .ops = &tegra_clk_m_ops,
6460 .max_rate = 48000000,
6463 static struct clk tegra_clk_m_div2 = {
6464 .name = "clk_m_div2",
6465 .ops = &tegra_clk_m_div_ops,
6466 .parent = &tegra_clk_m,
6470 .max_rate = 24000000,
6473 static struct clk tegra_clk_m_div4 = {
6474 .name = "clk_m_div4",
6475 .ops = &tegra_clk_m_div_ops,
6476 .parent = &tegra_clk_m,
6480 .max_rate = 12000000,
6483 static struct clk tegra_pll_ref = {
6485 .flags = ENABLE_ON_INIT,
6486 .ops = &tegra_pll_ref_ops,
6487 .parent = &tegra_clk_m,
6488 .max_rate = 26000000,
6491 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
6492 { 12000000, 600000000, 100, 1, 2},
6493 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6494 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6495 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6496 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6497 { 0, 0, 0, 0, 0, 0 },
6500 static struct clk tegra_pll_c = {
6502 .ops = &tegra_pllxc_ops,
6504 .parent = &tegra_pll_ref,
6505 .max_rate = 1400000000,
6507 .input_min = 12000000,
6508 .input_max = 800000000,
6510 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6511 .vco_min = 600000000,
6512 .vco_max = 1400000000,
6513 .freq_table = tegra_pll_c_freq_table,
6515 .misc1 = 0x88 - 0x80,
6516 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
6520 static struct clk tegra_pll_c_out1 = {
6521 .name = "pll_c_out1",
6522 .ops = &tegra_pll_div_ops,
6523 #ifdef CONFIG_TEGRA_DUAL_CBUS
6526 .flags = DIV_U71 | PERIPH_ON_CBUS,
6528 .parent = &tegra_pll_c,
6531 .max_rate = 700000000,
6534 static struct clk_pll_freq_table tegra_pll_cx_freq_table[] = {
6535 { 12000000, 600000000, 100, 1, 2},
6536 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6537 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6538 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6539 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6540 { 0, 0, 0, 0, 0, 0 },
6543 static struct clk tegra_pll_c2 = {
6545 .ops = &tegra_pllcx_ops,
6546 .flags = PLL_ALT_MISC_REG,
6548 .parent = &tegra_pll_ref,
6549 .max_rate = 1200000000,
6551 .input_min = 12000000,
6552 .input_max = 48000000,
6555 .vco_min = 650000000,
6556 .vco_max = 1300000000,
6557 .freq_table = tegra_pll_cx_freq_table,
6559 .misc1 = 0x4f0 - 0x4e8,
6560 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
6564 static struct clk tegra_pll_c3 = {
6566 .ops = &tegra_pllcx_ops,
6567 .flags = PLL_ALT_MISC_REG,
6569 .parent = &tegra_pll_ref,
6570 .max_rate = 1200000000,
6572 .input_min = 12000000,
6573 .input_max = 48000000,
6576 .vco_min = 650000000,
6577 .vco_max = 1300000000,
6578 .freq_table = tegra_pll_cx_freq_table,
6580 .misc1 = 0x504 - 0x4fc,
6581 .round_p_to_pdiv = pllcx_round_p_to_pdiv,
6585 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
6586 { 12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
6587 { 13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
6588 { 16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
6589 { 19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
6590 { 26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
6591 { 0, 0, 0, 0, 0, 0 },
6594 static struct clk tegra_pll_m = {
6597 .ops = &tegra_pllm_ops,
6599 .parent = &tegra_pll_ref,
6600 .max_rate = 1200000000,
6602 .input_min = 12000000,
6603 .input_max = 500000000,
6605 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6606 .vco_min = 500000000,
6607 .vco_max = 1200000000,
6608 .freq_table = tegra_pll_m_freq_table,
6610 .misc1 = 0x98 - 0x90,
6611 .round_p_to_pdiv = pllm_round_p_to_pdiv,
6615 static struct clk tegra_pll_m_out1 = {
6616 .name = "pll_m_out1",
6617 .ops = &tegra_pll_div_ops,
6618 .flags = DIV_U71 | DIV_U71_INT,
6619 .parent = &tegra_pll_m,
6622 .max_rate = 1200000000,
6625 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
6626 { 12000000, 408000000, 816, 12, 2, 8},
6627 { 13000000, 408000000, 816, 13, 2, 8},
6628 { 16800000, 408000000, 680, 14, 2, 8},
6629 { 19200000, 408000000, 680, 16, 2, 8},
6630 { 26000000, 408000000, 816, 26, 2, 8},
6631 { 0, 0, 0, 0, 0, 0 },
6634 static struct clk tegra_pll_p = {
6636 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
6637 .ops = &tegra_pllp_ops,
6639 .parent = &tegra_pll_ref,
6640 .max_rate = 432000000,
6642 .input_min = 2000000,
6643 .input_max = 31000000,
6646 .vco_min = 200000000,
6647 .vco_max = 700000000,
6648 .freq_table = tegra_pll_p_freq_table,
6653 static struct clk tegra_pll_p_out1 = {
6654 .name = "pll_p_out1",
6655 .ops = &tegra_pll_div_ops,
6656 .flags = DIV_U71 | DIV_U71_FIXED,
6657 .parent = &tegra_pll_p,
6660 .max_rate = 432000000,
6663 static struct clk tegra_pll_p_out2 = {
6664 .name = "pll_p_out2",
6665 .ops = &tegra_pll_div_ops,
6666 .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
6667 .parent = &tegra_pll_p,
6670 .max_rate = 432000000,
6673 static struct clk tegra_pll_p_out3 = {
6674 .name = "pll_p_out3",
6675 .ops = &tegra_pll_div_ops,
6676 .flags = DIV_U71 | DIV_U71_FIXED,
6677 .parent = &tegra_pll_p,
6680 .max_rate = 432000000,
6683 static struct clk tegra_pll_p_out4 = {
6684 .name = "pll_p_out4",
6685 .ops = &tegra_pll_div_ops,
6686 .flags = DIV_U71 | DIV_U71_FIXED,
6687 .parent = &tegra_pll_p,
6690 .max_rate = 432000000,
6693 static struct clk tegra_pll_p_out5 = {
6694 .name = "pll_p_out5",
6695 .ops = &tegra_pll_div_ops,
6696 .flags = DIV_U71 | DIV_U71_FIXED,
6697 .parent = &tegra_pll_p,
6700 .max_rate = 432000000,
6703 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
6704 { 9600000, 282240000, 147, 5, 1, 4},
6705 { 9600000, 368640000, 192, 5, 1, 4},
6706 { 9600000, 240000000, 200, 8, 1, 8},
6708 { 28800000, 282240000, 245, 25, 1, 8},
6709 { 28800000, 368640000, 320, 25, 1, 8},
6710 { 28800000, 240000000, 200, 24, 1, 8},
6711 { 0, 0, 0, 0, 0, 0 },
6714 static struct clk tegra_pll_a = {
6716 .flags = PLL_HAS_CPCON,
6717 .ops = &tegra_pll_ops,
6719 .parent = &tegra_pll_p_out1,
6720 .max_rate = 700000000,
6722 .input_min = 2000000,
6723 .input_max = 31000000,
6726 .vco_min = 200000000,
6727 .vco_max = 700000000,
6728 .freq_table = tegra_pll_a_freq_table,
6733 static struct clk tegra_pll_a_out0 = {
6734 .name = "pll_a_out0",
6735 .ops = &tegra_pll_div_ops,
6737 .parent = &tegra_pll_a,
6740 .max_rate = 100000000,
6743 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
6744 { 12000000, 216000000, 864, 12, 4, 12},
6745 { 13000000, 216000000, 864, 13, 4, 12},
6746 { 16800000, 216000000, 720, 14, 4, 12},
6747 { 19200000, 216000000, 720, 16, 4, 12},
6748 { 26000000, 216000000, 864, 26, 4, 12},
6750 { 12000000, 594000000, 99, 2, 1, 8},
6751 { 13000000, 594000000, 594, 13, 1, 12},
6752 { 16800000, 594000000, 495, 14, 1, 12},
6753 { 19200000, 594000000, 495, 16, 1, 12},
6754 { 26000000, 594000000, 594, 26, 1, 12},
6756 { 12000000, 1000000000, 1000, 12, 1, 12},
6757 { 13000000, 1000000000, 1000, 13, 1, 12},
6758 { 19200000, 1000000000, 625, 12, 1, 12},
6759 { 26000000, 1000000000, 1000, 26, 1, 12},
6761 { 0, 0, 0, 0, 0, 0 },
6764 static struct clk tegra_pll_d = {
6766 .flags = PLL_HAS_CPCON | PLLD,
6767 .ops = &tegra_plld_ops,
6769 .parent = &tegra_pll_ref,
6770 .max_rate = 1500000000,
6772 .input_min = 2000000,
6773 .input_max = 40000000,
6776 .vco_min = 500000000,
6777 .vco_max = 1500000000,
6778 .freq_table = tegra_pll_d_freq_table,
6783 static struct clk tegra_pll_d_out0 = {
6784 .name = "pll_d_out0",
6785 .ops = &tegra_pll_div_ops,
6786 .flags = DIV_2 | PLLD,
6787 .parent = &tegra_pll_d,
6788 .max_rate = 750000000,
6791 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
6792 { 12000000, 480000000, 960, 12, 2, 12},
6793 { 13000000, 480000000, 960, 13, 2, 12},
6794 { 16800000, 480000000, 400, 7, 2, 5},
6795 { 19200000, 480000000, 200, 4, 2, 3},
6796 { 26000000, 480000000, 960, 26, 2, 12},
6797 { 0, 0, 0, 0, 0, 0 },
6800 static struct clk tegra_pll_u = {
6802 .flags = PLL_HAS_CPCON | PLLU,
6803 .ops = &tegra_pll_ops,
6805 .parent = &tegra_pll_ref,
6806 .max_rate = 480000000,
6808 .input_min = 2000000,
6809 .input_max = 40000000,
6812 .vco_min = 480000000,
6813 .vco_max = 960000000,
6814 .freq_table = tegra_pll_u_freq_table,
6819 static struct clk tegra_pll_u_480M = {
6820 .name = "pll_u_480M",
6822 .ops = &tegra_pll_div_ops,
6825 .parent = &tegra_pll_u,
6828 .max_rate = 480000000,
6831 static struct clk tegra_pll_u_60M = {
6832 .name = "pll_u_60M",
6834 .ops = &tegra_pll_div_ops,
6837 .parent = &tegra_pll_u,
6840 .max_rate = 60000000,
6843 static struct clk tegra_pll_u_48M = {
6844 .name = "pll_u_48M",
6846 .ops = &tegra_pll_div_ops,
6849 .parent = &tegra_pll_u,
6852 .max_rate = 48000000,
6855 static struct clk tegra_pll_u_12M = {
6856 .name = "pll_u_12M",
6858 .ops = &tegra_pll_div_ops,
6861 .parent = &tegra_pll_u,
6864 .max_rate = 12000000,
6867 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
6869 { 12000000, 1000000000, 83, 1, 1}, /* actual: 996.0 MHz */
6870 { 13000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
6871 { 16800000, 1000000000, 59, 1, 1}, /* actual: 991.2 MHz */
6872 { 19200000, 1000000000, 52, 1, 1}, /* actual: 998.4 MHz */
6873 { 26000000, 1000000000, 76, 2, 1}, /* actual: 988.0 MHz */
6875 { 0, 0, 0, 0, 0, 0 },
6878 static struct clk tegra_pll_x = {
6880 .flags = PLL_ALT_MISC_REG | PLLX,
6881 .ops = &tegra_pllxc_ops,
6882 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
6887 .parent = &tegra_pll_ref,
6888 .max_rate = 3000000000UL,
6890 .input_min = 12000000,
6891 .input_max = 800000000,
6893 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
6894 .vco_min = 1200000000,
6895 .vco_max = 3000000000UL,
6896 .freq_table = tegra_pll_x_freq_table,
6898 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
6899 .misc1 = 0x510 - 0xe0,
6903 .round_p_to_pdiv = pllxc_round_p_to_pdiv,
6907 static struct clk tegra_pll_x_out0 = {
6908 .name = "pll_x_out0",
6909 .ops = &tegra_pll_div_ops,
6910 .flags = DIV_2 | PLLX,
6911 .parent = &tegra_pll_x,
6912 .max_rate = 1500000000UL,
6915 static struct clk tegra_dfll_cpu = {
6918 .ops = &tegra_dfll_ops,
6919 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
6924 .max_rate = 3000000000UL,
6927 static struct clk_pll_freq_table tegra_pllc4_freq_table[] = {
6928 { 12000000, 600000000, 100, 1, 2},
6929 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
6930 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
6931 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
6932 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
6933 { 0, 0, 0, 0, 0, 0 },
6936 static struct clk tegra_pll_c4 = {
6938 .flags = PLL_ALT_MISC_REG,
6939 .ops = &tegra_pllss_ops,
6941 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
6942 .max_rate = 600000000,
6944 .input_min = 12000000,
6945 .input_max = 1000000000,
6947 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6948 .vco_min = 600000000,
6949 .vco_max = 1200000000,
6950 .freq_table = tegra_pllc4_freq_table,
6953 .round_p_to_pdiv = pllss_round_p_to_pdiv,
6958 static struct clk_pll_freq_table tegra_plldp_freq_table[] = {
6959 { 12000000, 270000000, 90, 1, 4},
6960 { 13000000, 270000000, 83, 1, 4}, /* actual: 269.8 MHz */
6961 { 16800000, 270000000, 96, 1, 6}, /* actual: 268.8 MHz */
6962 { 19200000, 270000000, 84, 1, 6}, /* actual: 268.8 MHz */
6963 { 26000000, 270000000, 83, 2, 4}, /* actual: 269.8 MHz */
6964 { 0, 0, 0, 0, 0, 0 },
6967 static struct clk tegra_pll_dp = {
6969 .flags = PLL_ALT_MISC_REG,
6970 .ops = &tegra_pllss_ops,
6972 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
6973 .max_rate = 600000000,
6975 .input_min = 12000000,
6976 .input_max = 1000000000,
6978 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
6979 .vco_min = 600000000,
6980 .vco_max = 1200000000,
6981 .freq_table = tegra_plldp_freq_table,
6984 .round_p_to_pdiv = pllss_round_p_to_pdiv,
6989 static struct clk_pll_freq_table tegra_plld2_freq_table[] = {
6990 { 12000000, 594000000, 99, 1, 2, 3}, /*4kx2k @ 30Hz*/
6991 { 12000000, 297000000, 99, 1, 4, 1}, /*1080p @ 60Hz*/
6992 { 12000000, 148500000, 99, 1, 8, 1}, /* 720p @ 60Hz*/
6993 { 12000000, 54000000, 54, 1, 6, 1}, /* 480p @ 60Hz*/
6994 { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */
6995 { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */
6996 { 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */
6997 { 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */
6998 { 0, 0, 0, 0, 0, 0 },
7001 static struct clk tegra_pll_d2 = {
7003 .flags = PLL_ALT_MISC_REG,
7004 .ops = &tegra_pllss_ops,
7006 .parent = &tegra_pll_ref, /* s/w policy, always tegra_pll_ref */
7007 .max_rate = 600000000,
7009 .input_min = 12000000,
7010 .input_max = 1000000000,
7012 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
7013 .vco_min = 600000000,
7014 .vco_max = 1200000000,
7015 .freq_table = tegra_plld2_freq_table,
7017 .misc1 = 0x570 - 0x4b8,
7018 .round_p_to_pdiv = pllss_round_p_to_pdiv,
7023 static struct clk tegra_pll_re_vco = {
7024 .name = "pll_re_vco",
7025 .flags = PLL_ALT_MISC_REG,
7026 .ops = &tegra_pllre_ops,
7028 .parent = &tegra_pll_ref,
7029 .max_rate = 672000000,
7031 .input_min = 12000000,
7032 .input_max = 1000000000,
7034 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
7035 .vco_min = 300000000,
7036 .vco_max = 672000000,
7038 .round_p_to_pdiv = pllre_round_p_to_pdiv,
7042 static struct clk tegra_pll_re_out = {
7043 .name = "pll_re_out",
7044 .ops = &tegra_pllre_out_ops,
7045 .parent = &tegra_pll_re_vco,
7047 .max_rate = 672000000,
7050 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
7051 /* PLLE special case: use cpcon field to store cml divider value */
7052 { 336000000, 100000000, 100, 21, 16, 11},
7053 { 312000000, 100000000, 200, 26, 24, 13},
7054 { 13000000, 100000000, 200, 1, 26, 13},
7055 { 12000000, 100000000, 200, 1, 24, 13},
7056 { 0, 0, 0, 0, 0, 0 },
7059 static struct clk tegra_pll_e = {
7061 .flags = PLL_ALT_MISC_REG,
7062 .ops = &tegra_plle_ops,
7064 .max_rate = 100000000,
7066 .input_min = 12000000,
7067 .input_max = 1000000000,
7070 .vco_min = 1600000000,
7071 .vco_max = 2400000000U,
7072 .freq_table = tegra_pll_e_freq_table,
7074 .fixed_rate = 100000000,
7080 static struct clk tegra_cml0_clk = {
7082 .parent = &tegra_pll_e,
7083 .ops = &tegra_cml_clk_ops,
7085 .max_rate = 100000000,
7091 static struct clk tegra_cml1_clk = {
7093 .parent = &tegra_pll_e,
7094 .ops = &tegra_cml_clk_ops,
7096 .max_rate = 100000000,
7102 static struct clk tegra_pciex_clk = {
7104 .parent = &tegra_pll_e,
7105 .ops = &tegra_pciex_clk_ops,
7106 .max_rate = 500000000,
7112 /* Audio sync clocks */
7113 #define SYNC_SOURCE(_id, _dev) \
7115 .name = #_id "_sync", \
7118 .con_id = "ext_audio_sync", \
7121 .max_rate = 24000000, \
7122 .ops = &tegra_sync_source_ops \
7124 static struct clk tegra_sync_source_list[] = {
7125 SYNC_SOURCE(spdif_in, tegra30-spdif),
7126 SYNC_SOURCE(i2s0, tegra30-i2s.0),
7127 SYNC_SOURCE(i2s1, tegra30-i2s.1),
7128 SYNC_SOURCE(i2s2, tegra30-i2s.2),
7129 SYNC_SOURCE(i2s3, tegra30-i2s.3),
7130 SYNC_SOURCE(i2s4, tegra30-i2s.4),
7131 SYNC_SOURCE(vimclk, vimclk),
7134 static struct clk_mux_sel mux_d_audio_clk[] = {
7135 { .input = &tegra_pll_a_out0, .value = 0},
7136 { .input = &tegra_pll_p, .value = 0x8000},
7137 { .input = &tegra_clk_m, .value = 0xc000},
7138 { .input = &tegra_sync_source_list[0], .value = 0xE000},
7139 { .input = &tegra_sync_source_list[1], .value = 0xE001},
7140 { .input = &tegra_sync_source_list[2], .value = 0xE002},
7141 { .input = &tegra_sync_source_list[3], .value = 0xE003},
7142 { .input = &tegra_sync_source_list[4], .value = 0xE004},
7143 { .input = &tegra_sync_source_list[5], .value = 0xE005},
7144 { .input = &tegra_pll_a_out0, .value = 0xE006},
7145 { .input = &tegra_sync_source_list[6], .value = 0xE007},
7149 static struct clk_mux_sel mux_audio_sync_clk[] =
7151 { .input = &tegra_sync_source_list[0], .value = 0},
7152 { .input = &tegra_sync_source_list[1], .value = 1},
7153 { .input = &tegra_sync_source_list[2], .value = 2},
7154 { .input = &tegra_sync_source_list[3], .value = 3},
7155 { .input = &tegra_sync_source_list[4], .value = 4},
7156 { .input = &tegra_sync_source_list[5], .value = 5},
7157 { .input = &tegra_pll_a_out0, .value = 6},
7158 { .input = &tegra_sync_source_list[6], .value = 7},
7162 #define AUDIO_SYNC_CLK(_id, _dev, _index) \
7167 .con_id = "audio_sync", \
7169 .inputs = mux_audio_sync_clk, \
7170 .reg = 0x4A0 + (_index) * 4, \
7171 .max_rate = 24000000, \
7172 .ops = &tegra_audio_sync_clk_ops \
7174 static struct clk tegra_clk_audio_list[] = {
7175 AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
7176 AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
7177 AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
7178 AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
7179 AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
7180 AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
7183 #define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
7185 .name = #_id "_2x", \
7188 .con_id = "audio_sync_2x" \
7190 .flags = PERIPH_NO_RESET, \
7191 .max_rate = 48000000, \
7192 .ops = &tegra_clk_double_ops, \
7194 .reg_shift = 24 + (_index), \
7195 .parent = &tegra_clk_audio_list[(_index)], \
7197 .clk_num = 113 + (_index), \
7200 static struct clk tegra_clk_audio_2x_list[] = {
7201 AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
7202 AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
7203 AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
7204 AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
7205 AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
7206 AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
7209 #define MUX_I2S_SPDIF(_id, _index) \
7210 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
7211 {.input = &tegra_pll_a_out0, .value = 0}, \
7212 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 2}, \
7213 {.input = &tegra_pll_p, .value = 4}, \
7214 {.input = &tegra_clk_m, .value = 6}, \
7217 MUX_I2S_SPDIF(audio0, 0);
7218 MUX_I2S_SPDIF(audio1, 1);
7219 MUX_I2S_SPDIF(audio2, 2);
7220 MUX_I2S_SPDIF(audio3, 3);
7221 MUX_I2S_SPDIF(audio4, 4);
7222 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
7224 /* External clock outputs (through PMC) */
7225 #define MUX_EXTERN_OUT(_id) \
7226 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
7227 {.input = &tegra_clk_m, .value = 0}, \
7228 {.input = &tegra_clk_m_div2, .value = 1}, \
7229 {.input = &tegra_clk_m_div4, .value = 2}, \
7230 {.input = NULL, .value = 3}, /* placeholder */ \
7237 static struct clk_mux_sel *mux_extern_out_list[] = {
7238 mux_clkm_clkm2_clkm4_extern1,
7239 mux_clkm_clkm2_clkm4_extern2,
7240 mux_clkm_clkm2_clkm4_extern3,
7243 #define CLK_OUT_CLK(_id, _max_rate) \
7245 .name = "clk_out_" #_id, \
7247 .dev_id = "clk_out_" #_id, \
7248 .con_id = "extern" #_id, \
7250 .ops = &tegra_clk_out_ops, \
7252 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
7253 .flags = MUX_CLK_OUT, \
7254 .max_rate = _max_rate, \
7256 .clk_num = (_id - 1) * 8 + 2, \
7259 static struct clk tegra_clk_out_list[] = {
7260 CLK_OUT_CLK(1, 26000000),
7261 CLK_OUT_CLK(2, 40800000),
7262 CLK_OUT_CLK(3, 26000000),
7265 /* called after peripheral external clocks are initialized */
7266 static void init_clk_out_mux(void)
7271 /* output clock con_id is the name of peripheral
7272 external clock connected to input 3 of the output mux */
7273 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
7274 c = tegra_get_clock_by_name(
7275 tegra_clk_out_list[i].lookup.con_id);
7277 pr_err("%s: could not find clk %s\n", __func__,
7278 tegra_clk_out_list[i].lookup.con_id);
7279 mux_extern_out_list[i][3].input = c;
7283 static struct clk_mux_sel mux_sclk[] = {
7284 { .input = &tegra_clk_m, .value = 0},
7285 { .input = &tegra_pll_c_out1, .value = 1},
7286 { .input = &tegra_pll_p_out4, .value = 2},
7287 { .input = &tegra_pll_p, .value = 3},
7288 { .input = &tegra_pll_p_out2, .value = 4},
7289 { .input = &tegra_pll_c, .value = 5},
7290 { .input = &tegra_clk_32k, .value = 6},
7291 { .input = &tegra_pll_m_out1, .value = 7},
7295 static struct clk tegra_clk_sclk = {
7299 .ops = &tegra_super_ops,
7300 .max_rate = 420000000,
7301 .min_rate = 12000000,
7304 /* Peripheral muxes */
7305 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
7306 static struct clk_mux_sel mux_cclk_g[] = {
7307 { .input = &tegra_clk_m, .value = 0},
7308 { .input = &tegra_pll_c, .value = 1},
7309 { .input = &tegra_clk_32k, .value = 2},
7310 { .input = &tegra_pll_m, .value = 3},
7311 { .input = &tegra_pll_p, .value = 4},
7312 { .input = &tegra_pll_p_out4, .value = 5},
7313 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra12x */
7314 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra12x */
7315 { .input = &tegra_pll_x, .value = 8},
7316 { .input = &tegra_dfll_cpu, .value = 15},
7320 static struct clk_mux_sel mux_cclk_lp[] = {
7321 { .input = &tegra_clk_m, .value = 0},
7322 { .input = &tegra_pll_c, .value = 1},
7323 { .input = &tegra_clk_32k, .value = 2},
7324 { .input = &tegra_pll_m, .value = 3},
7325 { .input = &tegra_pll_p, .value = 4},
7326 { .input = &tegra_pll_p_out4, .value = 5},
7327 /* { .input = &tegra_pll_c2, .value = 6}, - no use on tegra12x */
7328 /* { .input = &tegra_clk_c3, .value = 7}, - no use on tegra12x */
7329 { .input = &tegra_pll_x_out0, .value = 8},
7330 { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS},
7335 static struct clk_mux_sel mux_cclk_g[] = {
7336 { .input = &tegra_clk_m, .value = 0},
7337 /* { .input = , .value = 1}, - testclk */
7338 { .input = &tegra_clk_m, .value = 2},
7339 { .input = &tegra_pll_ref, .value = 3},
7340 { .input = &tegra_pll_m, .value = 4},
7341 { .input = &tegra_pll_p, .value = 5},
7342 { .input = &tegra_clk_sclk, .value = 6},
7343 { .input = &tegra_clk_m, .value = 7},
7344 { .input = &tegra_pll_x, .value = 8},
7345 /* { .input = , .value = 9}, - High jitter DFLL */
7346 /* { .input = , .value = 14}, - High jitter PLLX */
7347 { .input = &tegra_dfll_cpu, .value = 15},
7353 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
7354 static struct clk tegra_clk_cclk_g = {
7356 .flags = DIV_U71 | DIV_U71_INT | MUX,
7357 .inputs = mux_cclk_g,
7359 .ops = &tegra_super_ops,
7360 .max_rate = 3000000000UL,
7363 static struct clk tegra_clk_cclk_lp = {
7365 .flags = DIV_2 | DIV_U71 | DIV_U71_INT | MUX,
7366 .inputs = mux_cclk_lp,
7368 .ops = &tegra_super_ops,
7369 .max_rate = 1350000000,
7373 static struct clk tegra_clk_cclk_g = {
7375 .flags = DIV_U71 | DIV_U71_INT | MUX,
7376 .inputs = mux_cclk_g,
7378 .ops = &tegra13_super_cclk_ops,
7379 .max_rate = 3000000000UL,
7384 static struct raw_notifier_head cpu_g_rate_change_nh;
7386 static struct clk tegra_clk_virtual_cpu_g = {
7388 .parent = &tegra_clk_cclk_g,
7389 .ops = &tegra_cpu_ops,
7390 .max_rate = 3000000000UL,
7391 .min_rate = 3187500,
7393 .main = &tegra_pll_x,
7394 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
7395 .backup = &tegra_pll_p_out4,
7397 .backup = &tegra_pll_p,
7399 .dynamic = &tegra_dfll_cpu,
7402 .rate_change_nh = &cpu_g_rate_change_nh,
7405 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
7406 static struct clk tegra_clk_virtual_cpu_lp = {
7408 .parent = &tegra_clk_cclk_lp,
7409 .ops = &tegra_cpu_ops,
7410 .max_rate = 1350000000,
7411 .min_rate = 3187500,
7413 .main = &tegra_pll_x,
7414 .backup = &tegra_pll_p_out4,
7420 static struct clk_mux_sel mux_cpu_cmplx[] = {
7421 { .input = &tegra_clk_virtual_cpu_g, .value = 0},
7422 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
7423 { .input = &tegra_clk_virtual_cpu_lp, .value = 1},
7428 static struct clk tegra_clk_cpu_cmplx = {
7430 .inputs = mux_cpu_cmplx,
7431 .ops = &tegra_cpu_cmplx_ops,
7432 .max_rate = 3000000000UL,
7435 static struct clk tegra_clk_cop = {
7437 .parent = &tegra_clk_sclk,
7438 .ops = &tegra_cop_ops,
7439 .max_rate = 408000000,
7442 static struct clk tegra_clk_hclk = {
7445 .parent = &tegra_clk_sclk,
7448 .ops = &tegra_bus_ops,
7449 .max_rate = 408000000,
7450 .min_rate = 12000000,
7453 static struct clk tegra_clk_pclk = {
7456 .parent = &tegra_clk_hclk,
7459 .ops = &tegra_bus_ops,
7460 .max_rate = 204000000,
7461 .min_rate = 12000000,
7464 static struct raw_notifier_head sbus_rate_change_nh;
7466 static struct clk tegra_clk_sbus_cmplx = {
7468 .parent = &tegra_clk_sclk,
7469 .ops = &tegra_sbus_cmplx_ops,
7471 .pclk = &tegra_clk_pclk,
7472 .hclk = &tegra_clk_hclk,
7473 .sclk_low = &tegra_pll_p_out2,
7474 #ifdef CONFIG_TEGRA_PLLM_SCALED
7475 .sclk_high = &tegra_pll_c_out1,
7477 .sclk_high = &tegra_pll_m_out1,
7480 .rate_change_nh = &sbus_rate_change_nh,
7483 static struct clk tegra_clk_ahb = {
7486 .parent = &tegra_clk_sbus_cmplx,
7487 .ops = &tegra_clk_ahb_ops,
7490 static struct clk tegra_clk_apb = {
7493 .parent = &tegra_clk_ahb,
7494 .ops = &tegra_clk_apb_ops,
7497 static struct clk tegra_clk_blink = {
7499 .parent = &tegra_clk_32k,
7501 .ops = &tegra_blink_clk_ops,
7506 /* Multimedia modules muxes */
7507 static struct clk_mux_sel mux_pllm_pllc2_c_c3_pllp_plla[] = {
7508 { .input = &tegra_pll_m, .value = 0},
7509 { .input = &tegra_pll_c2, .value = 1},
7510 { .input = &tegra_pll_c, .value = 2},
7511 { .input = &tegra_pll_c3, .value = 3},
7512 { .input = &tegra_pll_p, .value = 4},
7513 { .input = &tegra_pll_a_out0, .value = 6},
7517 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
7518 { .input = &tegra_pll_m, .value = 0},
7519 { .input = &tegra_pll_c, .value = 2},
7520 { .input = &tegra_pll_p, .value = 4},
7521 { .input = &tegra_pll_a_out0, .value = 6},
7525 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_v2[] = {
7526 { .input = &tegra_pll_m, .value = 0},
7527 { .input = &tegra_pll_c, .value = 1},
7528 { .input = &tegra_pll_p, .value = 2},
7529 { .input = &tegra_pll_a_out0, .value = 3},
7535 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
7536 { .input = &tegra_pll_m, .value = 0},
7537 { .input = &tegra_pll_c, .value = 1},
7538 { .input = &tegra_pll_p, .value = 2},
7539 { .input = &tegra_pll_a_out0, .value = 3},
7540 { .input = &tegra_pll_c2, .value = 4},
7541 { .input = &tegra_pll_c3, .value = 5},
7542 { .input = &tegra_clk_m, .value = 6},
7546 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_pllc4[] = {
7547 { .input = &tegra_pll_m, .value = 0},
7549 { .input = &tegra_pll_c, .value = 2},
7551 { .input = &tegra_pll_p, .value = 4},
7552 { .input = &tegra_pll_a_out0, .value = 6},
7553 { .input = &tegra_pll_c4, .value = 7},
7557 static struct clk_mux_sel mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
7558 { .input = &tegra_pll_m, .value = 0},
7559 { .input = &tegra_pll_c, .value = 1},
7560 { .input = &tegra_pll_p, .value = 2},
7561 { .input = &tegra_pll_a_out0, .value = 3},
7562 /* Skip C2(4) & C3(5) */
7563 { .input = &tegra_clk_m, .value = 6},
7564 { .input = &tegra_pll_c4, .value = 7},
7568 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
7569 { .input = &tegra_pll_a_out0, .value = 0},
7570 { .input = &tegra_pll_c, .value = 2},
7571 { .input = &tegra_pll_p, .value = 4},
7572 { .input = &tegra_clk_m, .value = 6},
7577 /* FIXME: add EMC latency mux */
7578 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
7579 { .input = &tegra_pll_m, .value = 0},
7580 { .input = &tegra_pll_c, .value = 1},
7581 { .input = &tegra_pll_p, .value = 2},
7582 { .input = &tegra_clk_m, .value = 3},
7583 { .input = &tegra_pll_m, .value = 4}, /* low jitter PLLM output */
7584 /* { .input = &tegra_pll_c2, .value = 5}, - no use on tegra12x */
7585 /* { .input = &tegra_pll_c3, .value = 6}, - no use on tegra12x */
7586 { .input = &tegra_pll_c, .value = 7}, /* low jitter PLLC output */
7591 /* Display subsystem muxes */
7592 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
7593 {.input = &tegra_pll_p, .value = 0},
7594 {.input = &tegra_pll_m, .value = 1},
7595 {.input = &tegra_pll_d_out0, .value = 2},
7596 {.input = &tegra_pll_a_out0, .value = 3},
7597 {.input = &tegra_pll_c, .value = 4},
7598 {.input = &tegra_pll_d2, .value = 5},
7599 {.input = &tegra_clk_m, .value = 6},
7603 static struct clk_mux_sel mux_plld_out0[] = {
7604 { .input = &tegra_pll_d_out0, .value = 0},
7608 /* Peripheral muxes */
7609 static struct clk_mux_sel mux_pllp_pllc_clkm[] = {
7610 {.input = &tegra_pll_p, .value = 0},
7611 {.input = &tegra_pll_c, .value = 2},
7612 {.input = &tegra_clk_m, .value = 6},
7616 static struct clk_mux_sel mux_pllp_pllc_clkm1[] = {
7617 {.input = &tegra_pll_p, .value = 0},
7618 {.input = &tegra_pll_c, .value = 1},
7619 {.input = &tegra_clk_m, .value = 3},
7623 static struct clk_mux_sel mux_pllp_pllc2_c_c3_pllm_clkm[] = {
7624 { .input = &tegra_pll_p, .value = 0},
7625 { .input = &tegra_pll_c2, .value = 1},
7626 { .input = &tegra_pll_c, .value = 2},
7627 { .input = &tegra_pll_c3, .value = 3},
7628 { .input = &tegra_pll_m, .value = 4},
7629 { .input = &tegra_clk_m, .value = 6},
7633 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
7634 { .input = &tegra_pll_p, .value = 0},
7635 { .input = &tegra_pll_c, .value = 2},
7636 { .input = &tegra_pll_m, .value = 4},
7637 { .input = &tegra_clk_m, .value = 6},
7641 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
7642 {.input = &tegra_pll_p, .value = 0},
7643 {.input = &tegra_pll_c, .value = 2},
7644 {.input = &tegra_pll_m, .value = 4},
7648 static struct clk_mux_sel mux_pllp_clkm_clk32_plle[] = {
7649 { .input = &tegra_pll_p, .value = 0},
7650 { .input = &tegra_clk_m, .value = 1},
7651 { .input = &tegra_clk_32k, .value = 2},
7652 { .input = &tegra_pll_e, .value = 3},
7656 static struct clk_mux_sel mux_pllp_clkm[] = {
7657 { .input = &tegra_pll_p, .value = 0},
7658 { .input = &tegra_clk_m, .value = 6},
7662 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
7663 {.input = &tegra_pll_p, .value = 0},
7664 {.input = &tegra_pll_c, .value = 2},
7665 {.input = &tegra_clk_32k, .value = 4},
7666 {.input = &tegra_clk_m, .value = 6},
7670 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
7671 {.input = &tegra_pll_p, .value = 0},
7672 {.input = &tegra_pll_c, .value = 2},
7673 {.input = &tegra_clk_m, .value = 4},
7674 {.input = &tegra_clk_32k, .value = 6},
7678 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
7679 { .input = &tegra_pll_a_out0, .value = 0},
7680 { .input = &tegra_clk_32k, .value = 1},
7681 { .input = &tegra_pll_p, .value = 2},
7682 { .input = &tegra_clk_m, .value = 3},
7683 { .input = &tegra_pll_e, .value = 4},
7687 static struct clk_mux_sel mux_clkm_pllp_pllc_pllre[] = {
7688 { .input = &tegra_clk_m, .value = 0},
7689 { .input = &tegra_pll_p, .value = 1},
7690 { .input = &tegra_pll_c, .value = 3},
7691 { .input = &tegra_pll_re_out, .value = 5},
7695 static struct clk_mux_sel mux_clkm_48M_pllp_480M[] = {
7696 { .input = &tegra_clk_m, .value = 0},
7697 { .input = &tegra_pll_u_48M, .value = 2},
7698 { .input = &tegra_pll_p, .value = 4},
7699 { .input = &tegra_pll_u_480M, .value = 6},
7703 static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
7704 { .input = &tegra_clk_m, .value = 0},
7705 { .input = &tegra_pll_re_out, .value = 1},
7706 { .input = &tegra_clk_32k, .value = 2},
7707 { .input = &tegra_pll_u_480M, .value = 3},
7708 { .input = &tegra_pll_c, .value = 4},
7709 { .input = &tegra_pll_ref, .value = 7},
7713 static struct clk_mux_sel mux_pllp3_pllc_clkm[] = {
7714 { .input = &tegra_pll_p_out3, .value = 0},
7715 { .input = &tegra_pll_c, .value = 1},
7716 { .input = &tegra_clk_m, .value = 3},
7720 /* Single clock source ("fake") muxes */
7721 static struct clk_mux_sel mux_clk_m[] = {
7722 { .input = &tegra_clk_m, .value = 0},
7726 static struct clk_mux_sel mux_pllp_out3[] = {
7727 { .input = &tegra_pll_p_out3, .value = 0},
7731 static struct clk_mux_sel mux_clk_32k[] = {
7732 { .input = &tegra_clk_32k, .value = 0},
7736 static struct clk_mux_sel mux_plld[] = {
7737 { .input = &tegra_pll_d_out0, .value = 1},
7742 static struct raw_notifier_head emc_rate_change_nh;
7744 static struct clk tegra_clk_emc = {
7746 .ops = &tegra_emc_clk_ops,
7748 .max_rate = 1200000000,
7749 .min_rate = 12750000,
7750 .inputs = mux_pllm_pllc_pllp_clkm,
7751 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
7755 .rate_change_nh = &emc_rate_change_nh,
7758 static struct clk tegra_clk_mc = {
7760 .ops = &tegra_mc_clk_ops,
7761 .max_rate = 533000000,
7762 .parent = &tegra_clk_emc,
7763 .flags = PERIPH_NO_RESET,
7769 static struct raw_notifier_head host1x_rate_change_nh;
7771 static struct clk tegra_clk_host1x = {
7776 .ops = &tegra_1xbus_clk_ops,
7778 .inputs = mux_pllm_pllc_pllp_plla,
7779 .flags = MUX | DIV_U71 | DIV_U71_INT,
7780 .max_rate = 500000000,
7781 .min_rate = 12000000,
7784 .pll_low = &tegra_pll_p,
7785 #ifdef CONFIG_TEGRA_PLLM_SCALED
7786 .pll_high = &tegra_pll_c,
7788 .pll_high = &tegra_pll_m,
7791 .rate_change_nh = &host1x_rate_change_nh,
7794 static struct raw_notifier_head mselect_rate_change_nh;
7796 static struct clk tegra_clk_mselect = {
7799 .dev_id = "mselect",
7801 .ops = &tegra_1xbus_clk_ops,
7803 .inputs = mux_pllp_clkm,
7804 .flags = MUX | DIV_U71 | DIV_U71_INT,
7805 .max_rate = 408000000,
7806 .min_rate = 12000000,
7809 .pll_low = &tegra_pll_p,
7810 .pll_high = &tegra_pll_p,
7811 .threshold = 408000000,
7813 .rate_change_nh = &mselect_rate_change_nh,
7816 #ifdef CONFIG_TEGRA_DUAL_CBUS
7818 static struct raw_notifier_head c2bus_rate_change_nh;
7819 static struct raw_notifier_head c3bus_rate_change_nh;
7821 static struct clk tegra_clk_c2bus = {
7823 .parent = &tegra_pll_c2,
7824 .ops = &tegra_clk_cbus_ops,
7825 .max_rate = 700000000,
7828 .flags = PERIPH_ON_CBUS,
7829 .shared_bus_backup = {
7830 .input = &tegra_pll_p,
7832 .rate_change_nh = &c2bus_rate_change_nh,
7834 static struct clk tegra_clk_c3bus = {
7836 .parent = &tegra_pll_c3,
7837 .ops = &tegra_clk_cbus_ops,
7838 .max_rate = 900000000,
7841 .flags = PERIPH_ON_CBUS,
7842 .shared_bus_backup = {
7843 .input = &tegra_pll_p,
7845 .rate_change_nh = &c3bus_rate_change_nh,
7848 #ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
7849 static DEFINE_MUTEX(cbus_mutex);
7850 #define CROSS_CBUS_MUTEX (&cbus_mutex)
7852 #define CROSS_CBUS_MUTEX NULL
7856 static struct clk_mux_sel mux_clk_cbus[] = {
7857 { .input = &tegra_clk_c2bus, .value = 0},
7858 { .input = &tegra_clk_c3bus, .value = 1},
7862 #define DUAL_CBUS_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
7869 .ops = &tegra_clk_shared_bus_user_ops, \
7870 .parent = _parent, \
7871 .inputs = mux_clk_cbus, \
7873 .u.shared_bus_user = { \
7875 .client_div = _div, \
7878 .cross_clk_mutex = CROSS_CBUS_MUTEX, \
7883 static struct raw_notifier_head cbus_rate_change_nh;
7885 static struct clk tegra_clk_cbus = {
7887 .parent = &tegra_pll_c,
7888 .ops = &tegra_clk_cbus_ops,
7889 .max_rate = 700000000,
7892 .flags = PERIPH_ON_CBUS,
7893 .shared_bus_backup = {
7894 .input = &tegra_pll_p,
7896 .rate_change_nh = &cbus_rate_change_nh,
7900 static struct clk_ops tegra_clk_gpu_ops = {
7901 .enable = &tegra12_periph_clk_enable,
7902 .disable = &tegra12_periph_clk_disable,
7903 .reset = &tegra12_periph_clk_reset,
7906 /* This is a dummy clock for gpu. The enable/disable/reset routine controls
7907 input clock of the actual gpu clock. The input clock itself has a fixed
7908 frequency. The actual gpu clock's frequency is controlled by gpu driver,
7909 not here in clock framework. However, we assoicate this dummy clock with
7910 dvfs to control voltage of gpu rail along with frequency change of actual
7911 gpu clock. So frequency here and in dvfs are based on the acutal gpu clock. */
7912 static struct clk tegra_clk_gpu = {
7914 .ops = &tegra_clk_gpu_ops,
7915 .parent = &tegra_pll_ref,
7919 .max_rate = 48000000,
7920 .min_rate = 12000000,
7923 #define RATE_GRANULARITY 100000 /* 0.1 MHz */
7924 #if defined(CONFIG_TEGRA_CLOCK_DEBUG_FUNC)
7925 static int gbus_round_pass_thru;
7926 void tegra_gbus_round_pass_thru_enable(bool enable)
7929 gbus_round_pass_thru = 1;
7931 gbus_round_pass_thru = 0;
7933 EXPORT_SYMBOL(tegra_gbus_round_pass_thru_enable);
7935 #define gbus_round_pass_thru 0
7938 static void tegra12_clk_gbus_init(struct clk *c)
7943 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7944 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7946 if (!c->u.export_clk.ops || !c->u.export_clk.ops->init)
7949 c->u.export_clk.ops->init(c->u.export_clk.ops->data, &rate, &enabled);
7950 c->div = clk_get_rate(c->parent) / RATE_GRANULARITY;
7951 c->mul = rate / RATE_GRANULARITY;
7952 c->state = enabled ? ON : OFF;
7955 static int tegra12_clk_gbus_enable(struct clk *c)
7957 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7958 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7960 if (!c->u.export_clk.ops || !c->u.export_clk.ops->enable)
7963 return c->u.export_clk.ops->enable(c->u.export_clk.ops->data);
7966 static void tegra12_clk_gbus_disable(struct clk *c)
7968 pr_debug("%s on clock %s (export ops %s)\n", __func__,
7969 c->name, c->u.export_clk.ops ? "ready" : "not ready");
7971 if (!c->u.export_clk.ops || !c->u.export_clk.ops->disable)
7974 c->u.export_clk.ops->disable(c->u.export_clk.ops->data);
7977 static int tegra12_clk_gbus_set_rate(struct clk *c, unsigned long rate)
7981 pr_debug("%s %lu on clock %s (export ops %s)\n", __func__,
7982 rate, c->name, c->u.export_clk.ops ? "ready" : "not ready");
7984 if (!c->u.export_clk.ops || !c->u.export_clk.ops->set_rate)
7987 ret = c->u.export_clk.ops->set_rate(c->u.export_clk.ops->data, &rate);
7989 c->mul = rate / RATE_GRANULARITY;
7993 static long tegra12_clk_gbus_round_updown(struct clk *c, unsigned long rate,
7996 return gbus_round_pass_thru ? rate :
7997 tegra12_clk_cbus_round_updown(c, rate, up);
8000 static long tegra12_clk_gbus_round_rate(struct clk *c, unsigned long rate)
8002 return tegra12_clk_gbus_round_updown(c, rate, true);
8005 static struct clk_ops tegra_clk_gbus_ops = {
8006 .init = tegra12_clk_gbus_init,
8007 .enable = tegra12_clk_gbus_enable,
8008 .disable = tegra12_clk_gbus_disable,
8009 .set_rate = tegra12_clk_gbus_set_rate,
8010 .round_rate = tegra12_clk_gbus_round_rate,
8011 .round_rate_updown = tegra12_clk_gbus_round_updown,
8012 .shared_bus_update = tegra12_clk_shared_connector_update, /* re-use */
8015 static struct raw_notifier_head gbus_rate_change_nh;
8017 static struct clk tegra_clk_gbus = {
8019 .ops = &tegra_clk_gbus_ops,
8020 .parent = &tegra_clk_gpu,
8021 .max_rate = 1032000000,
8022 .shared_bus_flags = SHARED_BUS_RETENTION,
8023 .rate_change_nh = &gbus_rate_change_nh,
8026 static void tegra12_camera_mclk_init(struct clk *c)
8031 if (!strcmp(c->name, "mclk")) {
8032 c->parent = tegra_get_clock_by_name("vi_sensor");
8033 c->max_rate = c->parent->max_rate;
8034 } else if (!strcmp(c->name, "mclk2")) {
8035 c->parent = tegra_get_clock_by_name("vi_sensor2");
8036 c->max_rate = c->parent->max_rate;
8040 static int tegra12_camera_mclk_set_rate(struct clk *c, unsigned long rate)
8042 return clk_set_rate(c->parent, rate);
8045 static struct clk_ops tegra_camera_mclk_ops = {
8046 .init = tegra12_camera_mclk_init,
8047 .enable = tegra12_periph_clk_enable,
8048 .disable = tegra12_periph_clk_disable,
8049 .set_rate = tegra12_camera_mclk_set_rate,
8052 static struct clk tegra_camera_mclk = {
8054 .ops = &tegra_camera_mclk_ops,
8056 .clk_num = 92, /* csus */
8058 .flags = PERIPH_NO_RESET,
8061 static struct clk tegra_camera_mclk2 = {
8063 .ops = &tegra_camera_mclk_ops,
8065 .clk_num = 171, /* vim2_clk */
8067 .flags = PERIPH_NO_RESET,
8070 static struct clk tegra_clk_isp = {
8072 .ops = &tegra_periph_clk_ops,
8074 .max_rate = 700000000,
8075 .inputs = mux_pllm_pllc_pllp_plla_clkm_pllc4,
8076 .flags = MUX | DIV_U71 | PERIPH_NO_ENB | PERIPH_NO_RESET,
8079 static struct clk_mux_sel mux_isp[] = {
8080 { .input = &tegra_clk_isp, .value = 0},
8084 static struct raw_notifier_head c4bus_rate_change_nh;
8086 static struct clk tegra_clk_c4bus = {
8088 .parent = &tegra_pll_c4,
8089 .ops = &tegra_clk_cbus_ops,
8090 .max_rate = 700000000,
8093 .shared_bus_backup = {
8094 .input = &tegra_pll_p,
8096 .rate_change_nh = &c4bus_rate_change_nh,
8099 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
8106 .ops = &tegra_periph_clk_ops, \
8108 .inputs = _inputs, \
8112 .clk_num = _clk_num, \
8116 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
8126 .inputs = _inputs, \
8130 .clk_num = _clk_num, \
8134 #define D_AUDIO_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
8141 .ops = &tegra_periph_clk_ops, \
8143 .inputs = _inputs, \
8147 .clk_num = _clk_num, \
8148 .src_mask = 0xE01F << 16, \
8153 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
8160 .ops = &tegra_clk_shared_bus_user_ops, \
8161 .parent = _parent, \
8162 .u.shared_bus_user = { \
8164 .client_div = _div, \
8168 #define SHARED_LIMIT(_name, _dev, _con, _parent, _id, _div, _mode)\
8175 .ops = &tegra_clk_shared_bus_user_ops, \
8176 .parent = _parent, \
8177 .flags = BUS_RATE_LIMIT, \
8178 .u.shared_bus_user = { \
8180 .client_div = _div, \
8184 #define SHARED_CONNECT(_name, _dev, _con, _parent, _id, _div, _mode)\
8191 .ops = &tegra_clk_shared_connector_ops, \
8192 .parent = _parent, \
8193 .u.shared_bus_user = { \
8195 .client_div = _div, \
8200 #define SHARED_EMC_CLK(_name, _dev, _con, _parent, _id, _div, _mode, _flag)\
8207 .ops = &tegra_clk_shared_bus_user_ops, \
8208 .parent = _parent, \
8209 .u.shared_bus_user = { \
8211 .client_div = _div, \
8213 .usage_flag = _flag, \
8217 static DEFINE_MUTEX(sbus_cross_mutex);
8218 #define SHARED_SCLK(_name, _dev, _con, _parent, _id, _div, _mode)\
8225 .ops = &tegra_clk_shared_bus_user_ops, \
8226 .parent = _parent, \
8227 .u.shared_bus_user = { \
8229 .client_div = _div, \
8232 .cross_clk_mutex = &sbus_cross_mutex, \
8235 struct clk tegra_list_clks[] = {
8236 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
8237 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
8238 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
8239 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
8240 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8241 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8242 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8243 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8244 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 24576000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8245 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 24576000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8246 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 24576000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8247 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 24576000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8248 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 24576000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8249 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 24576000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8250 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
8251 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 48000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8252 D_AUDIO_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
8253 D_AUDIO_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
8254 D_AUDIO_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
8255 D_AUDIO_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 40000000, mux_d_audio_clk, MUX | DIV_U71 | PERIPH_ON_APB),
8256 PERIPH_CLK("adx", "adx", NULL, 154, 0x638, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8257 PERIPH_CLK("adx1", "adx1", NULL, 180, 0x670, 24580000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8258 PERIPH_CLK("amx", "amx", NULL, 153, 0x63c, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8259 PERIPH_CLK("amx1", "amx1", NULL, 185, 0x674, 24600000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8260 PERIPH_CLK("afc0", "tegra124-afc.0", NULL, 186, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8261 PERIPH_CLK("afc1", "tegra124-afc.1", NULL, 187, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8262 PERIPH_CLK("afc2", "tegra124-afc.2", NULL, 188, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8263 PERIPH_CLK("afc3", "tegra124-afc.3", NULL, 189, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8264 PERIPH_CLK("afc4", "tegra124-afc.4", NULL, 190, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8265 PERIPH_CLK("afc5", "tegra124-afc.5", NULL, 191, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8266 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8267 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8268 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
8269 PERIPH_CLK("sbc1", "spi-tegra114.0", NULL, 41, 0x134, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8270 PERIPH_CLK("sbc2", "spi-tegra114.1", NULL, 44, 0x118, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8271 PERIPH_CLK("sbc3", "spi-tegra114.2", NULL, 46, 0x11c, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8272 PERIPH_CLK("sbc4", "spi-tegra114.3", NULL, 68, 0x1b4, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8273 PERIPH_CLK("sbc5", "spi-tegra114.4", NULL, 104, 0x3c8, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8274 PERIPH_CLK("sbc6", "spi-tegra114.5", NULL, 105, 0x3cc, 33000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8275 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8276 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8277 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
8278 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8279 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8280 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8281 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8282 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8283 PERIPH_CLK("sdmmc1_ddr", "sdhci-tegra.0", "ddr", 14, 0x150, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8284 PERIPH_CLK("sdmmc3_ddr", "sdhci-tegra.2", "ddr", 69, 0x1bc, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8285 PERIPH_CLK("sdmmc4_ddr", "sdhci-tegra.3", "ddr", 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8286 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
8287 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
8288 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
8289 PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 250000000, mux_clk_m, PERIPH_ON_APB),
8290 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
8291 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8292 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8293 PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8294 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8295 PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
8296 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8297 PERIPH_CLK("i2c1", "tegra12-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8298 PERIPH_CLK("i2c2", "tegra12-i2c.1", "div-clk", 54, 0x198, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8299 PERIPH_CLK("i2c3", "tegra12-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8300 PERIPH_CLK("i2c4", "tegra12-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8301 PERIPH_CLK("i2c5", "tegra12-i2c.4", "div-clk", 47, 0x128, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8302 PERIPH_CLK("i2c6", "tegra12-i2c.5", "div-clk", 166, 0x65c, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
8303 PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, PERIPH_ON_APB),
8304 PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
8305 PERIPH_CLK("uarta", "serial-tegra.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
8306 PERIPH_CLK("uartb", "serial-tegra.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
8307 PERIPH_CLK("uartc", "serial-tegra.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
8308 PERIPH_CLK("uartd", "serial-tegra.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
8309 PERIPH_CLK("vic03", "vic03", NULL, 178, 0x678, 900000000, mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, MUX | DIV_U71),
8310 PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 700000000, mux_pllm_pllc_pllp_plla_pllc4, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
8311 PERIPH_CLK("vi_sensor", NULL, "vi_sensor", 164, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
8312 PERIPH_CLK("vi_sensor2", NULL, "vi_sensor2", 165, 0x658, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
8313 PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
8314 PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 900000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
8315 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
8316 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 594000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71),
8317 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
8318 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX),
8319 PERIPH_CLK_EX("sor0", "sor0", NULL, 182, 0x414, 540000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | DIV_U71, &tegra_sor_clk_ops),
8320 PERIPH_CLK("dpaux", "dpaux", NULL, 181, 0, 24000000, mux_clk_m, 0),
8321 PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
8322 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0),
8323 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0),
8324 PERIPH_CLK_EX("dsia", "tegradc.0", "dsia", 48, 0xd0, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
8325 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 750000000, mux_plld_out0, PLLD, &tegra_dsi_clk_ops),
8326 PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
8327 PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
8328 PERIPH_CLK("csi", "vi", "csi", 52, 0, 750000000, mux_plld, PLLD),
8329 PERIPH_CLK("ispa", "isp", "ispa", 23, 0, 700000000, mux_isp, PERIPH_ON_APB),
8330 PERIPH_CLK("ispb", "isp", "ispb", 3, 0, 700000000, mux_isp, PERIPH_ON_APB),
8331 PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
8332 PERIPH_CLK("vim2_clk", "vi", "vim2_clk", 171, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
8333 PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8334 PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8335 PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8336 PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8337 PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
8338 PERIPH_CLK("entropy", "entropy", NULL, 149, 0x628, 102000000, mux_pllp_clkm_clk32_plle, MUX | DIV_U71),
8339 PERIPH_CLK("hdmi_audio", "hdmi_audio", NULL, 176, 0x668, 48000000, mux_pllp_pllc_clkm1, MUX | DIV_U71 | PERIPH_NO_RESET),
8340 PERIPH_CLK("clk72mhz", "clk72mhz", NULL, 177, 0x66c, 102000000, mux_pllp3_pllc_clkm, MUX | DIV_U71 | PERIPH_NO_RESET),
8342 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
8343 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
8344 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8345 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8346 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | DIV_U71),
8347 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
8348 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
8349 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
8350 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8351 PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8352 PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
8353 PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla_v2, MUX | DIV_U71 | PERIPH_ON_APB),
8355 PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8356 PERIPH_CLK("dp2", "dp2", NULL, 152, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
8358 SHARED_SCLK("automotive.hclk", "automotive", "hclk", &tegra_clk_ahb, NULL, 0, 0),
8359 SHARED_SCLK("automotive.pclk", "automotive", "pclk", &tegra_clk_apb, NULL, 0, 0),
8361 SHARED_SCLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8362 SHARED_SCLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8363 SHARED_SCLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8364 SHARED_SCLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8365 SHARED_SCLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8366 SHARED_SCLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_ahb, NULL, 0, 0),
8367 SHARED_SCLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8368 SHARED_SCLK("automotive.sclk", "automotive", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8369 SHARED_SCLK("via.sclk", "tegra_vi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8370 SHARED_SCLK("vib.sclk", "tegra_vi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8371 SHARED_SCLK("ispa.sclk", "tegra_isp.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8372 SHARED_SCLK("ispb.sclk", "tegra_isp.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8373 SHARED_SCLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
8374 SHARED_SCLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8375 SHARED_SCLK("cap.vcore.sclk", "cap.vcore.sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8376 SHARED_SCLK("cap.throttle.sclk", "cap_throttle", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
8377 SHARED_SCLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
8378 SHARED_SCLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
8379 SHARED_SCLK("sbc1.sclk", "tegra12-spi.0", "sclk", &tegra_clk_apb, NULL, 0, 0),
8380 SHARED_SCLK("sbc2.sclk", "tegra12-spi.1", "sclk", &tegra_clk_apb, NULL, 0, 0),
8381 SHARED_SCLK("sbc3.sclk", "tegra12-spi.2", "sclk", &tegra_clk_apb, NULL, 0, 0),
8382 SHARED_SCLK("sbc4.sclk", "tegra12-spi.3", "sclk", &tegra_clk_apb, NULL, 0, 0),
8383 SHARED_SCLK("sbc5.sclk", "tegra12-spi.4", "sclk", &tegra_clk_apb, NULL, 0, 0),
8384 SHARED_SCLK("sbc6.sclk", "tegra12-spi.5", "sclk", &tegra_clk_apb, NULL, 0, 0),
8386 SHARED_EMC_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8387 SHARED_EMC_CLK("mon_cpu.emc", "tegra_mon", "cpu_emc", &tegra_clk_emc, NULL, 0, 0, 0),
8388 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
8389 SHARED_EMC_CLK("cpu.emc", "tegra-cpu", "cpu_emc", &tegra_clk_emc, NULL, 0, 0, 0),
8391 SHARED_EMC_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC1)),
8392 SHARED_EMC_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_DC2)),
8393 SHARED_EMC_CLK("disp1.la.emc", "tegradc.0", "emc.la", &tegra_clk_emc, NULL, 0, 0, 0),
8394 SHARED_EMC_CLK("disp2.la.emc", "tegradc.1", "emc.la", &tegra_clk_emc, NULL, 0, 0, 0),
8395 SHARED_EMC_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8396 SHARED_EMC_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8397 SHARED_EMC_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8398 SHARED_EMC_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8399 SHARED_EMC_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8400 SHARED_EMC_CLK("sdmmc3.emc", "sdhci-tegra.2","emc", &tegra_clk_emc, NULL, 0, 0, 0),
8401 SHARED_EMC_CLK("sdmmc4.emc", "sdhci-tegra.3","emc", &tegra_clk_emc, NULL, 0, 0, 0),
8402 SHARED_EMC_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8403 SHARED_EMC_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8404 SHARED_EMC_CLK("cap.vcore.emc", "cap.vcore.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8405 SHARED_EMC_CLK("cap.throttle.emc", "cap_throttle", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING_BUT_ISO, 0),
8406 SHARED_EMC_CLK("3d.emc", "tegra_gk20a.0", "emc", &tegra_clk_emc, NULL, 0, 0, BIT(EMC_USER_3D)),
8407 SHARED_EMC_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, BIT(EMC_USER_MSENC)),
8408 SHARED_EMC_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8409 SHARED_EMC_CLK("via.emc", "tegra_vi.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI)),
8410 SHARED_EMC_CLK("vib.emc", "tegra_vi.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_VI2)),
8411 SHARED_EMC_CLK("ispa.emc", "tegra_isp.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP1)),
8412 SHARED_EMC_CLK("ispb.emc", "tegra_isp.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_ISO_BW, BIT(EMC_USER_ISP2)),
8413 SHARED_EMC_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8414 SHARED_EMC_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE, 0),
8415 SHARED_EMC_CLK("vic.emc", "tegra_vic03.0", "emc", &tegra_clk_emc, NULL, 0, 0, 0),
8416 SHARED_EMC_CLK("battery.emc", "battery_edp", "emc", &tegra_clk_emc, NULL, 0, SHARED_CEILING, 0),
8417 SHARED_LIMIT("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
8418 SHARED_LIMIT("floor.profile.emc", "profile.emc", "floor", &tegra_clk_emc, NULL, 0, 0),
8420 #ifdef CONFIG_TEGRA_DUAL_CBUS
8421 DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c2bus, "msenc", 0, 0),
8422 DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c2bus, "vde", 0, 0),
8423 DUAL_CBUS_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_c2bus, "se", 0, 0),
8424 SHARED_LIMIT("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8425 SHARED_LIMIT("cap.vcore.c2bus", "cap.vcore.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8426 SHARED_LIMIT("cap.throttle.c2bus", "cap_throttle", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
8427 SHARED_LIMIT("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
8428 SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
8430 DUAL_CBUS_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_c3bus, "vic03", 0, 0),
8431 DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
8432 SHARED_LIMIT("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8433 SHARED_LIMIT("cap.vcore.c3bus", "cap.vcore.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8434 SHARED_LIMIT("cap.throttle.c3bus", "cap_throttle", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
8435 SHARED_LIMIT("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
8436 SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
8438 SHARED_CLK("vic03.cbus", "tegra_vic03.0", "vic03", &tegra_clk_cbus, "vic03", 0, 0),
8439 SHARED_CLK("msenc.cbus","tegra_msenc", "msenc",&tegra_clk_cbus, "msenc", 0, 0),
8440 SHARED_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_cbus, "tsec", 0, 0),
8441 SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0),
8442 SHARED_CLK("se.cbus", "tegra12-se", NULL, &tegra_clk_cbus, "se", 0, 0),
8443 SHARED_LIMIT("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8444 SHARED_LIMIT("cap.vcore.cbus", "cap.vcore.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8445 SHARED_LIMIT("cap.throttle.cbus", "cap_throttle", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
8446 SHARED_LIMIT("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
8447 SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
8449 SHARED_CLK("gk20a.gbus", "tegra_gk20a", "gpu", &tegra_clk_gbus, NULL, 0, 0),
8450 SHARED_LIMIT("cap.gbus", "cap.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8451 SHARED_LIMIT("edp.gbus", "edp.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8452 SHARED_LIMIT("battery.gbus", "battery_edp", "gpu", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8453 SHARED_LIMIT("cap.throttle.gbus", "cap_throttle", NULL, &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8454 SHARED_LIMIT("cap.profile.gbus", "profile.gbus", "cap", &tegra_clk_gbus, NULL, 0, SHARED_CEILING),
8455 SHARED_CLK("override.gbus", "override.gbus", NULL, &tegra_clk_gbus, NULL, 0, SHARED_OVERRIDE),
8456 SHARED_LIMIT("floor.gbus", "floor.gbus", NULL, &tegra_clk_gbus, NULL, 0, 0),
8457 SHARED_LIMIT("floor.profile.gbus", "profile.gbus", "floor", &tegra_clk_gbus, NULL, 0, 0),
8459 SHARED_CLK("automotive.host1x", "automotive", "host1x", &tegra_clk_host1x, NULL, 0, 0),
8460 SHARED_CLK("nv.host1x", "tegra_host1x", "host1x", &tegra_clk_host1x, NULL, 0, 0),
8461 SHARED_CLK("vi.host1x", "tegra_vi", "host1x", &tegra_clk_host1x, NULL, 0, 0),
8462 SHARED_LIMIT("cap.host1x", "cap.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
8463 SHARED_LIMIT("cap.vcore.host1x", "cap.vcore.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_CEILING),
8464 SHARED_LIMIT("floor.host1x", "floor.host1x", NULL, &tegra_clk_host1x, NULL, 0, 0),
8465 SHARED_CLK("override.host1x", "override.host1x", NULL, &tegra_clk_host1x, NULL, 0, SHARED_OVERRIDE),
8467 SHARED_CLK("cpu.mselect", "cpu", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8468 SHARED_CLK("pcie.mselect", "tegra_pcie", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8469 SHARED_CLK("automotive.mselect", "automotive", "mselect", &tegra_clk_mselect, NULL, 0, 0),
8470 SHARED_LIMIT("cap.vcore.mselect", "cap.vcore.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_CEILING),
8471 SHARED_CLK("override.mselect", "override.mselect", NULL, &tegra_clk_mselect, NULL, 0, SHARED_OVERRIDE),
8475 static struct clk tegra_visp_clks[] = {
8476 SHARED_CONNECT("vi.c4bus", "vi.c4bus", NULL, &tegra_clk_c4bus, "vi", 0, 0),
8477 SHARED_CONNECT("isp.c4bus", "isp.c4bus", NULL, &tegra_clk_c4bus, "isp", 0, 0),
8478 SHARED_CLK("override.c4bus", "override.c4bus", NULL, &tegra_clk_c4bus, NULL, 0, SHARED_OVERRIDE),
8480 SHARED_CLK("via.vi.c4bus", "via.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
8481 SHARED_CLK("vib.vi.c4bus", "vib.vi", NULL, &tegra_visp_clks[0], NULL, 0, 0),
8483 SHARED_CLK("ispa.isp.c4bus", "ispa.isp", NULL, &tegra_visp_clks[1], "ispa", 0, 0),
8484 SHARED_CLK("ispb.isp.c4bus", "ispb.isp", NULL, &tegra_visp_clks[1], "ispb", 0, 0),
8488 #define XUSB_ID "tegra-xhci"
8489 /* xusb common clock gate - enabled on init and never disabled */
8490 static void tegra12_xusb_gate_clk_init(struct clk *c)
8492 tegra12_periph_clk_enable(c);
8495 static struct clk_ops tegra_xusb_gate_clk_ops = {
8496 .init = tegra12_xusb_gate_clk_init,
8499 static struct clk tegra_clk_xusb_gate = {
8500 .name = "xusb_gate",
8501 .flags = ENABLE_ON_INIT | PERIPH_NO_RESET,
8502 .ops = &tegra_xusb_gate_clk_ops,
8504 .max_rate = 48000000,
8510 static struct clk tegra_xusb_source_clks[] = {
8511 PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
8512 PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 336000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET),
8513 PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | PERIPH_NO_RESET),
8514 PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | DIV_U71 | PERIPH_NO_RESET),
8515 PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 112000000, mux_clkm_pllp_pllc_pllre, MUX | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
8516 SHARED_EMC_CLK("xusb.emc", XUSB_ID, "emc", &tegra_clk_emc, NULL, 0, SHARED_BW, 0),
8519 static struct clk tegra_xusb_ss_div2 = {
8520 .name = "xusb_ss_div2",
8521 .ops = &tegra_clk_m_div_ops,
8522 .parent = &tegra_xusb_source_clks[3],
8526 .max_rate = 61200000,
8529 static struct clk_mux_sel mux_ss_div2_pllu_60M[] = {
8530 { .input = &tegra_xusb_ss_div2, .value = 0},
8531 { .input = &tegra_pll_u_60M, .value = 1},
8535 static struct clk tegra_xusb_hs_src = {
8536 .name = "xusb_hs_src",
8541 .ops = &tegra_periph_clk_ops,
8543 .inputs = mux_ss_div2_pllu_60M,
8544 .flags = MUX | PLLU | PERIPH_NO_ENB,
8545 .max_rate = 60000000,
8547 .src_mask = 0x1 << 25,
8552 static struct clk_mux_sel mux_xusb_host[] = {
8553 { .input = &tegra_xusb_source_clks[0], .value = 0},
8554 { .input = &tegra_xusb_source_clks[1], .value = 1},
8555 { .input = &tegra_xusb_source_clks[2], .value = 2},
8556 { .input = &tegra_xusb_hs_src, .value = 5},
8560 static struct clk_mux_sel mux_xusb_ss[] = {
8561 { .input = &tegra_xusb_source_clks[3], .value = 3},
8562 { .input = &tegra_xusb_source_clks[0], .value = 0},
8563 { .input = &tegra_xusb_source_clks[1], .value = 1},
8567 static struct clk_mux_sel mux_xusb_dev[] = {
8568 { .input = &tegra_xusb_source_clks[4], .value = 4},
8569 { .input = &tegra_xusb_source_clks[2], .value = 2},
8570 { .input = &tegra_xusb_source_clks[3], .value = 3},
8574 static struct clk tegra_xusb_coupled_clks[] = {
8575 PERIPH_CLK_EX("xusb_host", XUSB_ID, "host", 89, 0, 350000000, mux_xusb_host, 0, &tegra_clk_coupled_gate_ops),
8576 PERIPH_CLK_EX("xusb_ss", XUSB_ID, "ss", 156, 0, 350000000, mux_xusb_ss, 0, &tegra_clk_coupled_gate_ops),
8577 PERIPH_CLK_EX("xusb_dev", XUSB_ID, "dev", 95, 0, 120000000, mux_xusb_dev, 0, &tegra_clk_coupled_gate_ops),
8580 #define CLK_DUPLICATE(_name, _dev, _con) \
8589 /* Some clocks may be used by different drivers depending on the board
8590 * configuration. List those here to register them twice in the clock lookup
8591 * table under two names.
8593 struct clk_duplicate tegra_clk_duplicates[] = {
8594 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
8595 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
8596 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
8597 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
8598 CLK_DUPLICATE("usbd", XUSB_ID, "utmip-pad"),
8599 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
8600 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
8601 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
8602 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.0", NULL),
8603 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.0", "emc"),
8604 CLK_DUPLICATE("disp1", "tegra_dc_dsi_vs1.1", NULL),
8605 CLK_DUPLICATE("disp1.emc", "tegra_dc_dsi_vs1.1", "emc"),
8606 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
8607 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
8608 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
8609 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
8610 CLK_DUPLICATE("dsiblp", "tegradc.0", "dsiblp"),
8611 CLK_DUPLICATE("dsialp", "tegradc.1", "dsialp"),
8612 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.0", "dsia"),
8613 CLK_DUPLICATE("dsia", "tegra_dc_dsi_vs1.1", "dsia"),
8614 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.0", "dsialp"),
8615 CLK_DUPLICATE("dsialp", "tegra_dc_dsi_vs1.1", "dsialp"),
8616 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.0", "dsi-fixed"),
8617 CLK_DUPLICATE("dsi1-fixed", "tegra_dc_dsi_vs1.1", "dsi-fixed"),
8618 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
8619 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
8620 CLK_DUPLICATE("cop", "nvavp", "cop"),
8621 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
8622 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
8623 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
8624 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
8625 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
8626 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
8627 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
8628 CLK_DUPLICATE("clk_m", NULL, "apb_pclk"),
8629 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
8630 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
8631 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
8632 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
8633 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
8634 CLK_DUPLICATE("cl_dvfs_ref", "tegra12-i2c.4", NULL),
8635 CLK_DUPLICATE("cl_dvfs_soc", "tegra12-i2c.4", NULL),
8636 CLK_DUPLICATE("sbc1", "tegra11-spi-slave.0", NULL),
8637 CLK_DUPLICATE("sbc2", "tegra11-spi-slave.1", NULL),
8638 CLK_DUPLICATE("sbc3", "tegra11-spi-slave.2", NULL),
8639 CLK_DUPLICATE("sbc4", "tegra11-spi-slave.3", NULL),
8640 CLK_DUPLICATE("sbc5", "tegra11-spi-slave.4", NULL),
8641 CLK_DUPLICATE("sbc6", "tegra11-spi-slave.5", NULL),
8642 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
8643 CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
8644 CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
8645 CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
8646 CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
8647 CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
8648 CLK_DUPLICATE("actmon", "tegra_host1x", "actmon"),
8649 CLK_DUPLICATE("gpu_ref", "tegra_gk20a.0", "PLLG_ref"),
8650 CLK_DUPLICATE("gbus", "tegra_gk20a.0", "PLLG_out"),
8651 CLK_DUPLICATE("pll_p_out5", "tegra_gk20a.0", "pwr"),
8652 CLK_DUPLICATE("ispa.isp.c4bus", "tegra_isp.0", "isp"),
8653 CLK_DUPLICATE("ispb.isp.c4bus", "tegra_isp.1", "isp"),
8654 CLK_DUPLICATE("via.vi.c4bus", "tegra_vi.0", "vi"),
8655 CLK_DUPLICATE("vib.vi.c4bus", "tegra_vi.1", "vi"),
8656 CLK_DUPLICATE("csi", "tegra_vi.0", "csi"),
8657 CLK_DUPLICATE("csi", "tegra_vi.1", "csi"),
8658 CLK_DUPLICATE("csus", "tegra_vi.0", "csus"),
8659 CLK_DUPLICATE("vim2_clk", "tegra_vi.1", "vim2_clk"),
8660 CLK_DUPLICATE("cilab", "tegra_vi.0", "cilab"),
8661 CLK_DUPLICATE("cilcd", "tegra_vi.1", "cilcd"),
8662 CLK_DUPLICATE("cile", "tegra_vi.1", "cile"),
8663 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
8664 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
8665 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
8666 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
8667 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
8668 CLK_DUPLICATE("dam0", NULL, "dam0"),
8669 CLK_DUPLICATE("dam1", NULL, "dam1"),
8670 CLK_DUPLICATE("dam2", NULL, "dam2"),
8671 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
8672 CLK_DUPLICATE("mclk", NULL, "default_mclk"),
8673 CLK_DUPLICATE("amx", NULL, "amx"),
8674 CLK_DUPLICATE("amx1", NULL, "amx1"),
8675 CLK_DUPLICATE("adx", NULL, "adx"),
8676 CLK_DUPLICATE("adx1", NULL, "adx1"),
8677 CLK_DUPLICATE("afc0", NULL, "afc0"),
8678 CLK_DUPLICATE("afc1", NULL, "afc1"),
8679 CLK_DUPLICATE("afc2", NULL, "afc2"),
8680 CLK_DUPLICATE("afc3", NULL, "afc3"),
8681 CLK_DUPLICATE("afc4", NULL, "afc4"),
8682 CLK_DUPLICATE("afc5", NULL, "afc5"),
8683 CLK_DUPLICATE("amx", "tegra124-amx.0", NULL),
8684 CLK_DUPLICATE("amx1", "tegra124-amx.1", NULL),
8685 CLK_DUPLICATE("adx", "tegra124-adx.0", NULL),
8686 CLK_DUPLICATE("adx1", "tegra124-adx.1", NULL),
8687 CLK_DUPLICATE("amx", "tegra30-ahub-apbif", "amx"),
8688 CLK_DUPLICATE("amx1", "tegra30-ahub-apbif", "amx1"),
8689 CLK_DUPLICATE("adx", "tegra30-ahub-apbif", "adx"),
8690 CLK_DUPLICATE("adx1", "tegra30-ahub-apbif", "adx1"),
8691 CLK_DUPLICATE("d_audio", "tegra30-ahub-xbar", "d_audio"),
8692 CLK_DUPLICATE("apbif", "tegra30-ahub-apbif", "apbif"),
8693 CLK_DUPLICATE("afc0", "tegra30-ahub-apbif", "afc0"),
8694 CLK_DUPLICATE("afc1", "tegra30-ahub-apbif", "afc1"),
8695 CLK_DUPLICATE("afc2", "tegra30-ahub-apbif", "afc2"),
8696 CLK_DUPLICATE("afc3", "tegra30-ahub-apbif", "afc3"),
8697 CLK_DUPLICATE("afc4", "tegra30-ahub-apbif", "afc4"),
8698 CLK_DUPLICATE("afc5", "tegra30-ahub-apbif", "afc5"),
8699 CLK_DUPLICATE("cpu_g", "tegra_simon", "cpu"),
8702 struct clk *tegra_ptr_clks[] = {
8724 &tegra_clk_xusb_gate,
8743 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
8749 &tegra_clk_virtual_cpu_g,
8750 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
8751 &tegra_clk_virtual_cpu_lp,
8753 &tegra_clk_cpu_cmplx,
8756 &tegra_clk_sbus_cmplx,
8763 #ifdef CONFIG_TEGRA_DUAL_CBUS
8775 struct clk *tegra_ptr_camera_mclks[] = {
8777 &tegra_camera_mclk2,
8781 * Use this API only when all the clocks are not registered to the clock
8784 static struct clk *query_clk_from_list(char *clk_name)
8791 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
8792 if (!strcmp(tegra_list_clks[i].name, clk_name))
8793 return &tegra_list_clks[i];
8799 * Handle special clocks to check if they can be set to safe rate
8801 static bool tegra12_periph_is_special_reset(struct clk *c)
8805 if (!strcmp(c->name, "isp")) {
8806 /* Make sure that ispa and ispb are in reset */
8809 * Since clocks may not have been registered by this time,
8810 * so query clock structure directly from the list
8812 temp = query_clk_from_list("ispa");
8816 /* If ispa is not in reset, return false */
8817 if (!IS_PERIPH_IN_RESET(temp))
8820 temp = query_clk_from_list("ispb");
8824 /* If ispb is not in reset, return false */
8825 if (!IS_PERIPH_IN_RESET(temp))
8831 if (!strcmp(c->name, "vi_sensor") || !strcmp(c->name, "vi_sensor2")) {
8832 temp = query_clk_from_list("vi");
8836 /* If vi is not in reset, return false */
8837 if (!IS_PERIPH_IN_RESET(temp))
8844 if (!strcmp(c->name, "hdmi_audio")) {
8845 temp = query_clk_from_list("hdmi");
8849 /* If hdmi is not in reset, return false */
8850 if (!IS_PERIPH_IN_RESET(temp))
8859 /* Return true from this function if the target rate can be locked without
8860 switching pll clients to back-up source */
8861 static bool tegra12_is_dyn_ramp(
8862 struct clk *c, unsigned long rate, bool from_vco_min)
8864 #if PLLCX_USE_DYN_RAMP
8865 /* PLLC2, PLLC3 support dynamic ramp only when output divider <= 8 */
8866 if ((c == &tegra_pll_c2) || (c == &tegra_pll_c3)) {
8867 struct clk_pll_freq_table cfg, old_cfg;
8868 unsigned long input_rate = clk_get_rate(c->parent);
8870 u32 val = clk_readl(c->reg + PLL_BASE);
8871 PLL_BASE_PARSE(PLLCX, old_cfg, val);
8872 old_cfg.p = pllcx_p[old_cfg.p];
8874 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
8875 if ((cfg.n == old_cfg.n) ||
8876 PLLCX_IS_DYN(cfg.p, old_cfg.p))
8882 #if PLLXC_USE_DYN_RAMP
8883 /* PPLX, PLLC support dynamic ramp when changing NDIV only */
8884 if ((c == &tegra_pll_x) || (c == &tegra_pll_c)) {
8885 struct clk_pll_freq_table cfg, old_cfg;
8886 unsigned long input_rate = clk_get_rate(c->parent);
8889 old_cfg.m = PLL_FIXED_MDIV(c, input_rate);
8892 if (c->flags & PLLX)
8893 u32 val = clk_readlx(c->reg + PLL_BASE);
8895 u32 val = clk_readl(c->reg + PLL_BASE);
8896 PLL_BASE_PARSE(PLLXC, old_cfg, val);
8897 old_cfg.p = pllxc_p[old_cfg.p];
8900 if (!pll_dyn_ramp_find_cfg(c, &cfg, rate, input_rate, NULL)) {
8901 if ((cfg.m == old_cfg.m) && (cfg.p == old_cfg.p))
8909 /* DFLL late init called with CPU clock lock taken */
8910 static void __init tegra12_dfll_cpu_late_init(struct clk *c)
8912 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
8914 struct clk *cpu = &tegra_clk_virtual_cpu_g;
8916 if (!cpu || !cpu->dvfs) {
8917 pr_err("%s: CPU dvfs is not present\n", __func__);
8920 tegra_dvfs_set_dfll_tune_trimmers(cpu->dvfs, tune_cpu_trimmers);
8922 /* release dfll clock source reset, init cl_dvfs control logic, and
8923 move dfll to initialized state, so it can be used as CPU source */
8924 tegra_periph_reset_deassert(c);
8925 ret = tegra_init_cl_dvfs();
8928 if (tegra_platform_is_silicon()) {
8929 use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
8930 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
8931 if (tegra_cpu_speedo_id() == 0)
8935 tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
8936 tegra_cl_dvfs_debug_init(c);
8937 pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n",
8944 * Backup pll is used as transitional CPU clock source while main pll is
8945 * relocking; in addition all CPU rates below backup level are sourced from
8946 * backup pll only. Target backup levels for each CPU mode are selected high
8947 * enough to avoid voltage droop when CPU clock is switched between backup and
8948 * main plls. Actual backup rates will be rounded to match backup source fixed
8949 * frequency. Backup rates are also used as stay-on-backup thresholds, and must
8950 * be kept the same in G and LP mode (will need to add a separate stay-on-backup
8951 * parameter to allow different backup rates if necessary).
8953 * Sbus threshold must be exact factor of pll_p rate.
8955 #define CPU_G_BACKUP_RATE_TARGET 200000000
8956 #define CPU_LP_BACKUP_RATE_TARGET 200000000
8958 static void tegra12_pllp_init_dependencies(unsigned long pllp_rate)
8960 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
8962 unsigned long backup_rate;
8965 switch (pllp_rate) {
8967 tegra_pll_p_out1.u.pll_div.default_rate = 28800000;
8968 tegra_pll_p_out3.u.pll_div.default_rate = 72000000;
8969 tegra_clk_sbus_cmplx.u.system.threshold = 108000000;
8970 tegra_clk_host1x.u.periph.threshold = 108000000;
8973 tegra_pll_p_out1.u.pll_div.default_rate = 9600000;
8974 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
8975 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
8976 tegra_clk_host1x.u.periph.threshold = 204000000;
8979 tegra_pll_p_out1.u.pll_div.default_rate = 4800000;
8980 tegra_pll_p_out3.u.pll_div.default_rate = 102000000;
8981 tegra_clk_sbus_cmplx.u.system.threshold = 204000000;
8982 tegra_clk_host1x.u.periph.threshold = 204000000;
8985 pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate);
8988 pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate);
8990 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
8991 div = pllp_rate / CPU_G_BACKUP_RATE_TARGET;
8992 backup_rate = pllp_rate / div;
8993 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate;
8995 div = pllp_rate / CPU_LP_BACKUP_RATE_TARGET;
8996 backup_rate = pllp_rate / div;
8997 tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate;
8999 tegra_clk_virtual_cpu_g.u.cpu.backup_rate = pllp_rate;
9003 static void tegra12_init_one_clock(struct clk *c)
9006 INIT_LIST_HEAD(&c->shared_bus_list);
9007 if (!c->lookup.dev_id && !c->lookup.con_id)
9008 c->lookup.con_id = c->name;
9010 clkdev_add(&c->lookup);
9013 /* Direct access to CPU clock sources fot CPU idle driver */
9014 int tegra12_cpu_g_idle_rate_exchange(unsigned long *rate)
9017 struct clk *dfll = tegra_clk_cpu_cmplx.parent->u.cpu.dynamic;
9018 unsigned long old_rate, new_rate, flags;
9020 if (!dfll || !tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
9023 /* Clipping min to oscillator rate is pretty much arbitrary */
9024 new_rate = max(*rate, tegra_clk_m.rate);
9026 clk_lock_save(dfll, &flags);
9028 old_rate = clk_get_rate_locked(dfll);
9030 if (new_rate != old_rate)
9031 ret = clk_set_rate_locked(dfll, new_rate);
9033 clk_unlock_restore(dfll, &flags);
9037 int tegra12_cpu_lp_idle_rate_exchange(unsigned long *rate)
9040 struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
9041 unsigned long old_rate, flags;
9042 unsigned long new_rate = min(
9043 *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
9045 clk_lock_save(backup, &flags);
9047 old_rate = clk_get_rate_locked(backup);
9049 if (new_rate != old_rate)
9050 ret = clk_set_rate_locked(backup, new_rate);
9052 clk_unlock_restore(backup, &flags);
9056 void tegra_edp_throttle_cpu_now(u8 factor)
9058 /* empty definition for tegra12 */
9062 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
9065 * Most of the Tegra12 multimedia and peripheral muxes include pll_c2
9066 * and pll_c3 as possible inputs. However, per clock policy these plls
9067 * are allowed to be used only by handful devices aggregated on cbus.
9068 * For all others, instead of enforcing policy at run-time in this
9069 * function, we simply stripped out pll_c2 and pll_c3 options from the
9070 * respective muxes statically.
9074 * In configuration with dual cbus pll_c can be used as a scaled clock
9075 * source for EMC only when pll_m is fixed, or as a general fixed rate
9076 * clock source for EMC and other peripherals if pll_m is scaled. In
9077 * configuration with single cbus pll_c can be used as a scaled cbus
9078 * clock source only. No direct use for pll_c by super clocks.
9080 if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
9081 if (c->ops == &tegra_super_ops)
9083 #ifdef CONFIG_TEGRA_DUAL_CBUS
9084 #ifndef CONFIG_TEGRA_PLLM_SCALED
9085 return c->flags & PERIPH_EMC_ENB;
9088 return c->flags & PERIPH_ON_CBUS;
9093 * In any configuration pll_m must not be used as a clock source for
9094 * cbus modules. If pll_m is scaled it can be used as EMC source only.
9095 * Otherwise fixed rate pll_m can be used as clock source for EMC and
9096 * other peripherals. No direct use for pll_m by super clocks.
9098 if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
9099 if (c->ops == &tegra_super_ops)
9102 if (c->flags & PERIPH_ON_CBUS)
9104 #ifdef CONFIG_TEGRA_PLLM_SCALED
9105 return c->flags & PERIPH_EMC_ENB;
9111 /* Internal LA may request some clocks to be enabled on init via TRANSACTION
9112 SCRATCH register settings */
9113 void __init tegra12x_clk_init_la(void)
9116 u32 reg = readl((void *)
9117 ((uintptr_t)misc_gp_base + MISC_GP_TRANSACTOR_SCRATCH_0));
9119 if (!(reg & MISC_GP_TRANSACTOR_SCRATCH_LA_ENABLE))
9122 c = tegra_get_clock_by_name("la");
9123 if (WARN(!c, "%s: could not find la clk\n", __func__))
9127 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DDS_ENABLE) {
9128 c = tegra_get_clock_by_name("dds");
9129 if (WARN(!c, "%s: could not find la clk\n", __func__))
9133 if (reg & MISC_GP_TRANSACTOR_SCRATCH_DP2_ENABLE) {
9134 c = tegra_get_clock_by_name("dp2");
9135 if (WARN(!c, "%s: could not find la clk\n", __func__))
9139 c = tegra_get_clock_by_name("hdmi");
9140 if (WARN(!c, "%s: could not find la clk\n", __func__))
9146 #ifdef CONFIG_CPU_FREQ
9149 * Frequency table index must be sequential starting at 0 and frequencies
9150 * must be ascending.
9152 #define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
9153 #define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
9155 static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
9156 static struct tegra_cpufreq_table_data freq_table_data;
9158 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
9159 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
9162 bool g_vmin_done = false;
9163 unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
9164 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
9165 struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
9167 /* Initialize once */
9168 if (freq_table_data.freq_table)
9169 return &freq_table_data;
9172 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
9173 freq_table[i].index = i;
9174 freq_table[i].frequency = CPUFREQ_TABLE_END;
9177 lp_backup_freq = cpu_clk_lp->u.cpu.backup_rate / 1000;
9178 if (!lp_backup_freq) {
9179 WARN(1, "%s: cannot make cpufreq table: no LP CPU backup rate\n",
9183 if (!cpu_clk_lp->dvfs) {
9184 WARN(1, "%s: cannot make cpufreq table: no LP CPU dvfs\n",
9188 if (!cpu_clk_g->dvfs) {
9189 WARN(1, "%s: cannot make cpufreq table: no G CPU dvfs\n",
9193 g_vmin_freq = cpu_clk_g->dvfs->freqs[0] / 1000;
9194 if (g_vmin_freq < lp_backup_freq) {
9195 WARN(1, "%s: cannot make cpufreq table: LP CPU backup rate"
9196 " exceeds G CPU rate at Vmin\n", __func__);
9199 /* Avoid duplicate frequency if g_vim_freq is already part of table */
9200 if (g_vmin_freq == lp_backup_freq)
9203 /* Start with backup frequencies */
9205 freq = lp_backup_freq;
9206 freq_table[i++].frequency = freq/4;
9207 freq_table[i++].frequency = freq/2;
9208 freq_table[i++].frequency = freq;
9210 /* Throttle low index at backup level*/
9211 freq_table_data.throttle_lowest_index = i - 1;
9214 * Next, set table steps along LP CPU dvfs ladder, but make sure G CPU
9215 * dvfs rate at minimum voltage is not missed (if it happens to be below
9218 max_freq = cpu_clk_lp->max_rate / 1000;
9219 for (j = 0; j < cpu_clk_lp->dvfs->num_freqs; j++) {
9220 freq = cpu_clk_lp->dvfs->freqs[j] / 1000;
9221 if (freq <= lp_backup_freq)
9224 if (!g_vmin_done && (freq >= g_vmin_freq)) {
9226 if (freq > g_vmin_freq)
9227 freq_table[i++].frequency = g_vmin_freq;
9229 freq_table[i++].frequency = freq;
9231 if (freq == max_freq)
9235 /* Set G CPU min rate at least one table step below LP maximum */
9236 cpu_clk_g->min_rate = min(freq_table[i-2].frequency, g_vmin_freq)*1000;
9238 /* Suspend index at max LP CPU */
9239 freq_table_data.suspend_index = i - 1;
9241 /* Fill in "hole" (if any) between LP CPU maximum rate and G CPU dvfs
9242 ladder rate at minimum voltage */
9243 if (freq < g_vmin_freq) {
9244 int n = (g_vmin_freq - freq) / CPU_FREQ_STEP;
9245 for (j = 0; j <= n; j++) {
9246 freq = g_vmin_freq - CPU_FREQ_STEP * (n - j);
9247 freq_table[i++].frequency = freq;
9251 /* Now, step along the rest of G CPU dvfs ladder */
9252 g_start_freq = freq;
9253 max_freq = cpu_clk_g->max_rate / 1000;
9254 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
9255 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
9256 if (freq > g_start_freq)
9257 freq_table[i++].frequency = freq;
9258 if (freq == max_freq)
9262 /* Throttle high index one step below maximum */
9263 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
9264 freq_table_data.throttle_highest_index = i - 2;
9265 freq_table_data.freq_table = freq_table;
9266 return &freq_table_data;
9271 #define GRANULARITY_KHZ 25500
9272 #define GRANULARITY_END 1020000
9273 #define CPU_THROTTLE_FREQ 408000
9274 #define CPU_SUSPEND_FREQ 408000
9276 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
9279 unsigned int freq, max_freq, cpu_min_freq;
9280 struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
9282 /* Initialize once */
9283 if (freq_table_data.freq_table)
9284 return &freq_table_data;
9287 for (i = 0; i < CPU_FREQ_TABLE_MAX_SIZE; i++) {
9288 freq_table[i].index = i;
9289 freq_table[i].frequency = CPUFREQ_TABLE_END;
9292 if (!cpu_clk_g->dvfs) {
9293 WARN(1, "%s: cannot make cpufreq table: no CPU dvfs\n",
9298 cpu_min_freq = 204000;
9300 cpu_clk_g->min_rate = cpu_min_freq*1000;
9303 freq_table[i++].frequency = cpu_min_freq;
9304 for (j=1; j <= (GRANULARITY_END - cpu_min_freq)/GRANULARITY_KHZ; j++)
9305 freq_table[i++].frequency = cpu_min_freq + j*GRANULARITY_KHZ;
9307 /* Now, step along the rest of G CPU dvfs ladder */
9308 max_freq = cpu_clk_g->max_rate / 1000;
9309 for (j = 0; j < cpu_clk_g->dvfs->num_freqs; j++) {
9310 freq = cpu_clk_g->dvfs->freqs[j] / 1000;
9311 if (freq > GRANULARITY_END)
9312 freq_table[i++].frequency = freq;
9313 if (freq == max_freq)
9317 freq_table_data.throttle_lowest_index = 0;
9318 freq_table_data.suspend_index = 0;
9320 for (j = 1; j < i; j++) {
9321 if ((freq_table[j].frequency > CPU_THROTTLE_FREQ) &&
9322 (freq_table[j-1].frequency <= CPU_THROTTLE_FREQ))
9323 freq_table_data.throttle_lowest_index = j - 1;
9324 if ((freq_table[j].frequency > CPU_SUSPEND_FREQ) &&
9325 (freq_table[j-1].frequency <= CPU_SUSPEND_FREQ))
9326 freq_table_data.suspend_index = j - 1;
9329 /* Throttle high index one step below maximum */
9330 BUG_ON(i >= CPU_FREQ_TABLE_MAX_SIZE);
9331 freq_table_data.throttle_highest_index = i - 2;
9332 freq_table_data.freq_table = freq_table;
9333 return &freq_table_data;
9338 /* EMC/CPU frequency ratio for power/performance optimization */
9339 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate)
9341 static unsigned long emc_max_rate;
9343 if (emc_max_rate == 0)
9344 emc_max_rate = clk_round_rate(
9345 tegra_get_clock_by_name("emc"), ULONG_MAX);
9347 /* Vote on memory bus frequency based on cpu frequency;
9348 cpu rate is in kHz, emc rate is in Hz */
9349 if (cpu_rate >= 1300000)
9350 return emc_max_rate; /* cpu >= 1.3GHz, emc max */
9351 else if (cpu_rate >= 975000)
9352 return 550000000; /* cpu >= 975 MHz, emc 550 MHz */
9353 else if (cpu_rate >= 725000)
9354 return 350000000; /* cpu >= 725 MHz, emc 350 MHz */
9355 else if (cpu_rate >= 500000)
9356 return 150000000; /* cpu >= 500 MHz, emc 150 MHz */
9357 else if (cpu_rate >= 275000)
9358 return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
9360 return 0; /* emc min */
9363 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
9364 /* EMC/CPU frequency operational requirement limit */
9365 unsigned long tegra_emc_cpu_limit(unsigned long cpu_rate)
9367 static unsigned long last_emc_rate;
9368 unsigned long emc_rate;
9370 /* Vote on memory bus frequency based on cpu frequency;
9371 cpu rate is in kHz, emc rate is in Hz */
9373 if ((tegra_revision != TEGRA_REVISION_A01) &&
9374 (tegra_revision != TEGRA_REVISION_A02))
9375 return 0; /* no frequency dependency for A03+ revisions */
9377 if (cpu_rate > 1020000)
9378 emc_rate = 600000000; /* cpu > 1.02GHz, emc 600MHz */
9380 emc_rate = 300000000; /* 300MHz floor always */
9382 /* When going down, allow some time for CPU DFLL to settle */
9383 if (emc_rate < last_emc_rate)
9384 udelay(200); /* FIXME: to be characterized */
9386 last_emc_rate = emc_rate;
9391 int tegra_update_mselect_rate(unsigned long cpu_rate)
9393 static struct clk *mselect; /* statics init to 0 */
9395 unsigned long mselect_rate;
9398 mselect = tegra_get_clock_by_name("cpu.mselect");
9403 /* Vote on mselect frequency based on cpu frequency:
9404 keep mselect at half of cpu rate up to 102 MHz;
9405 cpu rate is in kHz, mselect rate is in Hz */
9406 mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
9407 mselect_rate = min(mselect_rate, 102000000UL);
9408 return clk_set_rate(mselect, mselect_rate);
9412 #ifdef CONFIG_PM_SLEEP
9413 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
9414 PERIPH_CLK_SOURCE_NUM + 25];
9416 static int tegra12_clk_suspend(void)
9419 u32 *ctx = clk_rst_suspend;
9421 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
9422 *ctx++ = clk_readl(CPU_SOFTRST_CTRL);
9423 *ctx++ = clk_readl(CPU_SOFTRST_CTRL1);
9424 *ctx++ = clk_readl(CPU_SOFTRST_CTRL2);
9426 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
9427 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
9428 *ctx++ = clk_readl(tegra_pll_p_out5.reg);
9430 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
9431 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
9432 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
9433 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
9435 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
9436 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
9437 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
9439 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
9440 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
9441 *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
9444 *ctx++ = clk_readl(tegra_clk_sclk.reg);
9445 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
9446 *ctx++ = clk_readl(tegra_clk_pclk.reg);
9448 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_LA;
9450 if (off == PERIPH_CLK_SOURCE_EMC)
9452 *ctx++ = clk_readl(off);
9454 for (off = PERIPH_CLK_SOURCE_MSELECT; off <= PERIPH_CLK_SOURCE_SE;
9456 *ctx++ = clk_readl(off);
9458 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
9459 *ctx++ = clk_readl(off);
9461 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
9462 off <= PERIPH_CLK_SOURCE_VIC; off += 4)
9463 *ctx++ = clk_readl(off);
9465 *ctx++ = clk_readl(RST_DEVICES_L);
9466 *ctx++ = clk_readl(RST_DEVICES_H);
9467 *ctx++ = clk_readl(RST_DEVICES_U);
9468 *ctx++ = clk_readl(RST_DEVICES_V);
9469 *ctx++ = clk_readl(RST_DEVICES_W);
9470 *ctx++ = clk_readl(RST_DEVICES_X);
9472 *ctx++ = clk_readl(CLK_OUT_ENB_L);
9473 *ctx++ = clk_readl(CLK_OUT_ENB_H);
9474 *ctx++ = clk_readl(CLK_OUT_ENB_U);
9475 *ctx++ = clk_readl(CLK_OUT_ENB_V);
9476 *ctx++ = clk_readl(CLK_OUT_ENB_W);
9477 *ctx++ = clk_readl(CLK_OUT_ENB_X);
9479 *ctx++ = clk_readlx(tegra_clk_cclk_g.reg);
9480 *ctx++ = clk_readlx(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
9482 *ctx++ = clk_readl(SPARE_REG);
9483 *ctx++ = clk_readl(MISC_CLK_ENB);
9484 *ctx++ = clk_readl(CLK_MASK_ARM);
9486 *ctx++ = clk_get_rate_all_locked(&tegra_clk_emc);
9488 pr_debug("%s: suspend entries: %d, suspend array: %u\n", __func__,
9489 (s32)(ctx - clk_rst_suspend), (u32)ARRAY_SIZE(clk_rst_suspend));
9490 BUG_ON((ctx - clk_rst_suspend) > ARRAY_SIZE(clk_rst_suspend));
9494 static void tegra12_clk_resume(void)
9496 unsigned long off, rate;
9497 const u32 *ctx = clk_rst_suspend;
9501 u32 pll_p_out12, pll_p_out34;
9502 u32 pll_a_out0, pll_m_out1, pll_c_out1;
9505 /* FIXME: OSC_CTRL already restored by warm boot code? */
9506 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
9508 clk_writel(val, OSC_CTRL);
9509 clk_writel(*ctx++, CPU_SOFTRST_CTRL);
9510 clk_writel(*ctx++, CPU_SOFTRST_CTRL1);
9511 clk_writel(*ctx++, CPU_SOFTRST_CTRL2);
9513 /* Since we are going to reset devices and switch clock sources in this
9514 * function, plls and secondary dividers is required to be enabled. The
9515 * actual value will be restored back later. Note that boot plls: pllm,
9516 * pllp, and pllu are already configured and enabled
9518 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
9520 pll_p_out12 = *ctx++;
9521 clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg);
9522 pll_p_out34 = *ctx++;
9523 clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg);
9525 /* Restore as is, GPU is rail-gated, anyway */
9526 clk_writel(*ctx++, tegra_pll_p_out5.reg);
9528 tegra12_pllss_clk_resume_enable(&tegra_pll_c4);
9529 tegra12_pllss_clk_resume_enable(&tegra_pll_d2);
9530 tegra12_pllss_clk_resume_enable(&tegra_pll_dp);
9531 tegra12_pllcx_clk_resume_enable(&tegra_pll_c2);
9532 tegra12_pllcx_clk_resume_enable(&tegra_pll_c3);
9533 tegra12_pllxc_clk_resume_enable(&tegra_pll_c);
9534 tegra12_pllxc_clk_resume_enable(&tegra_pll_x);
9535 tegra12_pllre_clk_resume_enable(&tegra_pll_re_out);
9538 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
9539 clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE);
9542 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
9543 clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE);
9547 val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
9548 pll_m_out1 = *ctx++;
9549 clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg);
9550 pll_a_out0 = *ctx++;
9551 clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg);
9552 pll_c_out1 = *ctx++;
9553 clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
9555 #ifndef CONFIG_ARCH_TEGRA_13x_SOC
9557 tegra12_super_clk_resume(&tegra_clk_cclk_lp,
9558 tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
9559 clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
9562 clk_writel(*ctx++, tegra_clk_sclk.reg);
9563 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
9564 clk_writel(*ctx++, tegra_clk_pclk.reg);
9566 /* enable all clocks before configuring clock sources */
9567 clk_writel(CLK_OUT_ENB_L_RESET_MASK, CLK_OUT_ENB_L);
9568 clk_writel(CLK_OUT_ENB_H_RESET_MASK, CLK_OUT_ENB_H);
9569 clk_writel(CLK_OUT_ENB_U_RESET_MASK, CLK_OUT_ENB_U);
9570 clk_writel(CLK_OUT_ENB_V_RESET_MASK, CLK_OUT_ENB_V);
9571 clk_writel(CLK_OUT_ENB_W_RESET_MASK, CLK_OUT_ENB_W);
9572 clk_writel(CLK_OUT_ENB_X_RESET_MASK, CLK_OUT_ENB_X);
9575 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_LA;
9577 if (off == PERIPH_CLK_SOURCE_EMC)
9579 clk_writel(*ctx++, off);
9581 for (off = PERIPH_CLK_SOURCE_MSELECT; off <= PERIPH_CLK_SOURCE_SE;
9583 clk_writel(*ctx++, off);
9585 for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) {
9586 clk_writel(*ctx++, off);
9588 for (off = PERIPH_CLK_SOURCE_XUSB_HOST;
9589 off <= PERIPH_CLK_SOURCE_VIC; off += 4)
9590 clk_writel(*ctx++, off);
9592 udelay(RESET_PROPAGATION_DELAY);
9594 clk_writel(*ctx++, RST_DEVICES_L);
9595 clk_writel(*ctx++, RST_DEVICES_H);
9596 clk_writel(*ctx++, RST_DEVICES_U);
9597 clk_writel(*ctx++, RST_DEVICES_V);
9598 clk_writel(*ctx++, RST_DEVICES_W);
9599 clk_writel(*ctx++, RST_DEVICES_X);
9602 clk_writel(*ctx++, CLK_OUT_ENB_L);
9603 clk_writel(*ctx++, CLK_OUT_ENB_H);
9604 clk_writel(*ctx++, CLK_OUT_ENB_U);
9606 /* For LP0 resume, clk to lpcpu is required to be on */
9608 val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN;
9609 clk_writel(val, CLK_OUT_ENB_V);
9611 clk_writel(*ctx++, CLK_OUT_ENB_W);
9612 clk_writel(*ctx++, CLK_OUT_ENB_X);
9615 /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
9616 tegra12_dfll_clk_resume(&tegra_dfll_cpu);
9618 /* CPU G clock restored after DFLL and PLLs */
9619 clk_writelx(*ctx++, tegra_clk_cclk_g.reg);
9620 clk_writelx(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
9622 clk_writel(*ctx++, SPARE_REG);
9623 clk_writel(*ctx++, MISC_CLK_ENB);
9624 clk_writel(*ctx++, CLK_MASK_ARM);
9626 /* Restore back the actual pll and secondary divider values */
9627 clk_writel(pll_p_out12, tegra_pll_p_out1.reg);
9628 clk_writel(pll_p_out34, tegra_pll_p_out3.reg);
9631 if (p->state == OFF)
9632 tegra12_pllss_clk_disable(p);
9634 if (p->state == OFF)
9635 tegra12_pllss_clk_disable(p);
9637 if (p->state == OFF)
9638 tegra12_pllss_clk_disable(p);
9640 if (p->state == OFF)
9641 tegra12_pllcx_clk_disable(p);
9643 if (p->state == OFF)
9644 tegra12_pllcx_clk_disable(p);
9646 if (p->state == OFF)
9647 tegra12_pllxc_clk_disable(p);
9649 if (p->state == OFF)
9650 tegra12_pllxc_clk_disable(p);
9651 p = &tegra_pll_re_vco;
9652 if (p->state == OFF)
9653 tegra12_pllre_clk_disable(p);
9655 clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
9656 clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
9658 clk_writel(pll_m_out1, tegra_pll_m_out1.reg);
9659 clk_writel(pll_a_out0, tegra_pll_a_out0.reg);
9660 clk_writel(pll_c_out1, tegra_pll_c_out1.reg);
9662 /* Since EMC clock is not restored, and may not preserve parent across
9663 suspend, update current state, and mark EMC DFS as out of sync */
9664 p = tegra_clk_emc.parent;
9665 tegra12_periph_clk_init(&tegra_clk_emc);
9667 /* Turn Off pll_m if it was OFF before suspend, and emc was not switched
9668 to pll_m across suspend; re-init pll_m to sync s/w and h/w states */
9669 if ((tegra_pll_m.state == OFF) &&
9670 (&tegra_pll_m != tegra_clk_emc.parent))
9671 tegra12_pllm_clk_disable(&tegra_pll_m);
9672 tegra12_pllm_clk_init(&tegra_pll_m);
9674 if (p != tegra_clk_emc.parent) {
9675 pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)",
9676 p->name, p->refcnt, tegra_clk_emc.parent->name,
9677 tegra_clk_emc.parent->refcnt);
9679 /* emc switched to the new parent by low level code, but ref
9680 count and s/w state need to be updated */
9682 clk_enable(tegra_clk_emc.parent);
9685 rate = clk_get_rate_all_locked(&tegra_clk_emc);
9687 tegra_dvfs_set_rate(&tegra_clk_emc, rate);
9688 if (p == tegra_clk_emc.parent) {
9689 rate = clk_get_rate_all_locked(p);
9690 tegra_dvfs_set_rate(p, rate);
9693 tegra_emc_timing_invalidate();
9695 tegra12_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
9696 tegra12_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
9697 tegra12_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
9698 tegra12_mc_holdoff_enable();
9701 static struct syscore_ops tegra_clk_syscore_ops = {
9702 .suspend = tegra12_clk_suspend,
9703 .resume = tegra12_clk_resume,
9704 .save = tegra12_clk_suspend,
9705 .restore = tegra12_clk_resume,
9709 /* Tegra12 CPU clock and reset control functions */
9710 static void tegra12_wait_cpu_in_reset(u32 cpu)
9715 reg = readl(reg_clk_base +
9716 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
9718 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
9723 static void tegra12_put_cpu_in_reset(u32 cpu)
9725 writel(CPU_RESET(cpu),
9726 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
9730 static void tegra12_cpu_out_of_reset(u32 cpu)
9732 writel(CPU_RESET(cpu),
9733 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
9737 static void tegra12_enable_cpu_clock(u32 cpu)
9741 writel(CPU_CLOCK(cpu),
9742 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
9743 reg = readl(reg_clk_base +
9744 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
9746 static void tegra12_disable_cpu_clock(u32 cpu)
9750 static struct tegra_cpu_car_ops tegra12_cpu_car_ops = {
9751 .wait_for_reset = tegra12_wait_cpu_in_reset,
9752 .put_in_reset = tegra12_put_cpu_in_reset,
9753 .out_of_reset = tegra12_cpu_out_of_reset,
9754 .enable_clock = tegra12_enable_cpu_clock,
9755 .disable_clock = tegra12_disable_cpu_clock,
9758 void __init tegra12_cpu_car_ops_init(void)
9760 tegra_cpu_car_ops = &tegra12_cpu_car_ops;
9763 static void tegra12_init_xusb_clocks(void)
9767 for (i = 0; i < ARRAY_SIZE(tegra_xusb_source_clks); i++)
9768 tegra12_init_one_clock(&tegra_xusb_source_clks[i]);
9770 tegra12_init_one_clock(&tegra_xusb_ss_div2);
9771 tegra12_init_one_clock(&tegra_xusb_hs_src);
9773 for (i = 0; i < ARRAY_SIZE(tegra_xusb_coupled_clks); i++)
9774 tegra12_init_one_clock(&tegra_xusb_coupled_clks[i]);
9777 void __init tegra12x_init_clocks(void)
9782 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
9783 tegra12_init_one_clock(tegra_ptr_clks[i]);
9785 /* Fix bug in simulator clock routing */
9786 if (tegra_platform_is_linsim()) {
9787 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) {
9788 if (!strcmp("msenc", tegra_list_clks[i].name)) {
9789 tegra_list_clks[i].u.periph.clk_num = 60;
9790 tegra_list_clks[i].reg = 0x170;
9791 tegra_list_clks[i].flags &= ~MUX8;
9796 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
9797 tegra12_init_one_clock(&tegra_list_clks[i]);
9799 for (i = 0; i < ARRAY_SIZE(tegra_visp_clks); i++)
9800 tegra12_init_one_clock(&tegra_visp_clks[i]);
9802 for (i = 0; i < ARRAY_SIZE(tegra_ptr_camera_mclks); i++)
9803 tegra12_init_one_clock(tegra_ptr_camera_mclks[i]);
9805 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
9806 tegra12_init_one_clock(&tegra_sync_source_list[i]);
9807 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
9808 tegra12_init_one_clock(&tegra_clk_audio_list[i]);
9809 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
9810 tegra12_init_one_clock(&tegra_clk_audio_2x_list[i]);
9813 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
9814 tegra12_init_one_clock(&tegra_clk_out_list[i]);
9816 tegra12_init_xusb_clocks();
9818 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
9819 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
9821 pr_err("%s: Unknown duplicate clock %s\n", __func__,
9822 tegra_clk_duplicates[i].name);
9826 tegra_clk_duplicates[i].lookup.clk = c;
9827 clkdev_add(&tegra_clk_duplicates[i].lookup);
9830 /* Initialize to default */
9831 tegra_init_cpu_edp_limits(0);
9833 tegra12_cpu_car_ops_init();
9835 /* Tegra12 allows to change dividers of disabled clocks */
9836 tegra_clk_set_disabled_div_all();
9838 #ifdef CONFIG_PM_SLEEP
9839 register_syscore_ops(&tegra_clk_syscore_ops);
9844 static int __init tegra12x_clk_late_init(void)
9846 clk_disable(&tegra_pll_d);
9847 clk_disable(&tegra_pll_re_vco);
9850 late_initcall(tegra12x_clk_late_init);