drivers/media/i2c/tc358840.c

   1 /*
   2  * tc358840.c - Toshiba UH2C/D HDMI-CSI bridge driver
   3  *
   4  * Copyright (c) 2015, Armin Weiss <weii@zhaw.ch>
   5  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * This program is based on the tc358840 - Toshiba HDMI to CSI-2 bridge driver
   8  * from Cisco Systems, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23
  24 #include <linux/module.h>
  25
  26 #include <linux/i2c.h>
  27 #include <linux/regmap.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/of_gpio.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/videodev2.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/delay.h>
  35 #include <linux/hdmi.h>
  36 #include <linux/v4l2-dv-timings.h>
  37
  38 #include <media/v4l2-dv-timings.h>
  39 #include <media/v4l2-ctrls.h>
  40 #include <media/v4l2-event.h>
  41 #include <media/v4l2-device.h>
  42 #include <media/v4l2-subdev.h>
  43 #include <media/v4l2-of.h>
  44 #include <media/camera_common.h>
  45
  46 #include <media/i2c/tc358840.h>
  47 #include "tc358840_regs.h"
  48
  49
  50 static int debug;
  51 module_param(debug, int, 0644);
  52 MODULE_PARM_DESC(debug, "debug level (0-3)");
  53
  54 /* TODO: Implement Colorbar TPG */
  55
  56 #define EDID_NUM_BLOCKS_MAX 8
  57 #define EDID_BLOCK_SIZE 128
  58
  59 static u8 edid[] = {
  60         0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
  61         0x52, 0x62, 0x88, 0x88, 0x00, 0x88, 0x88, 0x88,
  62         0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
  63         0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
  64         0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  65         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  66         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xEC, 0x68,
  67         0x00, 0xA0, 0xF0, 0x70, 0x37, 0x80, 0x30, 0x20,
  68         0x3A, 0x00, 0x00, 0x70, 0xF8, 0x00, 0x00, 0x1C,
  69         0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
  70         0x58, 0x2C, 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00,
  71         0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
  72         0x6F, 0x73, 0x68, 0x69, 0x62, 0x61, 0x2D, 0x55,
  73         0x48, 0x32, 0x44, 0x0A, 0x00, 0x00, 0x00, 0xFD,
  74         0x00, 0x17, 0x3D, 0x0F, 0x8C, 0x17, 0x00, 0x0A,
  75         0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xAF,
  76         0x02, 0x03, 0x1A, 0x74, 0x47, 0x32, 0x10, 0x04,
  77         0x32, 0x32, 0x32, 0x32, 0x23, 0x09, 0x07, 0x01,
  78         0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
  79         0x10, 0x00, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0,
  80         0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E,
  81         0x21, 0x00, 0x00, 0x1E, 0xEC, 0x68, 0x00, 0xA0,
  82         0xF0, 0x70, 0x37, 0x80, 0x30, 0x20, 0x3A, 0x00,
  83         0x00, 0x70, 0xF8, 0x00, 0x00, 0x1C, 0xEC, 0x68,
  84         0x00, 0xA0, 0xF0, 0x70, 0x37, 0x80, 0x30, 0x20,
  85         0x3A, 0x00, 0x00, 0x70, 0xF8, 0x00, 0x00, 0x1C,
  86         0xEC, 0x68, 0x00, 0xA0, 0xF0, 0x70, 0x37, 0x80,
  87         0x30, 0x20, 0x3A, 0x00, 0x00, 0x70, 0xF8, 0x00,
  88         0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  89         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  90         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  91         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26,
  92 };
  93
  94 static const struct v4l2_dv_timings_cap tc358840_timings_cap = {
  95         .type = V4L2_DV_BT_656_1120,
  96         /* keep this initialization for compatibility with GCC < 4.4.6 */
  97         .reserved = { 0 },
  98         /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
  99         V4L2_INIT_BT_TIMINGS(
 100                 1, 10000, 1, 10000, 0, 297000000,
 101                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 102                 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 103                 V4L2_DV_BT_CAP_PROGRESSIVE |
 104                 V4L2_DV_BT_CAP_REDUCED_BLANKING |
 105                 V4L2_DV_BT_CAP_CUSTOM)
 106 };
 107
 108 struct tc358840_state {
 109         struct tc358840_platform_data pdata;
 110         struct v4l2_subdev sd;
 111         struct media_pad pad[2];
 112         struct v4l2_ctrl_handler hdl;
 113         struct i2c_client *i2c_client;
 114         bool enabled;
 115         bool format_changed;
 116
 117         /* controls */
 118         struct v4l2_ctrl *detect_tx_5v_ctrl;
 119         struct v4l2_ctrl *audio_sampling_rate_ctrl;
 120         struct v4l2_ctrl *audio_present_ctrl;
 121         struct v4l2_ctrl *splitter_width_ctrl;
 122
 123         /* work queues */
 124         struct workqueue_struct *work_queues;
 125         struct delayed_work delayed_work_enable_hotplug;
 126         struct work_struct process_isr;
 127         struct mutex isr_lock;
 128
 129         /* edid  */
 130         u8 edid_blocks_written;
 131
 132         /* timing / mbus */
 133         struct v4l2_dv_timings timings;
 134         u32 mbus_fmt_code;
 135 };
 136
 137 static inline struct tc358840_state *to_state(struct v4l2_subdev *sd)
 138 {
 139         return container_of(sd, struct tc358840_state, sd);
 140 }
 141
 142
 143 static void tc358840_enable_interrupts(
 144         struct v4l2_subdev *sd, bool cable_connected);
 145 static int tc358840_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
 146 static void tc358840_init_interrupts(struct v4l2_subdev *sd);
 147 static int tc358840_s_dv_timings(
 148         struct v4l2_subdev *sd, struct v4l2_dv_timings *timings);
 149 static void tc358840_set_csi(struct v4l2_subdev *sd);
 150 static void tc358840_set_splitter(struct v4l2_subdev *sd);
 151
 152 /* --------------- I2C --------------- */
 153
 154 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 155 {
 156         struct tc358840_state *state = to_state(sd);
 157         struct i2c_client *client = state->i2c_client;
 158         int err;
 159         u8 buf[2] = { reg >> 8, reg & 0xff };
 160         struct i2c_msg msgs[] = {
 161                 {
 162                         .addr = client->addr,
 163                         .flags = 0,
 164                         .len = 2,
 165                         .buf = buf,
 166                 },
 167                 {
 168                         .addr = client->addr,
 169                         .flags = I2C_M_RD,
 170                         .len = n,
 171                         .buf = values,
 172                 },
 173         };
 174
 175         err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 176         if (err != ARRAY_SIZE(msgs)) {
 177                 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
 178                         __func__, reg, client->addr);
 179         }
 180
 181         if (debug < 3)
 182                 return;
 183
 184         switch (n) {
 185         case 1:
 186                 v4l2_info(sd, "I2C read 0x%04X = 0x%02X\n", reg, values[0]);
 187                 break;
 188         case 2:
 189                 v4l2_info(sd, "I2C read 0x%04X = 0x%02X%02X\n",
 190                         reg, values[1], values[0]);
 191                 break;
 192         case 4:
 193                 v4l2_info(sd, "I2C read 0x%04X = 0x%02X%02X%02X%02X\n",
 194                         reg, values[3], values[2], values[1], values[0]);
 195                 break;
 196         default:
 197                 v4l2_info(sd, "I2C read %d bytes from address 0x%04X\n",
 198                         n, reg);
 199         }
 200
 201 }
 202
 203 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
 204 {
 205         struct tc358840_state *state = to_state(sd);
 206         struct i2c_client *client = state->i2c_client;
 207         int err, i;
 208         struct i2c_msg msg;
 209         u8 data[2 + n];
 210
 211         msg.addr = client->addr;
 212         msg.buf = data;
 213         msg.len = 2 + n;
 214         msg.flags = 0;
 215
 216         data[0] = reg >> 8;
 217         data[1] = reg & 0xff;
 218
 219         for (i = 0; i < n; i++)
 220                 data[2 + i] = values[i];
 221
 222         err = i2c_transfer(client->adapter, &msg, 1);
 223         if (err != 1) {
 224                 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
 225                         __func__, reg, client->addr);
 226                 return;
 227         }
 228
 229         if (debug < 3)
 230                 return;
 231
 232         switch (n) {
 233         case 1:
 234                 v4l2_info(sd, "I2C write 0x%04X = 0x%02X\n", reg, data[2]);
 235                 break;
 236         case 2:
 237                 v4l2_info(sd, "I2C write 0x%04X = 0x%02X%02X\n",
 238                         reg, data[3], data[2]);
 239                 break;
 240         case 4:
 241                 v4l2_info(sd, "I2C write 0x%04X = 0x%02X%02X%02X%02X\n",
 242                         reg, data[5], data[4], data[3], data[2]);
 243                 break;
 244         default:
 245                 v4l2_info(sd, "I2C write %d bytes from address 0x%04X\n",
 246                         n, reg);
 247         }
 248 }
 249
 250 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
 251 {
 252         u8 val;
 253
 254         i2c_rd(sd, reg, &val, 1);
 255
 256         return val;
 257 }
 258
 259 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
 260 {
 261         i2c_wr(sd, reg, &val, 1);
 262 }
 263
 264 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
 265                 u8 mask, u8 val)
 266 {
 267         i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
 268 }
 269
 270 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
 271 {
 272         u16 val;
 273
 274         i2c_rd(sd, reg, (u8 *)&val, 2);
 275
 276         return val;
 277 }
 278
 279 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
 280 {
 281         i2c_wr(sd, reg, (u8 *)&val, 2);
 282 }
 283
 284 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
 285 {
 286         i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
 287 }
 288
 289 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
 290 {
 291         u32 val;
 292
 293         i2c_rd(sd, reg, (u8 *)&val, 4);
 294
 295         return val;
 296 }
 297
 298 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
 299 {
 300         i2c_wr(sd, reg, (u8 *)&val, 4);
 301 }
 302
 303 static void i2c_wr32_and_or(struct v4l2_subdev *sd, u32 reg, u32 mask, u32 val)
 304 {
 305         i2c_wr32(sd, reg, (i2c_rd32(sd, reg) & mask) | val);
 306 }
 307
 308 /* --------------- STATUS --------------- */
 309
 310 static inline bool is_hdmi(struct v4l2_subdev *sd)
 311 {
 312         return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
 313 }
 314
 315 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
 316 {
 317         return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
 318 }
 319
 320 static inline bool no_signal(struct v4l2_subdev *sd)
 321 {
 322         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
 323 }
 324
 325 static inline bool no_sync(struct v4l2_subdev *sd)
 326 {
 327         return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
 328 }
 329
 330 static inline bool audio_present(struct v4l2_subdev *sd)
 331 {
 332         return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
 333 }
 334
 335 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
 336 {
 337         static const int code_to_rate[] = {
 338                 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
 339                 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
 340         };
 341
 342         /* Register FS_SET is not cleared when the cable is disconnected */
 343         if (no_signal(sd))
 344                 return 0;
 345
 346         return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
 347 }
 348
 349 static unsigned tc358840_num_csi_lanes_in_use(struct v4l2_subdev *sd)
 350 {
 351         /* FIXME: Read # of lanes from both, TX0 and TX1 */
 352         return i2c_rd32(sd, CSITX0_BASE_ADDR+LANEEN) & MASK_LANES;
 353 }
 354
 355 /* --------------- TIMINGS --------------- */
 356
 357 static inline unsigned fps(const struct v4l2_bt_timings *t)
 358 {
 359         if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
 360                 return 0;
 361
 362         return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
 363                         V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
 364 }
 365
 366 static int tc358840_get_detected_timings(struct v4l2_subdev *sd,
 367                 struct v4l2_dv_timings *timings)
 368 {
 369         struct v4l2_bt_timings *bt = &timings->bt;
 370         unsigned width, height, frame_width, frame_height, frame_interval, fps;
 371
 372         memset(timings, 0, sizeof(struct v4l2_dv_timings));
 373
 374         if (no_signal(sd)) {
 375                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
 376                 return -ENOLINK;
 377         }
 378         if (no_sync(sd)) {
 379                 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
 380                 return -ENOLCK;
 381         }
 382
 383         timings->type = V4L2_DV_BT_656_1120;
 384
 385         bt->interlaced = i2c_rd8(sd, VI_STATUS1) &
 386                 MASK_S_V_INTERLACE ? V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
 387
 388         width = ((i2c_rd8(sd, DE_HSIZE_HI) & 0x1f) << 8) +
 389                 i2c_rd8(sd, DE_HSIZE_LO);
 390         height = ((i2c_rd8(sd, DE_VSIZE_HI) & 0x1f) << 8) +
 391                 i2c_rd8(sd, DE_VSIZE_LO);
 392         frame_width = ((i2c_rd8(sd, IN_HSIZE_HI) & 0x1f) << 8) +
 393                 i2c_rd8(sd, IN_HSIZE_LO);
 394         frame_height = (((i2c_rd8(sd, IN_VSIZE_HI) & 0x3f) << 8) +
 395                 i2c_rd8(sd, IN_VSIZE_LO)) / 2;
 396
 397         /* TODO: Check if frame_interval is correct
 398          * since the register is not in the datasheet rev. 1.5 */
 399
 400         /* frame interval in milliseconds * 10
 401          * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
 402         frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
 403                 i2c_rd8(sd, FV_CNT_LO);
 404         fps = (frame_interval > 0) ?
 405                 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
 406
 407         bt->width = width;
 408         bt->height = height;
 409         bt->vsync = frame_height - height;
 410         bt->hsync = frame_width - width;
 411         bt->pixelclock = frame_width * frame_height * fps;
 412         if (bt->interlaced == V4L2_DV_INTERLACED) {
 413                 bt->height *= 2;
 414                 bt->il_vsync = bt->vsync + 1;
 415                 bt->pixelclock /= 2;
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* --------------- HOTPLUG / HDCP / EDID --------------- */
 422
 423 static void tc358840_delayed_work_enable_hotplug(struct work_struct *work)
 424 {
 425         struct delayed_work *dwork = to_delayed_work(work);
 426         struct tc358840_state *state = container_of(dwork,
 427                 struct tc358840_state, delayed_work_enable_hotplug);
 428         struct v4l2_subdev *sd = &state->sd;
 429
 430         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 431
 432         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
 433 }
 434
 435 static void tc358840_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
 436 {
 437         v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
 438                                 "enable" : "disable");
 439
 440         i2c_wr8_and_or(sd, HDCP_REG1,
 441                         ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
 442                         MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
 443
 444         i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
 445                         SET_AUTO_P3_RESET_FRAMES(0x0f));
 446
 447         /* HDCP is disabled by configuring the receiver as HDCP repeater. The
 448          * repeater mode require software support to work, so HDCP
 449          * authentication will fail.
 450          */
 451         i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
 452         i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
 453                         enable ?  (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
 454
 455         /* Apple MacBook Pro gen.8 has a bug that makes it freeze every fifth
 456          * second when HDCP is disabled, but the MAX_EXCED bit is handled
 457          * correctly and HDCP is disabled on the HDMI output.
 458          */
 459         i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
 460                         enable ? 0 : MASK_MAX_EXCED);
 461         i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
 462                         enable ? 0 : MASK_REPEATER | MASK_READY);
 463 }
 464
 465 static void tc358840_disable_edid(struct v4l2_subdev *sd)
 466 {
 467         struct tc358840_state *state = to_state(sd);
 468
 469         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 470
 471         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
 472
 473         /* DDC access to EDID is also disabled when hotplug is disabled. See
 474          * register DDC_CTL */
 475         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
 476 }
 477
 478 static void tc358840_enable_edid(struct v4l2_subdev *sd)
 479 {
 480         struct tc358840_state *state = to_state(sd);
 481
 482         if (state->edid_blocks_written == 0) {
 483                 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
 484                 return;
 485         }
 486
 487         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 488
 489         /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
 490          * hotplug is enabled. See register DDC_CTL */
 491         queue_delayed_work(state->work_queues,
 492                 &state->delayed_work_enable_hotplug, HZ / 10);
 493
 494         tc358840_enable_interrupts(sd, true);
 495         tc358840_s_ctrl_detect_tx_5v(sd);
 496 }
 497
 498 static void tc358840_erase_bksv(struct v4l2_subdev *sd)
 499 {
 500         int i;
 501
 502         for (i = 0; i < 5; i++)
 503                 i2c_wr8(sd, BKSV + i, 0);
 504 }
 505
 506 /* --------------- AVI infoframe --------------- */
 507
 508 static void print_avi_infoframe(struct v4l2_subdev *sd)
 509 {
 510         struct i2c_client *client = v4l2_get_subdevdata(sd);
 511         struct device *dev = &client->dev;
 512         union hdmi_infoframe frame;
 513         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
 514
 515         if (!is_hdmi(sd)) {
 516                 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
 517                 return;
 518         }
 519
 520         i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
 521
 522         if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
 523                 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
 524                 return;
 525         }
 526
 527         hdmi_infoframe_log(KERN_INFO, dev, &frame);
 528 }
 529
 530 /* --------------- CTRLS --------------- */
 531
 532 static int tc358840_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
 533 {
 534         struct tc358840_state *state = to_state(sd);
 535
 536         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 537                 tx_5v_power_present(sd));
 538 }
 539
 540 static int tc358840_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
 541 {
 542         struct tc358840_state *state = to_state(sd);
 543
 544         return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
 545                         get_audio_sampling_rate(sd));
 546 }
 547
 548 static int tc358840_s_ctrl_audio_present(struct v4l2_subdev *sd)
 549 {
 550         struct tc358840_state *state = to_state(sd);
 551
 552         return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
 553                         audio_present(sd));
 554 }
 555
 556 static int tc358840_update_controls(struct v4l2_subdev *sd)
 557 {
 558         int ret = 0;
 559
 560         ret |= tc358840_s_ctrl_detect_tx_5v(sd);
 561         ret |= tc358840_s_ctrl_audio_sampling_rate(sd);
 562         ret |= tc358840_s_ctrl_audio_present(sd);
 563
 564         return ret;
 565 }
 566
 567 /* --------------- INIT --------------- */
 568
 569 static void tc358840_reset_phy(struct v4l2_subdev *sd)
 570 {
 571         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 572
 573         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
 574         i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
 575 }
 576
 577 static void tc358840_reset(struct v4l2_subdev *sd, u16 mask)
 578 {
 579         u16 sysctl = i2c_rd16(sd, SYSCTL);
 580
 581         i2c_wr16(sd, SYSCTL, sysctl | mask);
 582         i2c_wr16(sd, SYSCTL, sysctl & ~mask);
 583 }
 584
 585 static inline void tc358840_sleep_mode(struct v4l2_subdev *sd, bool enable)
 586 {
 587         v4l2_dbg(1, debug, sd, "%s(): %s\n", __func__,
 588                 enable ? "enable" : "disable");
 589
 590         i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP, enable ? MASK_SLEEP : 0);
 591 }
 592
 593 static int enable_stream(struct v4l2_subdev *sd, bool enable)
 594 {
 595         struct tc358840_state *state = to_state(sd);
 596         struct tc358840_platform_data *pdata = &state->pdata;
 597
 598         u32 sync_timeout_ctr;
 599
 600         v4l2_dbg(2, debug, sd, "%s: %sable\n", __func__, enable ? "en" : "dis");
 601
 602         if (enable == state->enabled)
 603                 return;
 604
 605         if (enable) {
 606 #if 0           /* Wait until we can use the clock-noncontinuous property */
 607                 if (pdata->endpoint.bus.mipi_csi2.flags &
 608                     V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) {
 609                         i2c_wr32_and_or(sd, FUNCMODE, ~(MASK_CONTCLKMODE),
 610                                         MASK_FORCESTOP);
 611                 } else {
 612                         /* It is critical for CSI receiver to see lane transition
 613                          * LP11->HS. Set to non-continuous mode to enable clock lane
 614                          * LP11 state. */
 615                         i2c_wr32_and_or(sd, FUNCMODE, ~(MASK_CONTCLKMODE), 0);
 616                         /* Set to continuous mode to trigger LP11->HS transition */
 617                         i2c_wr32_and_or(sd, FUNCMODE, 0, MASK_CONTCLKMODE);
 618                 }
 619 #else
 620                 i2c_wr32_and_or(sd, FUNCMODE, ~(MASK_CONTCLKMODE),
 621                                 MASK_FORCESTOP);
 622 #endif
 623                 /* Unmute video */
 624                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
 625                 /* Signal end of initialization */
 626                 i2c_wr8(sd, INIT_END, MASK_INIT_END);
 627         } else {
 628                 /* Enable Registers to be initialized */
 629                 i2c_wr8_and_or(sd, INIT_END, ~(MASK_INIT_END), 0x00);
 630
 631                 /* Mute video so that all data lanes go to LSP11 state.
 632                  * No data is output to CSI Tx block. */
 633
 634                 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
 635                 tc358840_set_csi(sd);
 636                 tc358840_set_splitter(sd);
 637         }
 638
 639         /* Wait for HDMI input to become stable */
 640         if (enable) {
 641                 sync_timeout_ctr = 100;
 642                 while (no_sync(sd) && sync_timeout_ctr)
 643                         sync_timeout_ctr--;
 644
 645                 if (sync_timeout_ctr == 0) {
 646                         /* Disable stream again. Probably no cable inserted.. */
 647                         v4l2_err(sd, "%s: Timeout: HDMI input sync failed.\n",
 648                                         __func__);
 649                         enable_stream(sd, false);
 650                         return -EIO;
 651                 }
 652
 653                 v4l2_dbg(2, debug, sd,
 654                         "%s: Stream enabled! Remaining timeout attempts: %d\n",
 655                         __func__, sync_timeout_ctr);
 656         }
 657
 658         i2c_wr16_and_or(sd, CONFCTL0,
 659                 ~(MASK_VTX0EN | MASK_VTX1EN | MASK_ABUFEN),
 660                 enable ? ((pdata->csi_port & (MASK_VTX0EN | MASK_VTX1EN)) |
 661                 MASK_ABUFEN | MASK_TX_MSEL | MASK_AUTOINDEX) :
 662                 (MASK_TX_MSEL | MASK_AUTOINDEX));
 663         state->enabled = enable;
 664
 665         return 0;
 666 }
 667
 668 static void tc358840_set_splitter(struct v4l2_subdev *sd)
 669 {
 670         struct tc358840_state *state = to_state(sd);
 671
 672         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
 673
 674         if (state->timings.bt.width <= 1920) {
 675                 i2c_wr16_and_or(sd, SPLITTX0_CTRL, ~(MASK_IFEN | MASK_LCD_CSEL),
 676                                 MASK_SPBP);
 677                 i2c_wr16_and_or(sd, SPLITTX1_CTRL, ~(MASK_IFEN | MASK_LCD_CSEL),
 678                                 MASK_SPBP);
 679
 680                 i2c_wr16_and_or(sd, SPLITTX0_SPLIT, (u16)~(MASK_TX1SEL | MASK_EHW), 0);
 681         } else {
 682                 i2c_wr16_and_or(sd, SPLITTX0_CTRL, ~(MASK_IFEN | MASK_LCD_CSEL | MASK_SPBP), 0);
 683                 i2c_wr16_and_or(sd, SPLITTX1_CTRL, ~(MASK_IFEN | MASK_LCD_CSEL | MASK_SPBP), 0);
 684
 685                 i2c_wr16_and_or(sd, SPLITTX0_SPLIT, ~(MASK_TX1SEL), MASK_EHW);
 686         }
 687 }
 688
 689 static void tc358840_set_pll(struct v4l2_subdev *sd,
 690                                 enum tc358840_csi_port port)
 691 {
 692         struct tc358840_state *state = to_state(sd);
 693         struct tc358840_platform_data *pdata = &state->pdata;
 694         u16 base_addr;
 695         u16 pll_frs;
 696         u32 pllconf;
 697         u32 pllconf_new;
 698         u32 hsck;
 699
 700         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
 701
 702         BUG_ON((pdata->csi_port <= CSI_TX_NONE) ||
 703                 (pdata->csi_port > CSI_TX_BOTH));
 704
 705         if (pdata->csi_port == CSI_TX_NONE) {
 706                 v4l2_err(sd, "%s: No CSI port defined!\n", __func__);
 707                 return;
 708         }
 709
 710         base_addr = (port == CSI_TX_0) ? CSITX0_BASE_ADDR :
 711                                         CSITX1_BASE_ADDR;
 712         pllconf = i2c_rd32(sd, base_addr+PLLCONF);
 713         pllconf_new = SET_PLL_PRD(pdata->pll_prd) |
 714         SET_PLL_FBD(pdata->pll_fbd);
 715
 716         hsck = (pdata->refclk_hz / pdata->pll_prd) *
 717                         pdata->pll_fbd;
 718
 719         if (hsck > 500000000)
 720                 pll_frs = 0x0;
 721         else if (hsck > 250000000)
 722                 pll_frs = 0x1;
 723         else if (hsck > 125000000)
 724                 pll_frs = 0x2;
 725         else
 726                 pll_frs = 0x3;
 727
 728         v4l2_dbg(1, debug, sd, "%s: Updating PLL clock of CSI TX%d\n",
 729                         __func__, port-1);
 730
 731         i2c_wr32(sd, base_addr+PLLCONF,
 732                         pllconf_new | SET_PLL_FRS(pll_frs));
 733 }
 734
 735 static void tc358840_set_ref_clk(struct v4l2_subdev *sd)
 736 {
 737         struct tc358840_state *state = to_state(sd);
 738         struct tc358840_platform_data *pdata = &state->pdata;
 739
 740         u32 sys_freq;
 741         u32 lock_ref_freq;
 742         u32 nco;
 743         u16 csc;
 744
 745         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
 746
 747         BUG_ON((pdata->refclk_hz < 40000000) || (pdata->refclk_hz > 50000000));
 748
 749         /* System Frequency */
 750         sys_freq = pdata->refclk_hz / 10000;
 751         i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00FF);
 752         i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xFF00) >> 8);
 753
 754         /* Audio System Frequency */
 755         lock_ref_freq = pdata->refclk_hz / 100;
 756         i2c_wr8(sd, LOCK_REF_FREQA, lock_ref_freq & 0xFF);
 757         i2c_wr8(sd, LOCK_REF_FREQB, (lock_ref_freq >> 8) & 0xFF);
 758         i2c_wr8(sd, LOCK_REF_FREQC, (lock_ref_freq >> 16) & 0x0F);
 759
 760         /* Audio PLL */
 761         i2c_wr8(sd, NCO_F0_MOD, MASK_NCO_F0_MOD_REG);
 762         /* 6.144 * 2^28 = 1649267442 */
 763         nco = (1649267442 / (pdata->refclk_hz / 1000000));
 764         i2c_wr8(sd, NCO_48F0A, nco & 0xFF);
 765         i2c_wr8(sd, NCO_48F0B, (nco >> 8) & 0xFF);
 766         i2c_wr8(sd, NCO_48F0C, (nco >> 16) & 0xFF);
 767         i2c_wr8(sd, NCO_48F0D, (nco >> 24) & 0xFF);
 768
 769         /* Color Space Conversion */
 770         csc = pdata->refclk_hz / 10000;
 771         i2c_wr8(sd, SCLK_CSC0, csc & 0xFF);
 772         i2c_wr8(sd, SCLK_CSC1, (csc >> 8) & 0xFF);
 773 }
 774
 775 static void tc358840_set_csi_mbus_config(struct v4l2_subdev *sd)
 776 {
 777         struct tc358840_state *state = to_state(sd);
 778
 779         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
 780
 781         switch (state->mbus_fmt_code) {
 782         case V4L2_MBUS_FMT_UYVY8_1X16:
 783                 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
 784
 785                 i2c_wr8(sd, VOUT_FMT, MASK_OUTFMT_422 | MASK_422FMT_NORMAL);
 786                 i2c_wr8(sd, VOUT_FIL, MASK_422FIL_3_TAP_444 |
 787                         MASK_444FIL_2_TAP);
 788                 i2c_wr8(sd, VOUT_SYNC0, MASK_MODE_2);
 789                 i2c_wr8(sd, VOUT_CSC, MASK_CSC_MODE_BUILTIN |
 790                         MASK_COLOR_601_YCBCR_LIMITED);
 791                 i2c_wr16_and_or(sd, CONFCTL0, ~(MASK_YCBCRFMT),
 792                         MASK_YCBCRFMT_YCBCR422_8);
 793                 i2c_wr16(sd, CONFCTL1, 0x0);
 794                 break;
 795
 796         case V4L2_MBUS_FMT_RGB888_1X24:
 797                 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
 798
 799                 i2c_wr8(sd, VOUT_FMT, MASK_OUTFMT_444_RGB);
 800                 i2c_wr8(sd, VOUT_FIL, MASK_422FIL_3_TAP_444 |
 801                         MASK_444FIL_2_TAP);
 802                 i2c_wr8(sd, VOUT_SYNC0, MASK_MODE_2);
 803                 i2c_wr8(sd, VOUT_CSC, MASK_CSC_MODE_BUILTIN |
 804                         MASK_COLOR_RGB_LIMITED);
 805                 i2c_wr16_and_or(sd, CONFCTL0, ~(MASK_YCBCRFMT), 0x0);
 806                 i2c_wr16_and_or(sd, CONFCTL1, 0x0, MASK_TX_OUT_FMT_RGB888);
 807                 break;
 808
 809         default:
 810                 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
 811                                 __func__, state->mbus_fmt_code);
 812                 break;
 813         }
 814 }
 815
 816 static unsigned tc358840_num_csi_lanes_needed(struct v4l2_subdev *sd)
 817 {
 818
 819         /* TODO: Check if this can be useful */
 820 #if 0
 821         struct tc358840_state *state = to_state(sd);
 822         struct v4l2_bt_timings *bt = &state->timings.bt;
 823         struct tc358840_platform_data *pdata = &state->pdata;
 824         u32 bits_pr_pixel =
 825                 (state->mbus_fmt_code == V4L2_MBUS_FMT_UYVY8_1X16) ?  16 : 24;
 826         u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
 827         u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
 828
 829         return DIV_ROUND_UP(bps, bps_pr_lane);
 830 #endif
 831
 832         /* Always use 4 lanes for one CSI */
 833         return 4;
 834 }
 835
 836 static void tc358840_set_csi(struct v4l2_subdev *sd)
 837 {
 838         struct tc358840_state *state = to_state(sd);
 839         struct tc358840_platform_data *pdata = &state->pdata;
 840 #if 0
 841         struct v4l2_bt_timings *bt = &state->timings.bt;
 842 #endif
 843         unsigned lanes = tc358840_num_csi_lanes_needed(sd);
 844
 845         enum tc358840_csi_port port;
 846         u16 base_addr;
 847
 848         v4l2_dbg(3, debug, sd, "%s:\n", __func__);
 849
 850         tc358840_reset(sd, MASK_CTXRST);
 851
 852         for (port = CSI_TX_0; port <= CSI_TX_1; port++) {
 853                 base_addr = (port == CSI_TX_0) ? CSITX0_BASE_ADDR :
 854                                                  CSITX1_BASE_ADDR;
 855
 856                 if (pdata->csi_port != CSI_TX_BOTH &&
 857                     pdata->csi_port != port) {
 858                         v4l2_dbg(1, debug, sd,
 859                                 "%s: Disabling CSI TX%d\n", __func__, port-1);
 860
 861                         /* Disable CSI lanes (High Z)*/
 862                         i2c_wr32_and_or(sd, base_addr+LANEEN,
 863                                 ~(MASK_CLANEEN), 0);
 864                         continue;
 865                 }
 866
 867                 v4l2_dbg(1, debug, sd,
 868                         "%s: Enabling CSI TX%d\n", __func__, port-1);
 869
 870                 /* (0x0108) */
 871                 i2c_wr32(sd, base_addr+CSITX_CLKEN, MASK_CSITX_EN);
 872                 /*
 873                  * PLL has to be enabled between CSITX_CLKEN and
 874                  * LANEEN (0x02AC)
 875                  */
 876                 tc358840_set_pll(sd, port);
 877                 /* (0x02A0) */
 878                 i2c_wr32_and_or(sd, base_addr+MIPICLKEN,
 879                         ~(MASK_MP_CKEN), MASK_MP_ENABLE);
 880                 usleep_range(10000, 11000);
 881                 /* (0x02A0) */
 882                 i2c_wr32(sd, base_addr+MIPICLKEN,
 883                         MASK_MP_CKEN | MASK_MP_ENABLE);
 884                 /* (0x010C) */
 885                 i2c_wr32(sd, base_addr+PPICLKEN, MASK_HSTXCLKEN);
 886                 /* (0x0118) */
 887                 i2c_wr32(sd, base_addr+LANEEN,
 888                         (lanes & MASK_LANES) | MASK_CLANEEN);
 889
 890                 /* (0x0120) */
 891                 i2c_wr32(sd, base_addr+LINEINITCNT, pdata->lineinitcnt);
 892
 893                 /*
 894                  * TODO: Check if this is the correct register
 895                  * (0x0150)
 896                  */
 897                 i2c_rd32(sd, base_addr+FUNCMODE);
 898                 /* (0x0254) */
 899                 i2c_wr32(sd, base_addr+LPTXTIMECNT, pdata->lptxtimecnt);
 900                 /* (0x0258) */
 901                 i2c_wr32(sd, base_addr+TCLK_HEADERCNT,
 902                         pdata->tclk_headercnt);
 903                 /* (0x025C) */
 904                 i2c_wr32(sd, base_addr+TCLK_TRAILCNT,
 905                         pdata->tclk_trailcnt);
 906                 /* (0x0260) */
 907                 i2c_wr32(sd, base_addr+THS_HEADERCNT,
 908                         pdata->ths_headercnt);
 909                 /* (0x0264) */
 910                 i2c_wr32(sd, base_addr+TWAKEUP, pdata->twakeup);
 911                 /* (0x0268) */
 912                 i2c_wr32(sd, base_addr+TCLK_POSTCNT,
 913                         pdata->tclk_postcnt);
 914                 /* (0x026C) */
 915                 i2c_wr32(sd, base_addr+THS_TRAILCNT,
 916                         pdata->ths_trailcnt);
 917
 918                 /* (0x0270) */
 919                 i2c_wr32(sd, base_addr+HSTXVREGCNT, pdata->hstxvregcnt);
 920
 921                 /* (0x0274) */
 922                 i2c_wr32(sd, base_addr+HSTXVREGEN,
 923                         ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
 924                         ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
 925                         ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
 926                         ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
 927                         ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
 928
 929                 /*
 930                  * Finishing configuration by setting CSITX to start
 931                  * (0X011C)
 932                  */
 933                 i2c_wr32(sd, base_addr+CSITX_START, 0x00000001);
 934
 935                 i2c_rd32(sd, base_addr+CSITX_INTERNAL_STAT);
 936         }
 937 }
 938
 939 static void tc358840_set_hdmi_phy(struct v4l2_subdev *sd)
 940 {
 941         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
 942
 943         /* Reset PHY */
 944         tc358840_reset_phy(sd);
 945
 946         /* Set PHY to manual */
 947         i2c_wr8(sd, PHY_CTL, MASK_48_MHZ);
 948
 949         /* Enable PHY */
 950         i2c_wr8_and_or(sd, PHY_ENB, ~MASK_ENABLE_PHY, 0x0);
 951         i2c_wr8_and_or(sd, PHY_ENB, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
 952
 953         /* Enable Audio PLL */
 954         i2c_wr8(sd, APPL_CTL, MASK_APLL_CPCTL_NORMAL | MASK_APLL_ON);
 955
 956         /* Enable DDC IO */
 957         i2c_wr8(sd, DDCIO_CTL, MASK_DDC_PWR_ON);
 958 }
 959
 960 static void tc358840_set_hdmi_audio(struct v4l2_subdev *sd)
 961 {
 962         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
 963
 964         i2c_wr8(sd, FORCE_MUTE, 0x00);
 965         i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
 966                         MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
 967                         MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
 968         i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
 969         i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
 970         i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
 971         i2c_wr8(sd, FS_MUTE, 0x00);
 972         i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
 973         i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
 974         i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
 975         i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
 976         /*
 977          * TODO: Set output data bit length (currently 16 bit, 8 bit discarded)
 978          */
 979         i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
 980         i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
 981         i2c_wr16_and_or(sd, CONFCTL0, 0xFFFF, MASK_AUDCHNUM_2 |
 982                         MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
 983 }
 984
 985 static void tc358840_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
 986 {
 987         v4l2_dbg(3, debug, sd, "%s(): DUMMY\n", __func__);
 988
 989         /* TODO: Check which registers are needed/available */
 990 #if 0
 991         i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
 992                         MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
 993                         MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
 994                         MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
 995         i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
 996         i2c_wr8(sd, NO_PKT_CLR, 0x53);
 997         i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
 998         i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
 999         i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
1000 #endif
1001 }
1002
1003 static void tc358840_initial_setup(struct v4l2_subdev *sd)
1004 {
1005         static struct v4l2_dv_timings default_timing = V4L2_DV_BT_CEA_1920X1080P60;
1006         struct tc358840_state *state = to_state(sd);
1007         struct tc358840_platform_data *pdata = &state->pdata;
1008
1009         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1010
1011         /* *** Reset *** */
1012         enable_stream(sd, false);
1013
1014         tc358840_sleep_mode(sd, false);
1015         tc358840_reset(sd, MASK_RESET_ALL);
1016
1017         tc358840_init_interrupts(sd);
1018
1019         /* *** Init CSI *** */
1020         tc358840_s_dv_timings(sd, &default_timing);
1021
1022         tc358840_set_ref_clk(sd);
1023
1024         i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
1025                        pdata->ddc5v_delay & MASK_DDC5V_MODE);
1026
1027         i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE_ALL, MASK_RAM_EDDC);
1028
1029         i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_CTL0, 0);
1030
1031         tc358840_set_hdmi_phy(sd);
1032
1033         tc358840_set_hdmi_hdcp(sd, pdata->enable_hdcp);
1034         tc358840_set_hdmi_audio(sd);
1035         tc358840_set_hdmi_info_frame_mode(sd);
1036
1037         /* All CE and IT formats are detected as RGB full range in DVI mode */
1038         i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
1039 }
1040
1041 /* --------------- IRQ --------------- */
1042
1043 static void tc358840_format_change(struct v4l2_subdev *sd)
1044 {
1045         struct tc358840_state *state = to_state(sd);
1046         struct v4l2_dv_timings timings;
1047         static const struct v4l2_event tc358840_ev_fmt = {
1048                 .type = V4L2_EVENT_SOURCE_CHANGE,
1049                 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1050         };
1051
1052         if (tc358840_get_detected_timings(sd, &timings)) {
1053                 enable_stream(sd, false);
1054
1055                 v4l2_info(sd, "%s: No Signal\n", __func__);
1056         } else {
1057                 if (!v4l2_match_dv_timings(&state->timings, &timings, 0))
1058                         enable_stream(sd, false);
1059
1060                 v4l2_print_dv_timings(sd->name,
1061                                 "tc358840_format_change: New format: ",
1062                                 &timings, false);
1063         }
1064
1065         /* Application gets notified after CSI Tx's are reset */
1066         if (sd->devnode)
1067                 v4l2_subdev_notify_event(sd, &tc358840_ev_fmt);
1068 }
1069
1070 static void tc358840_init_interrupts(struct v4l2_subdev *sd)
1071 {
1072         u16 i;
1073
1074         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1075
1076         /* clear interrupt status registers */
1077         for (i = SYS_INT; i <= MISC_INT; i++) {
1078                 /* No interrupt register at Address 0x850A */
1079                 if (i != 0x850A)
1080                         i2c_wr8(sd, i, 0xFF);
1081         }
1082
1083         /* Clear and disable all interrupts */
1084         i2c_wr16(sd, INTSTATUS, MASK_INT_STATUS_MASK_ALL);
1085         i2c_wr16(sd, INTSTATUS, 0x0);
1086
1087         i2c_wr16(sd, INTMASK, MASK_INT_STATUS_MASK_ALL);
1088 }
1089
1090 static void tc358840_enable_interrupts(struct v4l2_subdev *sd,
1091                 bool cable_connected)
1092 {
1093         v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1094                         cable_connected);
1095
1096         if (cable_connected) {
1097                 i2c_wr8(sd, SYS_INTM, ~(MASK_DDC | MASK_DVI |
1098                                         MASK_HDMI) & 0xFF);
1099                 i2c_wr8(sd, SYS_INTM, ~(MASK_DDC) & 0xFF);
1100                 i2c_wr8(sd, CLK_INTM, ~MASK_IN_DE_CHG);
1101                 i2c_wr8(sd, CBIT_INTM, ~(MASK_CBIT_FS | MASK_AF_LOCK |
1102                                         MASK_AF_UNLOCK) & 0xFF);
1103                 i2c_wr8(sd, AUDIO_INTM, ~MASK_BUFINIT_END);
1104                 i2c_wr8(sd, MISC_INTM, ~MASK_SYNC_CHG);
1105         } else {
1106                 i2c_wr8(sd, SYS_INTM, ~MASK_DDC & 0xFF);
1107                 i2c_wr8(sd, CLK_INTM, 0xFF);
1108                 i2c_wr8(sd, CBIT_INTM, 0xFF);
1109                 i2c_wr8(sd, AUDIO_INTM, 0xFF);
1110                 i2c_wr8(sd, MISC_INTM, 0xFF);
1111         }
1112 }
1113
1114 static void tc358840_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1115                 bool *handled)
1116 {
1117         u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1118         u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1119
1120         i2c_wr8(sd, AUDIO_INT, audio_int);
1121
1122         v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1123
1124         tc358840_s_ctrl_audio_sampling_rate(sd);
1125         tc358840_s_ctrl_audio_present(sd);
1126 }
1127
1128 static void tc358840_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1129                 bool *handled)
1130 {
1131         struct tc358840_state *state = to_state(sd);
1132         u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1133         u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1134
1135         i2c_wr8(sd, MISC_INT, misc_int);
1136
1137         v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1138
1139         if (misc_int & MASK_SYNC_CHG) {
1140                 /* Reset the HDMI PHY to try to trigger proper lock on the
1141                  * incoming video format. Erase BKSV to prevent that old keys
1142                  * are used when a new source is connected. */
1143
1144                 state->format_changed = true;
1145
1146                 misc_int &= ~MASK_SYNC_CHG;
1147                 if (handled)
1148                         *handled = true;
1149         }
1150
1151         if (misc_int) {
1152                 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1153                                 __func__, misc_int);
1154         }
1155 }
1156
1157 static void tc358840_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1158                 bool *handled)
1159 {
1160         u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1161         u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1162
1163         i2c_wr8(sd, CBIT_INT, cbit_int);
1164
1165         v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1166
1167         if (cbit_int & MASK_CBIT_FS) {
1168
1169                 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1170                                 __func__);
1171                 tc358840_s_ctrl_audio_sampling_rate(sd);
1172
1173                 cbit_int &= ~MASK_CBIT_FS;
1174                 if (handled)
1175                         *handled = true;
1176         }
1177
1178         if (cbit_int & (MASK_AF_LOCK | MASK_AF_UNLOCK)) {
1179
1180                 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1181                                 __func__);
1182                 tc358840_s_ctrl_audio_present(sd);
1183
1184                 cbit_int &= ~(MASK_AF_LOCK | MASK_AF_UNLOCK);
1185                 if (handled)
1186                         *handled = true;
1187         }
1188
1189         if (cbit_int) {
1190                 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1191                                 __func__, cbit_int);
1192         }
1193 }
1194
1195 static void tc358840_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1196 {
1197         struct tc358840_state *state = to_state(sd);
1198         u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1199         u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1200
1201         /* Bit 7 and bit 6 are set even when they are masked */
1202         i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_OUT_H_CHG);
1203
1204         v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1205
1206         if (clk_int & (MASK_IN_DE_CHG)) {
1207
1208                 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1209                                 __func__);
1210
1211                 /* TODO: Check if also true for tc358840 */
1212                 /* If the source switch to a new resolution with the same pixel
1213                  * frequency as the existing (e.g. 1080p25 -> 720p50), the
1214                  * I_SYNC_CHG interrupt is not always triggered, while the
1215                  * I_IN_DE_CHG interrupt seems to work fine. FMT_CHANGE
1216                  * notifications are only sent when the signal is stable to
1217                  * reduce the number of notifications. */
1218                 if (!no_signal(sd) && !no_sync(sd))
1219                         state->format_changed = true;
1220
1221                 clk_int &= ~MASK_IN_DE_CHG;
1222                 if (handled)
1223                         *handled = true;
1224         }
1225
1226         if (clk_int) {
1227                 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1228                                 __func__, clk_int);
1229         }
1230 }
1231
1232 static void tc358840_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1233 {
1234         struct tc358840_state *state = to_state(sd);
1235         u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1236         u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1237
1238         i2c_wr8(sd, SYS_INT, sys_int);
1239
1240         v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1241
1242         if (sys_int & MASK_DDC) {
1243                 bool tx_5v = tx_5v_power_present(sd);
1244
1245                 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1246                                 __func__, tx_5v ?  "yes" : "no");
1247
1248                 if (tx_5v) {
1249                         tc358840_enable_edid(sd);
1250                 } else {
1251                         tc358840_enable_interrupts(sd, false);
1252                         tc358840_disable_edid(sd);
1253                         memset(&state->timings, 0, sizeof(state->timings));
1254                         tc358840_erase_bksv(sd);
1255                         tc358840_update_controls(sd);
1256                 }
1257
1258                 sys_int &= ~MASK_DDC;
1259                 if (handled)
1260                         *handled = true;
1261         }
1262
1263         if (sys_int & MASK_DVI) {
1264                 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1265                                 __func__);
1266
1267                 /* Reset the HDMI PHY to try to trigger proper lock on the
1268                  * incoming video format. Erase BKSV to prevent that old keys
1269                  * are used when a new source is connected. */
1270                 if (no_sync(sd) || no_signal(sd))
1271                         state->format_changed = true;
1272
1273                 sys_int &= ~MASK_DVI;
1274                 if (handled)
1275                         *handled = true;
1276         }
1277
1278         if (sys_int & MASK_HDMI) {
1279                 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1280                                 __func__);
1281
1282                 /* TODO: Check if reg is required. Reg not found in Rev. 1.5 */
1283 #if 0
1284                 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1285 #endif
1286                 sys_int &= ~MASK_HDMI;
1287                 if (handled)
1288                         *handled = true;
1289         }
1290
1291         if (sys_int) {
1292                 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1293                                 __func__, sys_int);
1294         }
1295 }
1296
1297 /* --------------- CORE OPS --------------- */
1298
1299 static int tc358840_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1300 {
1301         struct tc358840_state *state = to_state(sd);
1302         u16 intstatus;
1303         unsigned retry = 10;
1304
1305         //disable_irq_nosync(state->pdata.interrupt);
1306         intstatus = i2c_rd16(sd, INTSTATUS);
1307
1308         v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04X\n", __func__, intstatus);
1309
1310         /*
1311          * Need to figure out why these msleeps are needed, and which of these
1312          * are needed. Without msleeps the interrupts just stop.
1313          */
1314         usleep_range(500, 1000);
1315         state->format_changed = false;
1316         if (intstatus & MASK_HDMI_INT) {
1317                 u8 hdmi_int0;
1318                 u8 hdmi_int1;
1319 retry:
1320                 retry--;
1321                 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1322                 usleep_range(500, 1000);
1323                 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1324                 usleep_range(500, 1000);
1325
1326                 if (hdmi_int0 & MASK_MISC)
1327                         tc358840_hdmi_misc_int_handler(sd, handled);
1328                 if (hdmi_int1 & MASK_ACBIT)
1329                         tc358840_hdmi_cbit_int_handler(sd, handled);
1330                 if (hdmi_int1 & MASK_CLK)
1331                         tc358840_hdmi_clk_int_handler(sd, handled);
1332                 if (hdmi_int1 & MASK_SYS)
1333                         tc358840_hdmi_sys_int_handler(sd, handled);
1334                 if (hdmi_int1 & MASK_AUD)
1335                         tc358840_hdmi_audio_int_handler(sd, handled);
1336
1337                 usleep_range(500, 1000);
1338                 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1339                 intstatus &= ~MASK_HDMI_INT;
1340                 usleep_range(500, 1000);
1341
1342                 /* Display unhandled HDMI interrupts */
1343                 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1344                 if (hdmi_int0) {
1345                         v4l2_dbg(1, debug, sd,
1346                                 "%s: Unhandled HDMI_INT0 interrupts: 0x%02X\n",
1347                                 __func__, hdmi_int0);
1348                         if (retry)
1349                                 goto retry;
1350                 }
1351                 usleep_range(500, 1000);
1352                 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1353                 if (hdmi_int1) {
1354                         v4l2_dbg(1, debug, sd,
1355                                 "%s: Unhandled HDMI_INT1 interrupts: 0x%02X\n",
1356                                 __func__, hdmi_int1);
1357                         if (retry)
1358                                 goto retry;
1359                 }
1360         }
1361
1362         if (handled && state->format_changed) {
1363                 tc358840_format_change(sd);
1364                 if (no_sync(sd) || no_signal(sd)) {
1365                         tc358840_reset_phy(sd);
1366                         tc358840_erase_bksv(sd);
1367                 }
1368         }
1369
1370         if (intstatus & MASK_CSITX0_INT) {
1371                 v4l2_dbg(3, debug, sd, "%s: MASK_CSITX0_INT\n", __func__);
1372
1373                 i2c_wr16(sd, INTSTATUS, MASK_CSITX0_INT);
1374                 intstatus &= ~MASK_CSITX0_INT;
1375         }
1376
1377         if (intstatus & MASK_CSITX1_INT) {
1378                 v4l2_dbg(3, debug, sd, "%s: MASK_CSITX1_INT\n", __func__);
1379
1380                 i2c_wr16(sd, INTSTATUS, MASK_CSITX1_INT);
1381                 intstatus &= ~MASK_CSITX1_INT;
1382         }
1383
1384         if (intstatus) {
1385                 v4l2_dbg(1, debug, sd,
1386                         "%s: Unhandled IntStatus interrupts: 0x%04x\n",
1387                         __func__, intstatus);
1388         }
1389         //enable_irq(state->pdata.interrupt);
1390         return 0;
1391 }
1392
1393 static void tc358840_process_isr(struct work_struct *work)
1394 {
1395         struct tc358840_state *state = container_of(work,
1396                 struct tc358840_state, process_isr);
1397         struct v4l2_subdev *sd = &state->sd;
1398         bool handled;
1399
1400         v4l2_dbg(2, debug, sd, "%s:\n", __func__);
1401
1402         mutex_lock(&state->isr_lock);
1403         tc358840_isr(sd, 0, &handled);
1404         mutex_unlock(&state->isr_lock);
1405 }
1406
1407 static irqreturn_t tc358840_irq_handler(int irq, void *dev_id)
1408 {
1409         struct v4l2_subdev *sd = dev_id;
1410         struct tc358840_state *state = to_state(sd);
1411
1412         queue_work(state->work_queues, &state->process_isr);
1413
1414         return IRQ_HANDLED;
1415 }
1416
1417 /* --------------- PAD OPS --------------- */
1418
1419 static int tc358840_get_fmt(struct v4l2_subdev *sd,
1420                 struct v4l2_subdev_fh *fh,
1421                 struct v4l2_subdev_format *format)
1422 {
1423         struct tc358840_state *state = to_state(sd);
1424         u8 vout_csc = i2c_rd8(sd, VOUT_CSC);
1425         struct v4l2_mbus_framefmt *fmt;
1426
1427         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1428
1429         if (format->pad != 0)
1430                 return -EINVAL;
1431
1432         format->format.code = state->mbus_fmt_code;
1433         format->format.width = state->timings.bt.width;
1434         format->format.height = state->timings.bt.height;
1435         format->format.field = V4L2_FIELD_NONE;
1436
1437         switch (vout_csc & MASK_COLOR) {
1438         case MASK_COLOR_RGB_FULL:
1439         case MASK_COLOR_RGB_LIMITED:
1440                 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1441                 break;
1442         case MASK_COLOR_601_YCBCR_FULL:
1443         case MASK_COLOR_601_YCBCR_LIMITED:
1444                 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1445                 break;
1446         case MASK_COLOR_709_YCBCR_FULL:
1447         case MASK_COLOR_709_YCBCR_LIMITED:
1448                 format->format.colorspace = V4L2_COLORSPACE_REC709;
1449                 break;
1450         default:
1451                 format->format.colorspace = 0;
1452                 break;
1453         }
1454
1455         fmt = &format->format;
1456         v4l2_dbg(3, debug, sd,
1457                 "%s(): width=%d, height=%d, code=0x%08X, field=%d\n",
1458                 __func__, fmt->width, fmt->height, fmt->code, fmt->field);
1459
1460         return 0;
1461 }
1462
1463 static int tc358840_set_fmt(struct v4l2_subdev *sd,
1464                 struct v4l2_subdev_fh *fh,
1465                 struct v4l2_subdev_format *format)
1466 {
1467         struct tc358840_state *state = to_state(sd);
1468         u32 code = format->format.code; /* is overwritten by get_fmt */
1469         int ret = tc358840_get_fmt(sd, fh, format);
1470
1471         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1472
1473         format->format.code = code;
1474
1475         if (ret)
1476                 return ret;
1477
1478         switch (code) {
1479         case V4L2_MBUS_FMT_RGB888_1X24:
1480         case V4L2_MBUS_FMT_UYVY8_1X16:
1481                 break;
1482         default:
1483                 return -EINVAL;
1484         }
1485
1486         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1487                 return 0;
1488
1489         v4l2_dbg(3, debug, sd, "%s(): format->which=%d\n",
1490                 __func__, format->which);
1491
1492         state->mbus_fmt_code = format->format.code;
1493         enable_stream(sd, false);
1494         tc358840_set_csi(sd);
1495         tc358840_set_csi_mbus_config(sd);
1496
1497         return 0;
1498 }
1499
1500 static int tc358840_g_edid(struct v4l2_subdev *sd,
1501                 struct v4l2_subdev_edid *edid)
1502 {
1503         struct tc358840_state *state = to_state(sd);
1504
1505         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1506
1507         memset(edid->reserved, 0, sizeof(edid->reserved));
1508
1509         if (edid->pad != 0)
1510                 return -EINVAL;
1511
1512         if (edid->start_block == 0 && edid->blocks == 0) {
1513                 edid->blocks = state->edid_blocks_written;
1514                 return 0;
1515         }
1516
1517         if (state->edid_blocks_written == 0)
1518                 return -ENODATA;
1519
1520         if (edid->start_block >= state->edid_blocks_written ||
1521                         edid->blocks == 0)
1522                 return -EINVAL;
1523
1524         if (edid->start_block + edid->blocks > state->edid_blocks_written)
1525                 edid->blocks = state->edid_blocks_written - edid->start_block;
1526
1527         i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1528                    edid->blocks * EDID_BLOCK_SIZE);
1529
1530         return 0;
1531 }
1532
1533 static int tc358840_s_edid(struct v4l2_subdev *sd,
1534                                 struct v4l2_subdev_edid *edid)
1535 {
1536         struct tc358840_state *state = to_state(sd);
1537         u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1538         int i;
1539
1540         v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1541                  __func__, edid->pad, edid->start_block, edid->blocks);
1542
1543         memset(edid->reserved, 0, sizeof(edid->reserved));
1544
1545         if (edid->pad != 0)
1546                 return -EINVAL;
1547
1548         if (edid->start_block != 0)
1549                 return -EINVAL;
1550
1551         if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1552                 edid->blocks = EDID_NUM_BLOCKS_MAX;
1553                 return -E2BIG;
1554         }
1555
1556         tc358840_disable_edid(sd);
1557
1558         i2c_wr8(sd, EDID_LEN1, edid_len & 0xFF);
1559         i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1560
1561         if (edid->blocks == 0) {
1562                 state->edid_blocks_written = 0;
1563                 return 0;
1564         }
1565
1566         for (i = 0; i < 256; i++) {
1567                 unsigned int val;
1568                 val = edid->edid[i];
1569                 i2c_wr8(sd, EDID_RAM + i, val);
1570         }
1571
1572         state->edid_blocks_written = edid->blocks;
1573
1574         if (tx_5v_power_present(sd))
1575                 tc358840_enable_edid(sd);
1576
1577         return 0;
1578 }
1579
1580 static int tc358840_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1581                                     struct v4l2_event_subscription *sub)
1582 {
1583         switch (sub->type) {
1584         case V4L2_EVENT_SOURCE_CHANGE:
1585                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1586         case V4L2_EVENT_CTRL:
1587                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1588         default:
1589                 return -EINVAL;
1590         }
1591 }
1592
1593 /* --------------- VIDEO OPS --------------- */
1594
1595 static int tc358840_g_input_status(struct v4l2_subdev *sd, u32 *status)
1596 {
1597         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1598
1599         *status = 0;
1600         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1601         *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1602
1603         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1604
1605         return 0;
1606 }
1607
1608 static int tc358840_s_dv_timings(struct v4l2_subdev *sd,
1609                                  struct v4l2_dv_timings *timings)
1610 {
1611         struct tc358840_state *state = to_state(sd);
1612
1613         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1614
1615         if (!timings)
1616                 return -EINVAL;
1617
1618         if (debug)
1619                 v4l2_print_dv_timings(sd->name, "tc358840_s_dv_timings: ",
1620                                 timings, false);
1621
1622         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1623                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1624                 return 0;
1625         }
1626
1627         if (!v4l2_valid_dv_timings(timings, &tc358840_timings_cap, NULL, NULL)) {
1628                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1629                 return -ERANGE;
1630         }
1631
1632         state->timings = *timings;
1633
1634         enable_stream(sd, false);
1635         tc358840_set_csi(sd);
1636         tc358840_set_splitter(sd);
1637
1638         return 0;
1639 }
1640
1641 static int tc358840_g_dv_timings(struct v4l2_subdev *sd,
1642                                  struct v4l2_dv_timings *timings)
1643 {
1644         struct tc358840_state *state = to_state(sd);
1645
1646         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1647
1648         *timings = state->timings;
1649
1650         return 0;
1651 }
1652
1653 static int tc358840_enum_dv_timings(struct v4l2_subdev *sd,
1654                                     struct v4l2_enum_dv_timings *timings)
1655 {
1656         v4l2_dbg(3, debug, sd, "%s(): DUMMY\n", __func__);
1657
1658         if (timings->pad != 0)
1659                 return -EINVAL;
1660
1661         return v4l2_enum_dv_timings_cap(timings,
1662                         &tc358840_timings_cap, NULL, NULL);
1663 }
1664
1665 static int tc358840_query_dv_timings(struct v4l2_subdev *sd,
1666                                      struct v4l2_dv_timings *timings)
1667 {
1668         int ret;
1669
1670         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1671
1672         ret = tc358840_get_detected_timings(sd, timings);
1673         if (ret)
1674                 return ret;
1675
1676         if (debug)
1677                 v4l2_print_dv_timings(sd->name, "tc358840_query_dv_timings: ",
1678                         timings, false);
1679         if (!v4l2_valid_dv_timings(timings, &tc358840_timings_cap, NULL, NULL)) {
1680                 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1681                 return -ERANGE;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int tc358840_dv_timings_cap(struct v4l2_subdev *sd,
1688                                    struct v4l2_dv_timings_cap *cap)
1689 {
1690         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1691
1692         if (cap->pad != 0)
1693                 return -EINVAL;
1694
1695         *cap = tc358840_timings_cap;
1696
1697         return 0;
1698 }
1699
1700 static int tc358840_g_mbus_config(struct v4l2_subdev *sd,
1701                                   struct v4l2_mbus_config *cfg)
1702 {
1703         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1704
1705         cfg->type = V4L2_MBUS_CSI2;
1706
1707         /* Support for non-continuous CSI-2 clock is missing in the driver */
1708         cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | V4L2_MBUS_CSI2_CHANNEL_0;
1709
1710         switch (tc358840_num_csi_lanes_in_use(sd)) {
1711         case 1:
1712                 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1713                 break;
1714         case 2:
1715                 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1716                 break;
1717         case 3:
1718                 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1719                 break;
1720         case 4:
1721                 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1722                 break;
1723         default:
1724                 return -EINVAL;
1725         }
1726
1727         v4l2_dbg(2, debug, sd, "%s: Lanes: 0x%02X\n",
1728                 __func__, cfg->flags & 0x0F);
1729
1730         return 0;
1731 }
1732
1733 #ifdef CONFIG_VIDEO_ADV_DEBUG
1734 static int tc358840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1735 {
1736         switch (reg->size) {
1737         case 1:
1738                 reg->val = i2c_rd8(sd, reg->reg);
1739                 break;
1740         case 2:
1741                 reg->val = i2c_rd16(sd, reg->reg);
1742                 break;
1743         case 4:
1744         default:
1745                 reg->val = i2c_rd32(sd, reg->reg);
1746                 break;
1747         }
1748         return 0;
1749 }
1750
1751 static int tc358840_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1752 {
1753         switch (reg->size) {
1754         case 1:
1755                 i2c_wr8(sd, reg->reg, reg->val);
1756                 break;
1757         case 2:
1758                 i2c_wr16(sd, reg->reg, reg->val);
1759                 break;
1760         case 4:
1761         default:
1762                 i2c_wr32(sd, reg->reg, reg->val);
1763                 break;
1764         }
1765         return 0;
1766 }
1767 #endif
1768
1769 static int tc358840_log_status(struct v4l2_subdev *sd)
1770 {
1771         struct tc358840_state *state = to_state(sd);
1772         struct v4l2_dv_timings timings;
1773         u8 hdmi_sys_status =  i2c_rd8(sd, SYS_STATUS);
1774         u16 sysctl = i2c_rd16(sd, SYSCTL);
1775         u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1776         const int deep_color_mode[4] = { 8, 10, 12, 16 };
1777         static const char * const input_color_space[] = {
1778                 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1779                 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1780                 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1781
1782         v4l2_ctrl_subdev_log_status(sd);
1783         v4l2_info(sd, "-----Chip status-----\n");
1784         v4l2_info(sd, "Chip ID: 0x%02x\n",
1785                         (i2c_rd16(sd, CHIPID_ADDR) & MASK_CHIPID) >> 8);
1786         v4l2_info(sd, "Chip revision: 0x%02x\n",
1787                         i2c_rd16(sd, CHIPID_ADDR) & MASK_REVID);
1788         v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1789                         !!(sysctl & MASK_IRRST),
1790                         !!(sysctl & MASK_CECRST),
1791                         !!(sysctl & MASK_CTXRST),
1792                         !!(sysctl & MASK_HDMIRST));
1793         v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1794         v4l2_info(sd, "Cable detected (+5V power): %s\n",
1795                         hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1796         v4l2_info(sd, "DDC lines enabled: %s\n",
1797                         (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_ALL) ?
1798                         "yes" : "no");
1799         v4l2_info(sd, "Hotplug enabled: %s\n",
1800                         (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1801                         "yes" : "no");
1802         v4l2_info(sd, "CEC enabled: %s\n",
1803                         (i2c_rd16(sd, CECEN) & MASK_CECEN) ?  "yes" : "no");
1804         v4l2_info(sd, "-----Signal status-----\n");
1805         v4l2_info(sd, "TMDS signal detected: %s\n",
1806                         hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1807         v4l2_info(sd, "Stable sync signal: %s\n",
1808                         hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1809         v4l2_info(sd, "PHY PLL locked: %s\n",
1810                         hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1811         v4l2_info(sd, "PHY DE detected: %s\n",
1812                         hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1813
1814         if (tc358840_get_detected_timings(sd, &timings)) {
1815                 v4l2_info(sd, "No video detected\n");
1816         } else {
1817                 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1818                                 true);
1819         }
1820         v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1821                         true);
1822
1823         v4l2_info(sd, "-----CSI-TX status-----\n");
1824         v4l2_info(sd, "Lanes needed: %d\n",
1825                         tc358840_num_csi_lanes_needed(sd));
1826         v4l2_info(sd, "Lanes in use: %d\n",
1827                         tc358840_num_csi_lanes_in_use(sd));
1828         v4l2_info(sd, "Splitter %sabled\n",
1829                   (i2c_rd16(sd, SPLITTX0_CTRL) & MASK_SPBP) ? "dis" : "en");
1830         /*
1831         v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1832                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1833                         "yes" : "no");
1834         v4l2_info(sd, "Transmit mode: %s\n",
1835                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1836                         "yes" : "no");
1837         v4l2_info(sd, "Receive mode: %s\n",
1838                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1839                         "yes" : "no");
1840         v4l2_info(sd, "Stopped: %s\n",
1841                         (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1842                         "yes" : "no");*/
1843         v4l2_info(sd, "Color space: %s\n",
1844                         state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
1845                         "YCbCr 422 16-bit" :
1846                         state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1847                         "RGB 888 24-bit" : "Unsupported");
1848
1849         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1850         v4l2_info(sd, "HDCP encrypted content: %s\n",
1851                         hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1852         v4l2_info(sd, "Input color space: %s %s range\n",
1853                         input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1854                         (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1855         if (!is_hdmi(sd))
1856                 return 0;
1857         v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1858                         "off");
1859         v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1860                         deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1861                                 MASK_S_DEEPCOLOR) >> 2]);
1862         print_avi_infoframe(sd);
1863
1864         return 0;
1865 }
1866
1867 static int tc358840_s_stream(struct v4l2_subdev *sd, int enable)
1868 {
1869         v4l2_dbg(3, debug, sd, "%s():\n", __func__);
1870
1871         return enable_stream(sd, enable);
1872 }
1873
1874 static int tc358840_s_mbus_fmt(struct v4l2_subdev *sd,
1875                                struct v4l2_mbus_framefmt *fmt)
1876 {
1877         struct v4l2_subdev_format format;
1878
1879         v4l2_dbg(2, debug, sd, "%s()\n", __func__);
1880
1881         memcpy(&format.format, fmt, sizeof(struct v4l2_mbus_framefmt));
1882         format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1883         format.pad = 0;
1884
1885         return tc358840_set_fmt(sd, NULL, &format);
1886 }
1887
1888 static int tc358840_g_mbus_fmt(struct v4l2_subdev *sd,
1889                                struct v4l2_mbus_framefmt *fmt)
1890 {
1891         struct v4l2_subdev_format format;
1892         int ret;
1893
1894         v4l2_dbg(2, debug, sd, "%s()\n", __func__);
1895
1896         format.pad = 0;
1897         ret = tc358840_get_fmt(sd, NULL, &format);
1898         if (ret)
1899                 return ret;
1900
1901         *fmt = format.format;
1902
1903         return 0;
1904 }
1905
1906 static int tc358840_try_mbus_fmt(struct v4l2_subdev *sd,
1907                                  struct v4l2_mbus_framefmt *fmt)
1908 {
1909         struct v4l2_subdev_format format;
1910
1911         v4l2_dbg(2, debug, sd,
1912                 "%s(): width=%d, height=%d, code=0x%04X, field=%d\n",
1913                 __func__, fmt->width, fmt->height, fmt->code, fmt->field);
1914
1915         memcpy(&format.format, fmt, sizeof(struct v4l2_mbus_framefmt));
1916         format.which = V4L2_SUBDEV_FORMAT_TRY;
1917         format.pad = 0;
1918
1919         return tc358840_set_fmt(sd, NULL, &format);
1920 }
1921
1922 static int tc358840_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1923                                 struct v4l2_subdev_mbus_code_enum *code)
1924 {
1925         v4l2_dbg(2, debug, sd, "%s()\n", __func__);
1926
1927         if (code->index >= 2)
1928                 return -EINVAL;
1929
1930         switch (code->index) {
1931         case 0:
1932                 code->code = V4L2_MBUS_FMT_UYVY8_1X16;
1933                 break;
1934         case 1:
1935                 code->code = V4L2_MBUS_FMT_RGB888_1X24;
1936                 break;
1937         }
1938         return 0;
1939 }
1940
1941 static int tc358840_enum_framesizes(struct v4l2_subdev *sd,
1942                                     struct v4l2_frmsizeenum *fsizes)
1943 {
1944         const struct camera_common_frmfmt *frmfmt = tc358840_frmfmt;
1945         int num_frmfmt = ARRAY_SIZE(tc358840_frmfmt);
1946
1947         v4l2_dbg(2, debug, sd, "%s()\n", __func__);
1948
1949         if (fsizes->pixel_format != V4L2_PIX_FMT_UYVY &&
1950             fsizes->pixel_format != V4L2_PIX_FMT_ABGR32)
1951                 return -EINVAL;
1952
1953         if (fsizes->index >= num_frmfmt)
1954                 return -EINVAL;
1955
1956         fsizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1957         fsizes->discrete = frmfmt[fsizes->index].size;
1958
1959         return 0;
1960 }
1961
1962 static int tc358840_enum_frameintervals(struct v4l2_subdev *sd,
1963                                       struct v4l2_frmivalenum *fintervals)
1964 {
1965         const struct camera_common_frmfmt *frmfmt = tc358840_frmfmt;
1966         int num_frmfmt = ARRAY_SIZE(tc358840_frmfmt);
1967         int i;
1968
1969         v4l2_dbg(2, debug, sd, "%s()\n", __func__);
1970
1971         if (fintervals->pixel_format != V4L2_PIX_FMT_UYVY &&
1972             fintervals->pixel_format != V4L2_PIX_FMT_ABGR32)
1973                 return -EINVAL;
1974
1975         for (i = 0; i < num_frmfmt; i++) {
1976                 if (frmfmt[i].size.width == fintervals->width &&
1977                     frmfmt[i].size.height == fintervals->height)
1978                         break;
1979         }
1980         if (i >= num_frmfmt)
1981                 return -EINVAL;
1982
1983         if (fintervals->index >= frmfmt[i].num_framerates)
1984                 return -EINVAL;
1985
1986         fintervals->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1987         fintervals->discrete.numerator = 1;
1988         fintervals->discrete.denominator =
1989                 frmfmt[i].framerates[fintervals->index];
1990
1991         return 0;
1992 }
1993
1994 static int tc358840_s_power(struct v4l2_subdev *sd, int on)
1995 {
1996         return 0;
1997 }
1998
1999 static struct v4l2_subdev_video_ops tc358840_subdev_video_ops = {
2000         .g_input_status = tc358840_g_input_status,
2001         .s_dv_timings = tc358840_s_dv_timings,
2002         .g_dv_timings = tc358840_g_dv_timings,
2003         .query_dv_timings = tc358840_query_dv_timings,
2004         .g_mbus_config = tc358840_g_mbus_config,
2005         .s_stream = tc358840_s_stream,
2006
2007         .s_mbus_fmt = tc358840_s_mbus_fmt,
2008         .g_mbus_fmt = tc358840_g_mbus_fmt,
2009         .try_mbus_fmt = tc358840_try_mbus_fmt,
2010
2011         .enum_framesizes = tc358840_enum_framesizes,
2012         .enum_frameintervals = tc358840_enum_frameintervals,
2013 };
2014
2015 static struct v4l2_subdev_core_ops tc358840_subdev_core_ops = {
2016         .s_power = tc358840_s_power,
2017         .log_status = tc358840_log_status,
2018         .interrupt_service_routine = tc358840_isr,
2019         .subscribe_event = tc358840_subscribe_event,
2020         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2021 #ifdef CONFIG_VIDEO_ADV_DEBUG
2022         .g_register = tc358840_g_register,
2023         .s_register = tc358840_s_register,
2024 #endif
2025 };
2026
2027 static const struct v4l2_subdev_pad_ops tc358840_pad_ops = {
2028         .set_fmt = tc358840_set_fmt,
2029         .get_fmt = tc358840_get_fmt,
2030         .enum_mbus_code = tc358840_enum_mbus_code,
2031         .get_edid = tc358840_g_edid,
2032         .set_edid = tc358840_s_edid,
2033         .dv_timings_cap = tc358840_dv_timings_cap,
2034         .enum_dv_timings = tc358840_enum_dv_timings,
2035 };
2036
2037 static struct v4l2_subdev_ops tc358840_ops = {
2038         .core = &tc358840_subdev_core_ops,
2039         .video = &tc358840_subdev_video_ops,
2040         .pad = &tc358840_pad_ops,
2041 };
2042
2043
2044 /* --------------- CUSTOM CTRLS --------------- */
2045
2046 static const struct v4l2_ctrl_config tc358840_ctrl_audio_sampling_rate = {
2047         .id = TC358840_CID_AUDIO_SAMPLING_RATE,
2048         .name = "Audio sampling rate",
2049         .type = V4L2_CTRL_TYPE_INTEGER,
2050         .min = 0,
2051         .max = 768000,
2052         .step = 1,
2053         .def = 0,
2054         .flags = V4L2_CTRL_FLAG_READ_ONLY,
2055 };
2056
2057 static const struct v4l2_ctrl_config tc358840_ctrl_audio_present = {
2058         .id = TC358840_CID_AUDIO_PRESENT,
2059         .name = "Audio present",
2060         .type = V4L2_CTRL_TYPE_BOOLEAN,
2061         .min = 0,
2062         .max = 1,
2063         .step = 1,
2064         .def = 0,
2065         .flags = V4L2_CTRL_FLAG_READ_ONLY,
2066 };
2067
2068 static const struct v4l2_ctrl_config tc358840_ctrl_splitter_width = {
2069         .id = TC358840_CID_SPLITTER_WIDTH,
2070         .name = "Splitter Width",
2071         .type = V4L2_CTRL_TYPE_INTEGER,
2072         .min = 320,
2073         .max = 1920,
2074         .step = 16,
2075         .def = 1920,
2076         .flags = V4L2_CTRL_FLAG_READ_ONLY,
2077 };
2078
2079 /* --------------- PROBE / REMOVE --------------- */
2080
2081 #ifdef CONFIG_OF
2082
2083 static bool tc358840_parse_dt(struct tc358840_platform_data *pdata,
2084                 struct i2c_client *client)
2085 {
2086         struct device_node *node = client->dev.of_node;
2087         const u32 *property;
2088
2089         v4l_dbg(1, debug, client, "Device Tree Parameters:\n");
2090
2091         pdata->reset_gpio = of_get_named_gpio(node, "reset-gpios", 0);
2092         if (pdata->reset_gpio == 0)
2093                 return false;
2094         v4l_dbg(1, debug, client, "reset_gpio = %d\n", pdata->reset_gpio);
2095
2096 //      if (v4l2_of_parse_endpoint(node, &pdata->endpoint))
2097 //              return false;
2098
2099         property = of_get_property(node, "refclk_hz", NULL);
2100         if (property == NULL)
2101                 return false;
2102         pdata->refclk_hz = be32_to_cpup(property);
2103         v4l_dbg(1, debug, client, "refclk_hz = %d\n", be32_to_cpup(property));
2104
2105         property = of_get_property(node, "ddc5v_delay", NULL);
2106         if (property == NULL)
2107                 return false;
2108         pdata->ddc5v_delay = be32_to_cpup(property);
2109         if (pdata->ddc5v_delay > DDC5V_DELAY_MAX)
2110                 pdata->ddc5v_delay = DDC5V_DELAY_MAX;
2111         v4l_dbg(1, debug, client, "ddc5v_delay = %d ms\n",
2112                 50 * pdata->ddc5v_delay);
2113
2114         property = of_get_property(node, "enable_hdcp", NULL);
2115         if (property == NULL)
2116                 return false;
2117         pdata->enable_hdcp = be32_to_cpup(property);
2118         v4l_dbg(1, debug, client, "enable_hdcp = %d\n", be32_to_cpup(property));
2119
2120         property = of_get_property(node, "csi_port", NULL);
2121         if (property == NULL)
2122                 return false;
2123         pdata->csi_port = be32_to_cpup(property);
2124         v4l_dbg(1, debug, client, "csi_port = %d\n", be32_to_cpup(property));
2125
2126         property = of_get_property(node, "lineinitcnt", NULL);
2127         if (property == NULL)
2128                 return false;
2129         pdata->lineinitcnt = be32_to_cpup(property);
2130         v4l_dbg(1, debug, client, "lineinitcnt = %d\n", be32_to_cpup(property));
2131
2132         property = of_get_property(node, "lptxtimecnt", NULL);
2133         if (property == NULL)
2134                 return false;
2135         pdata->lptxtimecnt = be32_to_cpup(property);
2136         v4l_dbg(1, debug, client, "lptxtimecnt = %d\n", be32_to_cpup(property));
2137
2138         property = of_get_property(node, "tclk_headercnt", NULL);
2139         if (property == NULL)
2140                 return false;
2141         pdata->tclk_headercnt = be32_to_cpup(property);
2142         v4l_dbg(1, debug, client, "tclk_headercnt = %d\n",
2143                 be32_to_cpup(property));
2144
2145         property = of_get_property(node, "tclk_trailcnt", NULL);
2146         if (property == NULL)
2147                 return false;
2148         pdata->tclk_trailcnt = be32_to_cpup(property);
2149         v4l_dbg(1, debug, client, "tclk_trailcnt = %d\n",
2150                 be32_to_cpup(property));
2151
2152         property = of_get_property(node, "ths_headercnt", NULL);
2153         if (property == NULL)
2154                 return false;
2155         pdata->ths_headercnt = be32_to_cpup(property);
2156         v4l_dbg(1, debug, client, "ths_headercnt = %d\n",
2157                 be32_to_cpup(property));
2158
2159         property = of_get_property(node, "twakeup", NULL);
2160         if (property == NULL)
2161                 return false;
2162         pdata->twakeup = be32_to_cpup(property);
2163         v4l_dbg(1, debug, client, "twakeup = %d\n", be32_to_cpup(property));
2164
2165         property = of_get_property(node, "tclk_postcnt", NULL);
2166         if (property == NULL)
2167                 return false;
2168         pdata->tclk_postcnt = be32_to_cpup(property);
2169         v4l_dbg(1, debug, client, "tclk_postcnt = %d\n",
2170                 be32_to_cpup(property));
2171
2172         property = of_get_property(node, "ths_trailcnt", NULL);
2173         if (property == NULL)
2174                 return false;
2175         pdata->ths_trailcnt = be32_to_cpup(property);
2176         v4l_dbg(1, debug, client, "ths_trailcnt = %d\n",
2177                 be32_to_cpup(property));
2178
2179         property = of_get_property(node, "hstxvregcnt", NULL);
2180         if (property == NULL)
2181                 return false;
2182         pdata->hstxvregcnt = be32_to_cpup(property);
2183         v4l_dbg(1, debug, client, "hstxvregcnt = %d\n", be32_to_cpup(property));
2184
2185         property = of_get_property(node, "pll_prd", NULL);
2186         if (property == NULL)
2187                 return false;
2188         pdata->pll_prd = be32_to_cpup(property);
2189         v4l_dbg(1, debug, client, "pll_prd = %d\n", be32_to_cpup(property));
2190
2191         property = of_get_property(node, "pll_fbd", NULL);
2192         if (property == NULL)
2193                 return false;
2194         pdata->pll_fbd = be32_to_cpup(property);
2195         v4l_dbg(1, debug, client, "pll_fbd = %d\n", be32_to_cpup(property));
2196
2197         return true;
2198 }
2199 #endif
2200
2201 static int tc358840_pwr_init(struct tc358840_platform_data *pdata,
2202                 struct i2c_client *client)
2203 {
2204         struct device_node *node = client->dev.of_node;
2205         int cam2_rst;
2206         int err;
2207         struct regulator *dvdd;
2208         struct regulator *iovdd;
2209
2210         err = camera_common_regulator_get(client, &iovdd, "vif");
2211         if (err < 0) {
2212                 dev_err(&client->dev, "cannot get regulator vif %d\n", err);
2213                 return -EINVAL;
2214         }
2215
2216         err = camera_common_regulator_get(client, &dvdd, "vdig");
2217         if (err < 0) {
2218                 dev_err(&client->dev, "cannot get regulator vdig %d\n", err);
2219                 return -EINVAL;
2220         }
2221
2222         /*  cam2 rst */
2223         cam2_rst = of_get_named_gpio(node, "cam2_rst", 0);
2224         if (cam2_rst == 0)
2225                 return false;
2226         err = gpio_request(cam2_rst, "cam2-rst");
2227         if (err < 0)
2228                 dev_err(&client->dev,
2229                                 "cam2 rst gpio request failed %d\n", err);
2230
2231         gpio_direction_output(cam2_rst, 1);
2232
2233         if (dvdd) {
2234                 err = regulator_enable(dvdd);
2235                 if (err < 0) {
2236                         dev_err(&client->dev, "cannot enable regulator vif %d\n", err);
2237                         return -EINVAL;
2238                 }
2239         }
2240         if (iovdd) {
2241                 err = regulator_enable(iovdd);
2242                 if (err < 0) {
2243                         dev_err(&client->dev, "cannot enable regulator vdig %d\n", err);
2244                         return -EINVAL;
2245                 }
2246         }
2247         gpio_direction_output(cam2_rst, 1);
2248
2249         return true;
2250 }
2251
2252 static int tc358840_verify_chipid(struct v4l2_subdev *sd)
2253 {
2254         u16 cid = 0;
2255
2256         cid = i2c_rd16(sd, CHIPID_ADDR);
2257         if (cid != TC358840_CHIPID) {
2258                 v4l2_err(sd, "Invalid chip ID 0x%04X\n", cid);
2259                 return -ENODEV;
2260         }
2261
2262         v4l2_dbg(1, debug, sd, "TC358840 ChipID 0x%02x, Revision 0x%02x\n",
2263                 (cid & MASK_CHIPID) >> 8, cid & MASK_REVID);
2264
2265         return 0;
2266 }
2267
2268 static int tc358840_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2269 {
2270         struct i2c_client *client = v4l2_get_subdevdata(sd);
2271
2272         dev_dbg(&client->dev, "%s:\n", __func__);
2273         return 0;
2274 }
2275
2276 static const struct v4l2_subdev_internal_ops tc358840_subdev_internal_ops = {
2277         .open = tc358840_open,
2278 };
2279
2280 static const struct media_entity_operations tc358840_media_ops = {
2281 #ifdef CONFIG_MEDIA_CONTROLLER
2282         .link_validate = v4l2_subdev_link_validate,
2283 #endif
2284 };
2285
2286 static int tc358840_probe(struct i2c_client *client, const struct i2c_device_id *id)
2287 {
2288         struct v4l2_subdev_edid sd_edid = {
2289                 .blocks = 2,
2290                 .edid = edid,
2291         };
2292         struct tc358840_state *state;
2293         struct v4l2_subdev *sd;
2294         int err;
2295
2296         state = devm_kzalloc(&client->dev, sizeof(struct tc358840_state), GFP_KERNEL);
2297         if (!state)
2298                 return -ENOMEM;
2299
2300         if (client->dev.of_node) {
2301                 if (!tc358840_parse_dt(&state->pdata, client)) {
2302                         v4l_err(client, "Couldn't parse device tree\n");
2303                         return -ENODEV;
2304                 }
2305                 if (!tc358840_pwr_init(&state->pdata, client)) {
2306                         v4l_err(client, "Couldn't power init\n");
2307                         return -ENODEV;
2308                 }
2309         } else {
2310                 if (!client->dev.platform_data) {
2311                         v4l_err(client, "No platform data!\n");
2312                         return -ENODEV;
2313                 }
2314                 state->pdata = *(struct tc358840_platform_data *)client->dev.platform_data;
2315         }
2316
2317         state->i2c_client = client;
2318         sd = &state->sd;
2319
2320         i2c_set_clientdata(client, state);
2321
2322         v4l2_i2c_subdev_init(sd, client, &tc358840_ops);
2323
2324         /* Release System Reset (pin K8) */
2325         v4l2_info(sd, "Releasing System Reset (gpio 0x%04X)\n",
2326                 state->pdata.reset_gpio);
2327         if (!gpio_is_valid(state->pdata.reset_gpio)) {
2328                 v4l_err(client, "Reset GPIO is invalid!\n");
2329                 return state->pdata.reset_gpio;
2330         }
2331         err = devm_gpio_request_one(&client->dev, state->pdata.reset_gpio,
2332                                         GPIOF_OUT_INIT_HIGH, "tc358840-reset");
2333         if (err) {
2334                 dev_err(&client->dev,
2335                         "Failed to request Reset GPIO 0x%04X: %d\n",
2336                         state->pdata.reset_gpio, err);
2337                 return err;
2338         }
2339
2340         /*  */
2341         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2342                 return -EIO;
2343         v4l_info(client, "Chip found @ 7h%02X (%s)\n",
2344                 client->addr, client->adapter->name);
2345
2346
2347         /* Verify chip ID */
2348         err = tc358840_verify_chipid(sd);
2349         if (err)
2350                 return err;
2351
2352         /* Control Handlers */
2353         v4l2_ctrl_handler_init(&state->hdl, 4);
2354
2355         /* Custom controls */
2356         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
2357                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2358
2359         state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2360                         &tc358840_ctrl_audio_sampling_rate, NULL);
2361
2362         state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2363                         &tc358840_ctrl_audio_present, NULL);
2364
2365         state->splitter_width_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2366                         &tc358840_ctrl_splitter_width, NULL);
2367
2368         if (state->hdl.error) {
2369                 err = state->hdl.error;
2370                 goto err_hdl;
2371         }
2372
2373         sd->ctrl_handler = &state->hdl;
2374
2375         if (tc358840_update_controls(sd)) {
2376                 err = -ENODEV;
2377                 goto err_hdl;
2378         }
2379
2380         /* Work Queues */
2381         state->work_queues = create_singlethread_workqueue(client->name);
2382         if (!state->work_queues) {
2383                 v4l2_err(sd, "Could not create work queue!\n");
2384                 err = -ENOMEM;
2385                 goto err_hdl;
2386         }
2387         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2388                         tc358840_delayed_work_enable_hotplug);
2389         INIT_WORK(&state->process_isr, tc358840_process_isr);
2390         mutex_init(&state->isr_lock);
2391
2392         /* Initial Setup */
2393         state->mbus_fmt_code = V4L2_MBUS_FMT_UYVY8_1X16;
2394         tc358840_initial_setup(sd);
2395
2396         tc358840_set_csi_mbus_config(sd);
2397
2398         /* Get interrupt */
2399         if (client->irq) {
2400                 err = devm_request_threaded_irq(&state->i2c_client->dev,
2401                                                 client->irq, NULL, tc358840_irq_handler,
2402                                                 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
2403                                                 sd->name, (void *)sd);
2404                 if (err) {
2405                         v4l2_err(sd, "Could not request interrupt %d!\n",
2406                                  client->irq);
2407                         goto err_hdl;
2408                 }
2409         }
2410
2411         tc358840_enable_interrupts(sd, tx_5v_power_present(sd));
2412
2413         /*
2414          * FIXME: Don't know what MASK_CSITX0_INT and MASK_CSITX1_INT do.
2415          * Thus, disable them for now...
2416          */
2417 #if 0
2418         i2c_wr16(sd, INTMASK, ~(MASK_HDMI_INT | MASK_CSITX0_INT |
2419                 MASK_CSITX1_INT) & 0xFFFF);
2420 #endif
2421         i2c_wr16(sd, INTMASK, ~(MASK_HDMI_INT) & 0xFFFF);
2422
2423         v4l2_ctrl_handler_setup(sd->ctrl_handler);
2424
2425         v4l2_info(sd, "%s found @ 7h%02X (%s)\n", client->name,
2426                   client->addr, client->adapter->name);
2427
2428         sd->dev = &client->dev;
2429         sd->internal_ops = &tc358840_subdev_internal_ops;
2430         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2431 #if defined(CONFIG_MEDIA_CONTROLLER)
2432         state->pad[0].flags = MEDIA_PAD_FL_SOURCE;
2433         state->pad[1].flags = MEDIA_PAD_FL_SOURCE;
2434         sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
2435         sd->entity.ops = &tc358840_media_ops;
2436         err = media_entity_init(&sd->entity, 2, state->pad, 0);
2437         if (err < 0) {
2438                 dev_err(&client->dev, "unable to init media entity\n");
2439                 return err;
2440         }
2441 #endif
2442
2443         /* Temporary EDID. Should be set by userspace */
2444         tc358840_s_edid(sd, &sd_edid);
2445
2446         err = v4l2_async_register_subdev(sd);
2447         if (err == 0)
2448                 return 0;
2449
2450 err_hdl:
2451         v4l2_ctrl_handler_free(&state->hdl);
2452         return err;
2453 }
2454
2455 static int tc358840_remove(struct i2c_client *client)
2456 {
2457         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2458
2459         v4l_dbg(1, debug, client, "%s()\n", __func__);
2460
2461 #if defined(CONFIG_MEDIA_CONTROLLER)
2462         media_entity_cleanup(&sd->entity);
2463 #endif
2464         return 0;
2465 }
2466
2467 static const struct i2c_device_id tc358840_id[] = {
2468         { "tc358840", 0 },
2469         { }
2470 };
2471
2472 MODULE_DEVICE_TABLE(i2c, tc358840_id);
2473
2474 #ifdef CONFIG_OF
2475 static const struct of_device_id tc358840_of_table[] = {
2476         { .compatible = "toshiba,tc358840" },
2477         { }
2478 };
2479 MODULE_DEVICE_TABLE(of, tc358840_of_table);
2480 #endif
2481
2482 static struct i2c_driver tc358840_driver = {
2483         .driver = {
2484                 .of_match_table = of_match_ptr(tc358840_of_table),
2485                 .name = "tc358840",
2486                 .owner = THIS_MODULE,
2487         },
2488         .probe = tc358840_probe,
2489         .remove = tc358840_remove,
2490         .id_table = tc358840_id,
2491 };
2492 module_i2c_driver(tc358840_driver);
2493
2494 MODULE_DESCRIPTION("Driver for Toshiba TC358840 HDMI to CSI-2 Bridge");
2495 MODULE_AUTHOR("Armin Weiss (weii@zhaw.ch)");
2496 MODULE_LICENSE("GPL v2");