2 * ahci-tegra.c - AHCI SATA support for TEGRA AHCI device
4 * Copyright (c) 2011-2014, NVIDIA Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
22 * AHCI hardware documentation:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
28 #include <linux/platform_device.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/device.h>
38 #include <linux/dmi.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <scsi/scsi_host.h>
42 #include <scsi/scsi_cmnd.h>
43 #include <linux/libata.h>
44 #include <linux/regulator/machine.h>
45 #include <linux/pm_runtime.h>
48 #include <linux/clk.h>
49 #include <linux/clk/tegra.h>
50 #include <linux/tegra-powergate.h>
51 #include <linux/platform_data/tegra_ahci.h>
52 #include <linux/tegra-soc.h>
54 #include "../../arch/arm/mach-tegra/iomap.h"
56 #define DRV_NAME "tegra-sata"
57 #define DRV_VERSION "1.0"
59 #define ENABLE_AHCI_DBG_PRINT 0
60 #if ENABLE_AHCI_DBG_PRINT
61 #define AHCI_DBG_PRINT(fmt, arg...) printk(KERN_ERR fmt, ## arg)
63 #define AHCI_DBG_PRINT(fmt, arg...) do {} while (0)
66 /* number of AHCI ports */
67 #define TEGRA_AHCI_NUM_PORTS 1
69 /* idle timeout for PM in msec */
70 #define TEGRA_AHCI_MIN_IDLE_TIME 1000
71 #define TEGRA_AHCI_DEFAULT_IDLE_TIME 2000
73 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
74 static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME;
77 #define PORT_BASE (TEGRA_SATA_BAR5_BASE + 0x100)
79 /* Bit 0 (EN_FPCI) to allow FPCI accesses to SATA */
80 #define SATA_CONFIGURATION_0_OFFSET 0x180
81 #define EN_FPCI (1 << 0)
82 #define CLK_OVERRIDE (1 << 31)
84 #define SATA_INTR_MASK_0_OFFSET 0x188
85 #define IP_INT_MASK (1 << 16)
87 /* Need to write 0x00400200 to 0x70020094 */
88 #define SATA_FPCI_BAR5_0_OFFSET 0x094
89 #define PRI_ICTLR_CPU_IER_SET_0_OFFSET 0x024
90 #define CPU_IER_SATA_CTL (1 << 23)
92 #define AHCI_BAR5_CONFIG_LOCATION 0x24
93 #define TEGRA_SATA_BAR5_INIT_PROGRAM 0xFFFFFFFF
94 #define TEGRA_SATA_BAR5_FINAL_PROGRAM 0x40020000
96 #define FUSE_SATA_CALIB_OFFSET 0x224
97 #define FUSE_SATA_CALIB_MASK 0x3
99 #define T_SATA0_CFG_PHY_REG 0x120
100 #define T_SATA0_CFG_PHY_SQUELCH_MASK (1 << 24)
101 #define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK (1 << 11)
103 #define T_SATA0_CFG_POWER_GATE 0x4ac
104 #define POWER_GATE_SSTS_RESTORED_MASK (1 << 23)
105 #define POWER_GATE_SSTS_RESTORED_YES (1 << 23)
106 #define POWER_GATE_SSTS_RESTORED_NO (0 << 23)
108 #define T_SATA0_DBG0_OFFSET 0x550
110 #define T_SATA0_INDEX_OFFSET 0x680
111 #define SATA0_NONE_SELECTED 0
112 #define SATA0_CH1_SELECTED (1 << 0)
114 #define T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET 0x690
115 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
116 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK (0xff << 0)
117 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
118 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
120 #define T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET 0x694
121 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
122 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK (0xff << 0)
123 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
124 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
125 #define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT 24
126 #define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK (0xf << 24)
128 /* AHCI config space defines */
129 #define TEGRA_PRIVATE_AHCI_CC_BKDR 0x4a4
130 #define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE 0x54c
131 #define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN (1 << 12)
132 #define TEGRA_PRIVATE_AHCI_CC_BKDR_PGM 0x01060100
135 #define TEGRA_PRIVATE_AHCI_CAP_BKDR 0xa0
136 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
137 #define AHCI_HBA_PLL_CTRL_0 0xa8
139 #define CLAMP_TXCLK_ON_SLUMBER (1 << 13)
140 #define CLAMP_TXCLK_ON_DEVSLP (1 << 24)
141 #define NO_CLAMP_SHUT_DOWN (1 << 3)
143 #define TEGRA_SATA_IO_SPACE_OFFSET 4
144 #define TEGRA_SATA_ENABLE_IO_SPACE (1 << 0)
145 #define TEGRA_SATA_ENABLE_MEM_SPACE (1 << 1)
146 #define TEGRA_SATA_ENABLE_BUS_MASTER (1 << 2)
147 #define TEGRA_SATA_ENABLE_SERR (1 << 8)
148 #define TEGRA_SATA_CORE_CLOCK_FREQ_HZ (105*1000*1000)
149 #define TEGRA_SATA_OOB_CLOCK_FREQ_HZ (272*1000*1000)
151 #define APB_PMC_SATA_PWRGT_0_REG 0x1ac
152 #define APBDEV_PMC_PWRGATE_TOGGLE_0 0x30
153 #define APBDEV_PMC_PWRGATE_STATUS_0 0x38
154 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0 0x34
156 #define CLK_RST_SATA_PLL_CFG0_REG 0x490
157 #define CLK_RST_SATA_PLL_CFG1_REG 0x494
158 #define CLK_RST_CONTROLLER_RST_DEVICES_V_0 0x358
159 #define CLK_RST_CONTROLLER_RST_DEVICES_W_0 0x35c
160 #define CLK_RST_CONTROLLER_RST_DEV_W_CLR_0 0x43c
161 #define CLK_RST_CONTROLLER_RST_DEV_V_CLR_0 0x434
162 #define CLK_RST_CONTROLLER_CLK_ENB_V_CLR_0 0x444
163 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 0x440
164 #define CLK_RST_CONTROLLER_CLK_ENB_V_0 0x360
165 #define CLK_RST_CONTROLLER_RST_DEV_W_SET 0x438
166 #define CLK_RST_CONTROLLER_RST_DEV_V_SET 0x430
167 #define SET_CEC_RESET 0x100
170 #define CLR_CLK_ENB_SATA_OOB (1 << 27)
171 #define CLR_CLK_ENB_SATA (1 << 28)
173 #define CLK_RST_CONTROLLER_PLLE_MISC_0 0x0ec
174 #define CLK_RST_CONTROLLER_PLLE_MISC_0_VALUE 0x00070300
175 #define CLK_RST_CONTROLLER_PLLE_BASE_0 0xe8
176 #define PLLE_ENABLE (1 << 30)
177 #define CLK_RST_CONTROLLER_PLLE_AUX_0 0x48c
178 #define CLK_RST_CONTROLLER_PLLE_AUX_0_MASK (1 << 1)
180 #define CLR_SATACOLD_RST (1 << 1)
181 #define SWR_SATACOLD_RST (1 << 1)
182 #define SWR_SATA_RST (1 << 28)
183 #define SWR_SATA_OOB_RST (1 << 27)
184 #define DEVSLP_OVERRIDE (1 << 17)
185 #define SDS_SUPPORT (1 << 13)
186 #define DESO_SUPPORT (1 << 15)
187 #define SATA_AUX_PAD_PLL_CNTL_1_REG 0x1100
188 #define SATA_AUX_MISC_CNTL_1_REG 0x1108
189 #define SATA_AUX_SPARE_CFG0_0 0x1118
191 /* for APB_PMC_SATA_PWRGT_0_REG */
192 #define PG_INFO_MASK (1 << 6)
193 #define PG_INFO_ON (1 << 6)
194 #define PG_INFO_OFF (0 << 6)
195 #define PLLE_IDDQ_SWCTL_MASK (1 << 4)
196 #define PADPHY_IDDQ_OVERRIDE_VALUE_MASK (1 << 3)
197 #define PADPHY_IDDQ_OVERRIDE_VALUE_ON (1 << 3)
198 #define PADPHY_IDDQ_OVERRIDE_VALUE_OFF (0 << 3)
199 #define PADPHY_IDDQ_SWCTL_MASK (1 << 2)
200 #define PADPHY_IDDQ_SWCTL_ON (1 << 2)
201 #define PADPHY_IDDQ_SWCTL_OFF (0 << 2)
202 #define PADPLL_IDDQ_OVERRIDE_VALUE_MASK (1 << 1)
203 #define PADPLL_IDDQ_OVERRIDE_VALUE_ON (1 << 1)
204 #define PADPLL_IDDQ_OVERRIDE_VALUE_OFF (0 << 1)
205 #define PADPLL_IDDQ_SWCTL_MASK (1 << 0)
206 #define PADPLL_IDDQ_SWCTL_ON (1 << 0)
207 #define PADPLL_IDDQ_SWCTL_OFF (0 << 0)
209 #define START (1 < 8)
210 #define PARTID_VALUE 0x8
212 #define SAX_MASK (1 << 8)
214 /* for CLK_RST_SATA_PLL_CFG0_REG */
215 #define PADPLL_RESET_OVERRIDE_VALUE_MASK (1 << 1)
216 #define PADPLL_RESET_OVERRIDE_VALUE_ON (1 << 1)
217 #define PADPLL_RESET_OVERRIDE_VALUE_OFF (0 << 1)
218 #define PADPLL_RESET_SWCTL_MASK (1 << 0)
219 #define PADPLL_RESET_SWCTL_ON (1 << 0)
220 #define PADPLL_RESET_SWCTL_OFF (0 << 0)
221 #define PLLE_IDDQ_SWCTL_ON (1 << 4)
222 #define PLLE_IDDQ_SWCTL_OFF (0 << 4)
223 #define PLLE_SATA_SEQ_ENABLE (1 << 24)
224 #define PLLE_SATA_SEQ_START_STATE (1 << 25)
225 #define SATA_SEQ_PADPLL_PD_INPUT_VALUE (1 << 5)
226 #define SATA_SEQ_LANE_PD_INPUT_VALUE (1 << 6)
227 #define SATA_SEQ_RESET_INPUT_VALUE (1 << 7)
229 /* for CLK_RST_SATA_PLL_CFG1_REG */
230 #define IDDQ2LANE_SLUMBER_DLY_MASK (0xffL << 16)
231 #define IDDQ2LANE_SLUMBER_DLY_SHIFT 16
232 #define IDDQ2LANE_SLUMBER_DLY_3MS (3 << 16)
233 #define IDDQ2LANE_IDDQ_DLY_SHIFT 0
234 #define IDDQ2LANE_IDDQ_DLY_MASK (0xffL << 0)
236 /* for SATA_AUX_PAD_PLL_CNTL_1_REG */
237 #define REFCLK_SEL_MASK (3 << 11)
238 #define REFCLK_SEL_INT_CML (0 << 11)
239 #define LOCKDET_FIELD (1 << 6)
241 /* for SATA_AUX_MISC_CNTL_1_REG */
242 #define NVA2SATA_OOB_ON_POR_MASK (1 << 7)
243 #define NVA2SATA_OOB_ON_POR_YES (1 << 7)
244 #define NVA2SATA_OOB_ON_POR_NO (0 << 7)
245 #define L0_RX_IDLE_T_SAX_SHIFT 5
246 #define L0_RX_IDLE_T_SAX_MASK (3 << 5)
247 #define L0_RX_IDLE_T_NPG_SHIFT 3
248 #define L0_RX_IDLE_T_NPG_MASK (3 << 3)
249 #define L0_RX_IDLE_T_MUX_MASK (1 << 2)
250 #define L0_RX_IDLE_T_MUX_FROM_APB_MISC (1 << 2)
251 #define L0_RX_IDLE_T_MUX_FROM_SATA (0 << 2)
253 #define SSTAT_IPM_STATE_MASK 0xF00
254 #define SSTAT_IPM_SLUMBER_STATE 0x600
255 #define XUSB_PADCTL_USB3_PAD_MUX_0 0x134
256 #define FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 6)
257 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0 0x138
258 #define XUSB_PADCTL_PLL1_MODE (1 << 24)
259 #define XUSB_PADCTL_ELPG_PROGRAM_0 0x01c
260 #define AUX_ELPG_CLAMP_EN (1 << 24)
261 #define AUX_ELPG_CLAMP_EN_EARLY (1 << 25)
262 #define AUX_ELPG_VCORE_DOWN (1 << 26)
263 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0 0x148
264 #define XUSB_PADCTL_IOPHY_MISC_IDDQ_OVRD (1 << 1)
265 #define XUSB_PADCTL_IOPHY_MISC_IDDQ (1 << 0)
267 #define SATA_AXI_BAR5_START_0 0x54
268 #define SATA_AXI_BAR5_SZ_0 0x14
269 #define SATA_AXI_BAR5_START_VALUE 0x70020
270 #define AXI_BAR5_SIZE_VALUE 0x00008
271 #define FPCI_BAR5_0_START_VALUE 0x0010000
272 #define FPCI_BAR5_0_FINAL_VALUE 0x40020100
273 #define FPCI_BAR5_0_ACCESS_TYPE (1 << 0)
275 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0 0x148
276 #define IDDQ_OVRD_MASK (1 << 1)
277 #define IDDQ_MASK (1 << 0)
279 /* for XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0 */
280 #define PLL_PWR_OVRD_MASK (1 << 3)
281 #define PLL_RST_MASK (1 << 1)
282 #define PLL_IDDQ_MASK (1 << 0)
284 /* for CLK_RST_CONTROLLER_PLLE_MISC_0 */
285 #define T124_PLLE_IDDQ_SWCTL_MASK (1 << 14)
286 #define PLLE_IDDQ_OVERRIDE_VALUE_MASK (1 << 13)
288 /* Spread Settings */
289 #define SATA0_CHX_PHY_CTRL11_0 0x6D0
290 #define SATA0_CHX_PHY_CTRL2_0 0x69c
291 #define GEN2_RX_EQ (0x2800 << 16)
292 #define CDR_CNTL_GEN1 0x23
294 #define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0 0x68
295 #define PLLE_SSCCENTER (1 << 14)
296 #define PLLE_SSCINVERT (1 << 15)
297 #define PLLE_SSCMAX (0x25)
298 #define PLLE_SSCINCINTRV (0x20 << 24)
299 #define PLLE_SSCINC (1 << 16)
300 #define PLLE_BYPASS_SS (1 << 10)
301 #define PLLE_SSCBYP (1 << 12)
302 #define PLLE_INTERP_RESET (1 << 11)
304 #define SATA_AUX_RX_STAT_INT_0 0x110c
305 #define SATA_RX_STAT_INT_DISABLE (1 << 2)
307 #define T_SATA0_NVOOB 0x114
308 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT 24
309 #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (3 << 24)
310 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT 26
311 #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (3 << 26)
313 #define PXSSTS_DEVICE_DETECTED (1 << 0)
315 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
317 /* create a work for handling the async transfers */
318 static void tegra_ahci_work_handler(struct work_struct *work);
319 static DECLARE_WORK(tegra_ahci_work, tegra_ahci_work_handler);
320 static struct workqueue_struct *tegra_ahci_work_q;
327 enum port_idle_status {
330 PORT_IS_IDLE_NOT_SLUMBER,
342 enum clk_gate_state {
347 char *sata_power_rails[] = {
355 #define NUM_SATA_POWER_RAILS ARRAY_SIZE(sata_power_rails)
357 struct tegra_qc_list {
358 struct list_head list;
359 struct ata_queued_cmd *qc;
363 * tegra_ahci_host_priv is the extension of ahci_host_priv
364 * with extra fields: idle_timer, pg_save, pg_state, etc.
366 struct tegra_ahci_host_priv {
367 struct ahci_host_priv ahci_host_priv;
368 struct regulator *power_rails[NUM_SATA_POWER_RAILS];
369 void __iomem *bars_table[6];
370 struct ata_host *host;
371 struct timer_list idle_timer;
374 enum sata_state pg_state;
375 struct list_head qc_list;
376 struct clk *clk_sata;
377 struct clk *clk_sata_oob;
378 struct clk *clk_pllp;
379 struct clk *clk_cml1;
380 enum clk_gate_state clk_state;
385 static int tegra_ahci_init_one(struct platform_device *pdev);
386 static int tegra_ahci_remove_one(struct platform_device *pdev);
387 static void tegra_ahci_set_clk_rst_cnt_rst_dev(void);
388 static void tegra_ahci_clr_clk_rst_cnt_rst_dev(void);
389 static void tegra_ahci_pad_config(void);
390 static void tegra_ahci_put_sata_in_iddq(void);
391 static void tegra_ahci_iddqlane_config(void);
394 static bool tegra_ahci_power_un_gate(struct ata_host *host);
395 static bool tegra_ahci_power_gate(struct ata_host *host);
396 static void tegra_ahci_abort_power_gate(struct ata_host *host);
397 static int tegra_ahci_controller_suspend(struct platform_device *pdev);
398 static int tegra_ahci_controller_resume(struct platform_device *pdev);
399 static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg);
400 static int tegra_ahci_resume(struct platform_device *pdev);
401 static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap);
402 static bool tegra_ahci_are_all_ports_idle(struct ata_host *host);
403 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
404 static bool tegra_ahci_pad_resume(struct ata_host *host);
405 static bool tegra_ahci_pad_suspend(struct ata_host *host);
406 static void tegra_ahci_abort_pad_suspend(struct ata_host *host);
407 static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc);
408 static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
409 unsigned long deadline);
410 static int tegra_ahci_runtime_suspend(struct device *dev);
411 static int tegra_ahci_runtime_resume(struct device *dev);
412 static void tegra_ahci_idle_timer(unsigned long arg);
413 static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
414 struct ata_queued_cmd *qc);
415 static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv);
418 #define tegra_ahci_controller_suspend NULL
419 #define tegra_ahci_controller_resume NULL
420 #define tegra_ahci_suspend NULL
421 #define tegra_ahci_resume NULL
424 static struct scsi_host_template ahci_sht = {
425 AHCI_SHT("tegra-sata"),
428 static struct ata_port_operations tegra_ahci_ops = {
429 .inherits = &ahci_ops,
431 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
432 .qc_issue = tegra_ahci_qc_issue,
433 .hardreset = tegra_ahci_hardreset,
438 static const struct ata_port_info ahci_port_info = {
439 .flags = AHCI_FLAG_COMMON,
440 .pio_mask = 0x1f, /* pio0-4 */
441 .udma_mask = ATA_UDMA6,
442 .port_ops = &tegra_ahci_ops,
445 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
446 static const struct dev_pm_ops tegra_ahci_dev_rt_ops = {
447 .runtime_suspend = tegra_ahci_runtime_suspend,
448 .runtime_resume = tegra_ahci_runtime_resume,
452 static const struct of_device_id of_ahci_tegra_match[] = {
453 { .compatible = "nvidia,tegra114-ahci-sata", },
456 MODULE_DEVICE_TABLE(of, of_ahci_tegra_match);
458 static struct platform_driver tegra_platform_ahci_driver = {
459 .probe = tegra_ahci_init_one,
460 .remove = tegra_ahci_remove_one,
462 .suspend = tegra_ahci_suspend,
463 .resume = tegra_ahci_resume,
467 .owner = THIS_MODULE,
468 .of_match_table = of_match_ptr(of_ahci_tegra_match),
472 struct tegra_ahci_host_priv *g_tegra_hpriv;
474 static inline u32 port_readl(u32 offset)
478 val = readl(IO_ADDRESS(PORT_BASE + offset));
479 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", PORT_BASE + offset, val);
483 static inline void port_writel(u32 val, u32 offset)
485 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", PORT_BASE + offset, val);
486 writel(val, IO_ADDRESS(PORT_BASE + offset));
487 readl(IO_ADDRESS(PORT_BASE + offset));
490 static inline u32 bar5_readl(u32 offset)
493 val = readl(IO_ADDRESS(TEGRA_SATA_BAR5_BASE + offset));
494 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_BAR5_BASE+offset,
499 static inline void bar5_writel(u32 val, u32 offset)
501 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BAR5_BASE+offset,
503 writel(val, IO_ADDRESS(TEGRA_SATA_BAR5_BASE + offset));
504 readl(IO_ADDRESS(TEGRA_SATA_BAR5_BASE + offset));
508 static inline u32 xusb_readl(u32 offset)
511 val = readl(IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE + offset));
512 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_XUSB_PADCTL_BASE+offset,
517 static inline void xusb_writel(u32 val, u32 offset)
519 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_XUSB_PADCTL_BASE+offset,
521 writel(val, IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE + offset));
522 readl(IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE + offset));
526 static inline u32 pmc_readl(u32 offset)
529 val = readl(IO_ADDRESS(TEGRA_PMC_BASE + offset));
530 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PMC_BASE+offset, val);
534 static inline void pmc_writel(u32 val, u32 offset)
536 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PMC_BASE+offset, val);
537 writel(val, IO_ADDRESS(TEGRA_PMC_BASE + offset));
538 readl(IO_ADDRESS(TEGRA_PMC_BASE + offset));
541 static inline u32 clk_readl(u32 offset)
545 val = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
546 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
550 static inline void clk_writel(u32 val, u32 offset)
552 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
553 writel(val, IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
554 readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
557 static inline u32 misc_readl(u32 offset)
561 val = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
562 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
566 static inline void misc_writel(u32 val, u32 offset)
568 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
569 writel(val, IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
570 readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
573 static inline u32 sata_readl(u32 offset)
577 val = readl(IO_ADDRESS(TEGRA_SATA_BASE + offset));
578 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_BASE+offset, val);
582 static inline void sata_writel(u32 val, u32 offset)
584 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BASE+offset, val);
585 writel(val, IO_ADDRESS(TEGRA_SATA_BASE + offset));
586 readl(IO_ADDRESS(TEGRA_SATA_BASE + offset));
589 static inline u32 scfg_readl(u32 offset)
593 val = readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
594 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
599 static inline void scfg_writel(u32 val, u32 offset)
601 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
603 writel(val, IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
604 readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
607 static inline u32 pictlr_readl(u32 offset)
611 val = readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
612 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
617 static inline void pictlr_writel(u32 val, u32 offset)
619 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
621 writel(val, IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
622 readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
625 static inline u32 fuse_readl(u32 offset)
629 val = readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
630 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_FUSE_BASE+offset, val);
635 /* Sata Pad Cntrl Values */
636 struct sata_pad_cntrl {
643 static const struct sata_pad_cntrl sata_calib_pad_val[] = {
644 { /* SATA_CALIB[1:0] = 00 */
650 { /* SATA_CALIB[1:0] = 01 */
656 { /* SATA_CALIB[1:0] = 10 */
662 { /* SATA_CALIB[1:0] = 11 */
670 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
671 static void tegra_ahci_work_handler(struct work_struct *work)
673 tegra_ahci_runtime_resume(g_tegra_hpriv->dev);
677 static void tegra_ahci_set_pad_cntrl_regs(
678 struct tegra_ahci_host_priv *tegra_hpriv)
684 calib_val = fuse_readl(FUSE_SATA_CALIB_OFFSET) & FUSE_SATA_CALIB_MASK;
686 val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
687 val &= ~(PLLE_SSCCENTER | PLLE_SSCINVERT);
688 val |= (PLLE_SSCMAX | PLLE_SSCINCINTRV | PLLE_SSCINC);
689 clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
691 val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
692 val &= ~(PLLE_BYPASS_SS | PLLE_SSCBYP);
693 clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
697 val = clk_readl(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
698 val &= ~(PLLE_INTERP_RESET);
699 clk_writel(val, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0);
701 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
702 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
704 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
705 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
706 val |= (sata_calib_pad_val[calib_val].gen1_tx_amp <<
707 SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
708 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
710 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
711 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
712 val |= (sata_calib_pad_val[calib_val].gen1_tx_peak <<
713 SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
714 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
716 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
717 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
718 val |= (sata_calib_pad_val[calib_val].gen2_tx_amp <<
719 SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
720 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
722 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
723 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
724 val |= (sata_calib_pad_val[calib_val].gen2_tx_peak <<
725 SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
726 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
729 scfg_writel(val, SATA0_CHX_PHY_CTRL11_0);
732 scfg_writel(val, SATA0_CHX_PHY_CTRL2_0);
734 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
737 int tegra_ahci_get_rails(struct regulator *regulators[])
739 struct regulator *reg;
743 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
744 reg = regulator_get(g_tegra_hpriv->dev, sata_power_rails[i]);
745 if (IS_ERR_OR_NULL(reg)) {
746 pr_err("%s: can't get regulator %s\n",
747 __func__, sata_power_rails[i]);
758 void tegra_ahci_put_rails(struct regulator *regulators[])
762 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i)
763 regulator_put(regulators[i]);
766 int tegra_ahci_power_on_rails(struct regulator *regulators[])
768 struct regulator *reg;
772 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
774 ret = regulator_enable(reg);
776 pr_err("%s: can't enable regulator[%d]\n",
787 int tegra_ahci_power_off_rails(struct regulator *regulators[])
789 struct regulator *reg;
793 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
795 if (!IS_ERR_OR_NULL(reg)) {
796 ret = regulator_disable(reg);
798 pr_err("%s: can't disable regulator[%d]\n",
810 static void tegra_first_level_clk_gate(void)
812 if (g_tegra_hpriv->clk_state == CLK_OFF)
815 clk_disable_unprepare(g_tegra_hpriv->clk_sata);
816 clk_disable_unprepare(g_tegra_hpriv->clk_sata_oob);
817 clk_disable_unprepare(g_tegra_hpriv->clk_cml1);
818 g_tegra_hpriv->clk_state = CLK_OFF;
821 static int tegra_first_level_clk_ungate(void)
825 if (g_tegra_hpriv->clk_state == CLK_ON) {
830 if (clk_prepare_enable(g_tegra_hpriv->clk_sata)) {
831 pr_err("%s: unable to enable SATA clock\n", __func__);
835 if (clk_prepare_enable(g_tegra_hpriv->clk_sata_oob)) {
836 pr_err("%s: unable to enable SATA_OOB clock\n", __func__);
837 clk_disable_unprepare(g_tegra_hpriv->clk_sata);
841 if (clk_prepare_enable(g_tegra_hpriv->clk_cml1)) {
842 pr_err("%s: unable to enable cml1 clock\n", __func__);
843 clk_disable_unprepare(g_tegra_hpriv->clk_sata);
844 clk_disable_unprepare(g_tegra_hpriv->clk_sata_oob);
848 g_tegra_hpriv->clk_state = CLK_ON;
853 static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv,
857 struct clk *clk_sata = NULL;
858 struct clk *clk_sata_oob = NULL;
859 struct clk *clk_sata_cold = NULL;
860 struct clk *clk_pllp = NULL;
861 struct clk *clk_cml1 = NULL;
866 err = tegra_ahci_get_rails(tegra_hpriv->power_rails);
868 pr_err("%s: fails to get rails (%d)\n", __func__, err);
873 err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
875 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
879 /* pll_p is the parent of tegra_sata and tegra_sata_oob */
880 clk_pllp = clk_get_sys(NULL, "pll_p");
881 if (IS_ERR_OR_NULL(clk_pllp)) {
882 pr_err("%s: unable to get PLL_P clock\n", __func__);
883 err = PTR_ERR(clk_pllp);
887 clk_sata = clk_get_sys("tegra_sata", NULL);
888 if (IS_ERR_OR_NULL(clk_sata)) {
889 pr_err("%s: unable to get SATA clock\n", __func__);
890 err = PTR_ERR(clk_sata);
894 clk_sata_oob = clk_get_sys("tegra_sata_oob", NULL);
895 if (IS_ERR_OR_NULL(clk_sata_oob)) {
896 pr_err("%s: unable to get SATA OOB clock\n", __func__);
897 err = PTR_ERR(clk_sata_oob);
901 clk_sata_cold = clk_get_sys("tegra_sata_cold", NULL);
902 if (IS_ERR_OR_NULL(clk_sata_cold)) {
903 pr_err("%s: unable to get SATA COLD clock\n", __func__);
904 err = PTR_ERR(clk_sata_cold);
908 tegra_hpriv->clk_sata = clk_sata;
909 tegra_hpriv->clk_sata_oob = clk_sata_oob;
910 tegra_hpriv->clk_pllp = clk_pllp;
912 tegra_periph_reset_assert(clk_sata);
913 tegra_periph_reset_assert(clk_sata_oob);
914 tegra_periph_reset_assert(clk_sata_cold);
917 /* need to establish both clocks divisors before setting clk sources */
918 clk_set_rate(clk_sata, clk_get_rate(clk_sata)/10);
919 clk_set_rate(clk_sata_oob, clk_get_rate(clk_sata_oob)/10);
921 /* set SATA clk and SATA_OOB clk source */
922 clk_set_parent(clk_sata, clk_pllp);
923 clk_set_parent(clk_sata_oob, clk_pllp);
925 /* Configure SATA clocks */
926 /* Core clock runs at 108MHz */
927 if (clk_set_rate(clk_sata, TEGRA_SATA_CORE_CLOCK_FREQ_HZ)) {
931 /* OOB clock runs at 216MHz */
932 if (clk_set_rate(clk_sata_oob, TEGRA_SATA_OOB_CLOCK_FREQ_HZ)) {
937 if (clk_prepare_enable(clk_sata)) {
938 pr_err("%s: unable to enable SATA clock\n", __func__);
943 if (clk_prepare_enable(clk_sata_oob)) {
944 pr_err("%s: unable to enable SATA OOB clock\n", __func__);
949 tegra_periph_reset_deassert(clk_sata);
950 tegra_periph_reset_deassert(clk_sata_oob);
951 tegra_periph_reset_deassert(clk_sata_cold);
953 tegra_ahci_clr_clk_rst_cnt_rst_dev();
955 if (gpio_is_valid(tegra_hpriv->pexp_gpio)) {
956 val = gpio_request(tegra_hpriv->pexp_gpio,
959 pr_err("failed to allocate Port expander gpio\n");
963 gpio_direction_output(tegra_hpriv->pexp_gpio, 1);
967 pmc_writel(val, APBDEV_PMC_REMOVE_CLAMPING_CMD_0);
970 /* SATA_PADPLL_RESET_OVERRIDE_VALUE=1 and SATA_PADPLL_RESET_SWCTL=1 */
971 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
972 val |= (PADPLL_RESET_OVERRIDE_VALUE_ON | PADPLL_RESET_SWCTL_ON);
973 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
975 /* select internal CML ref clk
976 * select PLLE as input to IO phy */
977 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
978 val &= ~REFCLK_SEL_MASK;
979 val |= REFCLK_SEL_INT_CML;
980 misc_writel(val, SATA_AUX_PAD_PLL_CNTL_1_REG);
982 /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
983 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
984 val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
985 val |= IDDQ2LANE_SLUMBER_DLY_3MS;
986 clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
989 #if defined(CONFIG_TEGRA_SILICON_PLATFORM)
990 err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
992 pr_err("%s: ** failed to turn-on SATA (0x%x) **\n",
999 * place SATA Pad PLL out of reset by writing
1000 * SATA_PADPLL_RST_OVERRIDE_VALUE = 0
1002 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1003 val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
1004 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1007 * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
1013 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1014 if (val & LOCKDET_FIELD)
1018 pr_err("%s: AUX_PAD_PLL_CNTL_1 (0x%x) is not locked in 15us.\n",
1021 tegra_ahci_pad_config();
1023 clk_cml1 = clk_get_sys(NULL, "cml1");
1024 if (IS_ERR_OR_NULL(clk_cml1)) {
1025 pr_err("%s: unable to get cml1 clock Errone is %d\n",
1026 __func__, (int) PTR_ERR(clk_cml1));
1027 err = PTR_ERR(clk_cml1);
1030 tegra_hpriv->clk_cml1 = clk_cml1;
1031 if (clk_prepare_enable(clk_cml1)) {
1032 pr_err("%s: unable to enable cml1 clock\n", __func__);
1037 g_tegra_hpriv->clk_state = CLK_ON;
1039 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1040 val &= ~PADPLL_RESET_SWCTL_MASK;
1041 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1043 /* PLLE Programing for SATA */
1045 val = clk_readl(CLK_RST_CONTROLLER_PLLE_AUX_0);
1046 val |= CLK_RST_CONTROLLER_PLLE_AUX_0_MASK;
1047 clk_writel(val, CLK_RST_CONTROLLER_PLLE_AUX_0);
1049 /* bring SATA IOPHY out of IDDQ */
1050 val = xusb_readl(XUSB_PADCTL_USB3_PAD_MUX_0);
1051 val |= FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
1052 xusb_writel(val, XUSB_PADCTL_USB3_PAD_MUX_0);
1054 val = xusb_readl(XUSB_PADCTL_ELPG_PROGRAM_0);
1055 val &= ~(AUX_ELPG_CLAMP_EN | AUX_ELPG_CLAMP_EN_EARLY |
1056 AUX_ELPG_VCORE_DOWN);
1057 xusb_writel(val, XUSB_PADCTL_ELPG_PROGRAM_0);
1059 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1060 val = val | XUSB_PADCTL_PLL1_MODE;
1061 xusb_writel(val, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1063 /* clear NVA2SATA_OOB_ON_POR in SATA_AUX_MISC_CNTL_1_REG */
1064 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1065 val &= ~NVA2SATA_OOB_ON_POR_MASK;
1066 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1068 val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
1070 sata_writel(val, SATA_CONFIGURATION_0_OFFSET);
1072 val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
1073 val |= CLK_OVERRIDE;
1074 sata_writel(val, SATA_CONFIGURATION_0_OFFSET);
1076 /* program sata pad control based on the fuse */
1077 tegra_ahci_set_pad_cntrl_regs(tegra_hpriv);
1080 * clear bit T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD of
1083 val = scfg_readl(T_SATA0_CFG_PHY_REG);
1084 val |= T_SATA0_CFG_PHY_SQUELCH_MASK;
1085 scfg_writel(val, T_SATA0_CFG_PHY_REG);
1087 val = scfg_readl(T_SATA0_NVOOB);
1088 val |= (1 << T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT);
1089 val |= (3 << T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT);
1090 scfg_writel(val, T_SATA0_NVOOB);
1093 * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored.
1094 * To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to
1095 * be 1, and bit 8 needs to be 0.
1097 val = scfg_readl(T_SATA0_DBG0_OFFSET);
1100 scfg_writel(val, T_SATA0_DBG0_OFFSET);
1102 /* program class code and programming interface for AHCI */
1103 val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1104 val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1105 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1106 scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
1107 val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1108 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1110 /* Program config space registers: */
1112 /* Enable BUS_MASTER+MEM+IO space, and SERR */
1113 val = scfg_readl(TEGRA_SATA_IO_SPACE_OFFSET);
1114 val |= TEGRA_SATA_ENABLE_IO_SPACE | TEGRA_SATA_ENABLE_MEM_SPACE |
1115 TEGRA_SATA_ENABLE_BUS_MASTER | TEGRA_SATA_ENABLE_SERR;
1116 scfg_writel(val, TEGRA_SATA_IO_SPACE_OFFSET);
1118 /* program bar5 space, by first writing 1's to bar5 register */
1119 scfg_writel(TEGRA_SATA_BAR5_INIT_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
1121 val = scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
1123 /* then, write the BAR5_FINAL_PROGRAM address */
1124 scfg_writel(TEGRA_SATA_BAR5_FINAL_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
1126 scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
1128 sata_writel((FPCI_BAR5_0_FINAL_VALUE >> 8),
1129 SATA_FPCI_BAR5_0_OFFSET);
1131 val = scfg_readl(T_SATA0_AHCI_HBA_CAP_BKDR);
1132 val |= (HOST_CAP_ALPM | HOST_CAP_SSC | HOST_CAP_PART);
1133 scfg_writel(val, T_SATA0_AHCI_HBA_CAP_BKDR);
1135 /* Second Level Clock Gating*/
1136 val = bar5_readl(AHCI_HBA_PLL_CTRL_0);
1137 val |= (CLAMP_TXCLK_ON_SLUMBER | CLAMP_TXCLK_ON_DEVSLP);
1138 val &= ~NO_CLAMP_SHUT_DOWN;
1139 bar5_writel(val, AHCI_HBA_PLL_CTRL_0);
1141 /* set IP_INT_MASK */
1142 val = sata_readl(SATA_INTR_MASK_0_OFFSET);
1144 sata_writel(val, SATA_INTR_MASK_0_OFFSET);
1147 if (!IS_ERR_OR_NULL(clk_pllp))
1149 if (!IS_ERR_OR_NULL(clk_sata))
1151 if (!IS_ERR_OR_NULL(clk_sata_oob))
1152 clk_put(clk_sata_oob);
1153 if (!IS_ERR_OR_NULL(clk_sata_cold))
1154 clk_put(clk_sata_cold);
1155 if (!IS_ERR_OR_NULL(clk_cml1))
1159 /* turn off all SATA power rails; ignore returned status */
1160 tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
1161 /* return regulators to system */
1162 tegra_ahci_put_rails(tegra_hpriv->power_rails);
1167 static void tegra_ahci_save_initial_config(struct platform_device *pdev,
1168 struct ahci_host_priv *hpriv)
1170 ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
1173 static void tegra_ahci_controller_remove(struct platform_device *pdev)
1175 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1176 struct tegra_ahci_host_priv *tegra_hpriv;
1179 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1182 /* call tegra_ahci_controller_suspend() to power-down the SATA */
1183 status = tegra_ahci_controller_suspend(pdev);
1185 dev_err(host->dev, "remove: error suspend SATA (0x%x)\n",
1188 /* power off the sata */
1189 status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
1191 dev_err(host->dev, "remove: error turn-off SATA (0x%x)\n",
1193 tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
1196 /* return system resources */
1197 tegra_ahci_put_rails(tegra_hpriv->power_rails);
1201 static int tegra_ahci_controller_suspend(struct platform_device *pdev)
1203 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1204 struct tegra_ahci_host_priv *tegra_hpriv;
1205 unsigned long flags;
1207 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1209 /* stop the idle timer */
1210 if (timer_pending(&tegra_hpriv->idle_timer))
1211 del_timer_sync(&tegra_hpriv->idle_timer);
1213 spin_lock_irqsave(&host->lock, flags);
1214 if (tegra_hpriv->pg_state == SATA_OFF)
1215 dev_dbg(host->dev, "suspend: SATA already power gated\n");
1219 dev_dbg(host->dev, "suspend: power gating SATA...\n");
1220 pg_ok = tegra_ahci_power_gate(host);
1222 tegra_hpriv->pg_state = SATA_OFF;
1223 dev_dbg(host->dev, "suspend: SATA is power gated\n");
1225 tegra_ahci_abort_power_gate(host);
1226 spin_unlock_irqrestore(&host->lock, flags);
1231 if (gpio_is_valid(tegra_hpriv->pexp_gpio))
1232 gpio_free(tegra_hpriv->pexp_gpio);
1233 spin_unlock_irqrestore(&host->lock, flags);
1235 tegra_first_level_clk_gate();
1237 return tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
1240 static int tegra_ahci_controller_resume(struct platform_device *pdev)
1242 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1243 struct tegra_ahci_host_priv *tegra_hpriv;
1244 unsigned long flags;
1247 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1249 err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
1251 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
1255 err = tegra_first_level_clk_ungate();
1257 pr_err("%s: flcg ungate failed\n", __func__);
1261 spin_lock_irqsave(&host->lock, flags);
1262 if (tegra_hpriv->pg_state == SATA_ON) {
1263 dev_dbg(host->dev, "resume: SATA already powered on\n");
1265 dev_dbg(host->dev, "resume: powering on SATA...\n");
1266 tegra_ahci_power_un_gate(host);
1267 tegra_hpriv->pg_state = SATA_ON;
1269 spin_unlock_irqrestore(&host->lock, flags);
1270 tegra_first_level_clk_gate();
1275 static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg)
1277 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1278 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1282 dev_dbg(host->dev, "** entering %s: **\n", __func__);
1283 if (mesg.event & PM_EVENT_SLEEP) {
1285 * AHCI spec rev1.1 section 8.3.3:
1286 * Software must disable interrupts prior to requesting a
1287 * transition of the HBA to D3 state.
1289 ctl = readl(mmio + HOST_CTL);
1290 ctl &= ~HOST_IRQ_EN;
1291 writel(ctl, mmio + HOST_CTL);
1292 readl(mmio + HOST_CTL); /* flush */
1295 rc = ata_host_suspend(host, mesg);
1299 return tegra_ahci_controller_suspend(pdev);
1302 static int tegra_ahci_resume(struct platform_device *pdev)
1304 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1308 dev_dbg(host->dev, "** entering %s: **\n", __func__);
1309 rc = tegra_ahci_controller_resume(pdev);
1313 rc = tegra_ahci_controller_init(g_tegra_hpriv, 1);
1315 dev_err(host->dev, "TEGRA SATA init failed in resume\n");
1319 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1320 rc = ahci_reset_controller(host);
1324 val = misc_readl(SATA_AUX_RX_STAT_INT_0);
1325 if (val && SATA_RX_STAT_INT_DISABLE) {
1326 val &= ~SATA_RX_STAT_INT_DISABLE;
1327 misc_writel(val, SATA_AUX_RX_STAT_INT_0);
1330 ahci_init_controller(host);
1333 ata_host_resume(host);
1338 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
1339 static int tegra_ahci_runtime_suspend(struct device *dev)
1341 struct ata_host *host;
1342 struct tegra_ahci_host_priv *tegra_hpriv;
1344 unsigned long flags;
1347 host = dev_get_drvdata(dev);
1348 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1350 spin_lock_irqsave(&host->lock, flags);
1352 switch (tegra_hpriv->pg_state) {
1354 dev_dbg(dev, "** rt-suspend: already power gated **\n");
1357 case SATA_ABORT_OFF:
1358 dev_dbg(dev, "** rt-suspend: abort suspend **\n");
1359 tegra_hpriv->pg_state = SATA_ON;
1360 tegra_ahci_dequeue_qcs(tegra_hpriv);
1365 case SATA_GOING_OFF:
1366 if (tegra_ahci_are_all_ports_idle(host)) {
1367 /* if all ports are in idle, do power-gate */
1368 dev_dbg(dev, "** rt-suspend: power-down sata (%u) **\n",
1369 tegra_hpriv->pg_state);
1370 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
1371 pg_ok = tegra_ahci_power_gate(host);
1373 pg_ok = tegra_ahci_pad_suspend(host);
1375 dev_dbg(dev, "** rt-suspend: done **\n");
1377 tegra_hpriv->pg_state = SATA_OFF;
1379 dev_err(dev, "** rt-suspend: abort pg **\n");
1380 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
1381 tegra_ahci_abort_power_gate(host);
1383 tegra_ahci_abort_pad_suspend(host);
1385 tegra_hpriv->pg_state = SATA_ON;
1389 dev_dbg(dev, "** rt-suspend: port not idle (%u) **\n",
1390 tegra_hpriv->pg_state);
1397 dev_err(dev, "** rt-suspend: bad state (%u) **\n",
1398 tegra_hpriv->pg_state);
1405 spin_unlock_irqrestore(&host->lock, flags);
1410 static int tegra_ahci_runtime_resume(struct device *dev)
1412 struct ata_host *host;
1413 struct tegra_ahci_host_priv *tegra_hpriv;
1416 host = dev_get_drvdata(dev);
1417 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1419 if (tegra_hpriv->pg_state == SATA_ON) {
1420 dev_dbg(dev, "** rt-resume: already power ungated **\n");
1424 if ((tegra_hpriv->pg_state == SATA_OFF) ||
1425 (tegra_hpriv->pg_state == SATA_GOING_ON)) {
1426 dev_dbg(dev, "** rt-resume: power-up sata (%u) **\n",
1427 tegra_hpriv->pg_state);
1428 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
1429 tegra_ahci_power_un_gate(host);
1431 tegra_ahci_pad_resume(host);
1433 dev_dbg(dev, "** rt-resume: done **\n");
1434 tegra_hpriv->pg_state = SATA_ON;
1436 /* now qc_issue all qcs in the qc_list */
1437 tegra_ahci_dequeue_qcs(tegra_hpriv);
1440 dev_err(dev, "** rt-resume: bad state (%u) **\n",
1441 tegra_hpriv->pg_state);
1454 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
1455 static u16 pg_save_bar5_registers[] = {
1456 0x018, /* T_AHCI_HBA_CCC_PORTS */
1457 0x004, /* T_AHCI_HBA_GHC */
1458 0x014, /* T_AHCI_HBA_CCC_CTL - OP (optional) */
1459 0x01C, /* T_AHCI_HBA_EM_LOC */
1460 0x020 /* T_AHCI_HBA_EM_CTL - OP */
1463 static u16 pg_save_bar5_port_registers[] = {
1464 0x100, /* T_AHCI_PORT_PXCLB */
1465 0x104, /* T_AHCI_PORT_PXCLBU */
1466 0x108, /* T_AHCI_PORT_PXFB */
1467 0x10C, /* T_AHCI_PORT_PXFBU */
1468 0x114, /* T_AHCI_PORT_PXIE */
1469 0x118, /* T_AHCI_PORT_PXCMD */
1470 0x12C, /* T_AHCI_PORT_PXSCTL */
1471 0x144 /* T_AHCI_PORT_PXDEVSLP */
1475 * pg_save_bar5_bkdr_registers:
1476 * These registers in BAR5 are read only.
1477 * To restore back those register values, write the saved value
1478 * to the registers specified in pg_restore_bar5_bkdr_registers[].
1479 * These pg_restore_bar5_bkdr_registers[] are in SATA_CONFIG space.
1481 static u16 pg_save_bar5_bkdr_registers[] = {
1482 /* Save and restore via bkdr writes */
1483 0x000, /* T_AHCI_HBA_CAP */
1484 0x00C, /* T_AHCI_HBA_PI */
1485 0x024 /* T_AHCI_HBA_CAP2 */
1488 static u16 pg_restore_bar5_bkdr_registers[] = {
1489 /* Save and restore via bkdr writes */
1490 0x300, /* BKDR of T_AHCI_HBA_CAP */
1491 0x33c, /* BKDR of T_AHCI_HBA_PI */
1492 0x330 /* BKDR of T_AHCI_HBA_CAP2 */
1495 /* These registers are saved for each port */
1496 static u16 pg_save_bar5_bkdr_port_registers[] = {
1497 0x120, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
1498 0x124, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
1499 0x128 /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
1502 static u16 pg_restore_bar5_bkdr_port_registers[] = {
1503 /* Save and restore via bkdr writes */
1504 0x790, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
1505 0x794, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
1506 0x798 /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
1509 static u16 pg_save_config_registers[] = {
1510 0x004, /* T_SATA0_CFG_1 */
1511 0x00C, /* T_SATA0_CFG_3 */
1512 0x024, /* T_SATA0_CFG_9 */
1513 0x028, /* T_SATA0_CFG_10 */
1514 0x030, /* T_SATA0_CFG_12 */
1515 0x034, /* T_SATA0_CFG_13 */
1516 0x038, /* T_SATA0_CFG_14 */
1517 0x03C, /* T_SATA0_CFG_15 */
1518 0x040, /* T_SATA0_CFG_16 */
1519 0x044, /* T_SATA0_CFG_17 */
1520 0x048, /* T_SATA0_CFG_18 */
1521 0x0B0, /* T_SATA0_MSI_CTRL */
1522 0x0B4, /* T_SATA0_MSI_ADDR1 */
1523 0x0B8, /* T_SATA0_MSI_ADDR2 */
1524 0x0BC, /* T_SATA0_MSI_DATA */
1525 0x0C0, /* T_SATA0_MSI_QUEUE */
1526 0x0EC, /* T_SATA0_MSI_MAP */
1527 0x124, /* T_SATA0_CFG_PHY_POWER */
1528 0x128, /* T_SATA0_CFG_PHY_POWER_1 */
1529 0x12C, /* T_SATA0_CFG_PHY_1 */
1530 0x174, /* T_SATA0_CFG_LINK_0 */
1531 0x178, /* T_SATA0_CFG_LINK_1 */
1532 0x1D0, /* MCP_SATA0_CFG_TRANS_0 */
1533 0x238, /* T_SATA0_ALPM_CTRL */
1534 0x30C, /* T_SATA0_AHCI_HBA_CYA_0 */
1535 0x320, /* T_SATA0_AHCI_HBA_SPARE_1 */
1536 0x324, /* T_SATA0_AHCI_HBA_SPARE_2 */
1537 0x328, /* T_SATA0_AHCI_HBA_DYN_CLK_CLAMP */
1538 0x32C, /* T_SATA0_AHCI_CFG_ERR_CTRL */
1539 0x338, /* T_SATA0_AHCI_HBA_CYA_1 */
1540 0x340, /* T_SATA0_AHCI_HBA_PRE_STAGING_CONTROL */
1541 0x430, /* T_SATA0_CFG_FPCI_0 */
1542 0x494, /* T_SATA0_CFG_ESATA_CTRL */
1543 0x4A0, /* T_SATA0_CYA1 */
1544 0x4B0, /* T_SATA0_CFG_GLUE */
1545 0x534, /* T_SATA0_PHY_CTRL */
1546 0x540, /* T_SATA0_CTRL */
1547 0x550, /* T_SATA0_DBG0 */
1548 0x554 /* T_SATA0_LOW_POWER_COUNT */
1551 static u16 pg_save_config_port_registers[] = {
1552 /* Save and restore per port */
1553 /* need to have port selected */
1554 0x530, /* T_SATA0_CHXCFG1 */
1555 0x684, /* T_SATA0_CHX_MISC */
1556 0x700, /* T_SATA0_CHXCFG3 */
1557 0x704, /* T_SATA0_CHXCFG4_CHX */
1558 0x690, /* T_SATA0_CHX_PHY_CTRL1_GEN1 */
1559 0x694, /* T_SATA0_CHX_PHY_CTRL1_GEN2 */
1560 0x698, /* T_SATA0_CHX_PHY_CTRL1_GEN3 */
1561 0x69C, /* T_SATA0_CHX_PHY_CTRL_2 */
1562 0x6B0, /* T_SATA0_CHX_PHY_CTRL_3 */
1563 0x6B4, /* T_SATA0_CHX_PHY_CTRL_4 */
1564 0x6B8, /* T_SATA0_CHX_PHY_CTRL_5 */
1565 0x6BC, /* T_SATA0_CHX_PHY_CTRL_6 */
1566 0x714, /* T_SATA0_PRBS_CHX - OP */
1567 0x750, /* T_SATA0_CHX_LINK0 */
1568 0x7F0 /* T_SATA0_CHX_GLUE */
1571 static u16 pg_save_ipfs_registers[] = {
1572 0x094, /* SATA_FPCI_BAR5_0 */
1573 0x0C0, /* SATA_MSI_BAR_SZ_0 */
1574 0x0C4, /* SATA_MSI_AXI_BAR_ST_0 */
1575 0x0C8, /* SATA_MSI_FPCI_BAR_ST_0 */
1576 0x140, /* SATA_MSI_EN_VEC0_0 */
1577 0x144, /* SATA_MSI_EN_VEC1_0 */
1578 0x148, /* SATA_MSI_EN_VEC2_0 */
1579 0x14C, /* SATA_MSI_EN_VEC3_0 */
1580 0x150, /* SATA_MSI_EN_VEC4_0 */
1581 0x154, /* SATA_MSI_EN_VEC5_0 */
1582 0x158, /* SATA_MSI_EN_VEC6_0 */
1583 0x15C, /* SATA_MSI_EN_VEC7_0 */
1584 0x180, /* SATA_CONFIGURATION_0 */
1585 0x184, /* SATA_FPCI_ERROR_MASKS_0 */
1586 0x188, /* SATA_INTR_MASK_0 */
1587 0x1A0, /* SATA_CFG_REVID_0 */
1588 0x198, /* SATA_IPFS_INTR_ENABLE_0 */
1589 0x1BC, /* SATA_CLKGATE_HYSTERSIS_0 */
1590 0x1DC /* SATA_SATA_MCCIF_FIFOCTRL_0 */
1593 static void tegra_ahci_save_regs(u32 **save_addr,
1599 u32 *dest = *save_addr;
1600 void __iomem *base = IO_ADDRESS(reg_base);
1602 for (i = 0; i < regs; ++i, ++dest) {
1603 *dest = readl(base + (u32)reg_array[i]);
1604 AHCI_DBG_PRINT("save: [0x%x]=0x%08x\n",
1605 (reg_base+(u32)reg_array[i]), *dest);
1610 static void tegra_ahci_restore_regs(void **save_addr,
1616 u32 *src = *save_addr;
1617 void __iomem *base = IO_ADDRESS(reg_base);
1619 for (i = 0; i < regs; ++i, ++src) {
1620 writel(*src, base + (u32)reg_array[i]);
1621 AHCI_DBG_PRINT("restore: [0x%x]=0x%08x\n",
1622 (reg_base+(u32)reg_array[i]), *src);
1627 static void tegra_ahci_pg_save_registers(struct ata_host *host)
1629 struct tegra_ahci_host_priv *tegra_hpriv;
1634 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1635 pg_save = tegra_hpriv->pg_save;
1638 * Driver should save/restore the registers in the order of
1639 * IPFS, CFG, Ext CFG, BAR5.
1642 /* save IPFS registers */
1643 regs = ARRAY_SIZE(pg_save_ipfs_registers);
1644 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BASE,
1645 pg_save_ipfs_registers, regs);
1646 /* after the call, pg_save should point to the next address to save */
1648 /* save CONFIG registers */
1649 regs = ARRAY_SIZE(pg_save_config_registers);
1650 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1651 pg_save_config_registers, regs);
1653 /* save CONFIG per port registers */
1654 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1655 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1656 regs = ARRAY_SIZE(pg_save_config_port_registers);
1657 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1658 pg_save_config_port_registers, regs);
1660 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1662 /* save BAR5 registers */
1663 regs = ARRAY_SIZE(pg_save_bar5_registers);
1664 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1665 pg_save_bar5_registers, regs);
1667 /* save BAR5 port_registers */
1668 regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1669 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1670 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1671 pg_save_bar5_port_registers, regs);
1673 /* save bkdr registers */
1674 regs = ARRAY_SIZE(pg_save_bar5_bkdr_registers);
1675 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1676 pg_save_bar5_bkdr_registers, regs);
1678 /* and save bkdr per_port registers */
1679 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1680 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1681 regs = ARRAY_SIZE(pg_save_bar5_bkdr_port_registers);
1682 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1683 pg_save_bar5_bkdr_port_registers,
1686 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1689 static void tegra_ahci_pg_restore_registers(struct ata_host *host)
1691 struct tegra_ahci_host_priv *tegra_hpriv;
1696 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1697 pg_save = tegra_hpriv->pg_save;
1700 * Driver should restore the registers in the order of
1701 * IPFS, CFG, Ext CFG, BAR5.
1704 /* restore IPFS registers */
1705 regs = ARRAY_SIZE(pg_save_ipfs_registers);
1706 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BASE,
1707 pg_save_ipfs_registers, regs);
1708 /* after the call, pg_save should point to the next addr to restore */
1710 /* restore CONFIG registers */
1711 regs = ARRAY_SIZE(pg_save_config_registers);
1712 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1713 pg_save_config_registers, regs);
1715 /* restore CONFIG per port registers */
1716 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1717 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1718 regs = ARRAY_SIZE(pg_save_config_port_registers);
1719 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1720 pg_save_config_port_registers,
1723 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1725 /* restore BAR5 registers */
1726 regs = ARRAY_SIZE(pg_save_bar5_registers);
1727 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1728 pg_save_bar5_registers, regs);
1730 /* restore BAR5 port_registers */
1731 regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1732 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1733 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE+(0x80*i),
1734 pg_save_bar5_port_registers, regs);
1736 /* restore bkdr registers */
1737 regs = ARRAY_SIZE(pg_restore_bar5_bkdr_registers);
1738 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1739 pg_restore_bar5_bkdr_registers, regs);
1741 /* and restore BAR5 bkdr per_port registers */
1742 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1743 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1744 regs = ARRAY_SIZE(pg_restore_bar5_bkdr_port_registers);
1745 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1746 pg_restore_bar5_bkdr_port_registers,
1749 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1751 /* program class code and programming interface for AHCI */
1752 val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1753 val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1754 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1755 scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
1756 val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1757 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1760 static u32 tegra_ahci_port_error(struct ata_port *ap)
1762 void __iomem *port_mmio = ahci_port_base(ap);
1765 err_status = readl(port_mmio + PORT_IRQ_STAT);
1766 /* excludes PhyRdy and Connect Change status */
1767 err_status &= (PORT_IRQ_ERROR & (~(PORT_IRQ_PHYRDY|PORT_IRQ_CONNECT)));
1771 static bool tegra_ahci_check_errors(struct ata_host *host)
1773 struct ata_port *ap;
1776 for (i = 0; i < host->n_ports; i++) {
1777 ap = host->ports[i];
1778 err = tegra_ahci_port_error(ap);
1781 "pg-chk-err = 0x%08x on port %d\n", err, i);
1788 void tegra_ahci_iddqlane_config(void)
1793 /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
1794 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1795 val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
1796 val |= IDDQ2LANE_SLUMBER_DLY_3MS;
1797 clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
1799 /* wait for delay of IDDQ2LAND_SLUMBER_DLY */
1800 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1801 dat = (val & IDDQ2LANE_SLUMBER_DLY_MASK) >> IDDQ2LANE_SLUMBER_DLY_SHIFT;
1805 void tegra_ahci_put_sata_in_iddq()
1811 * Hw wake up is not needed:
1812 * Driver/RM shall place the SATA PHY and SATA PADPLL in IDDQ.
1813 * SATA_PADPLL_RESET_SWCTL =1
1814 * SATA_PADPLL_RESET_OVERRIDE_VALUE=1
1815 * SATA_PADPHY_IDDQ_SWCTL=1
1816 * SATA_PADPHY_IDDQ_OVERRIDE_VALUE=1
1819 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1820 val &= ~(PADPLL_RESET_SWCTL_MASK | PADPLL_RESET_OVERRIDE_VALUE_MASK);
1821 val |= (PADPLL_RESET_SWCTL_ON | PADPLL_RESET_OVERRIDE_VALUE_ON);
1822 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1824 /* Wait for time specified in SATA_LANE_IDDQ2_PADPLL_IDDQ */
1825 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1826 dat = (val & IDDQ2LANE_IDDQ_DLY_MASK) >> IDDQ2LANE_IDDQ_DLY_SHIFT;
1829 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1830 val |= (PLL_PWR_OVRD_MASK | PLL_IDDQ_MASK | PLL_RST_MASK);
1831 xusb_writel(val, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1834 void tegra_ahci_clr_clk_rst_cnt_rst_dev(void)
1838 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_V_CLR_0);
1839 val |= (SWR_SATA_OOB_RST | SWR_SATA_RST);
1840 clk_writel(val, CLK_RST_CONTROLLER_RST_DEV_V_CLR_0);
1842 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_W_CLR_0);
1843 val |= SWR_SATACOLD_RST;
1844 clk_writel(val, CLK_RST_CONTROLLER_RST_DEV_W_CLR_0);
1847 void tegra_ahci_set_clk_rst_cnt_rst_dev(void)
1852 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_V_CLR_0);
1853 val &= ~(SWR_SATA_OOB_RST | SWR_SATA_RST);
1854 clk_writel(val, CLK_RST_CONTROLLER_RST_DEV_V_CLR_0);
1856 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_W_CLR_0);
1857 val &= ~SWR_SATACOLD_RST;
1858 clk_writel(val, CLK_RST_CONTROLLER_RST_DEV_W_CLR_0);
1862 static void tegra_ahci_pad_config(void)
1866 /* clear SW control of SATA PADPLL, SATA PHY and PLLE */
1868 /* for SATA PHY IDDQ */
1869 val = xusb_readl(XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
1870 val &= ~(IDDQ_OVRD_MASK | IDDQ_MASK);
1871 xusb_writel(val, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
1873 /* for SATA PADPLL IDDQ */
1874 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1875 val &= ~(PLL_PWR_OVRD_MASK | PLL_IDDQ_MASK | PLL_RST_MASK);
1876 xusb_writel(val, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
1878 /* PLLE related stuff*/
1880 val = clk_readl(CLK_RST_CONTROLLER_PLLE_MISC_0);
1881 val &= ~(T124_PLLE_IDDQ_SWCTL_MASK | PLLE_IDDQ_OVERRIDE_VALUE_MASK);
1882 clk_writel(val, CLK_RST_CONTROLLER_PLLE_MISC_0);
1884 clk_writel(CLK_RST_CONTROLLER_PLLE_MISC_0_VALUE,
1885 CLK_RST_CONTROLLER_PLLE_MISC_0);
1887 val = clk_readl(CLK_RST_CONTROLLER_PLLE_BASE_0);
1889 clk_writel(val, CLK_RST_CONTROLLER_PLLE_BASE_0);
1893 static void tegra_ahci_abort_power_gate(struct ata_host *host)
1896 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1897 val &= ~PG_INFO_MASK;
1898 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1901 static bool tegra_ahci_power_gate(struct ata_host *host)
1905 struct tegra_ahci_host_priv *tegra_hpriv;
1908 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1910 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1911 val &= ~PG_INFO_MASK;
1913 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1915 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
1916 tegra_ahci_pg_save_registers(host);
1918 val = xusb_readl(XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
1919 val |= XUSB_PADCTL_IOPHY_MISC_IDDQ |
1920 XUSB_PADCTL_IOPHY_MISC_IDDQ_OVRD;
1921 xusb_writel(val, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
1924 * Read SATA_AUX_MISC_CNTL_1_0 register L0_RX_IDLE_T_SAX field and
1925 * write that value into same register L0_RX_IDLE_T_NPG field.
1926 * And write 1 to L0_RX_IDLE_T_MUX field.
1928 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1930 dat &= L0_RX_IDLE_T_SAX_MASK;
1931 dat >>= L0_RX_IDLE_T_SAX_SHIFT;
1932 dat <<= L0_RX_IDLE_T_NPG_SHIFT;
1933 val &= ~L0_RX_IDLE_T_NPG_MASK;
1935 val |= L0_RX_IDLE_T_MUX_FROM_APB_MISC;
1936 val |= DEVSLP_OVERRIDE;
1937 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1939 tegra_ahci_set_clk_rst_cnt_rst_dev();
1941 /* abort PG if there are errors occurred */
1942 if (tegra_ahci_check_errors(host)) {
1943 dev_err(host->dev, "** pg: errors; abort power gating **\n");
1946 /* make sure all ports have no outstanding commands and are idle. */
1947 if (!tegra_ahci_are_all_ports_idle(host)) {
1948 dev_err(host->dev, "** pg: cmds; abort power gating **\n");
1951 tegra_ahci_put_sata_in_iddq();
1953 val = pmc_readl(APBDEV_PMC_PWRGATE_TOGGLE_0);
1954 val |= PARTID_VALUE;
1956 pmc_writel(val, APBDEV_PMC_PWRGATE_TOGGLE_0);
1958 val = pmc_readl(APBDEV_PMC_PWRGATE_STATUS_0);
1960 pmc_writel(val, APBDEV_PMC_PWRGATE_STATUS_0);
1962 /* power off the sata */
1963 status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
1965 dev_err(host->dev, "** failed to turn-off SATA (0x%x) **\n",
1973 static bool tegra_ahci_power_un_gate(struct ata_host *host)
1977 struct tegra_ahci_host_priv *tegra_hpriv;
1980 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1982 tegra_ahci_iddqlane_config();
1984 val = pmc_readl(APBDEV_PMC_PWRGATE_TOGGLE_0);
1985 val |= PARTID_VALUE;
1987 pmc_writel(val, APBDEV_PMC_PWRGATE_TOGGLE_0);
1989 val = pmc_readl(APBDEV_PMC_PWRGATE_STATUS_0);
1991 pmc_writel(val, APBDEV_PMC_PWRGATE_STATUS_0);
1993 status = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
1995 dev_err(host->dev, "** failed to turn-on SATA (0x%x) **\n",
2000 /* deasset PADPLL and wait until it locks. */
2001 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2002 val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
2003 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2005 tegra_ahci_clr_clk_rst_cnt_rst_dev();
2007 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
2008 /* restore registers */
2009 tegra_ahci_pg_restore_registers(host);
2011 tegra_ahci_pad_config();
2014 * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
2020 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
2021 if (val & LOCKDET_FIELD)
2025 pr_err("%s: SATA_PAD_PLL is not locked in 15us.\n", __func__);
2028 * During the restoration of the registers, the driver would now need to
2029 * restore the register T_SATA0_CFG_POWER_GATE_SSTS_RESTORED after the
2030 * ssts_det, ssts_spd are restored. This register is used to tell the
2031 * controller whether a drive existed earlier or not and move the PHY
2032 * state machines into either HR_slumber or not.
2034 val = scfg_readl(T_SATA0_CFG_POWER_GATE);
2035 val &= ~POWER_GATE_SSTS_RESTORED_MASK;
2036 val |= POWER_GATE_SSTS_RESTORED_YES;
2037 scfg_writel(val, T_SATA0_CFG_POWER_GATE);
2041 * Driver needs to switch the rx_idle_t driven source back to from
2042 * Sata controller after SAX is power-ungated.
2044 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
2045 val &= ~DEVSLP_OVERRIDE;
2046 val &= ~L0_RX_IDLE_T_MUX_MASK;
2047 val |= L0_RX_IDLE_T_MUX_FROM_SATA;
2048 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
2050 /* Set the bits in the CAR to allow HW based low power sequencing. */
2051 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2052 val &= ~PADPLL_RESET_SWCTL_MASK;
2053 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2056 * power un-gating process is complete by clearing
2057 * APBDEV_PMC_SATA_PWRGT_0.Pmc2sata_pg_info = 0
2059 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
2060 val &= ~PG_INFO_MASK;
2061 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
2066 static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap)
2068 void __iomem *port_mmio = ahci_port_base(ap);
2070 if (readl(port_mmio + PORT_CMD_ISSUE) ||
2071 readl(port_mmio + PORT_SCR_ACT))
2072 return PORT_IS_NOT_IDLE;
2073 return PORT_IS_IDLE;
2076 /* check if all supported ports are idle (no outstanding commands) */
2077 static bool tegra_ahci_are_all_ports_idle(struct ata_host *host)
2079 struct ata_port *ap;
2081 for (i = 0; i < host->n_ports; i++) {
2082 ap = host->ports[i];
2083 if (ap && (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE))
2089 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2090 static void tegra_ahci_abort_pad_suspend(struct ata_host *host)
2092 /*No implementation*/
2095 static bool tegra_ahci_pad_suspend(struct ata_host *host)
2098 struct tegra_ahci_host_priv *tegra_hpriv;
2100 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
2102 /* Set the bits in the CAR to allow HW based low power sequencing. */
2103 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2104 val |= PADPLL_RESET_SWCTL_MASK;
2105 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2107 val = xusb_readl(XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
2108 val |= XUSB_PADCTL_IOPHY_MISC_IDDQ |
2109 XUSB_PADCTL_IOPHY_MISC_IDDQ_OVRD;
2110 xusb_writel(val, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_1_0);
2112 /* abort PG if there are errors occurred */
2113 if (tegra_ahci_check_errors(host)) {
2114 dev_err(host->dev, "** pg: errors; abort power gating **\n");
2117 /* make sure all ports have no outstanding commands and are idle. */
2118 if (!tegra_ahci_are_all_ports_idle(host)) {
2119 dev_err(host->dev, "** pg: cmds; abort power gating **\n");
2122 tegra_ahci_put_sata_in_iddq();
2124 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2125 val |= (SATA_SEQ_PADPLL_PD_INPUT_VALUE |
2126 SATA_SEQ_LANE_PD_INPUT_VALUE | SATA_SEQ_RESET_INPUT_VALUE);
2127 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2129 tegra_first_level_clk_gate();
2134 static bool tegra_ahci_pad_resume(struct ata_host *host)
2138 struct tegra_ahci_host_priv *tegra_hpriv;
2140 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
2142 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2143 val &= ~(SATA_SEQ_PADPLL_PD_INPUT_VALUE |
2144 SATA_SEQ_LANE_PD_INPUT_VALUE | SATA_SEQ_RESET_INPUT_VALUE);
2145 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2147 if (tegra_first_level_clk_ungate() < 0) {
2148 pr_err("%s: flcg ungate failed\n", __func__);
2152 tegra_ahci_iddqlane_config();
2154 /* deasset PADPLL and wait until it locks. */
2155 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2156 val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
2157 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2159 tegra_ahci_pad_config();
2162 * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
2168 val = xusb_readl(XUSB_PADCTL_IOPHY_PLL_S0_CTL1_0);
2169 if (val & LOCKDET_FIELD)
2173 pr_err("%s: SATA_PAD_PLL is not locked in 15us.\n", __func__);
2175 /* Set the bits in the CAR to allow HW based low power sequencing. */
2176 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
2177 val &= ~PADPLL_RESET_SWCTL_MASK;
2178 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
2183 static void tegra_ahci_to_add_idle_timer(struct ata_host *host)
2185 struct tegra_ahci_host_priv *tegra_hpriv;
2187 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
2189 /* note: the routine is called from interrupt context */
2190 spin_lock(&host->lock);
2191 /* start idle-timer if all ports have no outstanding commands */
2192 if (tegra_ahci_are_all_ports_idle(host)) {
2193 /* adjust tegra_ahci_idle_time to minimum if it is too small */
2194 tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
2195 tegra_ahci_idle_time);
2196 tegra_hpriv->idle_timer.expires =
2197 ata_deadline(jiffies, tegra_ahci_idle_time);
2198 mod_timer(&tegra_hpriv->idle_timer,
2199 tegra_hpriv->idle_timer.expires);
2201 spin_unlock(&host->lock);
2204 static void tegra_ahci_idle_timer(unsigned long arg)
2206 struct ata_host *host = (void *)arg;
2207 struct tegra_ahci_host_priv *tegra_hpriv;
2208 unsigned long flags;
2210 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
2212 spin_lock_irqsave(&host->lock, flags);
2213 if (tegra_hpriv->pg_state == SATA_ON)
2214 tegra_hpriv->pg_state = SATA_GOING_OFF;
2216 dev_err(host->dev, "idle_timer: bad state (%u)\n",
2217 tegra_hpriv->pg_state);
2219 spin_unlock_irqrestore(&host->lock, flags);
2222 spin_unlock_irqrestore(&host->lock, flags);
2223 tegra_ahci_runtime_suspend(tegra_hpriv->dev);
2226 static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
2227 struct ata_queued_cmd *qc)
2229 struct tegra_qc_list *qc_list;
2231 qc_list = kmalloc(sizeof(struct tegra_qc_list), GFP_ATOMIC);
2233 dev_err(tegra_hpriv->dev, "failed to alloc qc_list\n");
2234 return AC_ERR_SYSTEM;
2237 list_add_tail(&(qc_list->list), &(tegra_hpriv->qc_list));
2241 static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv)
2243 struct list_head *list, *next;
2244 struct tegra_qc_list *qc_list;
2245 struct ata_queued_cmd *qc;
2247 /* now qc_issue all qcs in the qc_list */
2248 list_for_each_safe(list, next, &tegra_hpriv->qc_list) {
2249 qc_list = list_entry(list, struct tegra_qc_list, list);
2251 ahci_ops.qc_issue(qc);
2257 static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc)
2259 struct ata_port *ap = qc->ap;
2260 struct ata_host *host = ap->host;
2261 struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
2263 /* stop the idle timer */
2264 if (timer_pending(&tegra_hpriv->idle_timer))
2265 del_timer_sync(&tegra_hpriv->idle_timer);
2267 /* note: host->lock is locked */
2268 switch (tegra_hpriv->pg_state) {
2270 /* normal case, issue the qc */
2271 return ahci_ops.qc_issue(qc);
2272 case SATA_GOING_OFF:
2273 case SATA_ABORT_OFF:
2274 /* SATA is going OFF, let's abort the suspend */
2275 dev_dbg(host->dev, "** qc_issue: going OFF **\n");
2276 tegra_hpriv->pg_state = SATA_ABORT_OFF;
2277 return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
2279 dev_dbg(host->dev, "** qc_issue: request power-up sata **\n");
2280 queue_work(tegra_ahci_work_q, &tegra_ahci_work);
2281 tegra_hpriv->pg_state = SATA_GOING_ON;
2282 /* continue with the following code to queue the qc */
2284 return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
2286 dev_err(host->dev, "** qc_issue: bad state (%u) **\n",
2287 tegra_hpriv->pg_state);
2289 return AC_ERR_SYSTEM;
2293 static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
2294 unsigned long deadline)
2296 struct ata_port *ap = link->ap;
2297 struct ata_host *host = ap->host;
2298 struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
2299 unsigned long flags;
2302 if (tegra_hpriv->pg_state == SATA_OFF) {
2303 dev_dbg(host->dev, "** hreset: request power-up sata **\n");
2304 spin_lock_irqsave(&host->lock, flags);
2305 rc = tegra_ahci_runtime_resume(tegra_hpriv->dev);
2306 spin_unlock_irqrestore(&host->lock, flags);
2307 /* rc == 0 means the request has been run successfully */
2309 dev_err(host->dev, "** hreset: rt_get()=%d **\n", rc);
2311 return AC_ERR_SYSTEM;
2313 tegra_hpriv->pg_state = SATA_ON;
2316 return ahci_ops.hardreset(link, class, deadline);
2319 static irqreturn_t tegra_ahci_interrupt(int irq, void *dev_instance)
2321 irqreturn_t irq_retval;
2324 val = misc_readl(SATA_AUX_RX_STAT_INT_0);
2325 if (!(val && SATA_RX_STAT_INT_DISABLE)) {
2326 val |= SATA_RX_STAT_INT_DISABLE;
2327 misc_writel(val, SATA_AUX_RX_STAT_INT_0);
2330 irq_retval = ahci_interrupt(irq, dev_instance);
2331 if (irq_retval == IRQ_NONE)
2335 tegra_ahci_to_add_idle_timer((struct ata_host *)dev_instance);
2343 static int tegra_ahci_remove_one(struct platform_device *pdev)
2345 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2346 struct ahci_host_priv *hpriv;
2348 BUG_ON(host == NULL);
2349 BUG_ON(host->iomap[AHCI_PCI_BAR] == NULL);
2350 hpriv = host->private_data;
2352 tegra_ahci_controller_remove(pdev);
2354 devm_iounmap(&pdev->dev, host->iomap[AHCI_PCI_BAR]);
2355 ata_host_detach(host);
2357 #ifdef TEGRA_AHCI_CONTEXT_RESTORE
2358 /* Free PG save/restore area */
2359 devm_kfree(&pdev->dev, ((struct tegra_ahci_host_priv *)hpriv)->pg_save);
2362 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2363 cancel_work_sync(&tegra_ahci_work);
2364 if (tegra_ahci_work_q)
2365 destroy_workqueue(tegra_ahci_work_q);
2368 devm_kfree(&pdev->dev, hpriv);
2372 void tegra_ahci_sata_clk_gate(void)
2376 if (!tegra_platform_is_silicon())
2379 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_W_SET);
2380 if (val & SET_CEC_RESET)
2381 clk_writel(0x108, CLK_RST_CONTROLLER_RST_DEV_V_SET);
2382 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_W_SET);
2383 while (val & SET_CEC_RESET)
2384 val = clk_readl(CLK_RST_CONTROLLER_RST_DEV_W_SET);
2387 static int tegra_ahci_init_one(struct platform_device *pdev)
2389 struct device_node *np = pdev->dev.of_node;
2390 struct ata_port_info pi = ahci_port_info;
2391 const struct ata_port_info *ppi[] = { &pi, NULL };
2392 struct device *dev = &pdev->dev;
2393 struct ahci_host_priv *hpriv = NULL;
2394 struct tegra_ahci_host_priv *tegra_hpriv;
2395 struct tegra_ahci_platform_data *ahci_pdata;
2396 struct ata_host *host = NULL;
2397 int n_ports, i, rc = 0;
2398 struct resource *res, *irq_res;
2401 #if defined(TEGRA_AHCI_CONTEXT_RESTORE)
2404 irq_handler_t irq_handler = ahci_interrupt;
2408 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2410 ata_print_version_once(&pdev->dev, DRV_VERSION);
2412 /* Simple resource validation */
2413 if (pdev->num_resources != 3) {
2414 dev_err(dev, "invalid number of resources\n");
2415 dev_err(dev, "not enough SATA resources\n");
2419 /* acquire bar resources */
2420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2424 /* acquire IRQ resource */
2425 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2426 if (irq_res == NULL)
2428 if (irq_res->start <= 0)
2431 /* allocate sizeof tegra_ahci_host_priv, which contains extra fields */
2432 hpriv = devm_kzalloc(dev, sizeof(struct tegra_ahci_host_priv),
2439 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2440 tegra_ahci_work_q = alloc_workqueue("tegra_ahci_work_q",
2441 WQ_HIGHPRI | WQ_UNBOUND, 16);
2442 if (!tegra_ahci_work_q) {
2443 dev_err(dev, "TEGRA WORKQUEUE SATA init failed\n");
2448 hpriv->flags |= (unsigned long)pi.private_data;
2449 tegra_hpriv = (struct tegra_ahci_host_priv *)hpriv;
2450 tegra_hpriv->dev = dev;
2452 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
2453 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
2454 tegra_hpriv->pexp_gpio =
2455 of_get_named_gpio(np, "nvidia,pexp-gpio", 0);
2456 if (!of_property_read_bool(np, "nvidia,enable-sata-port")) {
2457 dev_err(dev, "Not able to find enable-sata-port property\n");
2458 tegra_ahci_sata_clk_gate();
2462 ahci_pdata = tegra_hpriv->dev->platform_data;
2463 tegra_hpriv->pexp_gpio = ahci_pdata->pexp_gpio;
2465 g_tegra_hpriv = tegra_hpriv;
2467 /* Call tegra init routine */
2468 rc = tegra_ahci_controller_init(tegra_hpriv, 0);
2470 dev_err(dev, "TEGRA SATA init failed\n");
2475 * We reserve a table of 6 BARs in tegra_hpriv to store BARs.
2476 * Save the mapped AHCI_PCI_BAR address to the table.
2478 mmio = devm_ioremap(dev, res->start, (res->end-res->start+1));
2479 tegra_hpriv->bars_table[AHCI_PCI_BAR] = mmio;
2482 /* save initial config */
2483 tegra_ahci_save_initial_config(pdev, hpriv);
2484 dev_dbg(dev, "past save init config\n");
2487 if (hpriv->cap & HOST_CAP_NCQ) {
2488 pi.flags |= ATA_FLAG_NCQ;
2489 pi.flags |= ATA_FLAG_FPDMA_AA;
2493 * CAP.NP sometimes indicate the index of the last enabled
2494 * port, at other times, that of the last possible port, so
2495 * determining the maximum port number requires looking at
2496 * both CAP.NP and port_map.
2498 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2499 host = ata_host_alloc_pinfo(dev, ppi, n_ports);
2504 host->private_data = hpriv;
2505 tegra_hpriv->host = host;
2506 host->iomap = tegra_hpriv->bars_table;
2508 if (!(hpriv->cap & HOST_CAP_SSS))
2509 host->flags |= ATA_HOST_PARALLEL_SCAN;
2511 pr_info("ahci: SSS flag set, parallel bus scan disabled\n");
2513 for (i = 0; i < host->n_ports; i++) {
2514 struct ata_port *ap = host->ports[i];
2516 /* set initial link pm policy */
2517 ap->target_lpm_policy = ATA_LPM_UNKNOWN;
2519 /* disabled/not-implemented port */
2520 if (!(hpriv->port_map & (1 << i)))
2521 ap->ops = &ata_dummy_port_ops;
2523 ap->target_lpm_policy = ATA_LPM_MIN_POWER;
2526 rc = ahci_reset_controller(host);
2528 dev_err(dev, "Reset controller failed! (rc=%d)\n", rc);
2532 ahci_init_controller(host);
2533 ahci_print_info(host, "TEGRA-SATA");
2534 dev_dbg(dev, "controller init okay\n");
2536 #if defined(TEGRA_AHCI_CONTEXT_RESTORE)
2537 /* Setup PG save/restore area: */
2539 /* calculate the size */
2540 save_size = ARRAY_SIZE(pg_save_ipfs_registers) +
2541 ARRAY_SIZE(pg_save_config_registers) +
2542 ARRAY_SIZE(pg_save_bar5_registers) +
2543 ARRAY_SIZE(pg_save_bar5_bkdr_registers);
2545 /* and add save port_registers for all the ports */
2546 save_size += TEGRA_AHCI_NUM_PORTS *
2547 (ARRAY_SIZE(pg_save_config_port_registers) +
2548 ARRAY_SIZE(pg_save_bar5_port_registers) +
2549 ARRAY_SIZE(pg_save_bar5_bkdr_port_registers));
2552 * save_size is number of registers times number of bytes per
2553 * register to get total save size.
2555 save_size *= sizeof(u32);
2556 tegra_hpriv->pg_save = devm_kzalloc(dev, save_size, GFP_KERNEL);
2557 if (!tegra_hpriv->pg_save) {
2563 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2564 tegra_hpriv->pg_state = SATA_ON;
2566 /* setup sata idle timer */
2567 init_timer_deferrable(&tegra_hpriv->idle_timer);
2568 tegra_hpriv->idle_timer.function = tegra_ahci_idle_timer;
2569 tegra_hpriv->idle_timer.data = (unsigned long)host;
2571 INIT_LIST_HEAD(&tegra_hpriv->qc_list);
2573 /* use our own irq handler */
2574 irq_handler = tegra_ahci_interrupt;
2579 rc = ata_host_activate(host, irq_res->start, irq_handler, 0, &ahci_sht);
2585 if (host->iomap[AHCI_PCI_BAR])
2586 devm_iounmap(dev, host->iomap[AHCI_PCI_BAR]);
2587 ata_host_detach(host);
2590 devm_kfree(dev, hpriv);
2592 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2593 if (tegra_ahci_work_q)
2594 destroy_workqueue(tegra_ahci_work_q);
2600 static int __init ahci_init(void)
2602 return platform_driver_register(&tegra_platform_ahci_driver);
2605 static void __exit ahci_exit(void)
2607 platform_driver_unregister(&tegra_platform_ahci_driver);
2610 #ifdef CONFIG_DEBUG_FS
2612 #include <linux/debugfs.h>
2613 #include <linux/seq_file.h>
2615 static void dbg_ahci_dump_regs(struct seq_file *s, u32 *ptr, u32 base, u32 regs)
2617 #define REGS_PER_LINE 4
2620 u32 lines = regs / REGS_PER_LINE;
2622 for (i = 0; i < lines; i++) {
2623 seq_printf(s, "0x%08x: ", base+(i*16));
2624 for (j = 0; j < REGS_PER_LINE; ++j) {
2625 seq_printf(s, "0x%08x ", readl(ptr));
2630 #undef REGS_PER_LINE
2633 static int dbg_ahci_dump_show(struct seq_file *s, void *unused)
2639 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2641 tegra_ahci_runtime_resume(g_tegra_hpriv->dev);
2646 base = TEGRA_SATA_CONFIG_BASE;
2647 ptr = (u32 *)IO_TO_VIRT(base);
2648 seq_puts(s, "SATA CONFIG Registers:\n");
2649 seq_puts(s, "----------------------\n");
2650 dbg_ahci_dump_regs(s, ptr, base, 0x200);
2652 base = TEGRA_SATA_BAR5_BASE;
2653 ptr = (u32 *)IO_TO_VIRT(base);
2654 seq_puts(s, "\nAHCI HBA Registers:\n");
2655 seq_puts(s, "-------------------\n");
2656 dbg_ahci_dump_regs(s, ptr, base, 64);
2658 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
2659 base = TEGRA_SATA_BAR5_BASE + 0x100 + (0x80*i);
2660 ptr = (u32 *)IO_TO_VIRT(base);
2661 seq_printf(s, "\nPort %u Registers:\n", i);
2662 seq_puts(s, "---------------\n");
2663 dbg_ahci_dump_regs(s, ptr, base, 20);
2666 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2667 /* adjust tegra_ahci_idle_time to minimum if it is too small */
2668 tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
2669 tegra_ahci_idle_time);
2670 seq_printf(s, "\nIdle Timeout = %u milli-seconds.\n",
2671 tegra_ahci_idle_time);
2674 if (tegra_powergate_is_powered(TEGRA_POWERGATE_SATA))
2675 seq_puts(s, "\n=== SATA controller is powered on ===\n\n");
2677 seq_puts(s, "\n=== SATA controller is powered off ===\n\n");
2678 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2679 tegra_ahci_runtime_suspend(g_tegra_hpriv->dev);
2686 static int dbg_ahci_dump_open(struct inode *inode, struct file *file)
2688 return single_open(file, dbg_ahci_dump_show, &inode->i_private);
2691 static const struct file_operations debug_fops = {
2692 .open = dbg_ahci_dump_open,
2694 .llseek = seq_lseek,
2695 .release = single_release,
2698 static int __init tegra_ahci_dump_debuginit(void)
2700 (void) debugfs_create_file("tegra_ahci", S_IRUGO,
2701 NULL, NULL, &debug_fops);
2702 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2703 (void) debugfs_create_u32("tegra_ahci_idle_ms", S_IRUGO | S_IXUGO
2704 | S_IWUSR | S_IWGRP,
2705 NULL, &tegra_ahci_idle_time);
2709 late_initcall(tegra_ahci_dump_debuginit);
2712 MODULE_AUTHOR("NVIDIA");
2713 MODULE_DESCRIPTION("Tegra AHCI SATA low-level driver");
2714 MODULE_LICENSE("GPL v2");
2715 MODULE_VERSION(DRV_VERSION);
2717 module_init(ahci_init);
2718 module_exit(ahci_exit);