2 * drivers/misc/tegra-profiler/hrt.c
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/sched.h>
20 #include <linux/hrtimer.h>
21 #include <linux/slab.h>
22 #include <linux/cpu.h>
23 #include <linux/ptrace.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/nsproxy.h>
28 #include <asm/cputype.h>
29 #include <asm/irq_regs.h>
31 #include <linux/tegra_profiler.h>
38 #include "power_clk.h"
42 static struct quadd_hrt_ctx hrt;
45 read_all_sources(struct pt_regs *regs, struct task_struct *task);
47 struct hrt_event_value {
52 static enum hrtimer_restart hrtimer_handler(struct hrtimer *hrtimer)
56 regs = get_irq_regs();
59 return HRTIMER_NORESTART;
61 qm_debug_handler_sample(regs);
64 read_all_sources(regs, NULL);
66 hrtimer_forward_now(hrtimer, ns_to_ktime(hrt.sample_period));
67 qm_debug_timer_forward(regs, hrt.sample_period);
69 return HRTIMER_RESTART;
72 static void start_hrtimer(struct quadd_cpu_context *cpu_ctx)
74 u64 period = hrt.sample_period;
76 __hrtimer_start_range_ns(&cpu_ctx->hrtimer,
77 ns_to_ktime(period), 0,
78 HRTIMER_MODE_REL_PINNED, 0);
79 qm_debug_timer_start(NULL, period);
82 static void cancel_hrtimer(struct quadd_cpu_context *cpu_ctx)
84 hrtimer_cancel(&cpu_ctx->hrtimer);
85 qm_debug_timer_cancel();
88 static void init_hrtimer(struct quadd_cpu_context *cpu_ctx)
90 hrtimer_init(&cpu_ctx->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
91 cpu_ctx->hrtimer.function = hrtimer_handler;
94 u64 quadd_get_time(void)
98 do_posix_clock_monotonic_gettime(&ts);
99 return timespec_to_ns(&ts);
102 static void put_header(void)
104 int nr_events = 0, max_events = QUADD_MAX_COUNTERS;
105 int events[QUADD_MAX_COUNTERS];
106 struct quadd_record_data record;
107 struct quadd_header_data *hdr = &record.hdr;
108 struct quadd_parameters *param = &hrt.quadd_ctx->param;
109 unsigned int extra = param->reserved[QUADD_PARAM_IDX_EXTRA];
110 struct quadd_iovec vec;
111 struct quadd_ctx *ctx = hrt.quadd_ctx;
112 struct quadd_event_source_interface *pmu = ctx->pmu;
113 struct quadd_event_source_interface *pl310 = ctx->pl310;
115 record.record_type = QUADD_RECORD_TYPE_HEADER;
117 hdr->magic = QUADD_HEADER_MAGIC;
118 hdr->version = QUADD_SAMPLES_VERSION;
120 hdr->backtrace = param->backtrace;
121 hdr->use_freq = param->use_freq;
122 hdr->system_wide = param->system_wide;
124 /* TODO: dynamically */
125 #ifdef QM_DEBUG_SAMPLES_ENABLE
126 hdr->debug_samples = 1;
128 hdr->debug_samples = 0;
131 hdr->freq = param->freq;
132 hdr->ma_freq = param->ma_freq;
133 hdr->power_rate_freq = param->power_rate_freq;
135 hdr->power_rate = hdr->power_rate_freq > 0 ? 1 : 0;
136 hdr->get_mmap = (extra & QUADD_PARAM_EXTRA_GET_MMAP) ? 1 : 0;
139 hdr->extra_length = 0;
142 nr_events += pmu->get_current_events(events, max_events);
145 nr_events += pl310->get_current_events(events + nr_events,
146 max_events - nr_events);
148 hdr->nr_events = nr_events;
151 vec.len = nr_events * sizeof(events[0]);
153 quadd_put_sample(&record, &vec, 1);
156 void quadd_put_sample(struct quadd_record_data *data,
157 struct quadd_iovec *vec, int vec_count)
159 struct quadd_comm_data_interface *comm = hrt.quadd_ctx->comm;
161 comm->put_sample(data, vec, vec_count);
162 atomic64_inc(&hrt.counter_samples);
165 static int get_sample_data(struct quadd_sample_data *sample,
166 struct pt_regs *regs,
167 struct task_struct *task)
169 unsigned int cpu, flags;
170 struct quadd_ctx *quadd_ctx = hrt.quadd_ctx;
172 cpu = quadd_get_processor_id(regs, &flags);
176 (flags & QUADD_CPUMODE_TEGRA_POWER_CLUSTER_LP) ? 1 : 0;
177 sample->thumb_mode = (flags & QUADD_CPUMODE_THUMB) ? 1 : 0;
178 sample->user_mode = user_mode(regs) ? 1 : 0;
180 /* For security reasons, hide IPs from the kernel space. */
181 if (!sample->user_mode && !quadd_ctx->collect_kernel_ips)
184 sample->ip = instruction_pointer(regs);
186 sample->time = quadd_get_time();
187 sample->reserved = 0;
188 sample->pid = task->pid;
189 sample->in_interrupt = in_interrupt() ? 1 : 0;
194 static int read_source(struct quadd_event_source_interface *source,
195 struct pt_regs *regs,
196 struct hrt_event_value *events_vals,
200 u32 prev_val, val, res_val;
201 struct event_data events[QUADD_MAX_COUNTERS];
206 max_events = min_t(int, max_events, QUADD_MAX_COUNTERS);
207 nr_events = source->read(events, max_events);
209 for (i = 0; i < nr_events; i++) {
210 struct event_data *s = &events[i];
212 prev_val = s->prev_val;
216 res_val = val - prev_val;
218 res_val = QUADD_U32_MAX - prev_val + val;
220 if (s->event_source == QUADD_EVENT_SOURCE_PL310) {
221 int nr_active = atomic_read(&hrt.nr_active_all_core);
223 res_val /= nr_active;
226 events_vals[i].event_id = s->event_id;
227 events_vals[i].value = res_val;
234 read_all_sources(struct pt_regs *regs, struct task_struct *task)
236 u32 state, extra_data = 0;
237 int i, vec_idx = 0, bt_size = 0;
238 int nr_events = 0, nr_positive_events = 0;
239 struct pt_regs *user_regs;
240 struct quadd_iovec vec[5];
241 struct hrt_event_value events[QUADD_MAX_COUNTERS];
242 u32 events_extra[QUADD_MAX_COUNTERS];
244 struct quadd_record_data record_data;
245 struct quadd_sample_data *s = &record_data.sample;
247 struct quadd_ctx *ctx = hrt.quadd_ctx;
248 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
249 struct quadd_callchain *cc = &cpu_ctx->cc;
254 if (atomic_read(&cpu_ctx->nr_active) == 0)
261 if (!task_nsproxy(task)) {
267 if (ctx->pmu && ctx->pmu_info.active)
268 nr_events += read_source(ctx->pmu, regs,
269 events, QUADD_MAX_COUNTERS);
271 if (ctx->pl310 && ctx->pl310_info.active)
272 nr_events += read_source(ctx->pl310, regs,
274 QUADD_MAX_COUNTERS - nr_events);
282 user_regs = current_pt_regs();
284 if (get_sample_data(s, regs, task))
288 extra_data |= QUADD_SED_IP64;
290 vec[vec_idx].base = &extra_data;
291 vec[vec_idx].len = sizeof(extra_data);
295 cc->unw_method = QUADD_URC_SUCCESS;
297 if (ctx->param.backtrace) {
298 bt_size = quadd_get_user_callchain(user_regs, cc, ctx, task);
300 if (!bt_size && !user_mode(regs)) {
301 unsigned long pc = instruction_pointer(user_regs);
305 cc->cs_64 = compat_user_mode(user_regs) ? 0 : 1;
309 bt_size += quadd_callchain_store(cc, pc,
310 QUADD_UNW_TYPE_KCTX);
314 int ip_size = cc->cs_64 ? sizeof(u64) : sizeof(u32);
315 int nr_types = DIV_ROUND_UP(bt_size, 8);
317 vec[vec_idx].base = cc->cs_64 ?
318 (void *)cc->ip_64 : (void *)cc->ip_32;
319 vec[vec_idx].len = bt_size * ip_size;
322 vec[vec_idx].base = cc->types;
323 vec[vec_idx].len = nr_types * sizeof(cc->types[0]);
327 extra_data |= cc->unw_method << QUADD_SED_UNW_METHOD_SHIFT;
328 s->reserved |= cc->unw_rc << QUADD_SAMPLE_URC_SHIFT;
330 s->callchain_nr = bt_size;
332 record_data.record_type = QUADD_RECORD_TYPE_SAMPLE;
335 for (i = 0; i < nr_events; i++) {
336 u32 value = events[i].value;
338 s->events_flags |= 1 << i;
339 events_extra[nr_positive_events++] = value;
343 if (nr_positive_events == 0)
346 vec[vec_idx].base = events_extra;
347 vec[vec_idx].len = nr_positive_events * sizeof(events_extra[0]);
353 vec[vec_idx].base = &state;
354 vec[vec_idx].len = sizeof(state);
360 quadd_put_sample(&record_data, vec, vec_idx);
364 is_profile_process(struct task_struct *task)
367 pid_t pid, profile_pid;
368 struct quadd_ctx *ctx = hrt.quadd_ctx;
375 for (i = 0; i < ctx->param.nr_pids; i++) {
376 profile_pid = ctx->param.pids[i];
377 if (profile_pid == pid)
384 add_active_thread(struct quadd_cpu_context *cpu_ctx, pid_t pid, pid_t tgid)
386 struct quadd_thread_data *t_data = &cpu_ctx->active_thread;
388 if (t_data->pid > 0 ||
389 atomic_read(&cpu_ctx->nr_active) > 0) {
390 pr_warn_once("Warning for thread: %d\n", (int)pid);
399 static int remove_active_thread(struct quadd_cpu_context *cpu_ctx, pid_t pid)
401 struct quadd_thread_data *t_data = &cpu_ctx->active_thread;
406 if (t_data->pid == pid) {
412 pr_warn_once("Warning for thread: %d\n", (int)pid);
416 void __quadd_task_sched_in(struct task_struct *prev,
417 struct task_struct *task)
419 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
420 struct quadd_ctx *ctx = hrt.quadd_ctx;
421 struct event_data events[QUADD_MAX_COUNTERS];
422 /* static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 2); */
424 if (likely(!hrt.active))
427 if (__ratelimit(&ratelimit_state))
428 pr_info("sch_in, cpu: %d, prev: %u (%u) \t--> curr: %u (%u)\n",
429 smp_processor_id(), (unsigned int)prev->pid,
430 (unsigned int)prev->tgid, (unsigned int)task->pid,
431 (unsigned int)task->tgid);
434 if (is_profile_process(task)) {
435 add_active_thread(cpu_ctx, task->pid, task->tgid);
436 atomic_inc(&cpu_ctx->nr_active);
438 if (atomic_read(&cpu_ctx->nr_active) == 1) {
443 ctx->pl310->read(events, 1);
445 start_hrtimer(cpu_ctx);
446 atomic_inc(&hrt.nr_active_all_core);
451 void __quadd_task_sched_out(struct task_struct *prev,
452 struct task_struct *next)
455 struct pt_regs *user_regs;
456 struct quadd_cpu_context *cpu_ctx = this_cpu_ptr(hrt.cpu_ctx);
457 struct quadd_ctx *ctx = hrt.quadd_ctx;
458 /* static DEFINE_RATELIMIT_STATE(ratelimit_state, 5 * HZ, 2); */
460 if (likely(!hrt.active))
463 if (__ratelimit(&ratelimit_state))
464 pr_info("sch_out: cpu: %d, prev: %u (%u) \t--> next: %u (%u)\n",
465 smp_processor_id(), (unsigned int)prev->pid,
466 (unsigned int)prev->tgid, (unsigned int)next->pid,
467 (unsigned int)next->tgid);
470 if (is_profile_process(prev)) {
471 user_regs = task_pt_regs(prev);
473 read_all_sources(user_regs, prev);
475 n = remove_active_thread(cpu_ctx, prev->pid);
476 atomic_sub(n, &cpu_ctx->nr_active);
478 if (n && atomic_read(&cpu_ctx->nr_active) == 0) {
479 cancel_hrtimer(cpu_ctx);
480 atomic_dec(&hrt.nr_active_all_core);
488 void __quadd_event_mmap(struct vm_area_struct *vma)
490 struct quadd_parameters *param;
492 if (likely(!hrt.active))
495 if (!is_profile_process(current))
498 param = &hrt.quadd_ctx->param;
499 quadd_process_mmap(vma, param->pids[0]);
502 static void reset_cpu_ctx(void)
505 struct quadd_cpu_context *cpu_ctx;
506 struct quadd_thread_data *t_data;
508 for (cpu_id = 0; cpu_id < nr_cpu_ids; cpu_id++) {
509 cpu_ctx = per_cpu_ptr(hrt.cpu_ctx, cpu_id);
510 t_data = &cpu_ctx->active_thread;
512 atomic_set(&cpu_ctx->nr_active, 0);
519 int quadd_hrt_start(void)
525 struct quadd_ctx *ctx = hrt.quadd_ctx;
526 struct quadd_parameters *param = &ctx->param;
528 freq = ctx->param.freq;
529 freq = max_t(long, QUADD_HRT_MIN_FREQ, freq);
530 period = NSEC_PER_SEC / freq;
531 hrt.sample_period = period;
533 if (ctx->param.ma_freq > 0)
534 hrt.ma_period = MSEC_PER_SEC / ctx->param.ma_freq;
538 atomic64_set(&hrt.counter_samples, 0);
544 extra = param->reserved[QUADD_PARAM_IDX_EXTRA];
546 if (extra & QUADD_PARAM_EXTRA_GET_MMAP) {
547 err = quadd_get_current_mmap(param->pids[0]);
549 pr_err("error: quadd_get_current_mmap\n");
557 quadd_ma_start(&hrt);
561 pr_info("Start hrt: freq/period: %ld/%llu\n", freq, period);
565 void quadd_hrt_stop(void)
567 struct quadd_ctx *ctx = hrt.quadd_ctx;
569 pr_info("Stop hrt, number of samples: %llu\n",
570 atomic64_read(&hrt.counter_samples));
579 atomic64_set(&hrt.counter_samples, 0);
581 /* reset_cpu_ctx(); */
584 void quadd_hrt_deinit(void)
589 free_percpu(hrt.cpu_ctx);
592 void quadd_hrt_get_state(struct quadd_module_state *state)
594 state->nr_all_samples = atomic64_read(&hrt.counter_samples);
595 state->nr_skipped_samples = 0;
598 struct quadd_hrt_ctx *quadd_hrt_init(struct quadd_ctx *ctx)
603 struct quadd_cpu_context *cpu_ctx;
608 freq = ctx->param.freq;
609 freq = max_t(long, QUADD_HRT_MIN_FREQ, freq);
610 period = NSEC_PER_SEC / freq;
611 hrt.sample_period = period;
613 if (ctx->param.ma_freq > 0)
614 hrt.ma_period = MSEC_PER_SEC / ctx->param.ma_freq;
618 atomic64_set(&hrt.counter_samples, 0);
620 hrt.cpu_ctx = alloc_percpu(struct quadd_cpu_context);
622 return ERR_PTR(-ENOMEM);
624 for (cpu_id = 0; cpu_id < nr_cpu_ids; cpu_id++) {
625 cpu_ctx = per_cpu_ptr(hrt.cpu_ctx, cpu_id);
627 atomic_set(&cpu_ctx->nr_active, 0);
629 cpu_ctx->active_thread.pid = -1;
630 cpu_ctx->active_thread.tgid = -1;
632 init_hrtimer(cpu_ctx);