2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/i2c.h>
17 #include <linux/gpio.h>
18 #include <linux/mpu.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/nct1008.h>
22 #include <linux/pid_thermal_gov.h>
23 #include <linux/tegra-fuse.h>
24 #include <linux/of_platform.h>
26 #include <mach/pinmux-t12.h>
27 #include <mach/pinmux.h>
28 #include <mach/io_dpd.h>
29 #include <media/camera.h>
30 #include <media/ar0330.h>
31 #include <media/ar0261.h>
32 #include <media/ar1335.h>
33 #include <media/imx135.h>
34 #include <media/imx179.h>
35 #include <media/dw9718.h>
36 #include <media/as364x.h>
37 #include <media/ov5693.h>
38 #include <media/ov7695.h>
39 #include <media/mt9m114.h>
40 #include <media/ad5823.h>
41 #include <media/max77387.h>
43 #include <media/ov4689.h>
44 #include <linux/platform_device.h>
45 #include <media/soc_camera.h>
46 #include <media/soc_camera_platform.h>
47 #include <media/tegra_v4l2_camera.h>
48 #include <linux/generic_adc_thermal.h>
50 #include "cpu-tegra.h"
53 #include "board-common.h"
54 #include "board-ardbeg.h"
55 #include "tegra-board-id.h"
57 #if defined(ARCH_TEGRA_12x_SOC)
58 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
60 I2C_BOARD_INFO("cm32181", 0x48),
65 /* MPU board file definition */
66 static struct mpu_platform_data mpu9250_gyro_data = {
69 /* Located in board_[platformname].h */
70 .orientation = MPU_GYRO_ORIENTATION,
71 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
72 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
73 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
76 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
79 /* Located in board_[platformname].h */
80 .orientation = MPU_GYRO_ORIENTATION_E1762,
81 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
82 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
83 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
86 static struct mpu_platform_data mpu_compass_data = {
87 .orientation = MPU_COMPASS_ORIENTATION,
88 .config = NVI_CONFIG_BOOT_MPU,
91 static struct mpu_platform_data mpu_bmp_pdata = {
92 .config = NVI_CONFIG_BOOT_MPU,
95 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
97 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
98 .platform_data = &mpu9250_gyro_data,
101 /* The actual BMP180 address is 0x77 but because this conflicts
102 * with another device, this address is hacked so Linux will
103 * call the driver. The conflict is technically okay since the
104 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
105 * hard-coded address of 0x77 since it can't be changed anyway.
107 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
108 .platform_data = &mpu_bmp_pdata,
111 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
112 .platform_data = &mpu_compass_data,
116 static void mpuirq_init(void)
119 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
120 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
121 char *gyro_name = MPU_GYRO_NAME;
122 struct board_info board_info;
124 pr_info("*** MPU START *** mpuirq_init...\n");
126 tegra_get_board_info(&board_info);
128 ret = gpio_request(gyro_irq_gpio, gyro_name);
130 pr_err("%s: gpio_request failed %d\n", __func__, ret);
134 ret = gpio_direction_input(gyro_irq_gpio);
136 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
137 gpio_free(gyro_irq_gpio);
140 pr_info("*** MPU END *** mpuirq_init...\n");
142 /* TN8 with diferent Compass address from ardbeg */
143 if (of_machine_is_compatible("nvidia,tn8"))
144 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
146 if (board_info.board_id == BOARD_E1762)
147 inv_mpu9250_i2c0_board_info[0].platform_data =
148 &mpu9250_gyro_data_e1762;
149 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
150 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
151 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
155 * Soc Camera platform driver for testing
157 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
158 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
159 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
161 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
164 /* TODO: probably add clk opertaion here */
165 return 0; /* camera sensor always enabled */
168 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
169 .format_name = "RGB4",
172 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
173 .colorspace = V4L2_COLORSPACE_SRGB,
174 .field = V4L2_FIELD_NONE,
178 .set_capture = ardbeg_soc_camera_set_capture,
181 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
184 .port = TEGRA_CAMERA_PORT_CSI_A,
189 static struct soc_camera_link ardbeg_soc_camera_link = {
190 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
191 .add_device = ardbeg_soc_camera_add,
192 .del_device = ardbeg_soc_camera_del,
193 .module_name = "soc_camera_platform",
194 .priv = &ardbeg_camera_platform_data,
195 .dev_priv = &ardbeg_soc_camera_info,
198 static struct platform_device *ardbeg_pdev;
200 static void ardbeg_soc_camera_release(struct device *dev)
202 soc_camera_platform_release(&ardbeg_pdev);
205 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
207 return soc_camera_platform_add(icd, &ardbeg_pdev,
208 &ardbeg_soc_camera_link,
209 ardbeg_soc_camera_release, 0);
212 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
214 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
217 static struct platform_device ardbeg_soc_camera_device = {
218 .name = "soc-camera-pdrv",
221 .platform_data = &ardbeg_soc_camera_link,
226 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
227 static int ardbeg_imx135_power(struct device *dev, int enable)
232 struct imx135_platform_data ardbeg_imx135_data;
234 static struct i2c_board_info ardbeg_imx135_camera_i2c_device = {
235 I2C_BOARD_INFO("imx135_v4l2", 0x10),
236 .platform_data = &ardbeg_imx135_data,
239 static struct tegra_camera_platform_data ardbeg_imx135_camera_platform_data = {
242 .port = TEGRA_CAMERA_PORT_CSI_A,
247 static struct soc_camera_link imx135_iclink = {
248 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
249 .board_info = &ardbeg_imx135_camera_i2c_device,
250 .module_name = "imx135_v4l2",
252 .power = ardbeg_imx135_power,
253 .priv = &ardbeg_imx135_camera_platform_data,
256 static struct platform_device ardbeg_imx135_soc_camera_device = {
257 .name = "soc-camera-pdrv",
260 .platform_data = &imx135_iclink,
265 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
266 static int ardbeg_ar0261_power(struct device *dev, int enable)
271 struct ar0261_platform_data ardbeg_ar0261_data;
273 static struct i2c_board_info ardbeg_ar0261_camera_i2c_device = {
274 I2C_BOARD_INFO("ar0261_v4l2", 0x36),
275 .platform_data = &ardbeg_ar0261_data,
278 static struct tegra_camera_platform_data ardbeg_ar0261_camera_platform_data = {
281 .port = TEGRA_CAMERA_PORT_CSI_C,
286 static struct soc_camera_link ar0261_iclink = {
287 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
288 .board_info = &ardbeg_ar0261_camera_i2c_device,
289 .module_name = "ar0261_v4l2",
291 .power = ardbeg_ar0261_power,
292 .priv = &ardbeg_ar0261_camera_platform_data,
295 static struct platform_device ardbeg_ar0261_soc_camera_device = {
296 .name = "soc-camera-pdrv",
299 .platform_data = &ar0261_iclink,
304 static struct regulator *ardbeg_vcmvdd;
306 static int ardbeg_get_extra_regulators(void)
308 if (!ardbeg_vcmvdd) {
309 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
310 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
311 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
312 __func__, PTR_ERR(ardbeg_vcmvdd));
313 regulator_put(ardbeg_vcmvdd);
314 ardbeg_vcmvdd = NULL;
322 static struct tegra_io_dpd csia_io = {
324 .io_dpd_reg_index = 0,
328 static struct tegra_io_dpd csib_io = {
330 .io_dpd_reg_index = 0,
334 static struct tegra_io_dpd csie_io = {
336 .io_dpd_reg_index = 1,
340 static int ardbeg_ar0330_front_power_on(struct ar0330_power_rail *pw)
344 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
347 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
348 tegra_io_dpd_disable(&csie_io);
350 gpio_set_value(CAM2_PWDN, 0);
352 err = regulator_enable(pw->iovdd);
354 goto ar0330_front_iovdd_fail;
356 usleep_range(1000, 1100);
357 err = regulator_enable(pw->avdd);
359 goto ar0330_front_avdd_fail;
362 gpio_set_value(CAM2_PWDN, 1);
365 ar0330_front_avdd_fail:
366 regulator_disable(pw->iovdd);
368 ar0330_front_iovdd_fail:
369 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
370 tegra_io_dpd_enable(&csie_io);
371 pr_err("%s failed.\n", __func__);
375 static int ardbeg_ar0330_front_power_off(struct ar0330_power_rail *pw)
377 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
378 /* put CSIE IOs into DPD mode to
379 * save additional power for ardbeg
381 tegra_io_dpd_enable(&csie_io);
385 gpio_set_value(CAM2_PWDN, 0);
389 regulator_disable(pw->iovdd);
390 regulator_disable(pw->avdd);
391 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
392 tegra_io_dpd_enable(&csie_io);
396 struct ar0330_platform_data ardbeg_ar0330_front_data = {
397 .power_on = ardbeg_ar0330_front_power_on,
398 .power_off = ardbeg_ar0330_front_power_off,
399 .dev_name = "ar0330.1",
400 .mclk_name = "mclk2",
403 static int ardbeg_ar0330_power_on(struct ar0330_power_rail *pw)
407 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
410 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
411 tegra_io_dpd_disable(&csia_io);
412 tegra_io_dpd_disable(&csib_io);
414 gpio_set_value(CAM1_PWDN, 0);
416 err = regulator_enable(pw->iovdd);
418 goto ar0330_iovdd_fail;
420 usleep_range(1000, 1100);
421 err = regulator_enable(pw->avdd);
423 goto ar0330_avdd_fail;
426 gpio_set_value(CAM1_PWDN, 1);
430 regulator_disable(pw->iovdd);
433 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
434 tegra_io_dpd_enable(&csia_io);
435 tegra_io_dpd_enable(&csib_io);
436 pr_err("%s failed.\n", __func__);
440 static int ardbeg_ar0330_power_off(struct ar0330_power_rail *pw)
442 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
443 /* put CSIE IOs into DPD mode to
444 * save additional power for ardbeg
446 tegra_io_dpd_enable(&csia_io);
447 tegra_io_dpd_enable(&csib_io);
451 gpio_set_value(CAM1_PWDN, 0);
455 regulator_disable(pw->iovdd);
456 regulator_disable(pw->avdd);
457 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
458 tegra_io_dpd_enable(&csia_io);
459 tegra_io_dpd_enable(&csib_io);
463 struct ar0330_platform_data ardbeg_ar0330_data = {
464 .power_on = ardbeg_ar0330_power_on,
465 .power_off = ardbeg_ar0330_power_off,
466 .dev_name = "ar0330",
469 static int ardbeg_ov4689_power_on(struct ov4689_power_rail *pw)
471 pr_info("%s: ++\n", __func__);
472 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
473 tegra_io_dpd_disable(&csia_io);
474 tegra_io_dpd_disable(&csib_io);
476 gpio_set_value(TEGRA_GPIO_PBB5, 0);
477 usleep_range(10, 20);
478 gpio_set_value(TEGRA_GPIO_PBB5, 1);
479 usleep_range(820, 1000);
484 static int ardbeg_ov4689_power_off(struct ov4689_power_rail *pw)
486 pr_info("%s: ++\n", __func__);
488 gpio_set_value(TEGRA_GPIO_PBB5, 0);
490 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
491 tegra_io_dpd_enable(&csia_io);
492 tegra_io_dpd_enable(&csib_io);
497 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
501 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
504 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
505 tegra_io_dpd_disable(&csie_io);
507 if (ardbeg_get_extra_regulators())
508 goto ardbeg_ar0261_poweron_fail;
510 gpio_set_value(CAM_RSTN, 0);
511 gpio_set_value(CAM_AF_PWDN, 1);
514 err = regulator_enable(ardbeg_vcmvdd);
516 goto ar0261_vcm_fail;
518 err = regulator_enable(pw->dvdd);
520 goto ar0261_dvdd_fail;
522 err = regulator_enable(pw->avdd);
524 goto ar0261_avdd_fail;
526 err = regulator_enable(pw->iovdd);
528 goto ar0261_iovdd_fail;
531 gpio_set_value(CAM2_PWDN, 1);
533 gpio_set_value(CAM_RSTN, 1);
537 regulator_disable(pw->dvdd);
540 regulator_disable(pw->avdd);
543 regulator_disable(ardbeg_vcmvdd);
546 pr_err("%s vcmvdd failed.\n", __func__);
549 ardbeg_ar0261_poweron_fail:
550 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
551 tegra_io_dpd_enable(&csie_io);
552 pr_err("%s failed.\n", __func__);
556 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
558 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
560 /* put CSIE IOs into DPD mode to
561 * save additional power for ardbeg
563 tegra_io_dpd_enable(&csie_io);
567 gpio_set_value(CAM_RSTN, 0);
571 regulator_disable(pw->iovdd);
572 regulator_disable(pw->dvdd);
573 regulator_disable(pw->avdd);
574 regulator_disable(ardbeg_vcmvdd);
575 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
576 tegra_io_dpd_enable(&csie_io);
580 struct ar0261_platform_data ardbeg_ar0261_data = {
581 .power_on = ardbeg_ar0261_power_on,
582 .power_off = ardbeg_ar0261_power_off,
583 .mclk_name = "mclk2",
586 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
589 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
590 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
591 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
592 __func__, PTR_ERR(pw->ext_reg1));
599 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
600 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
601 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
602 __func__, PTR_ERR(pw->ext_reg2));
611 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
615 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
618 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
619 tegra_io_dpd_disable(&csia_io);
620 tegra_io_dpd_disable(&csib_io);
622 if (ardbeg_imx135_get_extra_regulators(pw))
623 goto imx135_poweron_fail;
625 err = regulator_enable(pw->ext_reg1);
627 goto imx135_ext_reg1_fail;
629 err = regulator_enable(pw->ext_reg2);
631 goto imx135_ext_reg2_fail;
634 gpio_set_value(CAM_AF_PWDN, 1);
635 gpio_set_value(CAM1_PWDN, 0);
636 usleep_range(10, 20);
638 err = regulator_enable(pw->avdd);
640 goto imx135_avdd_fail;
642 err = regulator_enable(pw->iovdd);
644 goto imx135_iovdd_fail;
647 gpio_set_value(CAM1_PWDN, 1);
649 usleep_range(300, 310);
655 regulator_disable(pw->avdd);
659 regulator_disable(pw->ext_reg2);
661 imx135_ext_reg2_fail:
663 regulator_disable(pw->ext_reg1);
664 gpio_set_value(CAM_AF_PWDN, 0);
666 imx135_ext_reg1_fail:
668 tegra_io_dpd_enable(&csia_io);
669 tegra_io_dpd_enable(&csib_io);
670 pr_err("%s failed.\n", __func__);
674 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
676 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
677 tegra_io_dpd_enable(&csia_io);
678 tegra_io_dpd_enable(&csib_io);
682 regulator_disable(pw->iovdd);
683 regulator_disable(pw->avdd);
685 regulator_disable(pw->ext_reg1);
686 regulator_disable(pw->ext_reg2);
688 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
689 tegra_io_dpd_enable(&csia_io);
690 tegra_io_dpd_enable(&csib_io);
694 static int ardbeg_ar1335_power_on(struct ar1335_power_rail *pw)
698 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
701 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
702 tegra_io_dpd_disable(&csia_io);
703 tegra_io_dpd_disable(&csib_io);
705 gpio_set_value(CAM_RSTN, 0);
706 usleep_range(10, 20);
708 err = regulator_enable(pw->avdd);
710 goto ar1335_avdd_fail;
712 err = regulator_enable(pw->iovdd);
714 goto ar1335_iovdd_fail;
716 err = regulator_enable(pw->dvdd);
718 goto ar1335_dvdd_fail;
721 gpio_set_value(CAM_RSTN, 1);
723 usleep_range(300, 310);
728 regulator_disable(pw->iovdd);
731 regulator_disable(pw->avdd);
734 tegra_io_dpd_enable(&csia_io);
735 tegra_io_dpd_enable(&csib_io);
736 pr_err("%s failed.\n", __func__);
740 static int ardbeg_ar1335_power_off(struct ar1335_power_rail *pw)
742 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
743 tegra_io_dpd_enable(&csia_io);
744 tegra_io_dpd_enable(&csib_io);
748 regulator_disable(pw->iovdd);
749 regulator_disable(pw->avdd);
750 regulator_disable(pw->dvdd);
752 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
753 tegra_io_dpd_enable(&csia_io);
754 tegra_io_dpd_enable(&csib_io);
758 static int ardbeg_imx179_power_on(struct imx179_power_rail *pw)
762 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
765 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
766 tegra_io_dpd_disable(&csia_io);
767 tegra_io_dpd_disable(&csib_io);
769 gpio_set_value(CAM_AF_PWDN, 1);
770 gpio_set_value(CAM_RSTN, 0);
771 gpio_set_value(CAM1_PWDN, 0);
772 usleep_range(10, 20);
774 err = regulator_enable(pw->avdd);
776 goto imx179_avdd_fail;
778 err = regulator_enable(pw->iovdd);
780 goto imx179_iovdd_fail;
782 err = regulator_enable(pw->dvdd);
784 goto imx179_dvdd_fail;
787 gpio_set_value(CAM_RSTN, 1);
789 usleep_range(300, 310);
795 regulator_disable(pw->iovdd);
798 regulator_disable(pw->avdd);
801 tegra_io_dpd_enable(&csia_io);
802 tegra_io_dpd_enable(&csib_io);
803 pr_err("%s failed.\n", __func__);
807 static int ardbeg_imx179_power_off(struct imx179_power_rail *pw)
809 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
810 tegra_io_dpd_enable(&csia_io);
811 tegra_io_dpd_enable(&csib_io);
815 regulator_disable(pw->dvdd);
816 regulator_disable(pw->iovdd);
817 regulator_disable(pw->avdd);
819 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
820 tegra_io_dpd_enable(&csia_io);
821 tegra_io_dpd_enable(&csib_io);
825 struct ar1335_platform_data ardbeg_ar1335_data = {
833 .power_on = ardbeg_ar1335_power_on,
834 .power_off = ardbeg_ar1335_power_off,
837 struct imx135_platform_data ardbeg_imx135_data = {
846 .power_on = ardbeg_imx135_power_on,
847 .power_off = ardbeg_imx135_power_off,
850 struct imx179_platform_data ardbeg_imx179_data = {
858 .power_on = ardbeg_imx179_power_on,
859 .power_off = ardbeg_imx179_power_off,
862 struct ov4689_platform_data ardbeg_ov4689_data = {
870 .power_on = ardbeg_ov4689_power_on,
871 .power_off = ardbeg_ov4689_power_off,
874 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
877 pr_info("%s\n", __func__);
879 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
882 err = regulator_enable(pw->vdd);
884 goto dw9718_vdd_fail;
886 err = regulator_enable(pw->vdd_i2c);
888 goto dw9718_i2c_fail;
890 err = regulator_enable(pw->vana);
892 goto dw9718_ana_fail;
894 usleep_range(1000, 1020);
896 /* return 1 to skip the in-driver power_on sequence */
897 pr_debug("%s --\n", __func__);
901 regulator_disable(pw->vdd_i2c);
904 regulator_disable(pw->vdd);
907 pr_err("%s FAILED\n", __func__);
911 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
913 pr_info("%s\n", __func__);
915 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
918 regulator_disable(pw->vdd);
919 regulator_disable(pw->vdd_i2c);
920 regulator_disable(pw->vana);
925 static u16 dw9718_devid;
926 static int ardbeg_dw9718_detect(void *buf, size_t size)
928 dw9718_devid = 0x9718;
932 static struct nvc_focus_cap dw9718_cap = {
934 .slew_rate = 0x3A200C,
936 .focus_infinity = 200,
940 static struct dw9718_platform_data ardbeg_dw9718_data = {
941 .cfg = NVC_CFG_NODEV,
944 .dev_name = "focuser",
946 .power_on = ardbeg_dw9718_power_on,
947 .power_off = ardbeg_dw9718_power_off,
948 .detect = ardbeg_dw9718_detect,
951 static struct as364x_platform_data ardbeg_as3648_data = {
954 .max_total_current_mA = 1000,
955 .max_peak_current_mA = 600,
956 .max_torch_current_mA = 600,
957 .vin_low_v_run_mV = 3070,
961 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
962 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
966 .gpio_strobe = CAM_FLASH_STROBE,
969 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
973 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
976 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
977 tegra_io_dpd_disable(&csie_io);
979 gpio_set_value(CAM2_PWDN, 0);
980 usleep_range(1000, 1020);
982 err = regulator_enable(pw->avdd);
984 goto ov7695_avdd_fail;
985 usleep_range(300, 320);
987 err = regulator_enable(pw->iovdd);
989 goto ov7695_iovdd_fail;
990 usleep_range(1000, 1020);
992 gpio_set_value(CAM2_PWDN, 1);
993 usleep_range(1000, 1020);
998 regulator_disable(pw->avdd);
1001 gpio_set_value(CAM_RSTN, 0);
1002 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1003 tegra_io_dpd_enable(&csie_io);
1007 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
1009 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
1010 /* put CSIE IOs into DPD mode to
1011 * save additional power for ardbeg
1013 tegra_io_dpd_enable(&csie_io);
1016 usleep_range(100, 120);
1018 gpio_set_value(CAM2_PWDN, 0);
1019 usleep_range(100, 120);
1021 regulator_disable(pw->iovdd);
1022 usleep_range(100, 120);
1024 regulator_disable(pw->avdd);
1026 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1027 tegra_io_dpd_enable(&csie_io);
1031 struct ov7695_platform_data ardbeg_ov7695_pdata = {
1032 .power_on = ardbeg_ov7695_power_on,
1033 .power_off = ardbeg_ov7695_power_off,
1034 .mclk_name = "mclk2",
1037 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
1040 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
1043 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
1044 tegra_io_dpd_disable(&csie_io);
1046 gpio_set_value(CAM_RSTN, 0);
1047 gpio_set_value(CAM2_PWDN, 1);
1048 usleep_range(1000, 1020);
1050 err = regulator_enable(pw->iovdd);
1052 goto mt9m114_iovdd_fail;
1054 err = regulator_enable(pw->avdd);
1056 goto mt9m114_avdd_fail;
1058 usleep_range(1000, 1020);
1059 gpio_set_value(CAM_RSTN, 1);
1060 gpio_set_value(CAM2_PWDN, 0);
1061 usleep_range(1000, 1020);
1063 /* return 1 to skip the in-driver power_on swquence */
1067 regulator_disable(pw->iovdd);
1070 gpio_set_value(CAM_RSTN, 0);
1071 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1072 tegra_io_dpd_enable(&csie_io);
1076 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
1078 if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
1079 /* put CSIE IOs into DPD mode to
1080 * save additional power for ardbeg
1082 tegra_io_dpd_enable(&csie_io);
1086 usleep_range(100, 120);
1087 gpio_set_value(CAM_RSTN, 0);
1088 usleep_range(100, 120);
1089 regulator_disable(pw->avdd);
1090 usleep_range(100, 120);
1091 regulator_disable(pw->iovdd);
1093 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
1094 tegra_io_dpd_enable(&csie_io);
1098 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
1099 .power_on = ardbeg_mt9m114_power_on,
1100 .power_off = ardbeg_mt9m114_power_off,
1101 .mclk_name = "mclk2",
1105 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
1109 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1112 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
1113 tegra_io_dpd_disable(&csia_io);
1114 tegra_io_dpd_disable(&csib_io);
1116 if (ardbeg_get_extra_regulators())
1117 goto ov5693_poweron_fail;
1119 gpio_set_value(CAM1_PWDN, 0);
1120 usleep_range(10, 20);
1122 err = regulator_enable(pw->avdd);
1124 goto ov5693_avdd_fail;
1126 err = regulator_enable(pw->dovdd);
1128 goto ov5693_iovdd_fail;
1131 gpio_set_value(CAM1_PWDN, 1);
1133 err = regulator_enable(ardbeg_vcmvdd);
1135 goto ov5693_vcmvdd_fail;
1137 usleep_range(1000, 1110);
1142 regulator_disable(pw->dovdd);
1145 regulator_disable(pw->avdd);
1148 gpio_set_value(CAM1_PWDN, 0);
1150 ov5693_poweron_fail:
1151 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1152 tegra_io_dpd_enable(&csia_io);
1153 tegra_io_dpd_enable(&csib_io);
1154 pr_err("%s FAILED\n", __func__);
1158 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
1160 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1161 /* put CSIA/B IOs into DPD mode to
1162 * save additional power for ardbeg
1164 tegra_io_dpd_enable(&csia_io);
1165 tegra_io_dpd_enable(&csib_io);
1169 usleep_range(21, 25);
1170 gpio_set_value(CAM1_PWDN, 0);
1173 regulator_disable(ardbeg_vcmvdd);
1174 regulator_disable(pw->dovdd);
1175 regulator_disable(pw->avdd);
1177 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1178 tegra_io_dpd_enable(&csia_io);
1179 tegra_io_dpd_enable(&csib_io);
1183 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
1184 { OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0, },
1187 #define NV_GUID(a, b, c, d, e, f, g, h) \
1188 ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
1189 (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
1190 (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
1191 (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
1193 static struct nvc_imager_cap ov5693_cap = {
1194 .identifier = "OV5693",
1195 .sensor_nvc_interface = 3,
1196 .pixel_types[0] = 0x101,
1199 .initial_clock_rate_khz = 6000,
1200 .clock_profiles[0] = {
1201 .external_clock_khz = 24000,
1202 .clock_multiplier = 8000000, /* value * 1000000 */
1204 .clock_profiles[1] = {
1205 .external_clock_khz = 0,
1206 .clock_multiplier = 0,
1213 .virtual_channel_id = 0,
1214 .discontinuous_clk_mode = 1,
1215 .cil_threshold_settle = 0,
1216 .min_blank_time_width = 16,
1217 .min_blank_time_height = 16,
1218 .preferred_mode_index = 0,
1220 NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
1222 NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
1223 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1224 .flash_control_enabled = 0,
1225 .adjustable_flash_timing = 0,
1230 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
1231 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
1232 .gpio = ov5693_gpio_pdata,
1233 .power_on = ardbeg_ov5693_power_on,
1234 .power_off = ardbeg_ov5693_power_off,
1235 .dev_name = "ov5693",
1237 .mclk_name = "mclk",
1239 .avdd = "avdd_ov5693",
1246 static int ardbeg_ov5693_front_power_on(struct ov5693_power_rail *pw)
1250 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1253 if (ardbeg_get_extra_regulators())
1254 goto ov5693_front_poweron_fail;
1256 gpio_set_value(CAM2_PWDN, 0);
1257 gpio_set_value(CAM_RSTN, 0);
1258 usleep_range(10, 20);
1260 err = regulator_enable(pw->avdd);
1262 goto ov5693_front_avdd_fail;
1264 err = regulator_enable(pw->dovdd);
1266 goto ov5693_front_iovdd_fail;
1269 gpio_set_value(CAM2_PWDN, 1);
1270 gpio_set_value(CAM_RSTN, 1);
1272 err = regulator_enable(ardbeg_vcmvdd);
1274 goto ov5693_front_vcmvdd_fail;
1276 usleep_range(1000, 1110);
1280 ov5693_front_vcmvdd_fail:
1281 regulator_disable(pw->dovdd);
1283 ov5693_front_iovdd_fail:
1284 regulator_disable(pw->avdd);
1286 ov5693_front_avdd_fail:
1287 gpio_set_value(CAM2_PWDN, 0);
1288 gpio_set_value(CAM_RSTN, 0);
1290 ov5693_front_poweron_fail:
1291 pr_err("%s FAILED\n", __func__);
1295 static int ardbeg_ov5693_front_power_off(struct ov5693_power_rail *pw)
1297 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1301 usleep_range(21, 25);
1302 gpio_set_value(CAM2_PWDN, 0);
1303 gpio_set_value(CAM_RSTN, 0);
1306 regulator_disable(ardbeg_vcmvdd);
1307 regulator_disable(pw->dovdd);
1308 regulator_disable(pw->avdd);
1313 static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
1314 { OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0, },
1315 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
1318 static struct nvc_imager_cap ov5693_front_cap = {
1319 .identifier = "OV5693.1",
1320 .sensor_nvc_interface = 4,
1321 .pixel_types[0] = 0x101,
1324 .initial_clock_rate_khz = 6000,
1325 .clock_profiles[0] = {
1326 .external_clock_khz = 24000,
1327 .clock_multiplier = 8000000, /* value * 1000000 */
1329 .clock_profiles[1] = {
1330 .external_clock_khz = 0,
1331 .clock_multiplier = 0,
1338 .virtual_channel_id = 0,
1339 .discontinuous_clk_mode = 1,
1340 .cil_threshold_settle = 0,
1341 .min_blank_time_width = 16,
1342 .min_blank_time_height = 16,
1343 .preferred_mode_index = 0,
1346 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1347 .flash_control_enabled = 0,
1348 .adjustable_flash_timing = 0,
1352 static struct ov5693_platform_data ardbeg_ov5693_front_pdata = {
1353 .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
1354 .gpio = ov5693_front_gpio_pdata,
1355 .power_on = ardbeg_ov5693_front_power_on,
1356 .power_off = ardbeg_ov5693_front_power_off,
1357 .dev_name = "ov5693.1",
1358 .mclk_name = "mclk2",
1359 .cap = &ov5693_front_cap,
1368 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
1372 pr_info("%s\n", __func__);
1373 gpio_set_value_cansleep(pdata->gpio, 1);
1374 pdata->pwr_dev = AD5823_PWR_DEV_ON;
1379 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
1381 pr_info("%s\n", __func__);
1382 gpio_set_value_cansleep(pdata->gpio, 0);
1383 pdata->pwr_dev = AD5823_PWR_DEV_OFF;
1388 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
1389 .gpio = CAM_AF_PWDN,
1390 .power_on = ardbeg_ad5823_power_on,
1391 .power_off = ardbeg_ad5823_power_off,
1394 static struct camera_data_blob ardbeg_camera_lut[] = {
1395 {"ardbeg_imx135_pdata", &ardbeg_imx135_data},
1396 {"ardbeg_dw9718_pdata", &ardbeg_dw9718_data},
1397 {"ardbeg_ar0261_pdata", &ardbeg_ar0261_data},
1398 {"ardbeg_mt9m114_pdata", &ardbeg_mt9m114_pdata},
1399 {"ardbeg_ov5693_pdata", &ardbeg_ov5693_pdata},
1400 {"ardbeg_ad5823_pdata", &ardbeg_ad5823_pdata},
1401 {"ardbeg_as3648_pdata", &ardbeg_as3648_data},
1402 {"ardbeg_ov7695_pdata", &ardbeg_ov7695_pdata},
1403 {"ardbeg_ov5693f_pdata", &ardbeg_ov5693_front_pdata},
1404 {"ardbeg_ar0330_pdata", &ardbeg_ar0330_data},
1405 {"ardbeg_ar0330_front_pdata", &ardbeg_ar0330_front_data},
1406 {"ardbeg_ov4689_pdata", &ardbeg_ov4689_data},
1407 {"ardbeg_ar1335_pdata", &ardbeg_ar1335_data},
1411 void __init ardbeg_camera_auxdata(void *data)
1413 struct of_dev_auxdata *aux_lut = data;
1414 while (aux_lut && aux_lut->compatible) {
1415 if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
1416 pr_info("%s: update camera lookup table.\n", __func__);
1417 aux_lut->platform_data = ardbeg_camera_lut;
1423 static int ardbeg_camera_init(void)
1425 struct board_info board_info;
1427 pr_debug("%s: ++\n", __func__);
1428 tegra_get_board_info(&board_info);
1430 /* put CSIA/B/C/D/E IOs into DPD mode to
1431 * save additional power for ardbeg
1433 tegra_io_dpd_enable(&csia_io);
1434 tegra_io_dpd_enable(&csib_io);
1435 tegra_io_dpd_enable(&csie_io);
1437 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
1438 platform_device_register(&ardbeg_soc_camera_device);
1441 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
1442 platform_device_register(&ardbeg_imx135_soc_camera_device);
1445 #if IS_ENABLED(CONFIG_SOC_CAMERA_AR0261)
1446 platform_device_register(&ardbeg_ar0261_soc_camera_device);
1451 static struct pid_thermal_gov_params cpu_pid_params = {
1452 .max_err_temp = 4000,
1453 .max_err_gain = 1000,
1458 .up_compensation = 15,
1459 .down_compensation = 15,
1462 static struct thermal_zone_params cpu_tzp = {
1463 .governor_name = "pid_thermal_gov",
1464 .governor_params = &cpu_pid_params,
1467 static struct thermal_zone_params board_tzp = {
1468 .governor_name = "pid_thermal_gov"
1471 static struct throttle_table cpu_throttle_table[] = {
1472 /* CPU_THROT_LOW cannot be used by other than CPU */
1473 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1474 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1475 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1476 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1477 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1478 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1479 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1480 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1481 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1482 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1483 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1484 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1485 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1486 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1487 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1488 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1489 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1490 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1491 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1492 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1493 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1494 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1495 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1496 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1497 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1498 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1499 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1500 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1501 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1502 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1503 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1504 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1505 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1506 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1507 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1508 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1509 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1510 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1511 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1512 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1513 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1514 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1515 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1516 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1517 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1518 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1519 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1520 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1521 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1522 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1523 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1524 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1525 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1526 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1527 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1528 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1529 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1530 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1531 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1532 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1533 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1534 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1535 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1536 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1537 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1538 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1539 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1540 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1541 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1542 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1543 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1544 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1545 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1546 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1547 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1548 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1549 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1550 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1551 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1552 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1553 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1554 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1555 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1556 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1559 static struct balanced_throttle cpu_throttle = {
1560 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1561 .throt_tab = cpu_throttle_table,
1564 static struct throttle_table gpu_throttle_table[] = {
1565 /* CPU_THROT_LOW cannot be used by other than CPU */
1566 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1567 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1568 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1569 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1570 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1571 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1572 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1573 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1574 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1575 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1576 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1577 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1578 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1579 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1580 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1581 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1582 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1583 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1584 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1585 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1586 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1587 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1588 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1589 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1590 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1591 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1592 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1593 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1594 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1595 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1596 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1597 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1598 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1599 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1600 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1601 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1602 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1603 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1604 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1605 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1606 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1607 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1608 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1609 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1610 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1611 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1612 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1613 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1614 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1615 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1616 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1617 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1618 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1619 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1620 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1621 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1622 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1623 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1624 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1625 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1626 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1627 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1628 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1629 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1630 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1631 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1632 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1633 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1634 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1635 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1636 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1637 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1638 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1639 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1640 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1641 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1642 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1643 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1644 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1645 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1646 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1647 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1648 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1649 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1652 static struct balanced_throttle gpu_throttle = {
1653 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1654 .throt_tab = gpu_throttle_table,
1657 /* throttle table that sets all clocks to approximately 50% of their max */
1658 static struct throttle_table emergency_throttle_table[] = {
1659 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1660 { { 1122000, 391000, 288000, 420000, 252000, 396000 } },
1663 static struct balanced_throttle emergency_throttle = {
1664 .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
1665 .throt_tab = emergency_throttle_table,
1668 static int __init ardbeg_balanced_throttle_init(void)
1670 if (of_machine_is_compatible("nvidia,ardbeg") ||
1671 of_machine_is_compatible("nvidia,norrin") ||
1672 of_machine_is_compatible("nvidia,bowmore") ||
1673 of_machine_is_compatible("nvidia,tn8")) {
1675 if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
1676 pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
1677 if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
1678 pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
1679 if (!balanced_throttle_register(&emergency_throttle,
1680 "emergency-balanced"))
1681 pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
1686 late_initcall(ardbeg_balanced_throttle_init);
1688 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1689 static struct thermal_trip_info skin_trips[] = {
1691 .cdev_type = "skin-balanced",
1693 .trip_type = THERMAL_TRIP_PASSIVE,
1694 .upper = THERMAL_NO_LIMIT,
1695 .lower = THERMAL_NO_LIMIT,
1700 static struct therm_est_subdevice skin_devs[] = {
1702 .dev_data = "Tdiode_tegra",
1712 .dev_data = "Tboard_tegra",
1723 static struct therm_est_subdevice tn8ffd_skin_devs[] = {
1725 .dev_data = "Tdiode",
1735 .dev_data = "Tboard",
1746 static struct therm_est_subdevice tn8ffd_t132_skin_devs[] = {
1748 .dev_data = "Tdiode",
1758 .dev_data = "Tboard",
1769 static struct pid_thermal_gov_params skin_pid_params = {
1770 .max_err_temp = 4000,
1771 .max_err_gain = 1000,
1776 .up_compensation = 15,
1777 .down_compensation = 15,
1780 static struct thermal_zone_params skin_tzp = {
1781 .governor_name = "pid_thermal_gov",
1782 .governor_params = &skin_pid_params,
1785 static struct therm_est_data skin_data = {
1786 .num_trips = ARRAY_SIZE(skin_trips),
1787 .trips = skin_trips,
1788 .polling_period = 1100,
1789 .passive_delay = 15000,
1796 static struct throttle_table skin_throttle_table[] = {
1797 /* CPU_THROT_LOW cannot be used by other than CPU */
1798 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1799 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1800 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1801 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1802 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1803 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1804 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1805 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1806 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1807 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1808 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1809 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1810 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1811 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1812 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1813 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1814 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1815 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1816 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1817 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1818 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1819 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1820 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1821 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1822 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1823 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1824 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1825 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1826 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1827 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1828 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1829 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1830 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1831 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1832 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1833 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1834 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1835 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1836 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1837 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1838 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1839 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1840 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1841 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1842 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1843 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1844 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1845 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1846 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1847 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1848 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1849 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1850 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1851 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1852 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1853 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1854 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1855 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1856 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1857 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1858 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1859 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1860 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1861 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1862 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1863 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1864 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1865 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1866 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1867 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1868 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1869 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1870 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1871 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1872 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1873 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1874 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1875 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1876 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1877 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1878 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1879 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1880 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1881 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1884 static struct balanced_throttle skin_throttle = {
1885 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1886 .throt_tab = skin_throttle_table,
1889 static int __init ardbeg_skin_init(void)
1891 struct board_info board_info;
1893 if (of_machine_is_compatible("nvidia,ardbeg") ||
1894 of_machine_is_compatible("nvidia,norrin") ||
1895 of_machine_is_compatible("nvidia,bowmore") ||
1896 of_machine_is_compatible("nvidia,tn8")) {
1898 tegra_get_board_info(&board_info);
1900 if (board_info.board_id == BOARD_P1761 &&
1901 board_info.fab == BOARD_FAB_D) {
1902 skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
1903 skin_data.devs = tn8ffd_t132_skin_devs;
1904 skin_data.toffset = 708;
1905 } else if (board_info.board_id == BOARD_P1761 ||
1906 board_info.board_id == BOARD_E1784 ||
1907 board_info.board_id == BOARD_E1971 ||
1908 board_info.board_id == BOARD_E1991 ||
1909 board_info.board_id == BOARD_E1922) {
1910 skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
1911 skin_data.devs = tn8ffd_skin_devs;
1912 skin_data.toffset = 4034;
1914 skin_data.ndevs = ARRAY_SIZE(skin_devs);
1915 skin_data.devs = skin_devs;
1916 skin_data.toffset = 9793;
1919 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1920 platform_device_register(&tegra_skin_therm_est_device);
1922 if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
1923 pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
1928 late_initcall(ardbeg_skin_init);
1931 static struct nct1008_platform_data ardbeg_nct72_pdata = {
1932 .loc_name = "tegra",
1933 .supported_hwrev = true,
1934 .conv_rate = 0x06, /* 4Hz conversion rate */
1936 .extended_range = true,
1941 .shutdown_limit = 120, /* C */
1942 .passive_delay = 1000,
1946 .cdev_type = "therm_est_activ",
1948 .trip_type = THERMAL_TRIP_ACTIVE,
1950 .upper = THERMAL_NO_LIMIT,
1951 .lower = THERMAL_NO_LIMIT,
1958 .shutdown_limit = 95, /* C */
1959 .passive_delay = 1000,
1963 .cdev_type = "shutdown_warning",
1965 .trip_type = THERMAL_TRIP_PASSIVE,
1966 .upper = THERMAL_NO_LIMIT,
1967 .lower = THERMAL_NO_LIMIT,
1971 .cdev_type = "cpu-balanced",
1973 .trip_type = THERMAL_TRIP_PASSIVE,
1974 .upper = THERMAL_NO_LIMIT,
1975 .lower = THERMAL_NO_LIMIT,
1984 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1985 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
1988 .supported_hwrev = true,
1989 .conv_rate = 0x06, /* 4Hz conversion rate */
1991 .extended_range = true,
1995 .shutdown_limit = 95, /* C */
2000 .shutdown_limit = 85, /* C */
2001 .passive_delay = 10000,
2002 .polling_delay = 1000,
2007 .cdev_type = "skin-balanced",
2009 .trip_type = THERMAL_TRIP_PASSIVE,
2010 .upper = THERMAL_NO_LIMIT,
2011 .lower = THERMAL_NO_LIMIT,
2020 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
2022 I2C_BOARD_INFO("nct72", 0x4c),
2023 .platform_data = &ardbeg_nct72_pdata,
2026 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
2028 I2C_BOARD_INFO("nct72", 0x4d),
2029 .platform_data = &ardbeg_nct72_tskin_pdata,
2035 static int ardbeg_nct72_init(void)
2037 int nct72_port = TEGRA_GPIO_PI6;
2040 struct thermal_trip_info *trip_state;
2041 struct board_info board_info;
2043 tegra_get_board_info(&board_info);
2044 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
2045 if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
2046 (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
2047 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit += 20;
2048 for (i = 0; i < ardbeg_nct72_pdata.sensors[EXT].num_trips;
2050 trip_state = &ardbeg_nct72_pdata.sensors[EXT].trips[i];
2051 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
2052 THERMAL_NAME_LENGTH)) {
2053 trip_state->cdev_type = "_none_";
2058 tegra_platform_edp_init(
2059 ardbeg_nct72_pdata.sensors[EXT].trips,
2060 &ardbeg_nct72_pdata.sensors[EXT].num_trips,
2061 12000); /* edp temperature margin */
2062 tegra_add_cpu_vmax_trips(
2063 ardbeg_nct72_pdata.sensors[EXT].trips,
2064 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2065 tegra_add_tgpu_trips(
2066 ardbeg_nct72_pdata.sensors[EXT].trips,
2067 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2069 ardbeg_nct72_pdata.sensors[EXT].trips,
2070 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2071 tegra_add_core_vmax_trips(
2072 ardbeg_nct72_pdata.sensors[EXT].trips,
2073 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2076 /* vmin trips are bound to soctherm on norrin */
2077 if (!(board_info.board_id == BOARD_PM374) &&
2078 !(board_info.board_id == BOARD_PM375))
2079 tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
2080 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
2082 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
2084 ret = gpio_request(nct72_port, "temp_alert");
2088 ret = gpio_direction_input(nct72_port);
2090 pr_info("%s: calling gpio_free(nct72_port)", __func__);
2091 gpio_free(nct72_port);
2094 /* norrin has thermal sensor on GEN1-I2C i.e. instance 0 */
2095 if (board_info.board_id == BOARD_PM374)
2096 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2097 1); /* only register device[0] */
2098 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
2099 else if (board_info.board_id == BOARD_PM358 ||
2100 board_info.board_id == BOARD_PM359 ||
2101 board_info.board_id == BOARD_PM370 ||
2102 board_info.board_id == BOARD_PM363)
2103 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2104 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2105 else if (board_info.board_id == BOARD_PM375 ||
2106 board_info.board_id == BOARD_PM377) {
2107 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 105;
2108 ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 100;
2109 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
2110 1); /* only register device[0] */
2113 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
2114 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
2119 struct ntc_thermistor_adc_table {
2120 int temp; /* degree C */
2124 static struct ntc_thermistor_adc_table tn8_thermistor_table[] = {
2125 { -40, 2578 }, { -39, 2577 }, { -38, 2576 }, { -37, 2575 },
2126 { -36, 2574 }, { -35, 2573 }, { -34, 2572 }, { -33, 2571 },
2127 { -32, 2569 }, { -31, 2568 }, { -30, 2567 }, { -29, 2565 },
2128 { -28, 2563 }, { -27, 2561 }, { -26, 2559 }, { -25, 2557 },
2129 { -24, 2555 }, { -23, 2553 }, { -22, 2550 }, { -21, 2548 },
2130 { -20, 2545 }, { -19, 2542 }, { -18, 2539 }, { -17, 2536 },
2131 { -16, 2532 }, { -15, 2529 }, { -14, 2525 }, { -13, 2521 },
2132 { -12, 2517 }, { -11, 2512 }, { -10, 2507 }, { -9, 2502 },
2133 { -8, 2497 }, { -7, 2492 }, { -6, 2486 }, { -5, 2480 },
2134 { -4, 2473 }, { -3, 2467 }, { -2, 2460 }, { -1, 2452 },
2135 { 0, 2445 }, { 1, 2437 }, { 2, 2428 }, { 3, 2419 },
2136 { 4, 2410 }, { 5, 2401 }, { 6, 2391 }, { 7, 2380 },
2137 { 8, 2369 }, { 9, 2358 }, { 10, 2346 }, { 11, 2334 },
2138 { 12, 2322 }, { 13, 2308 }, { 14, 2295 }, { 15, 2281 },
2139 { 16, 2266 }, { 17, 2251 }, { 18, 2236 }, { 19, 2219 },
2140 { 20, 2203 }, { 21, 2186 }, { 22, 2168 }, { 23, 2150 },
2141 { 24, 2131 }, { 25, 2112 }, { 26, 2092 }, { 27, 2072 },
2142 { 28, 2052 }, { 29, 2030 }, { 30, 2009 }, { 31, 1987 },
2143 { 32, 1964 }, { 33, 1941 }, { 34, 1918 }, { 35, 1894 },
2144 { 36, 1870 }, { 37, 1845 }, { 38, 1820 }, { 39, 1795 },
2145 { 40, 1769 }, { 41, 1743 }, { 42, 1717 }, { 43, 1691 },
2146 { 44, 1664 }, { 45, 1637 }, { 46, 1610 }, { 47, 1583 },
2147 { 48, 1555 }, { 49, 1528 }, { 50, 1500 }, { 51, 1472 },
2148 { 52, 1445 }, { 53, 1417 }, { 54, 1390 }, { 55, 1362 },
2149 { 56, 1334 }, { 57, 1307 }, { 58, 1280 }, { 59, 1253 },
2150 { 60, 1226 }, { 61, 1199 }, { 62, 1172 }, { 63, 1146 },
2151 { 64, 1120 }, { 65, 1094 }, { 66, 1069 }, { 67, 1044 },
2152 { 68, 1019 }, { 69, 994 }, { 70, 970 }, { 71, 946 },
2153 { 72, 922 }, { 73, 899 }, { 74, 877 }, { 75, 854 },
2154 { 76, 832 }, { 77, 811 }, { 78, 789 }, { 79, 769 },
2155 { 80, 748 }, { 81, 729 }, { 82, 709 }, { 83, 690 },
2156 { 84, 671 }, { 85, 653 }, { 86, 635 }, { 87, 618 },
2157 { 88, 601 }, { 89, 584 }, { 90, 568 }, { 91, 552 },
2158 { 92, 537 }, { 93, 522 }, { 94, 507 }, { 95, 493 },
2159 { 96, 479 }, { 97, 465 }, { 98, 452 }, { 99, 439 },
2160 { 100, 427 }, { 101, 415 }, { 102, 403 }, { 103, 391 },
2161 { 104, 380 }, { 105, 369 }, { 106, 359 }, { 107, 349 },
2162 { 108, 339 }, { 109, 329 }, { 110, 320 }, { 111, 310 },
2163 { 112, 302 }, { 113, 293 }, { 114, 285 }, { 115, 277 },
2164 { 116, 269 }, { 117, 261 }, { 118, 254 }, { 119, 247 },
2165 { 120, 240 }, { 121, 233 }, { 122, 226 }, { 123, 220 },
2166 { 124, 214 }, { 125, 208 },
2169 static struct ntc_thermistor_adc_table *thermistor_table;
2170 static int thermistor_table_size;
2172 static int gadc_thermal_thermistor_adc_to_temp(
2173 struct gadc_thermal_platform_data *pdata, int val, int val2)
2175 int temp = 0, adc_hi, adc_lo;
2178 for (i = 0; i < thermistor_table_size; i++)
2179 if (val >= thermistor_table[i].adc)
2183 temp = thermistor_table[i].temp * 1000;
2184 } else if (i >= (thermistor_table_size - 1)) {
2185 temp = thermistor_table[thermistor_table_size - 1].temp * 1000;
2187 adc_hi = thermistor_table[i - 1].adc;
2188 adc_lo = thermistor_table[i].adc;
2189 temp = thermistor_table[i].temp * 1000;
2190 temp -= ((val - adc_lo) * 1000 / (adc_hi - adc_lo));
2196 #define TDIODE_PRECISION_MULTIPLIER 1000000000LL
2197 #define TDIODE_MIN_TEMP -25000LL
2198 #define TDIODE_MAX_TEMP 125000LL
2200 static int gadc_thermal_tdiode_adc_to_temp(
2201 struct gadc_thermal_platform_data *pdata, int val, int val2)
2204 * Series resistance cancellation using multi-current ADC measurement.
2205 * diode temp = ((adc2 - k * adc1) - (b2 - k * b1)) / (m2 - k * m1)
2206 * - adc1 : ADC raw with current source 400uA
2207 * - m1, b1 : calculated with current source 400uA
2208 * - adc2 : ADC raw with current source 800uA
2209 * - m2, b2 : calculated with current source 800uA
2210 * - k : 2 (= 800uA / 400uA)
2212 const s64 m1 = -0.00571005 * TDIODE_PRECISION_MULTIPLIER;
2213 const s64 b1 = 2524.29891 * TDIODE_PRECISION_MULTIPLIER;
2214 const s64 m2 = -0.005519811 * TDIODE_PRECISION_MULTIPLIER;
2215 const s64 b2 = 2579.354349 * TDIODE_PRECISION_MULTIPLIER;
2216 s64 temp = TDIODE_PRECISION_MULTIPLIER;
2218 temp *= (s64)((val2) - 2 * (val));
2219 temp -= (b2 - 2 * b1);
2220 temp = div64_s64(temp, (m2 - 2 * m1));
2221 temp = min_t(s64, max_t(s64, temp, TDIODE_MIN_TEMP), TDIODE_MAX_TEMP);
2225 static struct gadc_thermal_platform_data gadc_thermal_thermistor_pdata = {
2226 .iio_channel_name = "thermistor",
2227 .tz_name = "Tboard",
2229 .adc_to_temp = gadc_thermal_thermistor_adc_to_temp,
2231 .polling_delay = 15000,
2235 .cdev_type = "therm_est_activ",
2237 .trip_type = THERMAL_TRIP_ACTIVE,
2239 .upper = THERMAL_NO_LIMIT,
2240 .lower = THERMAL_NO_LIMIT,
2247 static struct gadc_thermal_platform_data gadc_thermal_tdiode_pdata = {
2248 .iio_channel_name = "tdiode",
2249 .tz_name = "Tdiode",
2252 .adc_to_temp = gadc_thermal_tdiode_adc_to_temp,
2255 static struct platform_device gadc_thermal_thermistor = {
2256 .name = "generic-adc-thermal",
2259 .platform_data = &gadc_thermal_thermistor_pdata,
2263 static struct platform_device gadc_thermal_tdiode = {
2264 .name = "generic-adc-thermal",
2267 .platform_data = &gadc_thermal_tdiode_pdata,
2271 static struct platform_device *gadc_thermal_devices[] = {
2272 &gadc_thermal_thermistor,
2273 &gadc_thermal_tdiode,
2276 int __init ardbeg_sensors_init(void)
2278 struct board_info board_info;
2279 tegra_get_board_info(&board_info);
2280 /* PM363 and PM359 don't have mpu 9250 mounted */
2281 /* TN8 sensors use Device Tree */
2282 if (board_info.board_id != BOARD_PM363 &&
2283 board_info.board_id != BOARD_PM359 &&
2284 !of_machine_is_compatible("nvidia,tn8") &&
2285 !of_machine_is_compatible("nvidia,bowmore") &&
2286 board_info.board_id != BOARD_PM375 &&
2287 board_info.board_id != BOARD_PM377)
2289 ardbeg_camera_init();
2291 if (board_info.board_id == BOARD_P1761 ||
2292 board_info.board_id == BOARD_E1784 ||
2293 board_info.board_id == BOARD_E1971 ||
2294 board_info.board_id == BOARD_E1991 ||
2295 board_info.board_id == BOARD_E1922) {
2296 platform_add_devices(gadc_thermal_devices,
2297 ARRAY_SIZE(gadc_thermal_devices));
2298 thermistor_table = &tn8_thermistor_table[0];
2299 thermistor_table_size = ARRAY_SIZE(tn8_thermistor_table);
2301 ardbeg_nct72_init();
2303 #if defined(ARCH_TEGRA_12x_SOC)
2304 /* TN8 and PM359 don't have ALS CM32181 */
2305 if (!of_machine_is_compatible("nvidia,tn8") &&
2306 board_info.board_id != BOARD_PM359 &&
2307 board_info.board_id != BOARD_PM375 &&
2308 board_info.board_id != BOARD_PM377)
2309 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
2310 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));