2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/i2c.h>
17 #include <linux/gpio.h>
18 #include <linux/mpu.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/nct1008.h>
22 #include <linux/pid_thermal_gov.h>
23 #include <linux/tegra-fuse.h>
24 #include <linux/of_platform.h>
26 #include <mach/pinmux-t12.h>
27 #include <mach/pinmux.h>
28 #include <mach/io_dpd.h>
29 #include <media/camera.h>
30 #include <media/ar0261.h>
31 #include <media/imx135.h>
32 #include <media/imx179.h>
33 #include <media/dw9718.h>
34 #include <media/as364x.h>
35 #include <media/ov5693.h>
36 #include <media/ov7695.h>
37 #include <media/mt9m114.h>
38 #include <media/ad5823.h>
39 #include <media/max77387.h>
41 #include <linux/platform_device.h>
42 #include <media/soc_camera.h>
43 #include <media/soc_camera_platform.h>
44 #include <media/tegra_v4l2_camera.h>
45 #include <linux/generic_adc_thermal.h>
47 #include "cpu-tegra.h"
50 #include "board-common.h"
51 #include "board-ardbeg.h"
52 #include "tegra-board-id.h"
54 #if defined(ARCH_TEGRA_12x_SOC)
55 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
57 I2C_BOARD_INFO("cm32181", 0x48),
62 /* MPU board file definition */
63 static struct mpu_platform_data mpu9250_gyro_data = {
66 /* Located in board_[platformname].h */
67 .orientation = MPU_GYRO_ORIENTATION,
68 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
69 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
70 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
73 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
76 /* Located in board_[platformname].h */
77 .orientation = MPU_GYRO_ORIENTATION_E1762,
78 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
79 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
80 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
83 static struct mpu_platform_data mpu_compass_data = {
84 .orientation = MPU_COMPASS_ORIENTATION,
85 .config = NVI_CONFIG_BOOT_MPU,
88 static struct mpu_platform_data mpu_bmp_pdata = {
89 .config = NVI_CONFIG_BOOT_MPU,
92 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
94 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
95 .platform_data = &mpu9250_gyro_data,
98 /* The actual BMP180 address is 0x77 but because this conflicts
99 * with another device, this address is hacked so Linux will
100 * call the driver. The conflict is technically okay since the
101 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
102 * hard-coded address of 0x77 since it can't be changed anyway.
104 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
105 .platform_data = &mpu_bmp_pdata,
108 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
109 .platform_data = &mpu_compass_data,
113 static void mpuirq_init(void)
116 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
117 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
118 char *gyro_name = MPU_GYRO_NAME;
119 struct board_info board_info;
121 pr_info("*** MPU START *** mpuirq_init...\n");
123 tegra_get_board_info(&board_info);
125 ret = gpio_request(gyro_irq_gpio, gyro_name);
127 pr_err("%s: gpio_request failed %d\n", __func__, ret);
131 ret = gpio_direction_input(gyro_irq_gpio);
133 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
134 gpio_free(gyro_irq_gpio);
137 pr_info("*** MPU END *** mpuirq_init...\n");
139 /* TN8 with diferent Compass address from ardbeg */
140 if (of_machine_is_compatible("nvidia,tn8"))
141 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
143 if (board_info.board_id == BOARD_E1762)
144 inv_mpu9250_i2c0_board_info[0].platform_data =
145 &mpu9250_gyro_data_e1762;
146 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
147 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
148 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
152 * Soc Camera platform driver for testing
154 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
155 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
156 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
158 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
161 /* TODO: probably add clk opertaion here */
162 return 0; /* camera sensor always enabled */
165 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
166 .format_name = "RGB4",
169 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
170 .colorspace = V4L2_COLORSPACE_SRGB,
171 .field = V4L2_FIELD_NONE,
175 .set_capture = ardbeg_soc_camera_set_capture,
178 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
181 .port = TEGRA_CAMERA_PORT_CSI_A,
186 static struct soc_camera_link ardbeg_soc_camera_link = {
187 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
188 .add_device = ardbeg_soc_camera_add,
189 .del_device = ardbeg_soc_camera_del,
190 .module_name = "soc_camera_platform",
191 .priv = &ardbeg_camera_platform_data,
192 .dev_priv = &ardbeg_soc_camera_info,
195 static struct platform_device *ardbeg_pdev;
197 static void ardbeg_soc_camera_release(struct device *dev)
199 soc_camera_platform_release(&ardbeg_pdev);
202 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
204 return soc_camera_platform_add(icd, &ardbeg_pdev,
205 &ardbeg_soc_camera_link,
206 ardbeg_soc_camera_release, 0);
209 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
211 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
214 static struct platform_device ardbeg_soc_camera_device = {
215 .name = "soc-camera-pdrv",
218 .platform_data = &ardbeg_soc_camera_link,
223 static struct regulator *ardbeg_vcmvdd;
225 static int ardbeg_get_extra_regulators(void)
227 if (!ardbeg_vcmvdd) {
228 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
229 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
230 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
231 __func__, PTR_ERR(ardbeg_vcmvdd));
232 regulator_put(ardbeg_vcmvdd);
233 ardbeg_vcmvdd = NULL;
241 static struct tegra_io_dpd csia_io = {
243 .io_dpd_reg_index = 0,
247 static struct tegra_io_dpd csib_io = {
249 .io_dpd_reg_index = 0,
253 static struct tegra_io_dpd csie_io = {
255 .io_dpd_reg_index = 1,
259 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
263 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
266 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
267 tegra_io_dpd_disable(&csie_io);
269 if (ardbeg_get_extra_regulators())
270 goto ardbeg_ar0261_poweron_fail;
272 gpio_set_value(CAM_RSTN, 0);
273 gpio_set_value(CAM_AF_PWDN, 1);
276 err = regulator_enable(ardbeg_vcmvdd);
278 goto ar0261_vcm_fail;
280 err = regulator_enable(pw->dvdd);
282 goto ar0261_dvdd_fail;
284 err = regulator_enable(pw->avdd);
286 goto ar0261_avdd_fail;
288 err = regulator_enable(pw->iovdd);
290 goto ar0261_iovdd_fail;
293 gpio_set_value(CAM2_PWDN, 1);
295 gpio_set_value(CAM_RSTN, 1);
299 regulator_disable(pw->dvdd);
302 regulator_disable(pw->avdd);
305 regulator_disable(ardbeg_vcmvdd);
308 pr_err("%s vcmvdd failed.\n", __func__);
311 ardbeg_ar0261_poweron_fail:
312 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
313 tegra_io_dpd_enable(&csie_io);
314 pr_err("%s failed.\n", __func__);
318 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
320 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
322 /* put CSIE IOs into DPD mode to
323 * save additional power for ardbeg
325 tegra_io_dpd_enable(&csie_io);
329 gpio_set_value(CAM_RSTN, 0);
333 regulator_disable(pw->iovdd);
334 regulator_disable(pw->dvdd);
335 regulator_disable(pw->avdd);
336 regulator_disable(ardbeg_vcmvdd);
337 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
338 tegra_io_dpd_enable(&csie_io);
342 struct ar0261_platform_data ardbeg_ar0261_data = {
343 .power_on = ardbeg_ar0261_power_on,
344 .power_off = ardbeg_ar0261_power_off,
345 .mclk_name = "mclk2",
348 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
351 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
352 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
353 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
354 __func__, PTR_ERR(pw->ext_reg1));
361 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
362 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
363 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
364 __func__, PTR_ERR(pw->ext_reg2));
373 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
377 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
380 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
381 tegra_io_dpd_disable(&csia_io);
382 tegra_io_dpd_disable(&csib_io);
384 if (ardbeg_imx135_get_extra_regulators(pw))
385 goto imx135_poweron_fail;
387 err = regulator_enable(pw->ext_reg1);
389 goto imx135_ext_reg1_fail;
391 err = regulator_enable(pw->ext_reg2);
393 goto imx135_ext_reg2_fail;
396 gpio_set_value(CAM_AF_PWDN, 1);
397 gpio_set_value(CAM1_PWDN, 0);
398 usleep_range(10, 20);
400 err = regulator_enable(pw->avdd);
402 goto imx135_avdd_fail;
404 err = regulator_enable(pw->iovdd);
406 goto imx135_iovdd_fail;
409 gpio_set_value(CAM1_PWDN, 1);
411 usleep_range(300, 310);
417 regulator_disable(pw->avdd);
421 regulator_disable(pw->ext_reg2);
423 imx135_ext_reg2_fail:
425 regulator_disable(pw->ext_reg1);
426 gpio_set_value(CAM_AF_PWDN, 0);
428 imx135_ext_reg1_fail:
430 tegra_io_dpd_enable(&csia_io);
431 tegra_io_dpd_enable(&csib_io);
432 pr_err("%s failed.\n", __func__);
436 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
438 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
439 tegra_io_dpd_enable(&csia_io);
440 tegra_io_dpd_enable(&csib_io);
444 regulator_disable(pw->iovdd);
445 regulator_disable(pw->avdd);
447 regulator_disable(pw->ext_reg1);
448 regulator_disable(pw->ext_reg2);
450 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
451 tegra_io_dpd_enable(&csia_io);
452 tegra_io_dpd_enable(&csib_io);
456 static int ardbeg_imx179_power_on(struct imx179_power_rail *pw)
460 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
463 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
464 tegra_io_dpd_disable(&csia_io);
465 tegra_io_dpd_disable(&csib_io);
467 gpio_set_value(CAM_AF_PWDN, 1);
468 gpio_set_value(CAM_RSTN, 0);
469 gpio_set_value(CAM1_PWDN, 0);
470 usleep_range(10, 20);
472 err = regulator_enable(pw->avdd);
474 goto imx179_avdd_fail;
476 err = regulator_enable(pw->iovdd);
478 goto imx179_iovdd_fail;
480 err = regulator_enable(pw->dvdd);
482 goto imx179_dvdd_fail;
485 gpio_set_value(CAM_RSTN, 1);
487 usleep_range(300, 310);
493 regulator_disable(pw->iovdd);
496 regulator_disable(pw->avdd);
499 tegra_io_dpd_enable(&csia_io);
500 tegra_io_dpd_enable(&csib_io);
501 pr_err("%s failed.\n", __func__);
505 static int ardbeg_imx179_power_off(struct imx179_power_rail *pw)
507 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
508 tegra_io_dpd_enable(&csia_io);
509 tegra_io_dpd_enable(&csib_io);
513 regulator_disable(pw->dvdd);
514 regulator_disable(pw->iovdd);
515 regulator_disable(pw->avdd);
517 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
518 tegra_io_dpd_enable(&csia_io);
519 tegra_io_dpd_enable(&csib_io);
523 struct imx135_platform_data ardbeg_imx135_data = {
531 .power_on = ardbeg_imx135_power_on,
532 .power_off = ardbeg_imx135_power_off,
535 struct imx179_platform_data ardbeg_imx179_data = {
543 .power_on = ardbeg_imx179_power_on,
544 .power_off = ardbeg_imx179_power_off,
547 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
550 pr_info("%s\n", __func__);
552 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c))
555 err = regulator_enable(pw->vdd);
557 goto dw9718_vdd_fail;
559 err = regulator_enable(pw->vdd_i2c);
561 goto dw9718_i2c_fail;
563 usleep_range(1000, 1020);
565 /* return 1 to skip the in-driver power_on sequence */
566 pr_debug("%s --\n", __func__);
570 regulator_disable(pw->vdd);
573 pr_err("%s FAILED\n", __func__);
577 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
579 pr_info("%s\n", __func__);
581 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c))
584 regulator_disable(pw->vdd);
585 regulator_disable(pw->vdd_i2c);
590 static u16 dw9718_devid;
591 static int ardbeg_dw9718_detect(void *buf, size_t size)
593 dw9718_devid = 0x9718;
597 static struct nvc_focus_cap dw9718_cap = {
599 .slew_rate = 0x3A200C,
601 .focus_infinity = 200,
605 static struct dw9718_platform_data ardbeg_dw9718_data = {
606 .cfg = NVC_CFG_NODEV,
609 .dev_name = "focuser",
611 .power_on = ardbeg_dw9718_power_on,
612 .power_off = ardbeg_dw9718_power_off,
613 .detect = ardbeg_dw9718_detect,
616 static struct as364x_platform_data ardbeg_as3648_data = {
619 .max_total_current_mA = 1000,
620 .max_peak_current_mA = 600,
621 .max_torch_current_mA = 600,
622 .vin_low_v_run_mV = 3070,
626 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
627 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
631 .gpio_strobe = CAM_FLASH_STROBE,
634 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
638 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
641 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
642 tegra_io_dpd_disable(&csie_io);
644 gpio_set_value(CAM2_PWDN, 0);
645 usleep_range(1000, 1020);
647 err = regulator_enable(pw->avdd);
649 goto ov7695_avdd_fail;
650 usleep_range(300, 320);
652 err = regulator_enable(pw->iovdd);
654 goto ov7695_iovdd_fail;
655 usleep_range(1000, 1020);
657 gpio_set_value(CAM2_PWDN, 1);
658 usleep_range(1000, 1020);
663 regulator_disable(pw->avdd);
666 gpio_set_value(CAM_RSTN, 0);
667 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
668 tegra_io_dpd_enable(&csie_io);
672 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
674 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
675 /* put CSIE IOs into DPD mode to
676 * save additional power for ardbeg
678 tegra_io_dpd_enable(&csie_io);
681 usleep_range(100, 120);
683 gpio_set_value(CAM2_PWDN, 0);
684 usleep_range(100, 120);
686 regulator_disable(pw->iovdd);
687 usleep_range(100, 120);
689 regulator_disable(pw->avdd);
691 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
692 tegra_io_dpd_enable(&csie_io);
696 struct ov7695_platform_data ardbeg_ov7695_pdata = {
697 .power_on = ardbeg_ov7695_power_on,
698 .power_off = ardbeg_ov7695_power_off,
699 .mclk_name = "mclk2",
702 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
705 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
708 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
709 tegra_io_dpd_disable(&csie_io);
711 gpio_set_value(CAM_RSTN, 0);
712 gpio_set_value(CAM2_PWDN, 1);
713 usleep_range(1000, 1020);
715 err = regulator_enable(pw->iovdd);
717 goto mt9m114_iovdd_fail;
719 err = regulator_enable(pw->avdd);
721 goto mt9m114_avdd_fail;
723 usleep_range(1000, 1020);
724 gpio_set_value(CAM_RSTN, 1);
725 gpio_set_value(CAM2_PWDN, 0);
726 usleep_range(1000, 1020);
728 /* return 1 to skip the in-driver power_on swquence */
732 regulator_disable(pw->iovdd);
735 gpio_set_value(CAM_RSTN, 0);
736 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
737 tegra_io_dpd_enable(&csie_io);
741 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
743 if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
744 /* put CSIE IOs into DPD mode to
745 * save additional power for ardbeg
747 tegra_io_dpd_enable(&csie_io);
751 usleep_range(100, 120);
752 gpio_set_value(CAM_RSTN, 0);
753 usleep_range(100, 120);
754 regulator_disable(pw->avdd);
755 usleep_range(100, 120);
756 regulator_disable(pw->iovdd);
758 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
759 tegra_io_dpd_enable(&csie_io);
763 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
764 .power_on = ardbeg_mt9m114_power_on,
765 .power_off = ardbeg_mt9m114_power_off,
766 .mclk_name = "mclk2",
770 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
774 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
777 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
778 tegra_io_dpd_disable(&csia_io);
779 tegra_io_dpd_disable(&csib_io);
781 if (ardbeg_get_extra_regulators())
782 goto ov5693_poweron_fail;
784 gpio_set_value(CAM1_PWDN, 0);
785 usleep_range(10, 20);
787 err = regulator_enable(pw->avdd);
789 goto ov5693_avdd_fail;
791 err = regulator_enable(pw->dovdd);
793 goto ov5693_iovdd_fail;
796 gpio_set_value(CAM1_PWDN, 1);
798 err = regulator_enable(ardbeg_vcmvdd);
800 goto ov5693_vcmvdd_fail;
802 usleep_range(1000, 1110);
807 regulator_disable(pw->dovdd);
810 regulator_disable(pw->avdd);
813 gpio_set_value(CAM1_PWDN, 0);
816 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
817 tegra_io_dpd_enable(&csia_io);
818 tegra_io_dpd_enable(&csib_io);
819 pr_err("%s FAILED\n", __func__);
823 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
825 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
826 /* put CSIA/B IOs into DPD mode to
827 * save additional power for ardbeg
829 tegra_io_dpd_enable(&csia_io);
830 tegra_io_dpd_enable(&csib_io);
834 usleep_range(21, 25);
835 gpio_set_value(CAM1_PWDN, 0);
838 regulator_disable(ardbeg_vcmvdd);
839 regulator_disable(pw->dovdd);
840 regulator_disable(pw->avdd);
842 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
843 tegra_io_dpd_enable(&csia_io);
844 tegra_io_dpd_enable(&csib_io);
848 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
849 { OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0, },
852 #define NV_GUID(a, b, c, d, e, f, g, h) \
853 ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
854 (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
855 (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
856 (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
858 static struct nvc_imager_cap ov5693_cap = {
859 .identifier = "OV5693",
860 .sensor_nvc_interface = 3,
861 .pixel_types[0] = 0x101,
864 .initial_clock_rate_khz = 6000,
865 .clock_profiles[0] = {
866 .external_clock_khz = 24000,
867 .clock_multiplier = 8000000, /* value * 1000000 */
869 .clock_profiles[1] = {
870 .external_clock_khz = 0,
871 .clock_multiplier = 0,
878 .virtual_channel_id = 0,
879 .discontinuous_clk_mode = 1,
880 .cil_threshold_settle = 0,
881 .min_blank_time_width = 16,
882 .min_blank_time_height = 16,
883 .preferred_mode_index = 0,
885 NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
887 NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
888 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
889 .flash_control_enabled = 0,
890 .adjustable_flash_timing = 0,
895 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
896 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
897 .gpio = ov5693_gpio_pdata,
898 .power_on = ardbeg_ov5693_power_on,
899 .power_off = ardbeg_ov5693_power_off,
900 .dev_name = "ov5693",
904 .avdd = "avdd_ov5693",
911 static int ardbeg_ov5693_front_power_on(struct ov5693_power_rail *pw)
915 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
918 if (ardbeg_get_extra_regulators())
919 goto ov5693_front_poweron_fail;
921 gpio_set_value(CAM2_PWDN, 0);
922 gpio_set_value(CAM_RSTN, 0);
923 usleep_range(10, 20);
925 err = regulator_enable(pw->avdd);
927 goto ov5693_front_avdd_fail;
929 err = regulator_enable(pw->dovdd);
931 goto ov5693_front_iovdd_fail;
934 gpio_set_value(CAM2_PWDN, 1);
935 gpio_set_value(CAM_RSTN, 1);
937 err = regulator_enable(ardbeg_vcmvdd);
939 goto ov5693_front_vcmvdd_fail;
941 usleep_range(1000, 1110);
945 ov5693_front_vcmvdd_fail:
946 regulator_disable(pw->dovdd);
948 ov5693_front_iovdd_fail:
949 regulator_disable(pw->avdd);
951 ov5693_front_avdd_fail:
952 gpio_set_value(CAM2_PWDN, 0);
953 gpio_set_value(CAM_RSTN, 0);
955 ov5693_front_poweron_fail:
956 pr_err("%s FAILED\n", __func__);
960 static int ardbeg_ov5693_front_power_off(struct ov5693_power_rail *pw)
962 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
966 usleep_range(21, 25);
967 gpio_set_value(CAM2_PWDN, 0);
968 gpio_set_value(CAM_RSTN, 0);
971 regulator_disable(ardbeg_vcmvdd);
972 regulator_disable(pw->dovdd);
973 regulator_disable(pw->avdd);
978 static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
979 { OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0, },
980 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
983 static struct nvc_imager_cap ov5693_front_cap = {
984 .identifier = "OV5693.1",
985 .sensor_nvc_interface = 4,
986 .pixel_types[0] = 0x101,
989 .initial_clock_rate_khz = 6000,
990 .clock_profiles[0] = {
991 .external_clock_khz = 24000,
992 .clock_multiplier = 8000000, /* value * 1000000 */
994 .clock_profiles[1] = {
995 .external_clock_khz = 0,
996 .clock_multiplier = 0,
1003 .virtual_channel_id = 0,
1004 .discontinuous_clk_mode = 1,
1005 .cil_threshold_settle = 0,
1006 .min_blank_time_width = 16,
1007 .min_blank_time_height = 16,
1008 .preferred_mode_index = 0,
1011 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1012 .flash_control_enabled = 0,
1013 .adjustable_flash_timing = 0,
1017 static struct ov5693_platform_data ardbeg_ov5693_front_pdata = {
1018 .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
1019 .gpio = ov5693_front_gpio_pdata,
1020 .power_on = ardbeg_ov5693_front_power_on,
1021 .power_off = ardbeg_ov5693_front_power_off,
1022 .dev_name = "ov5693.1",
1023 .mclk_name = "mclk2",
1024 .cap = &ov5693_front_cap,
1033 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
1037 pr_info("%s\n", __func__);
1038 gpio_set_value_cansleep(pdata->gpio, 1);
1039 pdata->pwr_dev = AD5823_PWR_DEV_ON;
1044 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
1046 pr_info("%s\n", __func__);
1047 gpio_set_value_cansleep(pdata->gpio, 0);
1048 pdata->pwr_dev = AD5823_PWR_DEV_OFF;
1053 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
1054 .gpio = CAM_AF_PWDN,
1055 .power_on = ardbeg_ad5823_power_on,
1056 .power_off = ardbeg_ad5823_power_off,
1059 static struct camera_data_blob ardbeg_camera_lut[] = {
1060 {"ardbeg_imx135_pdata", &ardbeg_imx135_data},
1061 {"ardbeg_dw9718_pdata", &ardbeg_dw9718_data},
1062 {"ardbeg_ar0261_pdata", &ardbeg_ar0261_data},
1063 {"ardbeg_mt9m114_pdata", &ardbeg_mt9m114_pdata},
1064 {"ardbeg_ov5693_pdata", &ardbeg_ov5693_pdata},
1065 {"ardbeg_ad5823_pdata", &ardbeg_ad5823_pdata},
1066 {"ardbeg_as3648_pdata", &ardbeg_as3648_data},
1067 {"ardbeg_ov7695_pdata", &ardbeg_ov7695_pdata},
1068 {"ardbeg_ov5693f_pdata", &ardbeg_ov5693_front_pdata},
1072 void __init ardbeg_camera_auxdata(void *data)
1074 struct of_dev_auxdata *aux_lut = data;
1075 while (aux_lut && aux_lut->compatible) {
1076 if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
1077 pr_info("%s: update camera lookup table.\n", __func__);
1078 aux_lut->platform_data = ardbeg_camera_lut;
1084 static int ardbeg_camera_init(void)
1086 struct board_info board_info;
1088 pr_debug("%s: ++\n", __func__);
1089 tegra_get_board_info(&board_info);
1091 /* put CSIA/B/C/D/E IOs into DPD mode to
1092 * save additional power for ardbeg
1094 tegra_io_dpd_enable(&csia_io);
1095 tegra_io_dpd_enable(&csib_io);
1096 tegra_io_dpd_enable(&csie_io);
1098 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
1099 platform_device_register(&ardbeg_soc_camera_device);
1105 static struct pid_thermal_gov_params cpu_pid_params = {
1106 .max_err_temp = 4000,
1107 .max_err_gain = 1000,
1112 .up_compensation = 15,
1113 .down_compensation = 15,
1116 static struct thermal_zone_params cpu_tzp = {
1117 .governor_name = "pid_thermal_gov",
1118 .governor_params = &cpu_pid_params,
1121 static struct thermal_zone_params board_tzp = {
1122 .governor_name = "pid_thermal_gov"
1125 static struct throttle_table cpu_throttle_table[] = {
1126 /* CPU_THROT_LOW cannot be used by other than CPU */
1127 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1128 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1129 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1130 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1131 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1132 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1133 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1134 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1135 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1136 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1137 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1138 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1139 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1140 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1141 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1142 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1143 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1144 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1145 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1146 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1147 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1148 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1149 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1150 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1151 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1152 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1153 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1154 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1155 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1156 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1157 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1158 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1159 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1160 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1161 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1162 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1163 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1164 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1165 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1166 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1167 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1168 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1169 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1170 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1171 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1172 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1173 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1174 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1175 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1176 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1177 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1178 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1179 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1180 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1181 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1182 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1183 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1184 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1185 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1186 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1187 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1188 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1189 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1190 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1191 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1192 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1193 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1194 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1195 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1196 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1197 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1198 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1199 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1200 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1201 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1202 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1203 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1204 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1205 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1206 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1207 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1208 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1209 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1210 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1213 static struct balanced_throttle cpu_throttle = {
1214 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1215 .throt_tab = cpu_throttle_table,
1218 static struct throttle_table gpu_throttle_table[] = {
1219 /* CPU_THROT_LOW cannot be used by other than CPU */
1220 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1221 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1222 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1223 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1224 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1225 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1226 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1227 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1228 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1229 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1230 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1231 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1232 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1233 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1234 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1235 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1236 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1237 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1238 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1239 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1240 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1241 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1242 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1243 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1244 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1245 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1246 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1247 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1248 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1249 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1250 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1251 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1252 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1253 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1254 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1255 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1256 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1257 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1258 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1259 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1260 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1261 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1262 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1263 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1264 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1265 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1266 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1267 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1268 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1269 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1270 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1271 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1272 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1273 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1274 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1275 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1276 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1277 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1278 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1279 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1280 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1281 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1282 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1283 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1284 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1285 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1286 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1287 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1288 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1289 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1290 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1291 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1292 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1293 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1294 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1295 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1296 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1297 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1298 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1299 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1300 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1301 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1302 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1303 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1306 static struct balanced_throttle gpu_throttle = {
1307 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1308 .throt_tab = gpu_throttle_table,
1311 /* throttle table that sets all clocks to approximately 50% of their max */
1312 static struct throttle_table emergency_throttle_table[] = {
1313 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1314 { { 1122000, 391000, 288000, 420000, 252000, 396000 } },
1317 static struct balanced_throttle emergency_throttle = {
1318 .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
1319 .throt_tab = emergency_throttle_table,
1322 static int __init ardbeg_balanced_throttle_init(void)
1324 if (of_machine_is_compatible("nvidia,ardbeg") ||
1325 of_machine_is_compatible("nvidia,norrin") ||
1326 of_machine_is_compatible("nvidia,bowmore") ||
1327 of_machine_is_compatible("nvidia,tn8")) {
1329 if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
1330 pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
1331 if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
1332 pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
1333 if (!balanced_throttle_register(&emergency_throttle,
1334 "emergency-balanced"))
1335 pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
1340 late_initcall(ardbeg_balanced_throttle_init);
1342 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1343 static struct thermal_trip_info skin_trips[] = {
1345 .cdev_type = "skin-balanced",
1347 .trip_type = THERMAL_TRIP_PASSIVE,
1348 .upper = THERMAL_NO_LIMIT,
1349 .lower = THERMAL_NO_LIMIT,
1354 static struct therm_est_subdevice skin_devs[] = {
1356 .dev_data = "Tdiode_tegra",
1366 .dev_data = "Tboard_tegra",
1377 static struct therm_est_subdevice tn8ffd_skin_devs[] = {
1379 .dev_data = "Tdiode",
1389 .dev_data = "Tboard",
1400 static struct therm_est_subdevice tn8ffd_t132_skin_devs[] = {
1402 .dev_data = "Tdiode",
1412 .dev_data = "Tboard",
1423 static struct pid_thermal_gov_params skin_pid_params = {
1424 .max_err_temp = 4000,
1425 .max_err_gain = 1000,
1430 .up_compensation = 15,
1431 .down_compensation = 15,
1434 static struct thermal_zone_params skin_tzp = {
1435 .governor_name = "pid_thermal_gov",
1436 .governor_params = &skin_pid_params,
1439 static struct therm_est_data skin_data = {
1440 .num_trips = ARRAY_SIZE(skin_trips),
1441 .trips = skin_trips,
1442 .polling_period = 1100,
1443 .passive_delay = 15000,
1450 static struct throttle_table skin_throttle_table[] = {
1451 /* CPU_THROT_LOW cannot be used by other than CPU */
1452 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1453 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1454 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1455 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1456 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1457 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1458 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1459 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1460 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1461 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1462 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1463 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1464 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1465 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1466 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1467 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1468 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1469 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1470 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1471 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1472 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1473 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1474 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1475 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1476 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1477 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1478 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1479 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1480 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1481 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1482 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1483 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1484 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1485 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1486 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1487 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1488 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1489 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1490 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1491 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1492 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1493 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1494 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1495 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1496 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1497 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1498 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1499 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1500 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1501 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1502 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1503 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1504 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1505 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1506 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1507 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1508 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1509 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1510 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1511 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1512 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1513 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1514 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1515 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1516 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1517 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1518 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1519 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1520 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1521 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1522 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1523 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1524 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1525 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1526 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1527 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1528 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1529 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1530 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1531 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1532 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1533 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1534 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1535 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1538 static struct balanced_throttle skin_throttle = {
1539 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1540 .throt_tab = skin_throttle_table,
1543 static int __init ardbeg_skin_init(void)
1545 struct board_info board_info;
1547 if (of_machine_is_compatible("nvidia,ardbeg") ||
1548 of_machine_is_compatible("nvidia,norrin") ||
1549 of_machine_is_compatible("nvidia,bowmore") ||
1550 of_machine_is_compatible("nvidia,tn8")) {
1552 tegra_get_board_info(&board_info);
1554 if (board_info.board_id == BOARD_P1761 &&
1555 board_info.fab == BOARD_FAB_D) {
1556 skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
1557 skin_data.devs = tn8ffd_t132_skin_devs;
1558 skin_data.toffset = 708;
1559 } else if (board_info.board_id == BOARD_P1761 ||
1560 board_info.board_id == BOARD_E1784 ||
1561 board_info.board_id == BOARD_E1971 ||
1562 board_info.board_id == BOARD_E1991 ||
1563 board_info.board_id == BOARD_E1922) {
1564 skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
1565 skin_data.devs = tn8ffd_skin_devs;
1566 skin_data.toffset = 4034;
1568 skin_data.ndevs = ARRAY_SIZE(skin_devs);
1569 skin_data.devs = skin_devs;
1570 skin_data.toffset = 9793;
1573 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1574 platform_device_register(&tegra_skin_therm_est_device);
1576 if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
1577 pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
1582 late_initcall(ardbeg_skin_init);
1585 static struct nct1008_platform_data ardbeg_nct72_pdata = {
1586 .loc_name = "tegra",
1587 .supported_hwrev = true,
1588 .conv_rate = 0x06, /* 4Hz conversion rate */
1590 .extended_range = true,
1595 .shutdown_limit = 120, /* C */
1596 .passive_delay = 1000,
1600 .cdev_type = "therm_est_activ",
1602 .trip_type = THERMAL_TRIP_ACTIVE,
1604 .upper = THERMAL_NO_LIMIT,
1605 .lower = THERMAL_NO_LIMIT,
1612 .shutdown_limit = 95, /* C */
1613 .passive_delay = 1000,
1617 .cdev_type = "shutdown_warning",
1619 .trip_type = THERMAL_TRIP_PASSIVE,
1620 .upper = THERMAL_NO_LIMIT,
1621 .lower = THERMAL_NO_LIMIT,
1625 .cdev_type = "cpu-balanced",
1627 .trip_type = THERMAL_TRIP_PASSIVE,
1628 .upper = THERMAL_NO_LIMIT,
1629 .lower = THERMAL_NO_LIMIT,
1638 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1639 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
1642 .supported_hwrev = true,
1643 .conv_rate = 0x06, /* 4Hz conversion rate */
1645 .extended_range = true,
1649 .shutdown_limit = 95, /* C */
1654 .shutdown_limit = 85, /* C */
1655 .passive_delay = 10000,
1656 .polling_delay = 1000,
1661 .cdev_type = "skin-balanced",
1663 .trip_type = THERMAL_TRIP_PASSIVE,
1664 .upper = THERMAL_NO_LIMIT,
1665 .lower = THERMAL_NO_LIMIT,
1674 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
1676 I2C_BOARD_INFO("nct72", 0x4c),
1677 .platform_data = &ardbeg_nct72_pdata,
1680 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1682 I2C_BOARD_INFO("nct72", 0x4d),
1683 .platform_data = &ardbeg_nct72_tskin_pdata,
1689 static int ardbeg_nct72_init(void)
1691 int nct72_port = TEGRA_GPIO_PI6;
1694 struct thermal_trip_info *trip_state;
1695 struct board_info board_info;
1697 tegra_get_board_info(&board_info);
1698 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
1699 if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
1700 (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
1701 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit += 20;
1702 for (i = 0; i < ardbeg_nct72_pdata.sensors[EXT].num_trips;
1704 trip_state = &ardbeg_nct72_pdata.sensors[EXT].trips[i];
1705 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
1706 THERMAL_NAME_LENGTH)) {
1707 trip_state->cdev_type = "_none_";
1712 tegra_platform_edp_init(
1713 ardbeg_nct72_pdata.sensors[EXT].trips,
1714 &ardbeg_nct72_pdata.sensors[EXT].num_trips,
1715 12000); /* edp temperature margin */
1716 tegra_add_cpu_vmax_trips(
1717 ardbeg_nct72_pdata.sensors[EXT].trips,
1718 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1719 tegra_add_tgpu_trips(
1720 ardbeg_nct72_pdata.sensors[EXT].trips,
1721 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1723 ardbeg_nct72_pdata.sensors[EXT].trips,
1724 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1725 tegra_add_core_vmax_trips(
1726 ardbeg_nct72_pdata.sensors[EXT].trips,
1727 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1730 /* vmin trips are bound to soctherm on norrin */
1731 if (!(board_info.board_id == BOARD_PM374))
1732 tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
1733 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1735 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
1737 ret = gpio_request(nct72_port, "temp_alert");
1741 ret = gpio_direction_input(nct72_port);
1743 pr_info("%s: calling gpio_free(nct72_port)", __func__);
1744 gpio_free(nct72_port);
1747 /* norrin has thermal sensor on GEN1-I2C i.e. instance 0 */
1748 if (board_info.board_id == BOARD_PM374)
1749 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
1750 1); /* only register device[0] */
1751 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
1752 else if (board_info.board_id == BOARD_PM358 ||
1753 board_info.board_id == BOARD_PM359 ||
1754 board_info.board_id == BOARD_PM370 ||
1755 board_info.board_id == BOARD_PM363)
1756 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
1757 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
1758 else if (board_info.board_id == BOARD_PM375 ||
1759 board_info.board_id == BOARD_PM377) {
1760 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 100;
1761 ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 95;
1762 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
1763 1); /* only register device[0] */
1766 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
1767 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
1772 struct ntc_thermistor_adc_table {
1773 int temp; /* degree C */
1777 static struct ntc_thermistor_adc_table tn8_thermistor_table[] = {
1778 { -40, 2578 }, { -39, 2577 }, { -38, 2576 }, { -37, 2575 },
1779 { -36, 2574 }, { -35, 2573 }, { -34, 2572 }, { -33, 2571 },
1780 { -32, 2569 }, { -31, 2568 }, { -30, 2567 }, { -29, 2565 },
1781 { -28, 2563 }, { -27, 2561 }, { -26, 2559 }, { -25, 2557 },
1782 { -24, 2555 }, { -23, 2553 }, { -22, 2550 }, { -21, 2548 },
1783 { -20, 2545 }, { -19, 2542 }, { -18, 2539 }, { -17, 2536 },
1784 { -16, 2532 }, { -15, 2529 }, { -14, 2525 }, { -13, 2521 },
1785 { -12, 2517 }, { -11, 2512 }, { -10, 2507 }, { -9, 2502 },
1786 { -8, 2497 }, { -7, 2492 }, { -6, 2486 }, { -5, 2480 },
1787 { -4, 2473 }, { -3, 2467 }, { -2, 2460 }, { -1, 2452 },
1788 { 0, 2445 }, { 1, 2437 }, { 2, 2428 }, { 3, 2419 },
1789 { 4, 2410 }, { 5, 2401 }, { 6, 2391 }, { 7, 2380 },
1790 { 8, 2369 }, { 9, 2358 }, { 10, 2346 }, { 11, 2334 },
1791 { 12, 2322 }, { 13, 2308 }, { 14, 2295 }, { 15, 2281 },
1792 { 16, 2266 }, { 17, 2251 }, { 18, 2236 }, { 19, 2219 },
1793 { 20, 2203 }, { 21, 2186 }, { 22, 2168 }, { 23, 2150 },
1794 { 24, 2131 }, { 25, 2112 }, { 26, 2092 }, { 27, 2072 },
1795 { 28, 2052 }, { 29, 2030 }, { 30, 2009 }, { 31, 1987 },
1796 { 32, 1964 }, { 33, 1941 }, { 34, 1918 }, { 35, 1894 },
1797 { 36, 1870 }, { 37, 1845 }, { 38, 1820 }, { 39, 1795 },
1798 { 40, 1769 }, { 41, 1743 }, { 42, 1717 }, { 43, 1691 },
1799 { 44, 1664 }, { 45, 1637 }, { 46, 1610 }, { 47, 1583 },
1800 { 48, 1555 }, { 49, 1528 }, { 50, 1500 }, { 51, 1472 },
1801 { 52, 1445 }, { 53, 1417 }, { 54, 1390 }, { 55, 1362 },
1802 { 56, 1334 }, { 57, 1307 }, { 58, 1280 }, { 59, 1253 },
1803 { 60, 1226 }, { 61, 1199 }, { 62, 1172 }, { 63, 1146 },
1804 { 64, 1120 }, { 65, 1094 }, { 66, 1069 }, { 67, 1044 },
1805 { 68, 1019 }, { 69, 994 }, { 70, 970 }, { 71, 946 },
1806 { 72, 922 }, { 73, 899 }, { 74, 877 }, { 75, 854 },
1807 { 76, 832 }, { 77, 811 }, { 78, 789 }, { 79, 769 },
1808 { 80, 748 }, { 81, 729 }, { 82, 709 }, { 83, 690 },
1809 { 84, 671 }, { 85, 653 }, { 86, 635 }, { 87, 618 },
1810 { 88, 601 }, { 89, 584 }, { 90, 568 }, { 91, 552 },
1811 { 92, 537 }, { 93, 522 }, { 94, 507 }, { 95, 493 },
1812 { 96, 479 }, { 97, 465 }, { 98, 452 }, { 99, 439 },
1813 { 100, 427 }, { 101, 415 }, { 102, 403 }, { 103, 391 },
1814 { 104, 380 }, { 105, 369 }, { 106, 359 }, { 107, 349 },
1815 { 108, 339 }, { 109, 329 }, { 110, 320 }, { 111, 310 },
1816 { 112, 302 }, { 113, 293 }, { 114, 285 }, { 115, 277 },
1817 { 116, 269 }, { 117, 261 }, { 118, 254 }, { 119, 247 },
1818 { 120, 240 }, { 121, 233 }, { 122, 226 }, { 123, 220 },
1819 { 124, 214 }, { 125, 208 },
1822 static struct ntc_thermistor_adc_table *thermistor_table;
1823 static int thermistor_table_size;
1825 static int gadc_thermal_thermistor_adc_to_temp(
1826 struct gadc_thermal_platform_data *pdata, int val, int val2)
1828 int temp = 0, adc_hi, adc_lo;
1831 for (i = 0; i < thermistor_table_size; i++)
1832 if (val >= thermistor_table[i].adc)
1836 temp = thermistor_table[i].temp * 1000;
1837 } else if (i >= (thermistor_table_size - 1)) {
1838 temp = thermistor_table[thermistor_table_size - 1].temp * 1000;
1840 adc_hi = thermistor_table[i - 1].adc;
1841 adc_lo = thermistor_table[i].adc;
1842 temp = thermistor_table[i].temp * 1000;
1843 temp -= ((val - adc_lo) * 1000 / (adc_hi - adc_lo));
1849 #define TDIODE_PRECISION_MULTIPLIER 1000000000LL
1850 #define TDIODE_MIN_TEMP -25000LL
1851 #define TDIODE_MAX_TEMP 125000LL
1853 static int gadc_thermal_tdiode_adc_to_temp(
1854 struct gadc_thermal_platform_data *pdata, int val, int val2)
1857 * Series resistance cancellation using multi-current ADC measurement.
1858 * diode temp = ((adc2 - k * adc1) - (b2 - k * b1)) / (m2 - k * m1)
1859 * - adc1 : ADC raw with current source 400uA
1860 * - m1, b1 : calculated with current source 400uA
1861 * - adc2 : ADC raw with current source 800uA
1862 * - m2, b2 : calculated with current source 800uA
1863 * - k : 2 (= 800uA / 400uA)
1865 const s64 m1 = -0.00571005 * TDIODE_PRECISION_MULTIPLIER;
1866 const s64 b1 = 2524.29891 * TDIODE_PRECISION_MULTIPLIER;
1867 const s64 m2 = -0.005519811 * TDIODE_PRECISION_MULTIPLIER;
1868 const s64 b2 = 2579.354349 * TDIODE_PRECISION_MULTIPLIER;
1869 s64 temp = TDIODE_PRECISION_MULTIPLIER;
1871 temp *= (s64)((val2) - 2 * (val));
1872 temp -= (b2 - 2 * b1);
1873 temp = div64_s64(temp, (m2 - 2 * m1));
1874 temp = min_t(s64, max_t(s64, temp, TDIODE_MIN_TEMP), TDIODE_MAX_TEMP);
1878 static struct gadc_thermal_platform_data gadc_thermal_thermistor_pdata = {
1879 .iio_channel_name = "thermistor",
1880 .tz_name = "Tboard",
1882 .adc_to_temp = gadc_thermal_thermistor_adc_to_temp,
1884 .polling_delay = 15000,
1888 .cdev_type = "therm_est_activ",
1890 .trip_type = THERMAL_TRIP_ACTIVE,
1892 .upper = THERMAL_NO_LIMIT,
1893 .lower = THERMAL_NO_LIMIT,
1900 static struct gadc_thermal_platform_data gadc_thermal_tdiode_pdata = {
1901 .iio_channel_name = "tdiode",
1902 .tz_name = "Tdiode",
1905 .adc_to_temp = gadc_thermal_tdiode_adc_to_temp,
1908 static struct platform_device gadc_thermal_thermistor = {
1909 .name = "generic-adc-thermal",
1912 .platform_data = &gadc_thermal_thermistor_pdata,
1916 static struct platform_device gadc_thermal_tdiode = {
1917 .name = "generic-adc-thermal",
1920 .platform_data = &gadc_thermal_tdiode_pdata,
1924 static struct platform_device *gadc_thermal_devices[] = {
1925 &gadc_thermal_thermistor,
1926 &gadc_thermal_tdiode,
1929 int __init ardbeg_sensors_init(void)
1931 struct board_info board_info;
1932 tegra_get_board_info(&board_info);
1933 /* PM363 and PM359 don't have mpu 9250 mounted */
1934 /* TN8 sensors use Device Tree */
1935 if (board_info.board_id != BOARD_PM363 &&
1936 board_info.board_id != BOARD_PM359 &&
1937 !of_machine_is_compatible("nvidia,tn8") &&
1938 !of_machine_is_compatible("nvidia,bowmore") &&
1939 board_info.board_id != BOARD_PM375 &&
1940 board_info.board_id != BOARD_PM377)
1942 ardbeg_camera_init();
1944 if (board_info.board_id == BOARD_P1761 ||
1945 board_info.board_id == BOARD_E1784 ||
1946 board_info.board_id == BOARD_E1971 ||
1947 board_info.board_id == BOARD_E1991 ||
1948 board_info.board_id == BOARD_E1922) {
1949 platform_add_devices(gadc_thermal_devices,
1950 ARRAY_SIZE(gadc_thermal_devices));
1951 thermistor_table = &tn8_thermistor_table[0];
1952 thermistor_table_size = ARRAY_SIZE(tn8_thermistor_table);
1954 ardbeg_nct72_init();
1956 #if defined(ARCH_TEGRA_12x_SOC)
1957 /* TN8 and PM359 don't have ALS CM32181 */
1958 if (!of_machine_is_compatible("nvidia,tn8") &&
1959 board_info.board_id != BOARD_PM359 &&
1960 board_info.board_id != BOARD_PM375 &&
1961 board_info.board_id != BOARD_PM377)
1962 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
1963 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));