drivers/video/tegra/dc/dc.c

   1 /*
   2  * drivers/video/tegra/dc/dc.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/err.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26 #include <linux/io.h>
  27 #include <linux/pm.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/clk.h>
  30 #include <linux/mutex.h>
  31 #include <linux/delay.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/ktime.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/backlight.h>
  38 #include <linux/gpio.h>
  39 #include <linux/nvhost.h>
  40 #include <linux/clk/tegra.h>
  41 #include <video/tegrafb.h>
  42 #include <drm/drm_fixed.h>
  43 #ifdef CONFIG_SWITCH
  44 #include <linux/switch.h>
  45 #endif
  46 #include <linux/of_irq.h>
  47 #include <linux/of_address.h>
  48 #include <linux/tegra_pm_domains.h>
  49
  50 #define CREATE_TRACE_POINTS
  51 #include <trace/events/display.h>
  52
  53 #include <mach/dc.h>
  54 #include <mach/fb.h>
  55 #include <mach/mc.h>
  56 #include <linux/nvhost.h>
  57 #include <linux/nvhost_ioctl.h>
  58 #include <mach/latency_allowance.h>
  59
  60 #include "dc_reg.h"
  61 #include "dc_config.h"
  62 #include "dc_priv.h"
  63 #include "dev.h"
  64 #include "nvhost_sync.h"
  65 #include "nvsd.h"
  66 #include "dp.h"
  67 #include "nvsr.h"
  68
  69 #ifdef CONFIG_ADF_TEGRA
  70 #include "tegra_adf.h"
  71 #endif
  72
  73 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
  74 #include "hdmi.h"
  75 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
  76
  77 /* HACK! This needs to come from DT */
  78 #include "../../../../arch/arm/mach-tegra/iomap.h"
  79
  80 #define TEGRA_CRC_LATCHED_DELAY         34
  81
  82 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
  83 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
  84
  85 static struct fb_videomode tegra_dc_vga_mode = {
  86         .refresh = 60,
  87         .xres = 640,
  88         .yres = 480,
  89         .pixclock = KHZ2PICOS(25200),
  90         .hsync_len = 96,        /* h_sync_width */
  91         .vsync_len = 2,         /* v_sync_width */
  92         .left_margin = 48,      /* h_back_porch */
  93         .upper_margin = 33,     /* v_back_porch */
  94         .right_margin = 16,     /* h_front_porch */
  95         .lower_margin = 10,     /* v_front_porch */
  96         .vmode = 0,
  97         .sync = 0,
  98 };
  99
 100 static struct tegra_dc_mode override_disp_mode[3];
 101
 102 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
 103
 104 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
 105
 106 DEFINE_MUTEX(tegra_dc_lock);
 107 DEFINE_MUTEX(shared_lock);
 108
 109 static struct device_dma_parameters tegra_dc_dma_parameters = {
 110         .max_segment_size = UINT_MAX,
 111 };
 112
 113 static const struct {
 114         bool h;
 115         bool v;
 116 } can_filter[] = {
 117         /* Window A has no filtering */
 118         { false, false },
 119         /* Window B has both H and V filtering */
 120         { true,  true  },
 121         /* Window C has only H filtering */
 122         { false, true  },
 123 };
 124
 125 #ifdef CONFIG_TEGRA_DC_CMU
 126 static struct tegra_dc_cmu default_cmu = {
 127         /* lut1 maps sRGB to linear space. */
 128         {
 129                 0,    1,    2,    4,    5,    6,    7,    9,
 130                 10,   11,   12,   14,   15,   16,   18,   20,
 131                 21,   23,   25,   27,   29,   31,   33,   35,
 132                 37,   40,   42,   45,   48,   50,   53,   56,
 133                 59,   62,   66,   69,   72,   76,   79,   83,
 134                 87,   91,   95,   99,   103,  107,  112,  116,
 135                 121,  126,  131,  136,  141,  146,  151,  156,
 136                 162,  168,  173,  179,  185,  191,  197,  204,
 137                 210,  216,  223,  230,  237,  244,  251,  258,
 138                 265,  273,  280,  288,  296,  304,  312,  320,
 139                 329,  337,  346,  354,  363,  372,  381,  390,
 140                 400,  409,  419,  428,  438,  448,  458,  469,
 141                 479,  490,  500,  511,  522,  533,  544,  555,
 142                 567,  578,  590,  602,  614,  626,  639,  651,
 143                 664,  676,  689,  702,  715,  728,  742,  755,
 144                 769,  783,  797,  811,  825,  840,  854,  869,
 145                 884,  899,  914,  929,  945,  960,  976,  992,
 146                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 147                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 148                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 149                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 150                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 151                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 152                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 153                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 154                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 155                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 156                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 157                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 158                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 159                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 160                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 161         },
 162         /* csc */
 163         {
 164                 0x100, 0x0,   0x0,
 165                 0x0,   0x100, 0x0,
 166                 0x0,   0x0,   0x100,
 167         },
 168         /* lut2 maps linear space to sRGB*/
 169         {
 170                 0,    1,    2,    2,    3,    4,    5,    6,
 171                 6,    7,    8,    9,    10,   10,   11,   12,
 172                 13,   13,   14,   15,   15,   16,   16,   17,
 173                 18,   18,   19,   19,   20,   20,   21,   21,
 174                 22,   22,   23,   23,   23,   24,   24,   25,
 175                 25,   25,   26,   26,   27,   27,   27,   28,
 176                 28,   29,   29,   29,   30,   30,   30,   31,
 177                 31,   31,   32,   32,   32,   33,   33,   33,
 178                 34,   34,   34,   34,   35,   35,   35,   36,
 179                 36,   36,   37,   37,   37,   37,   38,   38,
 180                 38,   38,   39,   39,   39,   40,   40,   40,
 181                 40,   41,   41,   41,   41,   42,   42,   42,
 182                 42,   43,   43,   43,   43,   43,   44,   44,
 183                 44,   44,   45,   45,   45,   45,   46,   46,
 184                 46,   46,   46,   47,   47,   47,   47,   48,
 185                 48,   48,   48,   48,   49,   49,   49,   49,
 186                 49,   50,   50,   50,   50,   50,   51,   51,
 187                 51,   51,   51,   52,   52,   52,   52,   52,
 188                 53,   53,   53,   53,   53,   54,   54,   54,
 189                 54,   54,   55,   55,   55,   55,   55,   55,
 190                 56,   56,   56,   56,   56,   57,   57,   57,
 191                 57,   57,   57,   58,   58,   58,   58,   58,
 192                 58,   59,   59,   59,   59,   59,   59,   60,
 193                 60,   60,   60,   60,   60,   61,   61,   61,
 194                 61,   61,   61,   62,   62,   62,   62,   62,
 195                 62,   63,   63,   63,   63,   63,   63,   64,
 196                 64,   64,   64,   64,   64,   64,   65,   65,
 197                 65,   65,   65,   65,   66,   66,   66,   66,
 198                 66,   66,   66,   67,   67,   67,   67,   67,
 199                 67,   67,   68,   68,   68,   68,   68,   68,
 200                 68,   69,   69,   69,   69,   69,   69,   69,
 201                 70,   70,   70,   70,   70,   70,   70,   71,
 202                 71,   71,   71,   71,   71,   71,   72,   72,
 203                 72,   72,   72,   72,   72,   72,   73,   73,
 204                 73,   73,   73,   73,   73,   74,   74,   74,
 205                 74,   74,   74,   74,   74,   75,   75,   75,
 206                 75,   75,   75,   75,   75,   76,   76,   76,
 207                 76,   76,   76,   76,   77,   77,   77,   77,
 208                 77,   77,   77,   77,   78,   78,   78,   78,
 209                 78,   78,   78,   78,   78,   79,   79,   79,
 210                 79,   79,   79,   79,   79,   80,   80,   80,
 211                 80,   80,   80,   80,   80,   81,   81,   81,
 212                 81,   81,   81,   81,   81,   81,   82,   82,
 213                 82,   82,   82,   82,   82,   82,   83,   83,
 214                 83,   83,   83,   83,   83,   83,   83,   84,
 215                 84,   84,   84,   84,   84,   84,   84,   84,
 216                 85,   85,   85,   85,   85,   85,   85,   85,
 217                 85,   86,   86,   86,   86,   86,   86,   86,
 218                 86,   86,   87,   87,   87,   87,   87,   87,
 219                 87,   87,   87,   88,   88,   88,   88,   88,
 220                 88,   88,   88,   88,   88,   89,   89,   89,
 221                 89,   89,   89,   89,   89,   89,   90,   90,
 222                 90,   90,   90,   90,   90,   90,   90,   90,
 223                 91,   91,   91,   91,   91,   91,   91,   91,
 224                 91,   91,   92,   92,   92,   92,   92,   92,
 225                 92,   92,   92,   92,   93,   93,   93,   93,
 226                 93,   93,   93,   93,   93,   93,   94,   94,
 227                 94,   94,   94,   94,   94,   94,   94,   94,
 228                 95,   95,   95,   95,   95,   95,   95,   95,
 229                 95,   95,   96,   96,   96,   96,   96,   96,
 230                 96,   96,   96,   96,   96,   97,   97,   97,
 231                 97,   97,   97,   97,   97,   97,   97,   98,
 232                 98,   98,   98,   98,   98,   98,   98,   98,
 233                 98,   98,   99,   99,   99,   99,   99,   99,
 234                 99,   100,  101,  101,  102,  103,  103,  104,
 235                 105,  105,  106,  107,  107,  108,  109,  109,
 236                 110,  111,  111,  112,  113,  113,  114,  115,
 237                 115,  116,  116,  117,  118,  118,  119,  119,
 238                 120,  120,  121,  122,  122,  123,  123,  124,
 239                 124,  125,  126,  126,  127,  127,  128,  128,
 240                 129,  129,  130,  130,  131,  131,  132,  132,
 241                 133,  133,  134,  134,  135,  135,  136,  136,
 242                 137,  137,  138,  138,  139,  139,  140,  140,
 243                 141,  141,  142,  142,  143,  143,  144,  144,
 244                 145,  145,  145,  146,  146,  147,  147,  148,
 245                 148,  149,  149,  150,  150,  150,  151,  151,
 246                 152,  152,  153,  153,  153,  154,  154,  155,
 247                 155,  156,  156,  156,  157,  157,  158,  158,
 248                 158,  159,  159,  160,  160,  160,  161,  161,
 249                 162,  162,  162,  163,  163,  164,  164,  164,
 250                 165,  165,  166,  166,  166,  167,  167,  167,
 251                 168,  168,  169,  169,  169,  170,  170,  170,
 252                 171,  171,  172,  172,  172,  173,  173,  173,
 253                 174,  174,  174,  175,  175,  176,  176,  176,
 254                 177,  177,  177,  178,  178,  178,  179,  179,
 255                 179,  180,  180,  180,  181,  181,  182,  182,
 256                 182,  183,  183,  183,  184,  184,  184,  185,
 257                 185,  185,  186,  186,  186,  187,  187,  187,
 258                 188,  188,  188,  189,  189,  189,  189,  190,
 259                 190,  190,  191,  191,  191,  192,  192,  192,
 260                 193,  193,  193,  194,  194,  194,  195,  195,
 261                 195,  196,  196,  196,  196,  197,  197,  197,
 262                 198,  198,  198,  199,  199,  199,  200,  200,
 263                 200,  200,  201,  201,  201,  202,  202,  202,
 264                 202,  203,  203,  203,  204,  204,  204,  205,
 265                 205,  205,  205,  206,  206,  206,  207,  207,
 266                 207,  207,  208,  208,  208,  209,  209,  209,
 267                 209,  210,  210,  210,  211,  211,  211,  211,
 268                 212,  212,  212,  213,  213,  213,  213,  214,
 269                 214,  214,  214,  215,  215,  215,  216,  216,
 270                 216,  216,  217,  217,  217,  217,  218,  218,
 271                 218,  219,  219,  219,  219,  220,  220,  220,
 272                 220,  221,  221,  221,  221,  222,  222,  222,
 273                 223,  223,  223,  223,  224,  224,  224,  224,
 274                 225,  225,  225,  225,  226,  226,  226,  226,
 275                 227,  227,  227,  227,  228,  228,  228,  228,
 276                 229,  229,  229,  229,  230,  230,  230,  230,
 277                 231,  231,  231,  231,  232,  232,  232,  232,
 278                 233,  233,  233,  233,  234,  234,  234,  234,
 279                 235,  235,  235,  235,  236,  236,  236,  236,
 280                 237,  237,  237,  237,  238,  238,  238,  238,
 281                 239,  239,  239,  239,  240,  240,  240,  240,
 282                 240,  241,  241,  241,  241,  242,  242,  242,
 283                 242,  243,  243,  243,  243,  244,  244,  244,
 284                 244,  244,  245,  245,  245,  245,  246,  246,
 285                 246,  246,  247,  247,  247,  247,  247,  248,
 286                 248,  248,  248,  249,  249,  249,  249,  249,
 287                 250,  250,  250,  250,  251,  251,  251,  251,
 288                 251,  252,  252,  252,  252,  253,  253,  253,
 289                 253,  253,  254,  254,  254,  254,  255,  255,
 290         },
 291 };
 292
 293 static struct tegra_dc_cmu default_limited_cmu = {
 294         /* lut1 maps sRGB to linear space. */
 295         {
 296                 0,    1,    2,    4,    5,    6,    7,    9,
 297                 10,   11,   12,   14,   15,   16,   18,   20,
 298                 21,   23,   25,   27,   29,   31,   33,   35,
 299                 37,   40,   42,   45,   48,   50,   53,   56,
 300                 59,   62,   66,   69,   72,   76,   79,   83,
 301                 87,   91,   95,   99,   103,  107,  112,  116,
 302                 121,  126,  131,  136,  141,  146,  151,  156,
 303                 162,  168,  173,  179,  185,  191,  197,  204,
 304                 210,  216,  223,  230,  237,  244,  251,  258,
 305                 265,  273,  280,  288,  296,  304,  312,  320,
 306                 329,  337,  346,  354,  363,  372,  381,  390,
 307                 400,  409,  419,  428,  438,  448,  458,  469,
 308                 479,  490,  500,  511,  522,  533,  544,  555,
 309                 567,  578,  590,  602,  614,  626,  639,  651,
 310                 664,  676,  689,  702,  715,  728,  742,  755,
 311                 769,  783,  797,  811,  825,  840,  854,  869,
 312                 884,  899,  914,  929,  945,  960,  976,  992,
 313                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
 314                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
 315                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
 316                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
 317                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
 318                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
 319                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
 320                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
 321                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
 322                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
 323                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
 324                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
 325                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
 326                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
 327                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
 328         },
 329         /* csc */
 330         {
 331                 0x100, 0x000, 0x000,
 332                 0x000, 0x100, 0x000,
 333                 0x000, 0x000, 0x100,
 334         },
 335         /*
 336          * lut2 maps linear space back to sRGB, where
 337          * the output range is [16...235] (limited).
 338          */
 339         {
 340                 16,  17,  17,  18,  19,  19,  20,  21,
 341                 22,  22,  23,  24,  24,  25,  26,  26,
 342                 27,  27,  28,  29,  29,  30,  30,  31,
 343                 31,  32,  32,  32,  33,  33,  34,  34,
 344                 35,  35,  35,  36,  36,  36,  37,  37,
 345                 38,  38,  38,  39,  39,  39,  40,  40,
 346                 40,  41,  41,  41,  41,  42,  42,  42,
 347                 43,  43,  43,  43,  44,  44,  44,  45,
 348                 45,  45,  45,  46,  46,  46,  46,  47,
 349                 47,  47,  47,  48,  48,  48,  48,  49,
 350                 49,  49,  49,  49,  50,  50,  50,  50,
 351                 51,  51,  51,  51,  51,  52,  52,  52,
 352                 52,  53,  53,  53,  53,  53,  54,  54,
 353                 54,  54,  54,  55,  55,  55,  55,  55,
 354                 56,  56,  56,  56,  56,  56,  57,  57,
 355                 57,  57,  57,  58,  58,  58,  58,  58,
 356                 58,  59,  59,  59,  59,  59,  60,  60,
 357                 60,  60,  60,  60,  61,  61,  61,  61,
 358                 61,  61,  62,  62,  62,  62,  62,  62,
 359                 63,  63,  63,  63,  63,  63,  63,  64,
 360                 64,  64,  64,  64,  64,  65,  65,  65,
 361                 65,  65,  65,  65,  66,  66,  66,  66,
 362                 66,  66,  67,  67,  67,  67,  67,  67,
 363                 67,  68,  68,  68,  68,  68,  68,  68,
 364                 69,  69,  69,  69,  69,  69,  69,  69,
 365                 70,  70,  70,  70,  70,  70,  70,  71,
 366                 71,  71,  71,  71,  71,  71,  72,  72,
 367                 72,  72,  72,  72,  72,  72,  73,  73,
 368                 73,  73,  73,  73,  73,  73,  74,  74,
 369                 74,  74,  74,  74,  74,  74,  75,  75,
 370                 75,  75,  75,  75,  75,  75,  76,  76,
 371                 76,  76,  76,  76,  76,  76,  76,  77,
 372                 77,  77,  77,  77,  77,  77,  77,  78,
 373                 78,  78,  78,  78,  78,  78,  78,  78,
 374                 79,  79,  79,  79,  79,  79,  79,  79,
 375                 80,  80,  80,  80,  80,  80,  80,  80,
 376                 80,  81,  81,  81,  81,  81,  81,  81,
 377                 81,  81,  81,  82,  82,  82,  82,  82,
 378                 82,  82,  82,  82,  83,  83,  83,  83,
 379                 83,  83,  83,  83,  83,  84,  84,  84,
 380                 84,  84,  84,  84,  84,  84,  84,  85,
 381                 85,  85,  85,  85,  85,  85,  85,  85,
 382                 85,  86,  86,  86,  86,  86,  86,  86,
 383                 86,  86,  86,  87,  87,  87,  87,  87,
 384                 87,  87,  87,  87,  87,  88,  88,  88,
 385                 88,  88,  88,  88,  88,  88,  88,  89,
 386                 89,  89,  89,  89,  89,  89,  89,  89,
 387                 89,  89,  90,  90,  90,  90,  90,  90,
 388                 90,  90,  90,  90,  91,  91,  91,  91,
 389                 91,  91,  91,  91,  91,  91,  91,  92,
 390                 92,  92,  92,  92,  92,  92,  92,  92,
 391                 92,  92,  93,  93,  93,  93,  93,  93,
 392                 93,  93,  93,  93,  93,  94,  94,  94,
 393                 94,  94,  94,  94,  94,  94,  94,  94,
 394                 94,  95,  95,  95,  95,  95,  95,  95,
 395                 95,  95,  95,  95,  96,  96,  96,  96,
 396                 96,  96,  96,  96,  96,  96,  96,  96,
 397                 97,  97,  97,  97,  97,  97,  97,  97,
 398                 97,  97,  97,  97,  98,  98,  98,  98,
 399                 98,  98,  98,  98,  98,  98,  98,  98,
 400                 99,  99,  99,  99,  99,  99,  99,  99,
 401                 99,  99,  99,  99, 100, 100, 100, 100,
 402                 100, 100, 100, 100, 100, 100, 100, 100,
 403                 100, 101, 101, 101, 101, 101, 101, 101,
 404                 102, 102, 103, 104, 104, 105, 105, 106,
 405                 107, 107, 108, 108, 109, 109, 110, 111,
 406                 111, 112, 112, 113, 113, 114, 114, 115,
 407                 115, 116, 116, 117, 117, 118, 118, 119,
 408                 119, 120, 120, 121, 121, 122, 122, 123,
 409                 123, 124, 124, 125, 125, 126, 126, 127,
 410                 127, 127, 128, 128, 129, 129, 130, 130,
 411                 131, 131, 131, 132, 132, 133, 133, 134,
 412                 134, 134, 135, 135, 136, 136, 136, 137,
 413                 137, 138, 138, 139, 139, 139, 140, 140,
 414                 141, 141, 141, 142, 142, 142, 143, 143,
 415                 144, 144, 144, 145, 145, 145, 146, 146,
 416                 147, 147, 147, 148, 148, 148, 149, 149,
 417                 150, 150, 150, 151, 151, 151, 152, 152,
 418                 152, 153, 153, 153, 154, 154, 154, 155,
 419                 155, 155, 156, 156, 156, 157, 157, 157,
 420                 158, 158, 158, 159, 159, 159, 160, 160,
 421                 160, 161, 161, 161, 162, 162, 162, 163,
 422                 163, 163, 164, 164, 164, 165, 165, 165,
 423                 166, 166, 166, 166, 167, 167, 167, 168,
 424                 168, 168, 169, 169, 169, 169, 170, 170,
 425                 170, 171, 171, 171, 172, 172, 172, 172,
 426                 173, 173, 173, 174, 174, 174, 174, 175,
 427                 175, 175, 176, 176, 176, 176, 177, 177,
 428                 177, 178, 178, 178, 178, 179, 179, 179,
 429                 180, 180, 180, 180, 181, 181, 181, 181,
 430                 182, 182, 182, 183, 183, 183, 183, 184,
 431                 184, 184, 184, 185, 185, 185, 185, 186,
 432                 186, 186, 187, 187, 187, 187, 188, 188,
 433                 188, 188, 189, 189, 189, 189, 190, 190,
 434                 190, 190, 191, 191, 191, 191, 192, 192,
 435                 192, 192, 193, 193, 193, 193, 194, 194,
 436                 194, 194, 195, 195, 195, 195, 196, 196,
 437                 196, 196, 197, 197, 197, 197, 198, 198,
 438                 198, 198, 199, 199, 199, 199, 199, 200,
 439                 200, 200, 200, 201, 201, 201, 201, 202,
 440                 202, 202, 202, 203, 203, 203, 203, 203,
 441                 204, 204, 204, 204, 205, 205, 205, 205,
 442                 206, 206, 206, 206, 206, 207, 207, 207,
 443                 207, 208, 208, 208, 208, 208, 209, 209,
 444                 209, 209, 210, 210, 210, 210, 210, 211,
 445                 211, 211, 211, 212, 212, 212, 212, 212,
 446                 213, 213, 213, 213, 213, 214, 214, 214,
 447                 214, 215, 215, 215, 215, 215, 216, 216,
 448                 216, 216, 216, 217, 217, 217, 217, 218,
 449                 218, 218, 218, 218, 219, 219, 219, 219,
 450                 219, 220, 220, 220, 220, 220, 221, 221,
 451                 221, 221, 221, 222, 222, 222, 222, 222,
 452                 223, 223, 223, 223, 224, 224, 224, 224,
 453                 224, 225, 225, 225, 225, 225, 226, 226,
 454                 226, 226, 226, 227, 227, 227, 227, 227,
 455                 227, 228, 228, 228, 228, 228, 229, 229,
 456                 229, 229, 229, 230, 230, 230, 230, 230,
 457                 231, 231, 231, 231, 231, 232, 232, 232,
 458                 232, 232, 233, 233, 233, 233, 233, 233,
 459                 234, 234, 234, 234, 234, 235, 235, 235,
 460         },
 461 };
 462 #endif
 463
 464 void tegra_dc_clk_enable(struct tegra_dc *dc)
 465 {
 466         clk_prepare_enable(dc->clk);
 467         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
 468 }
 469
 470 void tegra_dc_clk_disable(struct tegra_dc *dc)
 471 {
 472         clk_disable_unprepare(dc->clk);
 473         tegra_dvfs_set_rate(dc->clk, 0);
 474 }
 475
 476 void tegra_dc_get(struct tegra_dc *dc)
 477 {
 478         tegra_dc_io_start(dc);
 479
 480         /* extra reference to dc clk */
 481         clk_prepare_enable(dc->clk);
 482 }
 483
 484 void tegra_dc_put(struct tegra_dc *dc)
 485 {
 486         /* balance extra dc clk reference */
 487         clk_disable_unprepare(dc->clk);
 488
 489         tegra_dc_io_end(dc);
 490 }
 491
 492 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
 493 {
 494         tegra_dc_get(dc);
 495         if (dc->out_ops && dc->out_ops->hold)
 496                 dc->out_ops->hold(dc);
 497 }
 498
 499 void tegra_dc_release_dc_out(struct tegra_dc *dc)
 500 {
 501         if (dc->out_ops && dc->out_ops->release)
 502                 dc->out_ops->release(dc);
 503         tegra_dc_put(dc);
 504 }
 505
 506 #define DUMP_REG(a) do {                        \
 507         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
 508                  #a, a, tegra_dc_readl(dc, a));               \
 509         print(data, buff);                                    \
 510         } while (0)
 511
 512 static void _dump_regs(struct tegra_dc *dc, void *data,
 513                        void (* print)(void *data, const char *str))
 514 {
 515         int i;
 516         char buff[256];
 517         const char winname[] = "ABCDHT";
 518         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
 519
 520         /* If gated, quietly return. */
 521         if (!tegra_powergate_is_powered(dc->powergate_id))
 522                 return;
 523
 524         mutex_lock(&dc->lock);
 525         tegra_dc_get(dc);
 526         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
 527                 DC_CMD_STATE_ACCESS);
 528
 529         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 530         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 531         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 532         DUMP_REG(DC_CMD_INT_STATUS);
 533         DUMP_REG(DC_CMD_INT_MASK);
 534         DUMP_REG(DC_CMD_INT_ENABLE);
 535         DUMP_REG(DC_CMD_INT_TYPE);
 536         DUMP_REG(DC_CMD_INT_POLARITY);
 537         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 538         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 539         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 540         DUMP_REG(DC_CMD_STATE_ACCESS);
 541         DUMP_REG(DC_CMD_STATE_CONTROL);
 542         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 543         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 544
 545         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 546         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 547         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 548         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
 549         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
 550         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 551         DUMP_REG(DC_DISP_REF_TO_SYNC);
 552         DUMP_REG(DC_DISP_SYNC_WIDTH);
 553         DUMP_REG(DC_DISP_BACK_PORCH);
 554         DUMP_REG(DC_DISP_DISP_ACTIVE);
 555         DUMP_REG(DC_DISP_FRONT_PORCH);
 556         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 557         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 558         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 559         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 560         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 561         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 562         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 563         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 564         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 565         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 566         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 567         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 568         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 569         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 570         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 571         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 572         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 573         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 574         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 575         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 576         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 577         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 578         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 579         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 580         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 581         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 582         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 583         DUMP_REG(DC_DISP_M0_CONTROL);
 584         DUMP_REG(DC_DISP_M1_CONTROL);
 585         DUMP_REG(DC_DISP_DI_CONTROL);
 586         DUMP_REG(DC_DISP_PP_CONTROL);
 587         DUMP_REG(DC_DISP_PP_SELECT_A);
 588         DUMP_REG(DC_DISP_PP_SELECT_B);
 589         DUMP_REG(DC_DISP_PP_SELECT_C);
 590         DUMP_REG(DC_DISP_PP_SELECT_D);
 591         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 592         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 593         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 594         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 595         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 596         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 597         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 598 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
 599         DUMP_REG(DC_DISP_BORDER_COLOR);
 600 #endif
 601         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 602         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 603         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 604         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 605         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 606         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 607         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 608         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 609 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 610         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
 611         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
 612 #endif
 613         DUMP_REG(DC_DISP_CURSOR_POSITION);
 614         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 615         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 616         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 617         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 618         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 619         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 620         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 621         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 622         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 623         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
 624 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 625         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 626 #endif
 627         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 628         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 629 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_TEGRA_DC_INTERLACE)
 630         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
 631         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
 632         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
 633         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
 634         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
 635         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
 636 #endif
 637         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
 638                 print(data, "\n");
 639                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
 640                 print(data, buff);
 641
 642                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
 643                                 DC_CMD_DISPLAY_WINDOW_HEADER);
 644                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 645                 DUMP_REG(DC_WIN_WIN_OPTIONS);
 646                 DUMP_REG(DC_WIN_BYTE_SWAP);
 647                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
 648                 DUMP_REG(DC_WIN_COLOR_DEPTH);
 649                 DUMP_REG(DC_WIN_POSITION);
 650                 DUMP_REG(DC_WIN_SIZE);
 651                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
 652                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
 653                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
 654                 DUMP_REG(DC_WIN_DDA_INCREMENT);
 655                 DUMP_REG(DC_WIN_LINE_STRIDE);
 656 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
 657                 DUMP_REG(DC_WIN_BUF_STRIDE);
 658                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 659 #endif
 660                 DUMP_REG(DC_WIN_BLEND_NOKEY);
 661                 DUMP_REG(DC_WIN_BLEND_1WIN);
 662                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
 663                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 664                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 665                 DUMP_REG(DC_WINBUF_START_ADDR);
 666                 DUMP_REG(DC_WINBUF_START_ADDR_U);
 667                 DUMP_REG(DC_WINBUF_START_ADDR_V);
 668                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 669                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 670 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 671                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
 672                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
 673                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
 674                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
 675                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
 676                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
 677                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
 678                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
 679                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
 680                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
 681                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
 682 #endif
 683                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 684                 DUMP_REG(DC_WIN_CSC_YOF);
 685                 DUMP_REG(DC_WIN_CSC_KYRGB);
 686                 DUMP_REG(DC_WIN_CSC_KUR);
 687                 DUMP_REG(DC_WIN_CSC_KVR);
 688                 DUMP_REG(DC_WIN_CSC_KUG);
 689                 DUMP_REG(DC_WIN_CSC_KVG);
 690                 DUMP_REG(DC_WIN_CSC_KUB);
 691                 DUMP_REG(DC_WIN_CSC_KVB);
 692         }
 693
 694         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 695         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
 696         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
 697         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
 698         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
 699         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
 700         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 701         DUMP_REG(DC_DISP_M1_CONTROL);
 702         DUMP_REG(DC_COM_PM1_CONTROL);
 703         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
 704         DUMP_REG(DC_DISP_SD_CONTROL);
 705 #ifdef CONFIG_TEGRA_DC_CMU
 706         DUMP_REG(DC_COM_CMU_CSC_KRR);
 707         DUMP_REG(DC_COM_CMU_CSC_KGR);
 708         DUMP_REG(DC_COM_CMU_CSC_KBR);
 709         DUMP_REG(DC_COM_CMU_CSC_KRG);
 710         DUMP_REG(DC_COM_CMU_CSC_KGG);
 711         DUMP_REG(DC_COM_CMU_CSC_KBR);
 712         DUMP_REG(DC_COM_CMU_CSC_KRB);
 713         DUMP_REG(DC_COM_CMU_CSC_KGB);
 714         DUMP_REG(DC_COM_CMU_CSC_KBB);
 715 #endif
 716
 717         tegra_dc_put(dc);
 718         mutex_unlock(&dc->lock);
 719 }
 720
 721 #undef DUMP_REG
 722
 723 #ifdef DEBUG
 724 static void dump_regs_print(void *data, const char *str)
 725 {
 726         struct tegra_dc *dc = data;
 727         dev_dbg(&dc->ndev->dev, "%s", str);
 728 }
 729
 730 static void dump_regs(struct tegra_dc *dc)
 731 {
 732         _dump_regs(dc, dc, dump_regs_print);
 733 }
 734 #else /* !DEBUG */
 735
 736 static void dump_regs(struct tegra_dc *dc) {}
 737
 738 #endif /* DEBUG */
 739
 740 #ifdef CONFIG_DEBUG_FS
 741
 742 static void dbg_regs_print(void *data, const char *str)
 743 {
 744         struct seq_file *s = data;
 745
 746         seq_printf(s, "%s", str);
 747 }
 748
 749 #undef DUMP_REG
 750
 751 static int dbg_dc_show(struct seq_file *s, void *unused)
 752 {
 753         struct tegra_dc *dc = s->private;
 754
 755         _dump_regs(dc, s, dbg_regs_print);
 756
 757         return 0;
 758 }
 759
 760
 761 static int dbg_dc_open(struct inode *inode, struct file *file)
 762 {
 763         return single_open(file, dbg_dc_show, inode->i_private);
 764 }
 765
 766 static const struct file_operations regs_fops = {
 767         .open           = dbg_dc_open,
 768         .read           = seq_read,
 769         .llseek         = seq_lseek,
 770         .release        = single_release,
 771 };
 772
 773 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
 774 {
 775         struct tegra_dc *dc = s->private;
 776         struct tegra_dc_mode *m;
 777
 778         mutex_lock(&dc->lock);
 779         m = &dc->mode;
 780         seq_printf(s,
 781                 "pclk: %d\n"
 782                 "h_ref_to_sync: %d\n"
 783                 "v_ref_to_sync: %d\n"
 784                 "h_sync_width: %d\n"
 785                 "v_sync_width: %d\n"
 786                 "h_back_porch: %d\n"
 787                 "v_back_porch: %d\n"
 788                 "h_active: %d\n"
 789                 "v_active: %d\n"
 790                 "h_front_porch: %d\n"
 791                 "v_front_porch: %d\n"
 792                 "stereo_mode: %d\n",
 793                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
 794                 m->h_sync_width, m->v_sync_width,
 795                 m->h_back_porch, m->v_back_porch,
 796                 m->h_active, m->v_active,
 797                 m->h_front_porch, m->v_front_porch,
 798                 m->stereo_mode);
 799         mutex_unlock(&dc->lock);
 800         return 0;
 801 }
 802
 803 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
 804 {
 805         return single_open(file, dbg_dc_mode_show, inode->i_private);
 806 }
 807
 808 static const struct file_operations mode_fops = {
 809         .open           = dbg_dc_mode_open,
 810         .read           = seq_read,
 811         .llseek         = seq_lseek,
 812         .release        = single_release,
 813 };
 814
 815 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
 816 {
 817         struct tegra_dc *dc = s->private;
 818
 819         mutex_lock(&dc->lock);
 820         seq_printf(s,
 821                 "underflows: %llu\n"
 822                 "underflows_a: %llu\n"
 823                 "underflows_b: %llu\n"
 824                 "underflows_c: %llu\n",
 825                 dc->stats.underflows,
 826                 dc->stats.underflows_a,
 827                 dc->stats.underflows_b,
 828                 dc->stats.underflows_c);
 829 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
 830         seq_printf(s,
 831                 "underflows_d: %llu\n"
 832                 "underflows_h: %llu\n"
 833                 "underflows_t: %llu\n",
 834                 dc->stats.underflows_d,
 835                 dc->stats.underflows_h,
 836                 dc->stats.underflows_t);
 837 #endif
 838         mutex_unlock(&dc->lock);
 839
 840         return 0;
 841 }
 842
 843 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
 844 {
 845         return single_open(file, dbg_dc_stats_show, inode->i_private);
 846 }
 847
 848 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
 849 {
 850         return 0;
 851 }
 852
 853 static ssize_t dbg_dc_event_inject_write(struct file *file,
 854         const char __user *addr, size_t len, loff_t *pos)
 855 {
 856         struct seq_file *m = file->private_data; /* single_open() initialized */
 857         struct tegra_dc *dc = m ? m->private : NULL;
 858         long event;
 859         int ret;
 860
 861         if (!dc)
 862                 return -EINVAL;
 863
 864         ret = kstrtol_from_user(addr, len, 10, &event);
 865         if (ret < 0)
 866                 return ret;
 867
 868         if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG */
 869                 tegra_dc_ext_process_hotplug(dc->ndev->id);
 870         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
 871                 tegra_dc_ext_process_bandwidth_renegotiate(
 872                                 dc->ndev->id, NULL);
 873         else {
 874                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
 875                 return -EINVAL; /* unknown event number */
 876         }
 877         return len;
 878 }
 879
 880 static const struct file_operations stats_fops = {
 881         .open           = dbg_dc_stats_open,
 882         .read           = seq_read,
 883         .llseek         = seq_lseek,
 884         .release        = single_release,
 885 };
 886
 887 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
 888 {
 889         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
 890 }
 891
 892 static const struct file_operations event_inject_fops = {
 893         .open           = dbg_dc_event_inject_open,
 894         .read           = seq_read,
 895         .write          = dbg_dc_event_inject_write,
 896         .llseek         = seq_lseek,
 897         .release        = single_release,
 898 };
 899
 900 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
 901 {
 902         if (dc->debugdir)
 903                 debugfs_remove_recursive(dc->debugdir);
 904         dc->debugdir = NULL;
 905 }
 906
 907 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
 908 {
 909         struct dentry *retval;
 910
 911         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
 912         if (!dc->debugdir)
 913                 goto remove_out;
 914
 915         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
 916                 &regs_fops);
 917         if (!retval)
 918                 goto remove_out;
 919
 920         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
 921                 &mode_fops);
 922         if (!retval)
 923                 goto remove_out;
 924
 925         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
 926                 &stats_fops);
 927         if (!retval)
 928                 goto remove_out;
 929
 930         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
 931                 &event_inject_fops);
 932         if (!retval)
 933                 goto remove_out;
 934
 935         return;
 936 remove_out:
 937         dev_err(&dc->ndev->dev, "could not create debugfs\n");
 938         tegra_dc_remove_debugfs(dc);
 939 }
 940
 941 #else /* !CONFIG_DEBUGFS */
 942 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
 943 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
 944 #endif /* CONFIG_DEBUGFS */
 945
 946 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
 947                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
 948 {
 949         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
 950         u32 reg_val = 0;
 951
 952         do {
 953                 usleep_range(poll_interval_us, poll_interval_us << 1);
 954                 reg_val = tegra_dc_readl(dc, reg);
 955         } while (((reg_val & mask) != exp_val) &&
 956                 time_after(timeout_jf, jiffies));
 957
 958         if ((reg_val & mask) == exp_val)
 959                 return 0;       /* success */
 960         dev_err(&dc->ndev->dev,
 961                 "dc_poll_register 0x%x: timeout\n", reg);
 962         return jiffies - timeout_jf + 1;
 963 }
 964
 965 static int tegra_dc_set(struct tegra_dc *dc, int index)
 966 {
 967         int ret = 0;
 968
 969         mutex_lock(&tegra_dc_lock);
 970         if (index >= TEGRA_MAX_DC) {
 971                 ret = -EINVAL;
 972                 goto out;
 973         }
 974
 975         if (dc != NULL && tegra_dcs[index] != NULL) {
 976                 ret = -EBUSY;
 977                 goto out;
 978         }
 979
 980         tegra_dcs[index] = dc;
 981
 982 out:
 983         mutex_unlock(&tegra_dc_lock);
 984
 985         return ret;
 986 }
 987
 988 unsigned int tegra_dc_has_multiple_dc(void)
 989 {
 990         unsigned int idx;
 991         unsigned int cnt = 0;
 992         struct tegra_dc *dc;
 993
 994         mutex_lock(&tegra_dc_lock);
 995         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
 996                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
 997         mutex_unlock(&tegra_dc_lock);
 998
 999         return (cnt > 1);
1000 }
1001
1002 /* get the stride size of a window.
1003  * return: stride size in bytes for window win. or 0 if unavailble. */
1004 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1005 {
1006         u32 stride;
1007
1008         if (!dc->enabled)
1009                 return 0;
1010         BUG_ON(win > DC_N_WINDOWS);
1011         mutex_lock(&dc->lock);
1012         tegra_dc_get(dc);
1013         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1014                 DC_CMD_DISPLAY_WINDOW_HEADER);
1015         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1016         tegra_dc_put(dc);
1017         mutex_unlock(&dc->lock);
1018         return GET_LINE_STRIDE(stride);
1019 }
1020 EXPORT_SYMBOL(tegra_dc_get_stride);
1021
1022 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1023 {
1024         if (idx < TEGRA_MAX_DC)
1025                 return tegra_dcs[idx];
1026         else
1027                 return NULL;
1028 }
1029 EXPORT_SYMBOL(tegra_dc_get_dc);
1030
1031 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1032 {
1033         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1034                 return NULL;
1035
1036         return &dc->windows[win];
1037 }
1038 EXPORT_SYMBOL(tegra_dc_get_window);
1039
1040 bool tegra_dc_get_connected(struct tegra_dc *dc)
1041 {
1042         return dc->connected;
1043 }
1044 EXPORT_SYMBOL(tegra_dc_get_connected);
1045
1046 bool tegra_dc_hpd(struct tegra_dc *dc)
1047 {
1048         int sense;
1049         int level;
1050         int hpd;
1051
1052         if (WARN_ON(!dc || !dc->out))
1053                 return false;
1054
1055         if (dc->out->hotplug_state != 0) {
1056                 if (dc->out->hotplug_state == 1) /* force on */
1057                         return true;
1058                 if (dc->out->hotplug_state == -1) /* force off */
1059                         return false;
1060         }
1061         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
1062
1063         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1064
1065         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1066                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1067
1068         if (dc->out->hotplug_report)
1069                 dc->out->hotplug_report(hpd);
1070
1071         return hpd;
1072 }
1073 EXPORT_SYMBOL(tegra_dc_hpd);
1074
1075 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1076 {
1077         unsigned i;
1078         unsigned v0 = 128;
1079         unsigned v1 = 0;
1080
1081         /* linear horizontal and vertical filters */
1082         for (i = 0; i < 16; i++) {
1083                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1084                                 DC_WIN_H_FILTER_P(i));
1085
1086                 tegra_dc_writel(dc, v0,
1087                                 DC_WIN_V_FILTER_P(i));
1088                 v0 -= 8;
1089                 v1 += 8;
1090         }
1091 }
1092
1093 #ifdef CONFIG_TEGRA_DC_CMU
1094 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
1095                                         struct tegra_dc_cmu *src_cmu)
1096 {
1097         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
1098                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
1099         dc->cmu_dirty = true;
1100 }
1101
1102 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1103 {
1104         u32 val;
1105         u32 i;
1106
1107         for (i = 0; i < 256; i++) {
1108                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1109                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1110         }
1111
1112         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1113         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1114         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1115         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1116         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1117         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1118         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1119         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1120         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1121
1122         for (i = 0; i < 960; i++) {
1123                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1124                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1125         }
1126
1127         dc->cmu_dirty = false;
1128 }
1129
1130 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1131 {
1132         u32 val;
1133
1134         if (!dc->cmu_enabled)
1135                 return;
1136
1137         tegra_dc_cache_cmu(dc, cmu);
1138
1139         if (dc->cmu_dirty) {
1140                 /* Disable CMU to avoid programming it while it is in use */
1141                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1142                 if (val & CMU_ENABLE) {
1143                         val &= ~CMU_ENABLE;
1144                         tegra_dc_writel(dc, val,
1145                                         DC_DISP_DISP_COLOR_CONTROL);
1146                         val = GENERAL_ACT_REQ;
1147                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
1148                         /*TODO: Sync up with vsync */
1149                         mdelay(20);
1150                 }
1151                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
1152                         dc->cmu_dirty);
1153
1154                 tegra_dc_set_cmu(dc, &dc->cmu);
1155         }
1156 }
1157
1158 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1159 {
1160         mutex_lock(&dc->lock);
1161         if (!dc->enabled) {
1162                 mutex_unlock(&dc->lock);
1163                 return 0;
1164         }
1165
1166         tegra_dc_get(dc);
1167
1168         _tegra_dc_update_cmu(dc, cmu);
1169         tegra_dc_set_color_control(dc);
1170
1171         tegra_dc_put(dc);
1172         mutex_unlock(&dc->lock);
1173
1174         return 0;
1175 }
1176 EXPORT_SYMBOL(tegra_dc_update_cmu);
1177
1178 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
1179 {
1180         if (dc->pdata->cmu)
1181                 return dc->pdata->cmu;
1182         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
1183                 return &default_limited_cmu;
1184         else
1185                 return &default_cmu;
1186 }
1187
1188 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
1189 {
1190         dc->cmu_enabled = cmu_enable;
1191         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
1192 }
1193 #else
1194 #define tegra_dc_cache_cmu(dc, src_cmu)
1195 #define tegra_dc_set_cmu(dc, cmu)
1196 #define tegra_dc_update_cmu(dc, cmu)
1197 #endif
1198
1199 /* disable_irq() blocks until handler completes, calling this function while
1200  * holding dc->lock can deadlock. */
1201 static inline void disable_dc_irq(const struct tegra_dc *dc)
1202 {
1203         disable_irq(dc->irq);
1204 }
1205
1206 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1207 {
1208         return dc->syncpt[i].id;
1209 }
1210 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1211
1212 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1213 {
1214         u32 max;
1215
1216         mutex_lock(&dc->lock);
1217         tegra_dc_get(dc);
1218         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1219                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1220         dc->syncpt[i].max = max;
1221         tegra_dc_put(dc);
1222         mutex_unlock(&dc->lock);
1223
1224         return max;
1225 }
1226
1227 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1228 {
1229         mutex_lock(&dc->lock);
1230
1231         tegra_dc_get(dc);
1232         while (dc->syncpt[i].min < val) {
1233                 dc->syncpt[i].min++;
1234                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1235                 }
1236         tegra_dc_put(dc);
1237         mutex_unlock(&dc->lock);
1238 }
1239
1240 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
1241 {
1242         struct nvhost_ctrl_sync_fence_info syncpt;
1243         u32 id = tegra_dc_get_syncpt_id(dc, i);
1244
1245         syncpt.id = id;
1246         syncpt.thresh = val;
1247         return nvhost_sync_create_fence(
1248                         to_platform_device(dc->ndev->dev.parent),
1249                         &syncpt, 1, dev_name(&dc->ndev->dev));
1250 }
1251
1252 void
1253 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1254 {
1255         unsigned int ctrl;
1256         unsigned long out_sel;
1257         unsigned long cmd_state;
1258
1259         mutex_lock(&dc->lock);
1260         if (!dc->enabled) {
1261                 mutex_unlock(&dc->lock);
1262                 return;
1263         }
1264
1265         tegra_dc_get(dc);
1266
1267         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1268                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1269                 cfg->clk_select);
1270
1271         /* The new value should be effected immediately */
1272         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1273         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1274
1275         switch (cfg->which_pwm) {
1276         case TEGRA_PWM_PM0:
1277                 /* Select the LM0 on PM0 */
1278                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1279                 out_sel &= ~(7 << 0);
1280                 out_sel |= (3 << 0);
1281                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1282                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1283                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1284                 break;
1285         case TEGRA_PWM_PM1:
1286                 /* Select the LM1 on PM1 */
1287                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1288                 out_sel &= ~(7 << 4);
1289                 out_sel |= (3 << 4);
1290                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1291                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1292                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1293                 break;
1294         default:
1295                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1296                 break;
1297         }
1298         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1299         tegra_dc_put(dc);
1300         mutex_unlock(&dc->lock);
1301 }
1302 EXPORT_SYMBOL(tegra_dc_config_pwm);
1303
1304 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1305                                 const struct tegra_dc_out_pin *pins,
1306                                 const unsigned int n_pins)
1307 {
1308         unsigned int i;
1309
1310         int name;
1311         int pol;
1312
1313         u32 pol1, pol3;
1314
1315         u32 set1, unset1;
1316         u32 set3, unset3;
1317
1318         set1 = set3 = unset1 = unset3 = 0;
1319
1320         for (i = 0; i < n_pins; i++) {
1321                 name = (pins + i)->name;
1322                 pol  = (pins + i)->pol;
1323
1324                 /* set polarity by name */
1325                 switch (name) {
1326                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1327                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1328                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1329                         else
1330                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1331                         break;
1332                 case TEGRA_DC_OUT_PIN_H_SYNC:
1333                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1334                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1335                         else
1336                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1337                         break;
1338                 case TEGRA_DC_OUT_PIN_V_SYNC:
1339                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1340                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1341                         else
1342                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1343                         break;
1344                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1345                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1346                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1347                         else
1348                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1349                         break;
1350                 default:
1351                         printk("Invalid argument in function %s\n",
1352                                __FUNCTION__);
1353                         break;
1354                 }
1355         }
1356
1357         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1358         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1359
1360         pol1 |= set1;
1361         pol1 &= ~unset1;
1362
1363         pol3 |= set3;
1364         pol3 &= ~unset3;
1365
1366         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1367         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1368 }
1369
1370 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1371 {
1372         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1373                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1374                 dc->out->type == TEGRA_DC_OUT_DSI)
1375                 return override_disp_mode[dc->out->type].pclk ?
1376                         &override_disp_mode[dc->out->type] : NULL;
1377         else
1378                 return NULL;
1379 }
1380
1381 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1382 {
1383         struct tegra_dc_mode *mode;
1384         int err = 0;
1385
1386         dc->out = out;
1387         mode = tegra_dc_get_override_mode(dc);
1388
1389         if (mode) {
1390                 tegra_dc_set_mode(dc, mode);
1391
1392                 /*
1393                  * Bootloader should and should only pass disp_params if
1394                  * it has initialized display controller.  Whenever we see
1395                  * override modes, we should skip things cause display resets.
1396                  */
1397                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
1398                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
1399                                 dc->mode.h_active, dc->mode.v_active,
1400                                 dc->out->h_size, dc->out->v_size,
1401                                 dc->mode.pclk);
1402                 dc->initialized = true;
1403
1404 #ifdef CONFIG_TEGRA_DC_CMU
1405                 /*
1406                  * If the bootloader already set the mode, assume the CMU
1407                  * parameters are also correctly set. It would be better to
1408                  * read them, but unfortunately there is no reliable and
1409                  * flicker-free way to do this!
1410                  */
1411                 tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
1412 #endif
1413         } else if (out->n_modes > 0)
1414                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1415
1416         switch (out->type) {
1417         case TEGRA_DC_OUT_RGB:
1418                 dc->out_ops = &tegra_dc_rgb_ops;
1419                 break;
1420
1421         case TEGRA_DC_OUT_HDMI:
1422                 dc->out_ops = &tegra_dc_hdmi_ops;
1423                 break;
1424
1425         case TEGRA_DC_OUT_DSI:
1426                 dc->out_ops = &tegra_dc_dsi_ops;
1427                 break;
1428
1429 #ifdef CONFIG_TEGRA_DP
1430         case TEGRA_DC_OUT_DP:
1431                 dc->out_ops = &tegra_dc_dp_ops;
1432                 break;
1433 #ifdef CONFIG_TEGRA_NVSR
1434         case TEGRA_DC_OUT_NVSR_DP:
1435                 dc->out_ops = &tegra_dc_nvsr_ops;
1436                 break;
1437 #endif
1438 #endif
1439 #ifdef CONFIG_TEGRA_LVDS
1440         case TEGRA_DC_OUT_LVDS:
1441                 dc->out_ops = &tegra_dc_lvds_ops;
1442                 break;
1443 #endif
1444         default:
1445                 dc->out_ops = NULL;
1446                 break;
1447         }
1448
1449         if (dc->out_ops && dc->out_ops->init) {
1450                 err = dc->out_ops->init(dc);
1451                 if (err < 0) {
1452                         dc->out = NULL;
1453                         dc->out_ops = NULL;
1454                         dev_err(&dc->ndev->dev,
1455                                 "Error: out->type:%d out_ops->init() failed\n",
1456                                 out->type);
1457                         return err;
1458                 }
1459         }
1460
1461         return err;
1462 }
1463
1464 /* returns on error: -EINVAL
1465  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1466 int tegra_dc_get_out(const struct tegra_dc *dc)
1467 {
1468         if (dc && dc->out)
1469                 return dc->out->type;
1470         return -EINVAL;
1471 }
1472
1473 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1474 {
1475         if (dc->out)
1476                 return dc->out->height;
1477         else
1478                 return 0;
1479 }
1480 EXPORT_SYMBOL(tegra_dc_get_out_height);
1481
1482 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1483 {
1484         if (dc->out)
1485                 return dc->out->width;
1486         else
1487                 return 0;
1488 }
1489 EXPORT_SYMBOL(tegra_dc_get_out_width);
1490
1491 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1492 {
1493         if (dc && dc->out)
1494                 return dc->out->max_pixclock;
1495         else
1496                 return 0;
1497 }
1498 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1499
1500 void tegra_dc_enable_crc(struct tegra_dc *dc)
1501 {
1502         u32 val;
1503
1504         mutex_lock(&dc->lock);
1505         tegra_dc_get(dc);
1506
1507         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1508                 CRC_ENABLE_ENABLE;
1509         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1510         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1511         tegra_dc_put(dc);
1512         mutex_unlock(&dc->lock);
1513
1514         /* Register a client of frame_end interrupt */
1515         tegra_dc_config_frame_end_intr(dc, true);
1516 }
1517
1518 void tegra_dc_disable_crc(struct tegra_dc *dc)
1519 {
1520         /* Unregister a client of frame_end interrupt */
1521         tegra_dc_config_frame_end_intr(dc, false);
1522
1523         mutex_lock(&dc->lock);
1524         tegra_dc_get(dc);
1525         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1526         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1527
1528         tegra_dc_put(dc);
1529         mutex_unlock(&dc->lock);
1530 }
1531
1532 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1533 {
1534         int crc = 0;
1535
1536         if (!dc) {
1537                 pr_err("Failed to get dc: NULL parameter.\n");
1538                 goto crc_error;
1539         }
1540
1541         /* If gated quitely return */
1542         if (!tegra_dc_is_powered(dc))
1543                 return 0;
1544
1545         INIT_COMPLETION(dc->crc_complete);
1546         if (dc->crc_pending &&
1547             wait_for_completion_interruptible(&dc->crc_complete)) {
1548                 pr_err("CRC read interrupted.\n");
1549                 goto crc_error;
1550         }
1551
1552         mutex_lock(&dc->lock);
1553         tegra_dc_get(dc);
1554         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1555         tegra_dc_put(dc);
1556         mutex_unlock(&dc->lock);
1557 crc_error:
1558         return crc;
1559 }
1560
1561 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1562 {
1563         u32 val;
1564
1565         if (tegra_platform_is_linsim())
1566                 return false;
1567
1568         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1569         if (val & WIN_ALL_ACT_REQ)
1570                 return true;
1571
1572         return false;
1573 }
1574
1575 static inline void enable_dc_irq(const struct tegra_dc *dc)
1576 {
1577         if (tegra_platform_is_fpga())
1578                 /* Always disable DC interrupts on FPGA. */
1579                 disable_irq(dc->irq);
1580         else
1581                 enable_irq(dc->irq);
1582 }
1583
1584 bool tegra_dc_has_vsync(struct tegra_dc *dc)
1585 {
1586         return !!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE);
1587 }
1588
1589 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1590 {
1591         int ret = -ENOTTY;
1592
1593         /* Generally vsync comes at 60Hz (~16.67ms per cycle).
1594          * 2 time periods should be good enough for the timeout.
1595          * We add some margin here for the default timeout value.
1596          */
1597         unsigned long timeout_ms = 40;
1598
1599         if (dc->out->type == TEGRA_DC_OUT_DSI &&
1600                 dc->out->dsi->rated_refresh_rate != 0)
1601                 timeout_ms = 2 * DIV_ROUND_UP(1000,
1602                          dc->out->dsi->rated_refresh_rate);
1603
1604         mutex_lock(&dc->one_shot_lp_lock);
1605
1606         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled) {
1607                 mutex_unlock(&dc->one_shot_lp_lock);
1608                 return ret;
1609         }
1610
1611         tegra_dc_get(dc);
1612         if (dc->out_ops && dc->out_ops->hold)
1613                 dc->out_ops->hold(dc);
1614
1615         /*
1616          * Logic is as follows
1617          * a) Indicate we need a vblank.
1618          * b) Wait for completion to be signalled from isr.
1619          * c) Initialize completion for next iteration.
1620          */
1621
1622         dc->out->user_needs_vblank = true;
1623
1624         mutex_lock(&dc->lock);
1625         tegra_dc_unmask_interrupt(dc, MSF_INT);
1626         mutex_unlock(&dc->lock);
1627
1628         ret = wait_for_completion_interruptible_timeout(
1629                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
1630         init_completion(&dc->out->user_vblank_comp);
1631
1632         mutex_lock(&dc->lock);
1633         tegra_dc_mask_interrupt(dc, MSF_INT);
1634         mutex_unlock(&dc->lock);
1635
1636         if (dc->out_ops && dc->out_ops->release)
1637                 dc->out_ops->release(dc);
1638         tegra_dc_put(dc);
1639
1640         mutex_unlock(&dc->one_shot_lp_lock);
1641         return ret;
1642 }
1643
1644 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1645 {
1646         /* Do the actual brightness update outside of the mutex dc->lock */
1647         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1648                 dc->out->sd_settings->bl_device_name) {
1649                 char *bl_device_name =
1650                         dc->out->sd_settings->bl_device_name;
1651                 dc->out->sd_settings->bl_device =
1652                         get_backlight_device_by_name(bl_device_name);
1653         }
1654
1655         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1656                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1657                 backlight_update_status(bl);
1658         }
1659 }
1660
1661 void tegra_dc_vsync_enable(struct tegra_dc *dc)
1662 {
1663         mutex_lock(&dc->lock);
1664         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
1665         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1666         mutex_unlock(&dc->lock);
1667 }
1668
1669 void tegra_dc_vsync_disable(struct tegra_dc *dc)
1670 {
1671         mutex_lock(&dc->lock);
1672         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
1673         if (!dc->vblank_ref_count)
1674                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1675         mutex_unlock(&dc->lock);
1676 }
1677
1678 static void tegra_dc_vblank(struct work_struct *work)
1679 {
1680         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1681         bool nvsd_updated = false;
1682
1683         mutex_lock(&dc->lock);
1684
1685         if (!dc->enabled) {
1686                 mutex_unlock(&dc->lock);
1687                 return;
1688         }
1689
1690         tegra_dc_get(dc);
1691
1692         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1693         if (!tegra_dc_windows_are_dirty(dc))
1694                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1695
1696         /* Update the SD brightness */
1697         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1698                 nvsd_updated = nvsd_update_brightness(dc);
1699                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1700                  * V_BLANK_NVSD bit of vblank ref-count. */
1701                 if (nvsd_updated) {
1702                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1703                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1704                 } else {
1705                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1706                 }
1707         }
1708
1709         /* Mask vblank interrupt if ref-count is zero. */
1710         if (!dc->vblank_ref_count)
1711                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1712
1713         tegra_dc_put(dc);
1714         mutex_unlock(&dc->lock);
1715
1716         /* Do the actual brightness update outside of the mutex dc->lock */
1717         if (nvsd_updated)
1718                 tegra_dc_prism_update_backlight(dc);
1719 }
1720
1721 static void tegra_dc_one_shot_worker(struct work_struct *work)
1722 {
1723         struct tegra_dc *dc = container_of(
1724                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1725         mutex_lock(&dc->lock);
1726
1727         /* memory client has gone idle */
1728         tegra_dc_clear_bandwidth(dc);
1729
1730         if (dc->out_ops && dc->out_ops->idle) {
1731                 tegra_dc_io_start(dc);
1732                 dc->out_ops->idle(dc);
1733                 tegra_dc_io_end(dc);
1734         }
1735
1736         mutex_unlock(&dc->lock);
1737 }
1738
1739 /* return an arbitrarily large number if count overflow occurs.
1740  * make it a nice base-10 number to show up in stats output */
1741 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1742 {
1743         unsigned count = tegra_dc_readl(dc, reg);
1744
1745         tegra_dc_writel(dc, 0, reg);
1746         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1747 }
1748
1749 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1750 {
1751         const u32 masks[] = {
1752                 WIN_A_UF_INT,
1753                 WIN_B_UF_INT,
1754                 WIN_C_UF_INT,
1755 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1756                 WIN_D_UF_INT,
1757                 HC_UF_INT,
1758                 WIN_T_UF_INT,
1759 #endif
1760         };
1761         int i;
1762
1763         dc->stats.underflows++;
1764         if (dc->underflow_mask & WIN_A_UF_INT)
1765                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1766                         DC_WINBUF_AD_UFLOW_STATUS);
1767         if (dc->underflow_mask & WIN_B_UF_INT)
1768                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1769                         DC_WINBUF_BD_UFLOW_STATUS);
1770         if (dc->underflow_mask & WIN_C_UF_INT)
1771                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1772                         DC_WINBUF_CD_UFLOW_STATUS);
1773 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1774         if (dc->underflow_mask & HC_UF_INT)
1775                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
1776                         DC_WINBUF_HD_UFLOW_STATUS);
1777         if (dc->underflow_mask & WIN_D_UF_INT)
1778                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
1779                         DC_WINBUF_DD_UFLOW_STATUS);
1780         if (dc->underflow_mask & WIN_T_UF_INT)
1781                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
1782                         DC_WINBUF_TD_UFLOW_STATUS);
1783 #endif
1784
1785         /* Check for any underflow reset conditions */
1786         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1787                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
1788                         "underflow stats unsupported"))
1789                         break; /* bail if the table above is missing entries */
1790                 if (!masks[i])
1791                         continue; /* skip empty entries */
1792
1793                 if (dc->underflow_mask & masks[i]) {
1794                         dc->windows[i].underflows++;
1795
1796 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1797                         if (i < 3 && dc->windows[i].underflows > 4) {
1798                                 schedule_work(&dc->reset_work);
1799                                 /* reset counter */
1800                                 dc->windows[i].underflows = 0;
1801                                 trace_display_reset(dc);
1802                         }
1803 #endif
1804 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1805                         if (i < 3 && dc->windows[i].underflows > 4) {
1806                                 trace_display_reset(dc);
1807                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1808                                                 DC_DISP_DISP_MISC_CONTROL);
1809                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1810                                                 DC_CMD_STATE_CONTROL);
1811
1812                                 tegra_dc_writel(dc, 0,
1813                                                 DC_DISP_DISP_MISC_CONTROL);
1814                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1815                                                 DC_CMD_STATE_CONTROL);
1816                         }
1817 #endif
1818                 } else {
1819                         dc->windows[i].underflows = 0;
1820                 }
1821         }
1822
1823         /* Clear the underflow mask now that we've checked it. */
1824         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1825         dc->underflow_mask = 0;
1826         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
1827         trace_underflow(dc);
1828 }
1829
1830 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1831 static void tegra_dc_vpulse2(struct work_struct *work)
1832 {
1833         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1834         bool nvsd_updated = false;
1835
1836         mutex_lock(&dc->lock);
1837
1838         if (!dc->enabled) {
1839                 mutex_unlock(&dc->lock);
1840                 return;
1841         }
1842
1843         tegra_dc_get(dc);
1844
1845         /* Clear the V_PULSE2_FLIP if no update */
1846         if (!tegra_dc_windows_are_dirty(dc))
1847                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1848
1849         /* Update the SD brightness */
1850         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1851                 nvsd_updated = nvsd_update_brightness(dc);
1852                 if (nvsd_updated) {
1853                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1854                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1855                 } else {
1856                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1857                 }
1858         }
1859
1860         /* Mask vpulse2 interrupt if ref-count is zero. */
1861         if (!dc->vpulse2_ref_count)
1862                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1863
1864         tegra_dc_put(dc);
1865         mutex_unlock(&dc->lock);
1866
1867         /* Do the actual brightness update outside of the mutex dc->lock */
1868         if (nvsd_updated)
1869                 tegra_dc_prism_update_backlight(dc);
1870 }
1871 #endif
1872
1873 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
1874                 ktime_t timestamp)
1875 {
1876         /* pending user vblank, so wakeup */
1877         if (status & (V_BLANK_INT | MSF_INT)) {
1878                 if (dc->out->user_needs_vblank) {
1879                         dc->out->user_needs_vblank = false;
1880                         complete(&dc->out->user_vblank_comp);
1881                 }
1882 #ifdef CONFIG_ADF_TEGRA
1883                 tegra_adf_process_vblank(dc->adf, timestamp);
1884 #endif
1885         }
1886
1887         if (status & V_BLANK_INT) {
1888                 /* Sync up windows. */
1889                 tegra_dc_trigger_windows(dc);
1890
1891                 /* Schedule any additional bottom-half vblank actvities. */
1892                 queue_work(system_freezable_wq, &dc->vblank_work);
1893         }
1894
1895         if (status & FRAME_END_INT) {
1896                 /* Mark the frame_end as complete. */
1897                 dc->crc_pending = false;
1898                 if (!completion_done(&dc->frame_end_complete))
1899                         complete(&dc->frame_end_complete);
1900                 if (!completion_done(&dc->crc_complete))
1901                         complete(&dc->crc_complete);
1902
1903                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
1904                         tegra_dc_put(dc);
1905         }
1906
1907 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1908         if (status & V_PULSE2_INT)
1909                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1910 #endif
1911 }
1912
1913 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
1914                 ktime_t timestamp)
1915 {
1916         /* Schedule any additional bottom-half vblank actvities. */
1917         if (status & V_BLANK_INT)
1918                 queue_work(system_freezable_wq, &dc->vblank_work);
1919
1920 #ifdef CONFIG_ADF_TEGRA
1921         if (status & (V_BLANK_INT | MSF_INT))
1922                 tegra_adf_process_vblank(dc->adf, timestamp);
1923 #endif
1924
1925         if (status & FRAME_END_INT) {
1926                 struct timespec tm = CURRENT_TIME;
1927                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1928                 wake_up(&dc->timestamp_wq);
1929
1930                 /* Mark the frame_end as complete. */
1931                 if (!completion_done(&dc->frame_end_complete))
1932                         complete(&dc->frame_end_complete);
1933                 if (!completion_done(&dc->crc_complete))
1934                         complete(&dc->crc_complete);
1935
1936                 tegra_dc_trigger_windows(dc);
1937         }
1938
1939 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1940         if (status & V_PULSE2_INT)
1941                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1942 #endif
1943 }
1944
1945 /* XXX: Not sure if we limit look ahead to 1 frame */
1946 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1947 {
1948         BUG_ON(!dc->frametime_ns);
1949         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1950 }
1951
1952 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1953 {
1954         BUG_ON(!dc->frametime_ns);
1955         return (((new_ts - old_ts) > dc->frametime_ns)
1956                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1957                         != div_s64((old_ts - dc->frame_end_timestamp),
1958                                 dc->frametime_ns)));
1959 }
1960
1961 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1962 {
1963         ktime_t timestamp = ktime_get();
1964         struct tegra_dc *dc = ptr;
1965         unsigned long status;
1966         unsigned long underflow_mask;
1967         u32 val;
1968         int need_disable = 0;
1969
1970         if (tegra_platform_is_fpga())
1971                 return IRQ_NONE;
1972
1973         mutex_lock(&dc->lock);
1974         if (!tegra_dc_is_powered(dc)) {
1975                 mutex_unlock(&dc->lock);
1976                 return IRQ_HANDLED;
1977         }
1978
1979         tegra_dc_get(dc);
1980
1981         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
1982                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
1983                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1984                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1985                 tegra_dc_put(dc);
1986                 mutex_unlock(&dc->lock);
1987                 return IRQ_HANDLED;
1988         }
1989
1990         /* clear all status flags except underflow, save those for the worker */
1991         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1992         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
1993         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1994         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
1995
1996         /*
1997          * Overlays can get thier internal state corrupted during and underflow
1998          * condition.  The only way to fix this state is to reset the DC.
1999          * if we get 4 consecutive frames with underflows, assume we're
2000          * hosed and reset.
2001          */
2002         underflow_mask = status & ALL_UF_INT();
2003
2004         /* Check underflow */
2005         if (underflow_mask) {
2006                 dc->underflow_mask |= underflow_mask;
2007                 schedule_delayed_work(&dc->underflow_work,
2008                         msecs_to_jiffies(1));
2009         }
2010
2011         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2012                 tegra_dc_one_shot_irq(dc, status, timestamp);
2013         else
2014                 tegra_dc_continuous_irq(dc, status, timestamp);
2015
2016         if (dc->nvsr)
2017                 tegra_dc_nvsr_irq(dc->nvsr, status);
2018
2019         /* update video mode if it has changed since the last frame */
2020         if (status & (FRAME_END_INT | V_BLANK_INT))
2021                 if (tegra_dc_update_mode(dc))
2022                         need_disable = 1; /* force display off on error */
2023
2024         if (status & FRAME_END_INT)
2025                 if (dc->disp_active_dirty) {
2026                         tegra_dc_writel(dc, dc->mode.h_active |
2027                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
2028                         tegra_dc_writel(dc,
2029                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2030
2031                         dc->disp_active_dirty = false;
2032                 }
2033
2034         tegra_dc_put(dc);
2035         mutex_unlock(&dc->lock);
2036
2037         if (need_disable)
2038                 tegra_dc_disable(dc);
2039         return IRQ_HANDLED;
2040 }
2041
2042 void tegra_dc_set_color_control(struct tegra_dc *dc)
2043 {
2044         u32 color_control;
2045
2046         switch (dc->out->depth) {
2047         case 3:
2048                 color_control = BASE_COLOR_SIZE111;
2049                 break;
2050
2051         case 6:
2052                 color_control = BASE_COLOR_SIZE222;
2053                 break;
2054
2055         case 8:
2056                 color_control = BASE_COLOR_SIZE332;
2057                 break;
2058
2059         case 9:
2060                 color_control = BASE_COLOR_SIZE333;
2061                 break;
2062
2063         case 12:
2064                 color_control = BASE_COLOR_SIZE444;
2065                 break;
2066
2067         case 15:
2068                 color_control = BASE_COLOR_SIZE555;
2069                 break;
2070
2071         case 16:
2072                 color_control = BASE_COLOR_SIZE565;
2073                 break;
2074
2075         case 18:
2076                 color_control = BASE_COLOR_SIZE666;
2077                 break;
2078
2079         default:
2080                 color_control = BASE_COLOR_SIZE888;
2081                 break;
2082         }
2083
2084         switch (dc->out->dither) {
2085         case TEGRA_DC_UNDEFINED_DITHER:
2086         case TEGRA_DC_DISABLE_DITHER:
2087                 color_control |= DITHER_CONTROL_DISABLE;
2088                 break;
2089         case TEGRA_DC_ORDERED_DITHER:
2090                 color_control |= DITHER_CONTROL_ORDERED;
2091                 break;
2092 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
2093         case TEGRA_DC_TEMPORAL_DITHER:
2094                 color_control |= DITHER_CONTROL_TEMPORAL;
2095                 break;
2096 #else
2097         case TEGRA_DC_ERRDIFF_DITHER:
2098                 /* The line buffer for error-diffusion dither is limited
2099                  * to 1280 pixels per line. This limits the maximum
2100                  * horizontal active area size to 1280 pixels when error
2101                  * diffusion is enabled.
2102                  */
2103                 BUG_ON(dc->mode.h_active > 1280);
2104                 color_control |= DITHER_CONTROL_ERRDIFF;
2105                 break;
2106 #endif
2107         default:
2108                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
2109         }
2110
2111 #ifdef CONFIG_TEGRA_DC_CMU
2112         if (dc->cmu_enabled)
2113                 color_control |= CMU_ENABLE;
2114 #endif
2115
2116         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2117 }
2118
2119 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2120 {
2121         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
2122                 return dc->win_syncpt[idx];
2123         BUG();
2124 }
2125
2126 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
2127 {
2128 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2129         u32 start, end;
2130         unsigned long val;
2131
2132         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
2133         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
2134
2135         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
2136                 dc->mode.v_back_porch + dc->mode.v_active;
2137         end = start + 1;
2138         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
2139         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
2140
2141         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2142         val |= V_PULSE2_INT;
2143         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
2144
2145         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2146         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2147 #endif
2148 }
2149
2150 static int tegra_dc_init(struct tegra_dc *dc)
2151 {
2152         int i;
2153         int int_enable;
2154         u32 val;
2155
2156         tegra_dc_io_start(dc);
2157         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2158         if (dc->ndev->id == 0) {
2159                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2160                                       TEGRA_MC_PRIO_MED);
2161                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2162                                       TEGRA_MC_PRIO_MED);
2163                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2164                                       TEGRA_MC_PRIO_MED);
2165 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2166                 /* only present on Tegra2 and 3 */
2167                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2168                                       TEGRA_MC_PRIO_MED);
2169 #endif
2170                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2171                                       TEGRA_MC_PRIO_HIGH);
2172         } else if (dc->ndev->id == 1) {
2173                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2174                                       TEGRA_MC_PRIO_MED);
2175                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2176                                       TEGRA_MC_PRIO_MED);
2177                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2178                                       TEGRA_MC_PRIO_MED);
2179 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2180                 /* only present on Tegra2 and 3 */
2181                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2182                                       TEGRA_MC_PRIO_MED);
2183 #endif
2184                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2185                                       TEGRA_MC_PRIO_HIGH);
2186         }
2187         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2188                         DC_CMD_CONT_SYNCPT_VSYNC);
2189
2190         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2191 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
2192         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2193                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
2194                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2195                 DC_CMD_INT_POLARITY);
2196 #else
2197         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2198                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2199                 DC_CMD_INT_POLARITY);
2200 #endif
2201         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2202         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2203 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2204         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2205 #endif
2206         /* enable interrupts for vblank, frame_end and underflows */
2207         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
2208         /* for panels with one-shot mode enable tearing effect interrupt */
2209         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2210                 int_enable |= MSF_INT;
2211
2212         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
2213         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
2214         tegra_dc_init_vpulse2_int(dc);
2215
2216 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
2217         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2218 #else
2219         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
2220 #endif
2221
2222 #ifdef CONFIG_TEGRA_DC_CMU
2223         _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2224 #endif
2225         tegra_dc_set_color_control(dc);
2226         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2227                 struct tegra_dc_win *win = &dc->windows[i];
2228                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2229                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2230                 tegra_dc_set_csc(dc, &win->csc);
2231                 tegra_dc_set_lut(dc, win);
2232                 tegra_dc_set_scaling_filter(dc);
2233         }
2234
2235 #ifdef CONFIG_TEGRA_DC_WIN_H
2236         /* Window H is set to window mode by default for t14x. */
2237         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
2238                         DC_DISP_BLEND_CURSOR_CONTROL);
2239 #endif
2240
2241         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2242                 u32 syncpt = get_syncpt(dc, i);
2243
2244                 /* refuse to operate on invalid syncpts */
2245                 if (WARN_ON(syncpt == NVSYNCPT_INVALID))
2246                         continue;
2247
2248                 dc->syncpt[i].id = syncpt;
2249
2250                 if (!nvhost_syncpt_read_ext_check(dc->ndev, syncpt, &val))
2251                         dc->syncpt[i].min = dc->syncpt[i].max = val;
2252         }
2253
2254         dc->crc_pending = false;
2255
2256         trace_display_mode(dc, &dc->mode);
2257
2258         if (dc->mode.pclk) {
2259                 if (!dc->initialized) {
2260                         if (tegra_dc_program_mode(dc, &dc->mode)) {
2261                                 tegra_dc_io_end(dc);
2262                                 dev_warn(&dc->ndev->dev,
2263                                         "%s: tegra_dc_program_mode failed\n",
2264                                         __func__);
2265                                 return -EINVAL;
2266                         }
2267                 } else {
2268                         dev_info(&dc->ndev->dev, "DC initialized, "
2269                                         "skipping tegra_dc_program_mode.\n");
2270                 }
2271         }
2272
2273         /* Initialize SD AFTER the modeset.
2274            nvsd_init handles the sd_settings = NULL case. */
2275         nvsd_init(dc, dc->out->sd_settings);
2276
2277         tegra_dc_io_end(dc);
2278
2279         return 0;
2280 }
2281
2282 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2283 {
2284         int failed_init = 0;
2285         int i;
2286
2287         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2288                 return false;
2289
2290         tegra_dc_unpowergate_locked(dc);
2291
2292         if (dc->out->enable)
2293                 dc->out->enable(&dc->ndev->dev);
2294
2295         tegra_dc_setup_clk(dc, dc->clk);
2296
2297         /* dc clk always on for continuous mode */
2298         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2299                 tegra_dc_clk_enable(dc);
2300         else
2301                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
2302
2303         tegra_dc_get(dc);
2304
2305         tegra_dc_power_on(dc);
2306
2307         /* do not accept interrupts during initialization */
2308         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2309
2310         enable_dc_irq(dc);
2311
2312         failed_init = tegra_dc_init(dc);
2313         if (failed_init) {
2314                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2315                 disable_irq_nosync(dc->irq);
2316                 tegra_dc_clear_bandwidth(dc);
2317                 if (dc->out && dc->out->disable)
2318                         dc->out->disable();
2319                 tegra_dc_put(dc);
2320                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2321                         tegra_dc_clk_disable(dc);
2322                 else
2323                         tegra_dvfs_set_rate(dc->clk, 0);
2324                 dev_warn(&dc->ndev->dev,
2325                         "%s: tegra_dc_init failed\n", __func__);
2326                 return false;
2327         }
2328
2329         tegra_dpaux_pad_power(dc, false);
2330
2331         if (dc->out_ops && dc->out_ops->enable)
2332                 dc->out_ops->enable(dc);
2333
2334         /* force a full blending update */
2335         for (i = 0; i < DC_N_WINDOWS; i++)
2336                 dc->blend.z[i] = -1;
2337
2338         tegra_dc_ext_enable(dc->ext);
2339
2340         /* initialize cursor to defaults, as driver depends on HW state */
2341         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
2342         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
2343 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2344         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
2345         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
2346 #endif
2347         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
2348         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
2349         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
2350         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
2351         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
2352
2353         trace_display_enable(dc);
2354
2355         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2356
2357         if (dc->out->postpoweron)
2358                 dc->out->postpoweron(&dc->ndev->dev);
2359
2360         if (dc->out_ops && dc->out_ops->postpoweron)
2361                 dc->out_ops->postpoweron(dc);
2362
2363         tegra_log_resume_time();
2364         /*
2365          * We will need to reinitialize the display the next time panel
2366          * is enabled.
2367          */
2368         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2369
2370         tegra_dc_put(dc);
2371
2372         return true;
2373 }
2374
2375 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2376 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2377 {
2378         bool ret = true;
2379
2380         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2381                 return false;
2382
2383         if (dc->out->enable)
2384                 dc->out->enable(&dc->ndev->dev);
2385
2386         tegra_dc_setup_clk(dc, dc->clk);
2387         tegra_dc_clk_enable(dc);
2388
2389         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2390                 mutex_lock(&tegra_dcs[1]->lock);
2391                 disable_irq_nosync(tegra_dcs[1]->irq);
2392         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2393                 mutex_lock(&tegra_dcs[0]->lock);
2394                 disable_irq_nosync(tegra_dcs[0]->irq);
2395         }
2396
2397         msleep(5);
2398         tegra_periph_reset_assert(dc->clk);
2399         msleep(2);
2400         if (tegra_platform_is_silicon()) {
2401                 tegra_periph_reset_deassert(dc->clk);
2402                 msleep(1);
2403         }
2404
2405         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2406                 enable_dc_irq(tegra_dcs[1]);
2407                 mutex_unlock(&tegra_dcs[1]->lock);
2408         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2409                 enable_dc_irq(tegra_dcs[0]);
2410                 mutex_unlock(&tegra_dcs[0]->lock);
2411         }
2412
2413         enable_dc_irq(dc);
2414
2415         if (tegra_dc_init(dc)) {
2416                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2417                 ret = false;
2418         }
2419
2420         if (dc->out_ops && dc->out_ops->enable)
2421                 dc->out_ops->enable(dc);
2422
2423         if (dc->out->postpoweron)
2424                 dc->out->postpoweron(&dc->ndev->dev);
2425
2426         /* force a full blending update */
2427         dc->blend.z[0] = -1;
2428
2429         tegra_dc_ext_enable(dc->ext);
2430
2431         if (!ret) {
2432                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2433                 _tegra_dc_controller_disable(dc);
2434         }
2435
2436         trace_display_reset(dc);
2437         return ret;
2438 }
2439 #endif
2440
2441 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2442 {
2443         if (dc->mode.pclk == 0) {
2444                 switch (dc->out->type) {
2445                 case TEGRA_DC_OUT_HDMI:
2446                 /* If DC is enable called, and HDMI is connected,
2447                  * but DC is not initialized by bootloader and no
2448                  * mode is set up, then set a fallback mode.
2449                  */
2450                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
2451                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2452                 } else
2453                         return false;
2454
2455                 break;
2456
2457                 case TEGRA_DC_OUT_DP:
2458                 case TEGRA_DC_OUT_NVSR_DP:
2459                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2460
2461                 /* Do nothing for other outputs for now */
2462                 case TEGRA_DC_OUT_RGB:
2463
2464                 case TEGRA_DC_OUT_DSI:
2465
2466                 default:
2467                         return false;
2468                 }
2469         }
2470
2471         return false;
2472 }
2473
2474 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2475 {
2476         return _tegra_dc_set_default_videomode(dc);
2477 }
2478
2479 static bool _tegra_dc_enable(struct tegra_dc *dc)
2480 {
2481         if (dc->mode.pclk == 0)
2482                 return false;
2483
2484         if (!dc->out)
2485                 return false;
2486
2487         if (dc->enabled)
2488                 return true;
2489
2490         pm_runtime_get_sync(&dc->ndev->dev);
2491
2492         if (dc->out->type == TEGRA_DC_OUT_HDMI && !tegra_dc_hpd(dc))
2493                 return false;
2494
2495         if (!_tegra_dc_controller_enable(dc)) {
2496                 pm_runtime_put_sync(&dc->ndev->dev);
2497                 return false;
2498         }
2499
2500         return true;
2501 }
2502
2503 void tegra_dc_enable(struct tegra_dc *dc)
2504 {
2505         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2506                 return;
2507
2508         mutex_lock(&dc->lock);
2509
2510         if (!dc->enabled)
2511                 dc->enabled = _tegra_dc_enable(dc);
2512
2513         mutex_unlock(&dc->lock);
2514         trace_display_mode(dc, &dc->mode);
2515 }
2516
2517 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
2518 {
2519         struct tegra_dc_win *w = &dc->windows[win];
2520
2521         /* reset window bandwidth */
2522         w->bandwidth = 0;
2523         w->new_bandwidth = 0;
2524
2525         /* disable windows */
2526         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2527
2528         /* refuse to operate on invalid syncpts */
2529         if (WARN_ON(dc->syncpt[win].id == NVSYNCPT_INVALID))
2530                 return;
2531
2532         /* flush any pending syncpt waits */
2533         dc->syncpt[win].max += 1;
2534         while (dc->syncpt[win].min < dc->syncpt[win].max) {
2535                 trace_display_syncpt_flush(dc, dc->syncpt[win].id,
2536                         dc->syncpt[win].min, dc->syncpt[win].max);
2537                 dc->syncpt[win].min++;
2538                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[win].id);
2539         }
2540 }
2541
2542 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2543 {
2544         unsigned i;
2545
2546         tegra_dc_get(dc);
2547
2548         if (dc->out && dc->out->prepoweroff)
2549                 dc->out->prepoweroff();
2550
2551         if (dc->out_ops && dc->out_ops->disable)
2552                 dc->out_ops->disable(dc);
2553
2554         if (tegra_powergate_is_powered(dc->powergate_id))
2555                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2556
2557         disable_irq_nosync(dc->irq);
2558
2559         tegra_dc_clear_bandwidth(dc);
2560
2561         if (dc->out && dc->out->disable)
2562                 dc->out->disable();
2563
2564         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2565                 tegra_dc_disable_window(dc, i);
2566         }
2567         trace_display_disable(dc);
2568
2569         if (dc->out_ops && dc->out_ops->postpoweroff)
2570                 dc->out_ops->postpoweroff(dc);
2571
2572         tegra_dc_put(dc);
2573
2574         /* disable always on dc clk in continuous mode */
2575         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2576                 tegra_dc_clk_disable(dc);
2577         else
2578                 tegra_dvfs_set_rate(dc->clk, 0);
2579 }
2580
2581 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2582 {
2583 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2584         u32 val;
2585         if (dc->enabled)  {
2586                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2587                 if (enable)
2588                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2589                 else
2590                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2591                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2592         }
2593 #endif
2594 }
2595
2596 bool tegra_dc_stats_get(struct tegra_dc *dc)
2597 {
2598 #if 0 /* right now it is always enabled */
2599         u32 val;
2600         bool res;
2601
2602         if (dc->enabled)  {
2603                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2604                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2605         } else {
2606                 res = false;
2607         }
2608
2609         return res;
2610 #endif
2611         return true;
2612 }
2613
2614 /* blank selected windows by disabling them */
2615 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
2616 {
2617         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2618         unsigned i;
2619         unsigned long int blank_windows;
2620         int nr_win = 0;
2621
2622         blank_windows = windows & dc->valid_windows;
2623
2624         if (!blank_windows)
2625                 return;
2626
2627         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
2628                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
2629                 if (!dcwins[nr_win])
2630                         continue;
2631                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2632         }
2633
2634         tegra_dc_update_windows(dcwins, nr_win, NULL);
2635         tegra_dc_sync_windows(dcwins, nr_win);
2636         tegra_dc_program_bandwidth(dc, true);
2637 }
2638
2639 int tegra_dc_restore(struct tegra_dc *dc)
2640 {
2641         return tegra_dc_ext_restore(dc->ext);
2642 }
2643
2644 static void _tegra_dc_disable(struct tegra_dc *dc)
2645 {
2646 #ifdef CONFIG_TEGRA_DC_CMU
2647         /* power down resets the registers, setting to true
2648          * causes CMU to be restored in tegra_dc_init(). */
2649         dc->cmu_dirty = true;
2650 #endif
2651
2652         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2653                 mutex_lock(&dc->one_shot_lock);
2654                 cancel_delayed_work_sync(&dc->one_shot_work);
2655         }
2656
2657         tegra_dc_io_start(dc);
2658         _tegra_dc_controller_disable(dc);
2659         tegra_dc_io_end(dc);
2660
2661         tegra_dc_powergate_locked(dc);
2662
2663         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2664                 mutex_unlock(&dc->one_shot_lock);
2665         pm_runtime_put(&dc->ndev->dev);
2666
2667         tegra_log_suspend_time();
2668 }
2669
2670 void tegra_dc_disable(struct tegra_dc *dc)
2671 {
2672         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2673                 return;
2674
2675         tegra_dc_ext_disable(dc->ext);
2676
2677         /* it's important that new underflow work isn't scheduled before the
2678          * lock is acquired. */
2679         cancel_delayed_work_sync(&dc->underflow_work);
2680
2681         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2682                 mutex_lock(&dc->one_shot_lp_lock);
2683         mutex_lock(&dc->lock);
2684
2685         if (dc->enabled) {
2686                 dc->enabled = false;
2687                 dc->blanked = false;
2688
2689                 if (!dc->suspended)
2690                         _tegra_dc_disable(dc);
2691         }
2692
2693 #ifdef CONFIG_SWITCH
2694         switch_set_state(&dc->modeset_switch, 0);
2695 #endif
2696         mutex_unlock(&dc->lock);
2697         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2698                 mutex_unlock(&dc->one_shot_lp_lock);
2699         synchronize_irq(dc->irq);
2700         trace_display_mode(dc, &dc->mode);
2701
2702         /* disable pending clks due to uncompleted frames */
2703         while (tegra_is_clk_enabled(dc->clk))
2704                 tegra_dc_put(dc);
2705 }
2706
2707 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2708 static void tegra_dc_reset_worker(struct work_struct *work)
2709 {
2710         struct tegra_dc *dc =
2711                 container_of(work, struct tegra_dc, reset_work);
2712
2713         unsigned long val = 0;
2714
2715         mutex_lock(&shared_lock);
2716
2717         dev_warn(&dc->ndev->dev,
2718                 "overlay stuck in underflow state.  resetting.\n");
2719
2720         tegra_dc_ext_disable(dc->ext);
2721
2722         mutex_lock(&dc->lock);
2723
2724         if (dc->enabled == false)
2725                 goto unlock;
2726
2727         dc->enabled = false;
2728
2729         /*
2730          * off host read bus
2731          */
2732         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2733         val &= ~(0x00000100);
2734         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2735
2736         /*
2737          * set DC to STOP mode
2738          */
2739         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2740
2741         msleep(10);
2742
2743         _tegra_dc_controller_disable(dc);
2744
2745         /* _tegra_dc_controller_reset_enable deasserts reset */
2746         _tegra_dc_controller_reset_enable(dc);
2747
2748         dc->enabled = true;
2749
2750         /* reopen host read bus */
2751         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2752         val &= ~(0x00000100);
2753         val |= 0x100;
2754         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2755
2756 unlock:
2757         mutex_unlock(&dc->lock);
2758         mutex_unlock(&shared_lock);
2759         trace_display_reset(dc);
2760 }
2761 #endif
2762
2763 static void tegra_dc_underflow_worker(struct work_struct *work)
2764 {
2765         struct tegra_dc *dc = container_of(
2766                 to_delayed_work(work), struct tegra_dc, underflow_work);
2767
2768         mutex_lock(&dc->lock);
2769         tegra_dc_get(dc);
2770
2771         if (dc->enabled) {
2772                 tegra_dc_underflow_handler(dc);
2773         }
2774         tegra_dc_put(dc);
2775         mutex_unlock(&dc->lock);
2776 }
2777
2778 static void (*flip_callback)(void);
2779 static spinlock_t flip_callback_lock;
2780 static bool init_tegra_dc_flip_callback_called;
2781
2782 static int __init init_tegra_dc_flip_callback(void)
2783 {
2784         spin_lock_init(&flip_callback_lock);
2785         init_tegra_dc_flip_callback_called = true;
2786         return 0;
2787 }
2788
2789 pure_initcall(init_tegra_dc_flip_callback);
2790
2791 int tegra_dc_set_flip_callback(void (*callback)(void))
2792 {
2793         WARN_ON(!init_tegra_dc_flip_callback_called);
2794
2795         spin_lock(&flip_callback_lock);
2796         flip_callback = callback;
2797         spin_unlock(&flip_callback_lock);
2798
2799         return 0;
2800 }
2801 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
2802
2803 int tegra_dc_unset_flip_callback()
2804 {
2805         spin_lock(&flip_callback_lock);
2806         flip_callback = NULL;
2807         spin_unlock(&flip_callback_lock);
2808
2809         return 0;
2810 }
2811 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
2812
2813 void tegra_dc_call_flip_callback()
2814 {
2815         spin_lock(&flip_callback_lock);
2816         if (flip_callback)
2817                 flip_callback();
2818         spin_unlock(&flip_callback_lock);
2819 }
2820 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
2821
2822 #ifdef CONFIG_SWITCH
2823 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2824 {
2825         struct tegra_dc *dc =
2826                 container_of(sdev, struct tegra_dc, modeset_switch);
2827
2828         if (!sdev->state)
2829                 return sprintf(buf, "offline\n");
2830
2831         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2832 }
2833 #endif
2834
2835 static int tegra_dc_probe(struct platform_device *ndev)
2836 {
2837         struct tegra_dc *dc;
2838         struct tegra_dc_mode *mode;
2839         struct tegra_dc_platform_data *dt_pdata = NULL;
2840         struct clk *clk;
2841 #ifndef CONFIG_TEGRA_ISOMGR
2842         struct clk *emc_clk;
2843 #else
2844         int isomgr_client_id = -1;
2845 #endif
2846         struct device_node *np = ndev->dev.of_node;
2847         struct resource *res;
2848         struct resource dt_res;
2849         struct resource *base_res;
2850         struct resource *fb_mem = NULL;
2851         int ret = 0;
2852         void __iomem *base;
2853         int irq;
2854         int i;
2855
2856         if (!np && !ndev->dev.platform_data) {
2857                 dev_err(&ndev->dev, "no platform data\n");
2858                 return -ENOENT;
2859         }
2860
2861         /* Specify parameters for the maximum physical segment size. */
2862         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
2863
2864         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2865         if (!dc) {
2866                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2867                 return -ENOMEM;
2868         }
2869
2870         if (np) {
2871                 dt_pdata = of_dc_parse_platform_data(ndev);
2872                 if (dt_pdata == NULL)
2873                         goto err_free;
2874
2875 #ifdef CONFIG_OF
2876                 irq = of_irq_to_resource(np, 0, NULL);
2877                 if (!irq)
2878                         goto err_free;
2879 #endif
2880
2881                 ret = of_address_to_resource(np, 0, &dt_res);
2882                 if (ret)
2883                         goto err_free;
2884
2885                 if (dt_res.start == TEGRA_DISPLAY_BASE)
2886                         ndev->id = 0;
2887                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
2888                         ndev->id = 1;
2889                 else
2890                         goto err_free;
2891
2892                 res = &dt_res;
2893         } else {
2894                 irq = platform_get_irq_byname(ndev, "irq");
2895                 if (irq <= 0) {
2896                         dev_err(&ndev->dev, "no irq\n");
2897                         ret = -ENOENT;
2898                         goto err_free;
2899                 }
2900
2901                 res = platform_get_resource_byname(ndev,
2902                         IORESOURCE_MEM, "regs");
2903                 if (!res) {
2904                         dev_err(&ndev->dev, "no mem resource\n");
2905                         ret = -ENOENT;
2906                         goto err_free;
2907                 }
2908         }
2909
2910         base_res = request_mem_region(res->start, resource_size(res),
2911                 ndev->name);
2912         if (!base_res) {
2913                 dev_err(&ndev->dev, "request_mem_region failed\n");
2914                 ret = -EBUSY;
2915                 goto err_free;
2916         }
2917
2918         base = ioremap(res->start, resource_size(res));
2919         if (!base) {
2920                 dev_err(&ndev->dev, "registers can't be mapped\n");
2921                 ret = -EBUSY;
2922                 goto err_release_resource_reg;
2923         }
2924
2925         for (i = 0; i < DC_N_WINDOWS; i++)
2926                 dc->win_syncpt[i] = NVSYNCPT_INVALID;
2927
2928         if (TEGRA_DISPLAY_BASE == res->start) {
2929                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2930                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp0_a");
2931                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp0_b");
2932                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp0_c");
2933                 dc->valid_windows = 0x07;
2934 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2935                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
2936                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp0_h");
2937                 dc->valid_windows |= 0x18;
2938 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2939                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
2940                 dc->valid_windows |= 0x08;
2941 #endif
2942                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2943 #ifdef CONFIG_TEGRA_ISOMGR
2944                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
2945 #endif
2946         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2947                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2948                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp1_a");
2949                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp1_b");
2950                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp1_c");
2951                 dc->valid_windows = 0x07;
2952 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2953                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp1_h");
2954                 dc->valid_windows |= 0x10;
2955 #endif
2956                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2957 #ifdef CONFIG_TEGRA_ISOMGR
2958                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
2959 #endif
2960         } else {
2961                 dev_err(&ndev->dev,
2962                         "Unknown base address %llx: unable to assign syncpt\n",
2963                         (u64)res->start);
2964         }
2965
2966         if (np) {
2967                 struct resource of_fb_res;
2968                 if (ndev->id == 0)
2969                         tegra_get_fb_resource(&of_fb_res);
2970                 else /*ndev->id == 1*/
2971                         tegra_get_fb2_resource(&of_fb_res);
2972
2973                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
2974                 if (fb_mem == NULL) {
2975                         ret = -ENOMEM;
2976                         goto err_iounmap_reg;
2977                 }
2978                 fb_mem->name = "fbmem";
2979                 fb_mem->flags = IORESOURCE_MEM;
2980                 fb_mem->start = (resource_size_t)of_fb_res.start;
2981                 fb_mem->end = (resource_size_t)of_fb_res.end;
2982         } else {
2983                 fb_mem = platform_get_resource_byname(ndev,
2984                         IORESOURCE_MEM, "fbmem");
2985         }
2986
2987         clk = clk_get(&ndev->dev, NULL);
2988         if (IS_ERR_OR_NULL(clk)) {
2989                 dev_err(&ndev->dev, "can't get clock\n");
2990                 ret = -ENOENT;
2991                 goto err_iounmap_reg;
2992         }
2993
2994         dc->clk = clk;
2995         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2996         /* Initialize one shot work delay, it will be assigned by dsi
2997          * according to refresh rate later. */
2998         dc->one_shot_delay_ms = 40;
2999
3000         dc->base_res = base_res;
3001         dc->base = base;
3002         dc->irq = irq;
3003         dc->ndev = ndev;
3004         dc->fb_mem = fb_mem;
3005
3006         if (!np)
3007                 dc->pdata = ndev->dev.platform_data;
3008         else
3009                 dc->pdata = dt_pdata;
3010
3011         dc->bw_kbps = 0;
3012
3013         mutex_init(&dc->lock);
3014         mutex_init(&dc->one_shot_lock);
3015         mutex_init(&dc->one_shot_lp_lock);
3016         init_completion(&dc->frame_end_complete);
3017         init_completion(&dc->crc_complete);
3018         init_waitqueue_head(&dc->wq);
3019         init_waitqueue_head(&dc->timestamp_wq);
3020 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3021         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3022 #endif
3023         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3024         dc->vblank_ref_count = 0;
3025 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3026         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
3027 #endif
3028         dc->vpulse2_ref_count = 0;
3029         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3030         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3031
3032         tegra_dc_init_lut_defaults(&dc->fb_lut);
3033
3034         dc->n_windows = DC_N_WINDOWS;
3035         for (i = 0; i < DC_N_WINDOWS; i++) {
3036                 struct tegra_dc_win *win = &dc->windows[i];
3037                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
3038                 if (!test_bit(i, &dc->valid_windows))
3039                         win->flags |= TEGRA_WIN_FLAG_INVALID;
3040                 win->idx = i;
3041                 win->dc = dc;
3042                 tmp_win->idx = i;
3043                 tmp_win->dc = dc;
3044                 tegra_dc_init_csc_defaults(&win->csc);
3045                 tegra_dc_init_lut_defaults(&win->lut);
3046         }
3047
3048         ret = tegra_dc_set(dc, ndev->id);
3049         if (ret < 0) {
3050                 dev_err(&ndev->dev, "can't add dc\n");
3051                 goto err_put_clk;
3052         }
3053
3054         platform_set_drvdata(ndev, dc);
3055
3056 #ifdef CONFIG_SWITCH
3057         dc->modeset_switch.name = dev_name(&ndev->dev);
3058         dc->modeset_switch.state = 0;
3059         dc->modeset_switch.print_state = switch_modeset_print_mode;
3060         ret = switch_dev_register(&dc->modeset_switch);
3061         if (ret < 0)
3062                 dev_err(&ndev->dev, "failed to register switch driver\n");
3063 #endif
3064
3065         tegra_dc_feature_register(dc);
3066
3067         if (dc->pdata->default_out) {
3068 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3069                 if (dc->pdata->default_out->hotplug_init)
3070                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
3071 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3072                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
3073                 if (ret < 0) {
3074                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
3075                         goto err_put_clk;
3076                 }
3077         } else {
3078                 dev_err(&ndev->dev,
3079                         "No default output specified.  Leaving output disabled.\n");
3080         }
3081         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
3082
3083 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3084         if (dc->out && dc->out->n_modes &&
3085             (dc->out->type == TEGRA_DC_OUT_HDMI)) {
3086                 struct fb_monspecs specs;
3087                 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
3088                 if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
3089                         struct tegra_dc_mode *dcmode = &dc->out->modes[0];
3090                         dcmode->pclk          = specs.modedb->pixclock;
3091                         dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
3092                         dcmode->pclk         *= 1000;
3093                         dcmode->h_ref_to_sync = 1;
3094                         dcmode->v_ref_to_sync = 1;
3095                         dcmode->h_sync_width  = specs.modedb->hsync_len;
3096                         dcmode->v_sync_width  = specs.modedb->vsync_len;
3097                         dcmode->h_back_porch  = specs.modedb->left_margin;
3098                         dcmode->v_back_porch  = specs.modedb->upper_margin;
3099                         dcmode->h_active      = specs.modedb->xres;
3100                         dcmode->v_active      = specs.modedb->yres;
3101                         dcmode->h_front_porch = specs.modedb->right_margin;
3102                         dcmode->v_front_porch = specs.modedb->lower_margin;
3103                         tegra_dc_set_mode(dc, dcmode);
3104                         dc->pdata->fb->xres = dcmode->h_active;
3105                         dc->pdata->fb->yres = dcmode->v_active;
3106                 }
3107         }
3108 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3109
3110 #ifndef CONFIG_TEGRA_ISOMGR
3111                 /*
3112                  * The emc is a shared clock, it will be set based on
3113                  * the requirements for each user on the bus.
3114                  */
3115                 emc_clk = clk_get(&ndev->dev, "emc");
3116                 if (IS_ERR_OR_NULL(emc_clk)) {
3117                         dev_err(&ndev->dev, "can't get emc clock\n");
3118                         ret = -ENOENT;
3119                         goto err_put_clk;
3120                 }
3121                 dc->emc_clk = emc_clk;
3122 #endif
3123
3124         dc->ext = tegra_dc_ext_register(ndev, dc);
3125         if (IS_ERR_OR_NULL(dc->ext)) {
3126                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3127                 dc->ext = NULL;
3128         }
3129
3130         /* interrupt handler must be registered before tegra_fb_register() */
3131         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
3132                         dev_name(&ndev->dev), dc)) {
3133                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3134                 ret = -EBUSY;
3135                 goto err_disable_dc;
3136         }
3137         disable_dc_irq(dc);
3138
3139         tegra_pd_add_device(&ndev->dev);
3140         pm_runtime_use_autosuspend(&ndev->dev);
3141         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
3142         pm_runtime_enable(&ndev->dev);
3143
3144 #ifdef CONFIG_TEGRA_DC_CMU
3145         /* if bootloader leaves this head enabled, then skip CMU programming. */
3146         dc->cmu_dirty = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) == 0;
3147         dc->cmu_enabled = dc->pdata->cmu_enable;
3148 #endif
3149
3150         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
3151                 /* WAR: BL is putting DC in bad state for EDP configuration */
3152                 if (dc->out->type == TEGRA_DC_OUT_DP ||
3153                         dc->out->type == TEGRA_DC_OUT_NVSR_DP) {
3154                         clk_prepare_enable(dc->clk);
3155                         tegra_periph_reset_assert(dc->clk);
3156                         udelay(10);
3157                         tegra_periph_reset_deassert(dc->clk);
3158                         udelay(10);
3159                         clk_disable_unprepare(dc->clk);
3160                 }
3161                 _tegra_dc_set_default_videomode(dc);
3162                 dc->enabled = _tegra_dc_enable(dc);
3163
3164 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3165                 /* BL or PG init will keep DISA unpowergated after booting.
3166                  * Adding an extra powergate to balance the refcount
3167                  * since _tegra_dc_enable() increases the refcount.
3168                  */
3169                 if (dc->powergate_id == TEGRA_POWERGATE_DISA)
3170                         tegra_dc_powergate_locked(dc);
3171 #endif
3172         }
3173
3174 #ifdef CONFIG_TEGRA_ISOMGR
3175         if (isomgr_client_id == -1) {
3176                 dc->isomgr_handle = NULL;
3177         } else {
3178                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
3179                         tegra_dc_calc_min_bandwidth(dc),
3180                         tegra_dc_bandwidth_renegotiate, dc);
3181                 if (IS_ERR(dc->isomgr_handle)) {
3182                         dev_err(&dc->ndev->dev,
3183                                 "could not register isomgr. err=%ld\n",
3184                                 PTR_ERR(dc->isomgr_handle));
3185                         ret = -ENOENT;
3186                         goto err_put_clk;
3187                 }
3188                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
3189                 /*
3190                  * Use maximum value so we can try to reserve as much as
3191                  * needed until we are told by isomgr to backoff.
3192                  */
3193                 dc->available_bw = UINT_MAX;
3194         }
3195 #endif
3196
3197         tegra_dc_create_debugfs(dc);
3198
3199         dev_info(&ndev->dev, "probed\n");
3200
3201         if (dc->pdata->fb) {
3202                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
3203                         unsigned long fmt;
3204                         tegra_dc_writel(dc,
3205                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3206                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3207
3208                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3209                         dc->pdata->fb->bits_per_pixel =
3210                                 tegra_dc_fmt_bpp(fmt);
3211                 }
3212
3213                 mode = tegra_dc_get_override_mode(dc);
3214                 if (mode) {
3215                         dc->pdata->fb->xres = mode->h_active;
3216                         dc->pdata->fb->yres = mode->v_active;
3217                 }
3218
3219 #ifdef CONFIG_ADF_TEGRA
3220                 tegra_dc_io_start(dc);
3221                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb);
3222                 tegra_dc_io_end(dc);
3223
3224                 if (IS_ERR(dc->adf)) {
3225                         tegra_dc_io_start(dc);
3226                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
3227                                         fb_mem);
3228                         tegra_dc_io_end(dc);
3229                         if (IS_ERR_OR_NULL(dc->fb)) {
3230                                 dc->fb = NULL;
3231                                 dev_err(&ndev->dev, "failed to register fb\n");
3232                                 goto err_remove_debugfs;
3233                         }
3234                 }
3235 #else
3236                 tegra_dc_io_start(dc);
3237                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3238                 tegra_dc_io_end(dc);
3239                 if (IS_ERR_OR_NULL(dc->fb)) {
3240                         dc->fb = NULL;
3241                         dev_err(&ndev->dev, "failed to register fb\n");
3242                         goto err_remove_debugfs;
3243                 }
3244 #endif
3245         }
3246
3247 #ifndef CONFIG_FRAMEBUFFER_CONSOLE
3248         if (dc->out && dc->out->hotplug_init)
3249                 dc->out->hotplug_init(&ndev->dev);
3250 #endif /* !CONFIG_FRAMEBUFFER_CONSOLE */
3251
3252         if (dc->out_ops) {
3253                 if (dc->out_ops->detect)
3254                         dc->connected = dc->out_ops->detect(dc);
3255                 else
3256                         dc->connected = true;
3257         }
3258         else
3259                 dc->connected = false;
3260
3261         /* Powergate display module when it's unconnected. */
3262         /* detect() function, if presetns, responsible for the powergate */
3263         if (!tegra_dc_get_connected(dc) &&
3264                         !(dc->out_ops && dc->out_ops->detect))
3265                 tegra_dc_powergate_locked(dc);
3266
3267         tegra_dc_create_sysfs(&dc->ndev->dev);
3268
3269         /*
3270          * Overriding the display mode only applies for modes set up during
3271          * boot. It should not apply for e.g. HDMI hotplug.
3272          */
3273         dc->initialized = false;
3274
3275         return 0;
3276
3277 err_remove_debugfs:
3278         tegra_dc_remove_debugfs(dc);
3279         free_irq(irq, dc);
3280 err_disable_dc:
3281         if (dc->ext) {
3282                 tegra_dc_ext_disable(dc->ext);
3283                 tegra_dc_ext_unregister(dc->ext);
3284         }
3285         mutex_lock(&dc->lock);
3286         if (dc->enabled)
3287                 _tegra_dc_disable(dc);
3288         dc->enabled = false;
3289         mutex_unlock(&dc->lock);
3290 #ifdef CONFIG_SWITCH
3291         switch_dev_unregister(&dc->modeset_switch);
3292 #endif
3293 #ifdef CONFIG_TEGRA_ISOMGR
3294         tegra_isomgr_unregister(dc->isomgr_handle);
3295 #else
3296         clk_put(emc_clk);
3297 #endif
3298 err_put_clk:
3299         clk_put(clk);
3300 err_iounmap_reg:
3301         iounmap(base);
3302         if (fb_mem) {
3303                 if (!np)
3304                         release_resource(fb_mem);
3305                 else
3306                         kfree(fb_mem);
3307         }
3308 err_release_resource_reg:
3309         release_resource(base_res);
3310 err_free:
3311         kfree(dc);
3312
3313         return ret;
3314 }
3315
3316 static int tegra_dc_remove(struct platform_device *ndev)
3317 {
3318         struct tegra_dc *dc = platform_get_drvdata(ndev);
3319         struct device_node *np = ndev->dev.of_node;
3320
3321         tegra_dc_remove_sysfs(&dc->ndev->dev);
3322         tegra_dc_remove_debugfs(dc);
3323
3324         if (dc->fb) {
3325                 tegra_fb_unregister(dc->fb);
3326                 if (dc->fb_mem) {
3327                         if (!np)
3328                                 release_resource(dc->fb_mem);
3329                         else
3330                                 kfree(dc->fb_mem);
3331                 }
3332         }
3333
3334 #ifdef CONFIG_ADF_TEGRA
3335         if (dc->adf)
3336                 tegra_adf_unregister(dc->adf);
3337 #endif
3338
3339         tegra_dc_ext_disable(dc->ext);
3340
3341         if (dc->ext)
3342                 tegra_dc_ext_unregister(dc->ext);
3343
3344         mutex_lock(&dc->lock);
3345         if (dc->enabled)
3346                 _tegra_dc_disable(dc);
3347         dc->enabled = false;
3348         mutex_unlock(&dc->lock);
3349         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3350
3351 #ifdef CONFIG_SWITCH
3352         switch_dev_unregister(&dc->modeset_switch);
3353 #endif
3354         free_irq(dc->irq, dc);
3355 #ifdef CONFIG_TEGRA_ISOMGR
3356         if (dc->isomgr_handle) {
3357                 tegra_isomgr_unregister(dc->isomgr_handle);
3358                 dc->isomgr_handle = NULL;
3359         }
3360 #else
3361         clk_put(dc->emc_clk);
3362 #endif
3363         clk_put(dc->clk);
3364         iounmap(dc->base);
3365         if (dc->fb_mem)
3366                 release_resource(dc->base_res);
3367         kfree(dc);
3368         tegra_dc_set(NULL, ndev->id);
3369
3370         return 0;
3371 }
3372
3373 #ifdef CONFIG_PM
3374 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
3375 {
3376         struct tegra_dc *dc = platform_get_drvdata(ndev);
3377         int ret = 0;
3378
3379         trace_display_suspend(dc);
3380         dev_info(&ndev->dev, "suspend\n");
3381
3382         tegra_dc_ext_disable(dc->ext);
3383
3384         tegra_dc_cursor_suspend(dc);
3385         mutex_lock(&dc->lock);
3386         ret = tegra_dc_io_start(dc);
3387
3388         if (dc->out_ops && dc->out_ops->suspend)
3389                 dc->out_ops->suspend(dc);
3390
3391         if (dc->enabled) {
3392                 _tegra_dc_disable(dc);
3393
3394                 dc->suspended = true;
3395         }
3396
3397         if (dc->out && dc->out->postsuspend) {
3398                 dc->out->postsuspend();
3399                 /* avoid resume event due to voltage falling on interfaces that
3400                  * support hotplug wake. And only do this if a panel is
3401                  * connected, if we are already disconnected, then no phantom
3402                  * hotplug can occur by disabling the voltage.
3403                  */
3404                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
3405                         && tegra_dc_get_connected(dc))
3406                         msleep(100);
3407         }
3408
3409         if (!ret)
3410                 tegra_dc_io_end(dc);
3411
3412 #ifdef CONFIG_TEGRA_DC_CMU
3413         /*
3414          * CMU settings are lost when the DC goes to sleep. User-space will
3415          * perform a blank ioctl upon resume which will call tegra_dc_init()
3416          * and apply CMU settings again, but only if the cached values are
3417          * different from those specified. Clearing the cache here ensures
3418          * that this will happen.
3419          *
3420          * It would be better to reapply the CMU settings in tegra_dc_resume(),
3421          * but color corruption sometimes happens if we do so and
3422          * tegra_dc_init() seems to be the only safe place for this.
3423          */
3424         memset(&dc->cmu, 0, sizeof(dc->cmu));
3425 #endif
3426
3427         mutex_unlock(&dc->lock);
3428         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3429
3430         return 0;
3431 }
3432
3433 static int tegra_dc_resume(struct platform_device *ndev)
3434 {
3435         struct tegra_dc *dc = platform_get_drvdata(ndev);
3436
3437         trace_display_resume(dc);
3438         dev_info(&ndev->dev, "resume\n");
3439
3440         mutex_lock(&dc->lock);
3441         dc->suspended = false;
3442
3443         /* To pan the fb on resume */
3444         tegra_fb_pan_display_reset(dc->fb);
3445
3446         if (dc->enabled) {
3447                 dc->enabled = false;
3448                 _tegra_dc_set_default_videomode(dc);
3449                 dc->enabled = _tegra_dc_enable(dc);
3450         }
3451
3452         if (dc->out && dc->out->hotplug_init)
3453                 dc->out->hotplug_init(&ndev->dev);
3454
3455         if (dc->out_ops && dc->out_ops->resume)
3456                 dc->out_ops->resume(dc);
3457
3458         mutex_unlock(&dc->lock);
3459         tegra_dc_cursor_resume(dc);
3460
3461         return 0;
3462 }
3463
3464 #endif /* CONFIG_PM */
3465
3466 static void tegra_dc_shutdown(struct platform_device *ndev)
3467 {
3468         struct tegra_dc *dc = platform_get_drvdata(ndev);
3469
3470         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3471                 return;
3472
3473         if (!dc->enabled)
3474                 return;
3475
3476         tegra_dc_disable(dc);
3477 }
3478
3479 extern int suspend_set(const char *val, struct kernel_param *kp)
3480 {
3481         if (!strcmp(val, "dump"))
3482                 dump_regs(tegra_dcs[0]);
3483 #ifdef CONFIG_PM
3484         else if (!strcmp(val, "suspend"))
3485                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3486         else if (!strcmp(val, "resume"))
3487                 tegra_dc_resume(tegra_dcs[0]->ndev);
3488 #endif
3489
3490         return 0;
3491 }
3492
3493 extern int suspend_get(char *buffer, struct kernel_param *kp)
3494 {
3495         return 0;
3496 }
3497
3498 int suspend;
3499
3500 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3501
3502
3503 #ifdef CONFIG_OF
3504 static struct of_device_id tegra_display_of_match[] = {
3505         {.compatible = "nvidia,tegra114-dc", },
3506         {.compatible = "nvidia,tegra124-dc", },
3507         { },
3508 };
3509 #endif
3510
3511 struct platform_driver tegra_dc_driver = {
3512         .driver = {
3513                 .name = "tegradc",
3514                 .owner = THIS_MODULE,
3515 #ifdef CONFIG_OF
3516                 .of_match_table =
3517                         of_match_ptr(tegra_display_of_match),
3518 #endif
3519         },
3520         .probe = tegra_dc_probe,
3521         .remove = tegra_dc_remove,
3522 #ifdef CONFIG_PM
3523         .suspend = tegra_dc_suspend,
3524         .resume = tegra_dc_resume,
3525 #endif
3526         .shutdown = tegra_dc_shutdown,
3527 };
3528
3529 #ifndef MODULE
3530 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
3531 {
3532         int i, params[11];
3533         char *p;
3534
3535         for (i = 0; i < ARRAY_SIZE(params); i++) {
3536                 if ((p = strsep(&options, ",")) != NULL) {
3537                         if (*p)
3538                                 params[i] = simple_strtoul(p, &p, 10);
3539                 } else
3540                         return -EINVAL;
3541         }
3542
3543         if ((mode->pclk = params[0]) == 0)
3544                 return -EINVAL;
3545
3546         mode->h_active      = params[1];
3547         mode->v_active      = params[2];
3548         mode->h_ref_to_sync = params[3];
3549         mode->v_ref_to_sync = params[4];
3550         mode->h_sync_width  = params[5];
3551         mode->v_sync_width  = params[6];
3552         mode->h_back_porch  = params[7];
3553         mode->v_back_porch  = params[8];
3554         mode->h_front_porch = params[9];
3555         mode->v_front_porch = params[10];
3556
3557         return 0;
3558 }
3559
3560 static int __init tegra_dc_mode_override(char *str)
3561 {
3562         char *p = str, *options;
3563
3564         if (!p || !*p)
3565                 return -EINVAL;
3566
3567         p = strstr(str, "hdmi:");
3568         if (p) {
3569                 p += 5;
3570                 options = strsep(&p, ";");
3571                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
3572                         return -EINVAL;
3573         }
3574
3575         p = strstr(str, "rgb:");
3576         if (p) {
3577                 p += 4;
3578                 options = strsep(&p, ";");
3579                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
3580                         return -EINVAL;
3581         }
3582
3583         p = strstr(str, "dsi:");
3584         if (p) {
3585                 p += 4;
3586                 options = strsep(&p, ";");
3587                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
3588                         return -EINVAL;
3589         }
3590
3591         return 0;
3592 }
3593
3594 __setup("disp_params=", tegra_dc_mode_override);
3595 #endif
3596
3597 static int __init tegra_dc_module_init(void)
3598 {
3599         int ret = tegra_dc_ext_module_init();
3600         if (ret)
3601                 return ret;
3602         return platform_driver_register(&tegra_dc_driver);
3603 }
3604
3605 static void __exit tegra_dc_module_exit(void)
3606 {
3607         platform_driver_unregister(&tegra_dc_driver);
3608         tegra_dc_ext_module_exit();
3609 }
3610
3611 module_exit(tegra_dc_module_exit);
3612 module_init(tegra_dc_module_init);