drivers/gpu/nvgpu/gk20a/channel_gk20a.c

   1 /*
   2  * drivers/video/tegra/host/gk20a/channel_gk20a.c
   3  *
   4  * GK20A Graphics channel
   5  *
   6  * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21
  22 #include <linux/nvhost.h>
  23 #include <linux/list.h>
  24 #include <linux/delay.h>
  25 #include <linux/highmem.h> /* need for nvmap.h*/
  26 #include <trace/events/gk20a.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/file.h>
  29 #include <linux/anon_inodes.h>
  30 #include <linux/dma-buf.h>
  31
  32 #include "debug_gk20a.h"
  33
  34 #include "gk20a.h"
  35 #include "dbg_gpu_gk20a.h"
  36
  37 #include "hw_ram_gk20a.h"
  38 #include "hw_fifo_gk20a.h"
  39 #include "hw_pbdma_gk20a.h"
  40 #include "hw_ccsr_gk20a.h"
  41 #include "hw_ltc_gk20a.h"
  42
  43 #define NVMAP_HANDLE_PARAM_SIZE 1
  44
  45 static struct channel_gk20a *acquire_unused_channel(struct fifo_gk20a *f);
  46 static void release_used_channel(struct fifo_gk20a *f, struct channel_gk20a *c);
  47
  48 static void free_priv_cmdbuf(struct channel_gk20a *c,
  49                              struct priv_cmd_entry *e);
  50 static void recycle_priv_cmdbuf(struct channel_gk20a *c);
  51
  52 static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c);
  53 static void channel_gk20a_free_priv_cmdbuf(struct channel_gk20a *c);
  54
  55 static int channel_gk20a_commit_userd(struct channel_gk20a *c);
  56 static int channel_gk20a_setup_userd(struct channel_gk20a *c);
  57 static int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
  58                         u64 gpfifo_base, u32 gpfifo_entries);
  59
  60 static void channel_gk20a_bind(struct channel_gk20a *ch_gk20a);
  61 static void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a);
  62
  63 static int channel_gk20a_alloc_inst(struct gk20a *g,
  64                                 struct channel_gk20a *ch);
  65 static void channel_gk20a_free_inst(struct gk20a *g,
  66                                 struct channel_gk20a *ch);
  67
  68 static int channel_gk20a_update_runlist(struct channel_gk20a *c,
  69                                         bool add);
  70 static void gk20a_free_error_notifiers(struct channel_gk20a *ch);
  71
  72 static struct channel_gk20a *acquire_unused_channel(struct fifo_gk20a *f)
  73 {
  74         struct channel_gk20a *ch = NULL;
  75         int chid;
  76
  77         mutex_lock(&f->ch_inuse_mutex);
  78         for (chid = 0; chid < f->num_channels; chid++) {
  79                 if (!f->channel[chid].in_use) {
  80                         f->channel[chid].in_use = true;
  81                         ch = &f->channel[chid];
  82                         break;
  83                 }
  84         }
  85         mutex_unlock(&f->ch_inuse_mutex);
  86
  87         return ch;
  88 }
  89
  90 static void release_used_channel(struct fifo_gk20a *f, struct channel_gk20a *c)
  91 {
  92         mutex_lock(&f->ch_inuse_mutex);
  93         f->channel[c->hw_chid].in_use = false;
  94         mutex_unlock(&f->ch_inuse_mutex);
  95 }
  96
  97 int channel_gk20a_commit_va(struct channel_gk20a *c)
  98 {
  99         u64 addr;
 100         u32 addr_lo;
 101         u32 addr_hi;
 102         void *inst_ptr;
 103
 104         gk20a_dbg_fn("");
 105
 106         inst_ptr = c->inst_block.cpuva;
 107         if (!inst_ptr)
 108                 return -ENOMEM;
 109
 110         addr = gk20a_mm_iova_addr(c->vm->pdes.sgt->sgl);
 111         addr_lo = u64_lo32(addr >> 12);
 112         addr_hi = u64_hi32(addr);
 113
 114         gk20a_dbg_info("pde pa=0x%llx addr_lo=0x%x addr_hi=0x%x",
 115                    (u64)addr, addr_lo, addr_hi);
 116
 117         gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(),
 118                 ram_in_page_dir_base_target_vid_mem_f() |
 119                 ram_in_page_dir_base_vol_true_f() |
 120                 ram_in_page_dir_base_lo_f(addr_lo));
 121
 122         gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(),
 123                 ram_in_page_dir_base_hi_f(addr_hi));
 124
 125         gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_lo_w(),
 126                  u64_lo32(c->vm->va_limit) | 0xFFF);
 127
 128         gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(),
 129                 ram_in_adr_limit_hi_f(u64_hi32(c->vm->va_limit)));
 130
 131         return 0;
 132 }
 133
 134 static int channel_gk20a_commit_userd(struct channel_gk20a *c)
 135 {
 136         u32 addr_lo;
 137         u32 addr_hi;
 138         void *inst_ptr;
 139
 140         gk20a_dbg_fn("");
 141
 142         inst_ptr = c->inst_block.cpuva;
 143         if (!inst_ptr)
 144                 return -ENOMEM;
 145
 146         addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v());
 147         addr_hi = u64_hi32(c->userd_iova);
 148
 149         gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx",
 150                 c->hw_chid, (u64)c->userd_iova);
 151
 152         gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_w(),
 153                  pbdma_userd_target_vid_mem_f() |
 154                  pbdma_userd_addr_f(addr_lo));
 155
 156         gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_hi_w(),
 157                  pbdma_userd_target_vid_mem_f() |
 158                  pbdma_userd_hi_addr_f(addr_hi));
 159
 160         return 0;
 161 }
 162
 163 static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
 164                                 u32 timeslice_timeout)
 165 {
 166         void *inst_ptr;
 167         int shift = 3;
 168         int value = timeslice_timeout;
 169
 170         inst_ptr = c->inst_block.cpuva;
 171         if (!inst_ptr)
 172                 return -ENOMEM;
 173
 174         /* disable channel */
 175         gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
 176                 gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
 177                 ccsr_channel_enable_clr_true_f());
 178
 179         /* preempt the channel */
 180         WARN_ON(gk20a_fifo_preempt_channel(c->g, c->hw_chid));
 181
 182         /* value field is 8 bits long */
 183         while (value >= 1 << 8) {
 184                 value >>= 1;
 185                 shift++;
 186         }
 187
 188         /* time slice register is only 18bits long */
 189         if ((value << shift) >= 1<<19) {
 190                 pr_err("Requested timeslice value is clamped to 18 bits\n");
 191                 value = 255;
 192                 shift = 10;
 193         }
 194
 195         /* set new timeslice */
 196         gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(),
 197                 value | (shift << 12) |
 198                 fifo_eng_timeslice_enable_true_f());
 199
 200         /* enable channel */
 201         gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
 202                 gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
 203                 ccsr_channel_enable_set_true_f());
 204
 205         return 0;
 206 }
 207
 208 static int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
 209                                 u64 gpfifo_base, u32 gpfifo_entries)
 210 {
 211         void *inst_ptr;
 212
 213         gk20a_dbg_fn("");
 214
 215         inst_ptr = c->inst_block.cpuva;
 216         if (!inst_ptr)
 217                 return -ENOMEM;
 218
 219         memset(inst_ptr, 0, ram_fc_size_val_v());
 220
 221         gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_w(),
 222                 pbdma_gp_base_offset_f(
 223                 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
 224
 225         gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_hi_w(),
 226                 pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
 227                 pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
 228
 229         gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(),
 230                  pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f());
 231
 232         gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(),
 233                 pbdma_formats_gp_fermi0_f() |
 234                 pbdma_formats_pb_fermi1_f() |
 235                 pbdma_formats_mp_fermi0_f());
 236
 237         gk20a_mem_wr32(inst_ptr, ram_fc_pb_header_w(),
 238                 pbdma_pb_header_priv_user_f() |
 239                 pbdma_pb_header_method_zero_f() |
 240                 pbdma_pb_header_subchannel_zero_f() |
 241                 pbdma_pb_header_level_main_f() |
 242                 pbdma_pb_header_first_true_f() |
 243                 pbdma_pb_header_type_inc_f());
 244
 245         gk20a_mem_wr32(inst_ptr, ram_fc_subdevice_w(),
 246                 pbdma_subdevice_id_f(1) |
 247                 pbdma_subdevice_status_active_f() |
 248                 pbdma_subdevice_channel_dma_enable_f());
 249
 250         gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f());
 251
 252         gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(),
 253                 pbdma_acquire_retry_man_2_f() |
 254                 pbdma_acquire_retry_exp_2_f() |
 255                 pbdma_acquire_timeout_exp_max_f() |
 256                 pbdma_acquire_timeout_man_max_f() |
 257                 pbdma_acquire_timeout_en_disable_f());
 258
 259         gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(),
 260                 fifo_eng_timeslice_timeout_128_f() |
 261                 fifo_eng_timeslice_timescale_3_f() |
 262                 fifo_eng_timeslice_enable_true_f());
 263
 264         gk20a_mem_wr32(inst_ptr, ram_fc_pb_timeslice_w(),
 265                 fifo_pb_timeslice_timeout_16_f() |
 266                 fifo_pb_timeslice_timescale_0_f() |
 267                 fifo_pb_timeslice_enable_true_f());
 268
 269         gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
 270
 271         return 0;
 272 }
 273
 274 static int channel_gk20a_setup_userd(struct channel_gk20a *c)
 275 {
 276         BUG_ON(!c->userd_cpu_va);
 277
 278         gk20a_dbg_fn("");
 279
 280         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_put_w(), 0);
 281         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_get_w(), 0);
 282         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_ref_w(), 0);
 283         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_put_hi_w(), 0);
 284         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_ref_threshold_w(), 0);
 285         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_top_level_get_w(), 0);
 286         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_top_level_get_hi_w(), 0);
 287         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_get_hi_w(), 0);
 288         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_get_w(), 0);
 289         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_put_w(), 0);
 290
 291         return 0;
 292 }
 293
 294 static void channel_gk20a_bind(struct channel_gk20a *ch_gk20a)
 295 {
 296         struct gk20a *g = ch_gk20a->g;
 297         struct fifo_gk20a *f = &g->fifo;
 298         struct fifo_engine_info_gk20a *engine_info =
 299                 f->engine_info + ENGINE_GR_GK20A;
 300
 301         u32 inst_ptr = ch_gk20a->inst_block.cpu_pa
 302                 >> ram_in_base_shift_v();
 303
 304         gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
 305                 ch_gk20a->hw_chid, inst_ptr);
 306
 307         ch_gk20a->bound = true;
 308
 309         gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid),
 310                 (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) &
 311                  ~ccsr_channel_runlist_f(~0)) |
 312                  ccsr_channel_runlist_f(engine_info->runlist_id));
 313
 314         gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid),
 315                 ccsr_channel_inst_ptr_f(inst_ptr) |
 316                 ccsr_channel_inst_target_vid_mem_f() |
 317                 ccsr_channel_inst_bind_true_f());
 318
 319         gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid),
 320                 (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) &
 321                  ~ccsr_channel_enable_set_f(~0)) |
 322                  ccsr_channel_enable_set_true_f());
 323 }
 324
 325 static void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a)
 326 {
 327         struct gk20a *g = ch_gk20a->g;
 328
 329         gk20a_dbg_fn("");
 330
 331         if (ch_gk20a->bound)
 332                 gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid),
 333                         ccsr_channel_inst_ptr_f(0) |
 334                         ccsr_channel_inst_bind_false_f());
 335
 336         ch_gk20a->bound = false;
 337
 338         /*
 339          * if we are agrressive then we can destroy the syncpt
 340          * resource at this point
 341          * if not, then it will be destroyed at channel_free()
 342          */
 343         if (ch_gk20a->sync && ch_gk20a->sync->syncpt_aggressive_destroy) {
 344                 ch_gk20a->sync->destroy(ch_gk20a->sync);
 345                 ch_gk20a->sync = NULL;
 346         }
 347 }
 348
 349 static int channel_gk20a_alloc_inst(struct gk20a *g,
 350                                 struct channel_gk20a *ch)
 351 {
 352         struct device *d = dev_from_gk20a(g);
 353         int err = 0;
 354         dma_addr_t iova;
 355
 356         gk20a_dbg_fn("");
 357
 358         ch->inst_block.size = ram_in_alloc_size_v();
 359         ch->inst_block.cpuva = dma_alloc_coherent(d,
 360                                         ch->inst_block.size,
 361                                         &iova,
 362                                         GFP_KERNEL);
 363         if (!ch->inst_block.cpuva) {
 364                 gk20a_err(d, "%s: memory allocation failed\n", __func__);
 365                 err = -ENOMEM;
 366                 goto clean_up;
 367         }
 368
 369         ch->inst_block.iova = iova;
 370         ch->inst_block.cpu_pa = gk20a_get_phys_from_iova(d,
 371                                                         ch->inst_block.iova);
 372         if (!ch->inst_block.cpu_pa) {
 373                 gk20a_err(d, "%s: failed to get physical address\n", __func__);
 374                 err = -ENOMEM;
 375                 goto clean_up;
 376         }
 377
 378         gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx",
 379                 ch->hw_chid, (u64)ch->inst_block.cpu_pa);
 380
 381         gk20a_dbg_fn("done");
 382         return 0;
 383
 384 clean_up:
 385         gk20a_err(d, "fail");
 386         channel_gk20a_free_inst(g, ch);
 387         return err;
 388 }
 389
 390 static void channel_gk20a_free_inst(struct gk20a *g,
 391                                 struct channel_gk20a *ch)
 392 {
 393         struct device *d = dev_from_gk20a(g);
 394
 395         if (ch->inst_block.cpuva)
 396                 dma_free_coherent(d, ch->inst_block.size,
 397                                 ch->inst_block.cpuva, ch->inst_block.iova);
 398         ch->inst_block.cpuva = NULL;
 399         ch->inst_block.iova = 0;
 400         memset(&ch->inst_block, 0, sizeof(struct inst_desc));
 401 }
 402
 403 static int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add)
 404 {
 405         return gk20a_fifo_update_runlist(c->g, 0, c->hw_chid, add, true);
 406 }
 407
 408 void gk20a_disable_channel_no_update(struct channel_gk20a *ch)
 409 {
 410         /* ensure no fences are pending */
 411         if (ch->sync)
 412                 ch->sync->set_min_eq_max(ch->sync);
 413
 414         /* disable channel */
 415         gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid),
 416                      gk20a_readl(ch->g,
 417                      ccsr_channel_r(ch->hw_chid)) |
 418                      ccsr_channel_enable_clr_true_f());
 419 }
 420
 421 static void channel_gk20a_enable(struct channel_gk20a *ch)
 422 {
 423         /* enable channel */
 424         gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid),
 425                 gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) |
 426                 ccsr_channel_enable_set_true_f());
 427 }
 428
 429 static void channel_gk20a_disable(struct channel_gk20a *ch)
 430 {
 431         /* disable channel */
 432         gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid),
 433                 gk20a_readl(ch->g,
 434                         ccsr_channel_r(ch->hw_chid)) |
 435                         ccsr_channel_enable_clr_true_f());
 436 }
 437
 438 int gk20a_wait_channel_idle(struct channel_gk20a *ch)
 439 {
 440         bool channel_idle = false;
 441         unsigned long end_jiffies = jiffies +
 442                 msecs_to_jiffies(gk20a_get_gr_idle_timeout(ch->g));
 443
 444         do {
 445                 mutex_lock(&ch->jobs_lock);
 446                 channel_idle = list_empty(&ch->jobs);
 447                 mutex_unlock(&ch->jobs_lock);
 448                 if (channel_idle)
 449                         break;
 450
 451                 usleep_range(1000, 3000);
 452         } while (time_before(jiffies, end_jiffies)
 453                         || !tegra_platform_is_silicon());
 454
 455         if (!channel_idle) {
 456                 gk20a_err(dev_from_gk20a(ch->g), "jobs not freed for channel %d\n",
 457                                 ch->hw_chid);
 458                 return -EBUSY;
 459         }
 460
 461         return 0;
 462 }
 463
 464 void gk20a_disable_channel(struct channel_gk20a *ch,
 465                            bool finish,
 466                            unsigned long finish_timeout)
 467 {
 468         if (finish) {
 469                 int err = gk20a_channel_finish(ch, finish_timeout);
 470                 WARN_ON(err);
 471         }
 472
 473         /* disable the channel from hw and increment syncpoints */
 474         gk20a_disable_channel_no_update(ch);
 475
 476         gk20a_wait_channel_idle(ch);
 477
 478         /* preempt the channel */
 479         gk20a_fifo_preempt_channel(ch->g, ch->hw_chid);
 480
 481         /* remove channel from runlist */
 482         channel_gk20a_update_runlist(ch, false);
 483 }
 484
 485 #if defined(CONFIG_GK20A_CYCLE_STATS)
 486
 487 static void gk20a_free_cycle_stats_buffer(struct channel_gk20a *ch)
 488 {
 489         /* disable existing cyclestats buffer */
 490         mutex_lock(&ch->cyclestate.cyclestate_buffer_mutex);
 491         if (ch->cyclestate.cyclestate_buffer_handler) {
 492                 dma_buf_vunmap(ch->cyclestate.cyclestate_buffer_handler,
 493                                 ch->cyclestate.cyclestate_buffer);
 494                 dma_buf_put(ch->cyclestate.cyclestate_buffer_handler);
 495                 ch->cyclestate.cyclestate_buffer_handler = NULL;
 496                 ch->cyclestate.cyclestate_buffer = NULL;
 497                 ch->cyclestate.cyclestate_buffer_size = 0;
 498         }
 499         mutex_unlock(&ch->cyclestate.cyclestate_buffer_mutex);
 500 }
 501
 502 static int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
 503                        struct nvhost_cycle_stats_args *args)
 504 {
 505         struct dma_buf *dmabuf;
 506         void *virtual_address;
 507
 508         if (args->nvmap_handle && !ch->cyclestate.cyclestate_buffer_handler) {
 509
 510                 /* set up new cyclestats buffer */
 511                 dmabuf = dma_buf_get(args->nvmap_handle);
 512                 if (IS_ERR(dmabuf))
 513                         return PTR_ERR(dmabuf);
 514                 virtual_address = dma_buf_vmap(dmabuf);
 515                 if (!virtual_address)
 516                         return -ENOMEM;
 517
 518                 ch->cyclestate.cyclestate_buffer_handler = dmabuf;
 519                 ch->cyclestate.cyclestate_buffer = virtual_address;
 520                 ch->cyclestate.cyclestate_buffer_size = dmabuf->size;
 521                 return 0;
 522
 523         } else if (!args->nvmap_handle &&
 524                         ch->cyclestate.cyclestate_buffer_handler) {
 525                 gk20a_free_cycle_stats_buffer(ch);
 526                 return 0;
 527
 528         } else if (!args->nvmap_handle &&
 529                         !ch->cyclestate.cyclestate_buffer_handler) {
 530                 /* no requst from GL */
 531                 return 0;
 532
 533         } else {
 534                 pr_err("channel already has cyclestats buffer\n");
 535                 return -EINVAL;
 536         }
 537 }
 538 #endif
 539
 540 static int gk20a_init_error_notifier(struct channel_gk20a *ch,
 541                 struct nvhost_set_error_notifier *args) {
 542         void *va;
 543
 544         struct dma_buf *dmabuf;
 545
 546         if (!args->mem) {
 547                 pr_err("gk20a_init_error_notifier: invalid memory handle\n");
 548                 return -EINVAL;
 549         }
 550
 551         dmabuf = dma_buf_get(args->mem);
 552
 553         if (ch->error_notifier_ref)
 554                 gk20a_free_error_notifiers(ch);
 555
 556         if (IS_ERR(dmabuf)) {
 557                 pr_err("Invalid handle: %d\n", args->mem);
 558                 return -EINVAL;
 559         }
 560         /* map handle */
 561         va = dma_buf_vmap(dmabuf);
 562         if (!va) {
 563                 dma_buf_put(dmabuf);
 564                 pr_err("Cannot map notifier handle\n");
 565                 return -ENOMEM;
 566         }
 567
 568         /* set channel notifiers pointer */
 569         ch->error_notifier_ref = dmabuf;
 570         ch->error_notifier = va + args->offset;
 571         ch->error_notifier_va = va;
 572         memset(ch->error_notifier, 0, sizeof(struct nvhost_notification));
 573         return 0;
 574 }
 575
 576 void gk20a_set_error_notifier(struct channel_gk20a *ch, __u32 error)
 577 {
 578         if (ch->error_notifier_ref) {
 579                 struct timespec time_data;
 580                 u64 nsec;
 581                 getnstimeofday(&time_data);
 582                 nsec = ((u64)time_data.tv_sec) * 1000000000u +
 583                                 (u64)time_data.tv_nsec;
 584                 ch->error_notifier->time_stamp.nanoseconds[0] =
 585                                 (u32)nsec;
 586                 ch->error_notifier->time_stamp.nanoseconds[1] =
 587                                 (u32)(nsec >> 32);
 588                 ch->error_notifier->info32 = error;
 589                 ch->error_notifier->status = 0xffff;
 590                 gk20a_err(dev_from_gk20a(ch->g),
 591                                 "error notifier set to %d\n", error);
 592         }
 593 }
 594
 595 static void gk20a_free_error_notifiers(struct channel_gk20a *ch)
 596 {
 597         if (ch->error_notifier_ref) {
 598                 dma_buf_vunmap(ch->error_notifier_ref, ch->error_notifier_va);
 599                 dma_buf_put(ch->error_notifier_ref);
 600                 ch->error_notifier_ref = 0;
 601                 ch->error_notifier = 0;
 602                 ch->error_notifier_va = 0;
 603         }
 604 }
 605
 606 void gk20a_free_channel(struct channel_gk20a *ch, bool finish)
 607 {
 608         struct gk20a *g = ch->g;
 609         struct device *d = dev_from_gk20a(g);
 610         struct fifo_gk20a *f = &g->fifo;
 611         struct gr_gk20a *gr = &g->gr;
 612         struct vm_gk20a *ch_vm = ch->vm;
 613         unsigned long timeout = gk20a_get_gr_idle_timeout(g);
 614         struct dbg_session_gk20a *dbg_s;
 615
 616         gk20a_dbg_fn("");
 617
 618         /* if engine reset was deferred, perform it now */
 619         mutex_lock(&f->deferred_reset_mutex);
 620         if (g->fifo.deferred_reset_pending) {
 621                 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "engine reset was"
 622                            " deferred, running now");
 623                 fifo_gk20a_finish_mmu_fault_handling(g, g->fifo.mmu_fault_engines);
 624                 g->fifo.mmu_fault_engines = 0;
 625                 g->fifo.deferred_reset_pending = false;
 626         }
 627         mutex_unlock(&f->deferred_reset_mutex);
 628
 629         if (!ch->bound)
 630                 return;
 631
 632         if (!gk20a_channel_as_bound(ch))
 633                 goto unbind;
 634
 635         gk20a_dbg_info("freeing bound channel context, timeout=%ld",
 636                         timeout);
 637
 638         gk20a_disable_channel(ch, finish && !ch->has_timedout, timeout);
 639
 640         gk20a_free_error_notifiers(ch);
 641
 642         /* release channel ctx */
 643         gk20a_free_channel_ctx(ch);
 644
 645         gk20a_gr_flush_channel_tlb(gr);
 646
 647         memset(&ch->ramfc, 0, sizeof(struct mem_desc_sub));
 648
 649         /* free gpfifo */
 650         if (ch->gpfifo.gpu_va)
 651                 gk20a_gmmu_unmap(ch_vm, ch->gpfifo.gpu_va,
 652                         ch->gpfifo.size, gk20a_mem_flag_none);
 653         if (ch->gpfifo.cpu_va)
 654                 dma_free_coherent(d, ch->gpfifo.size,
 655                         ch->gpfifo.cpu_va, ch->gpfifo.iova);
 656         ch->gpfifo.cpu_va = NULL;
 657         ch->gpfifo.iova = 0;
 658
 659         memset(&ch->gpfifo, 0, sizeof(struct gpfifo_desc));
 660
 661 #if defined(CONFIG_GK20A_CYCLE_STATS)
 662         gk20a_free_cycle_stats_buffer(ch);
 663 #endif
 664
 665         channel_gk20a_free_priv_cmdbuf(ch);
 666
 667         if (ch->sync) {
 668                 ch->sync->destroy(ch->sync);
 669                 ch->sync = NULL;
 670         }
 671
 672         /* release channel binding to the as_share */
 673         gk20a_as_release_share(ch_vm->as_share);
 674
 675 unbind:
 676         channel_gk20a_unbind(ch);
 677         channel_gk20a_free_inst(g, ch);
 678
 679         ch->vpr = false;
 680         ch->vm = NULL;
 681         WARN_ON(ch->sync);
 682
 683         /* unlink all debug sessions */
 684         mutex_lock(&ch->dbg_s_lock);
 685
 686         list_for_each_entry(dbg_s, &ch->dbg_s_list, dbg_s_list_node) {
 687                 dbg_s->ch = NULL;
 688                 list_del_init(&dbg_s->dbg_s_list_node);
 689         }
 690
 691         mutex_unlock(&ch->dbg_s_lock);
 692
 693         /* ALWAYS last */
 694         release_used_channel(f, ch);
 695 }
 696
 697 int gk20a_channel_release(struct inode *inode, struct file *filp)
 698 {
 699         struct channel_gk20a *ch = (struct channel_gk20a *)filp->private_data;
 700         struct gk20a *g = ch->g;
 701         int err;
 702
 703         trace_gk20a_channel_release(dev_name(&g->dev->dev));
 704
 705         err = gk20a_busy(ch->g->dev);
 706         if (err) {
 707                 gk20a_err(dev_from_gk20a(g), "failed to release channel %d",
 708                         ch->hw_chid);
 709                 return err;
 710         }
 711         gk20a_free_channel(ch, true);
 712         gk20a_idle(ch->g->dev);
 713
 714         gk20a_put_client(g);
 715         filp->private_data = NULL;
 716         return 0;
 717 }
 718
 719 static struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g)
 720 {
 721         struct fifo_gk20a *f = &g->fifo;
 722         struct channel_gk20a *ch;
 723
 724         ch = acquire_unused_channel(f);
 725         if (ch == NULL) {
 726                 /* TBD: we want to make this virtualizable */
 727                 gk20a_err(dev_from_gk20a(g), "out of hw chids");
 728                 return 0;
 729         }
 730
 731         ch->g = g;
 732
 733         if (channel_gk20a_alloc_inst(g, ch)) {
 734                 ch->in_use = false;
 735                 gk20a_err(dev_from_gk20a(g),
 736                            "failed to open gk20a channel, out of inst mem");
 737
 738                 return 0;
 739         }
 740         g->ops.fifo.bind_channel(ch);
 741         ch->pid = current->pid;
 742
 743         /* reset timeout counter and update timestamp */
 744         ch->timeout_accumulated_ms = 0;
 745         ch->timeout_gpfifo_get = 0;
 746         /* set gr host default timeout */
 747         ch->timeout_ms_max = gk20a_get_gr_idle_timeout(g);
 748         ch->timeout_debug_dump = true;
 749         ch->has_timedout = false;
 750         ch->obj_class = 0;
 751
 752         /* The channel is *not* runnable at this point. It still needs to have
 753          * an address space bound and allocate a gpfifo and grctx. */
 754
 755         init_waitqueue_head(&ch->notifier_wq);
 756         init_waitqueue_head(&ch->semaphore_wq);
 757         init_waitqueue_head(&ch->submit_wq);
 758
 759         return ch;
 760 }
 761
 762 static int __gk20a_channel_open(struct gk20a *g, struct file *filp)
 763 {
 764         int err;
 765         struct channel_gk20a *ch;
 766
 767         trace_gk20a_channel_open(dev_name(&g->dev->dev));
 768
 769         err = gk20a_get_client(g);
 770         if (err) {
 771                 gk20a_err(dev_from_gk20a(g),
 772                         "failed to get client ref");
 773                 return err;
 774         }
 775
 776         err = gk20a_busy(g->dev);
 777         if (err) {
 778                 gk20a_put_client(g);
 779                 gk20a_err(dev_from_gk20a(g), "failed to power on, %d", err);
 780                 return err;
 781         }
 782         ch = gk20a_open_new_channel(g);
 783         gk20a_idle(g->dev);
 784         if (!ch) {
 785                 gk20a_put_client(g);
 786                 gk20a_err(dev_from_gk20a(g),
 787                         "failed to get f");
 788                 return -ENOMEM;
 789         }
 790
 791         filp->private_data = ch;
 792         return 0;
 793 }
 794
 795 int gk20a_channel_open(struct inode *inode, struct file *filp)
 796 {
 797         struct gk20a *g = container_of(inode->i_cdev,
 798                         struct gk20a, channel.cdev);
 799         return __gk20a_channel_open(g, filp);
 800 }
 801
 802 /* allocate private cmd buffer.
 803    used for inserting commands before/after user submitted buffers. */
 804 static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c)
 805 {
 806         struct device *d = dev_from_gk20a(c->g);
 807         struct vm_gk20a *ch_vm = c->vm;
 808         struct priv_cmd_queue *q = &c->priv_cmd_q;
 809         struct priv_cmd_entry *e;
 810         u32 i = 0, size;
 811         int err = 0;
 812         struct sg_table *sgt;
 813         dma_addr_t iova;
 814
 815         /* Kernel can insert gpfifos before and after user gpfifos.
 816            Before user gpfifos, kernel inserts fence_wait, which takes
 817            syncpoint_a (2 dwords) + syncpoint_b (2 dwords) = 4 dwords.
 818            After user gpfifos, kernel inserts fence_get, which takes
 819            wfi (2 dwords) + syncpoint_a (2 dwords) + syncpoint_b (2 dwords)
 820            = 6 dwords.
 821            Worse case if kernel adds both of them for every user gpfifo,
 822            max size of priv_cmdbuf is :
 823            (gpfifo entry number * (2 / 3) * (4 + 6) * 4 bytes */
 824         size = roundup_pow_of_two(
 825                 c->gpfifo.entry_num * 2 * 10 * sizeof(u32) / 3);
 826
 827         q->mem.base_cpuva = dma_alloc_coherent(d, size,
 828                                         &iova,
 829                                         GFP_KERNEL);
 830         if (!q->mem.base_cpuva) {
 831                 gk20a_err(d, "%s: memory allocation failed\n", __func__);
 832                 err = -ENOMEM;
 833                 goto clean_up;
 834         }
 835
 836         q->mem.base_iova = iova;
 837         q->mem.size = size;
 838
 839         err = gk20a_get_sgtable(d, &sgt,
 840                         q->mem.base_cpuva, q->mem.base_iova, size);
 841         if (err) {
 842                 gk20a_err(d, "%s: failed to create sg table\n", __func__);
 843                 goto clean_up;
 844         }
 845
 846         memset(q->mem.base_cpuva, 0, size);
 847
 848         q->base_gpuva = gk20a_gmmu_map(ch_vm, &sgt,
 849                                         size,
 850                                         0, /* flags */
 851                                         gk20a_mem_flag_none);
 852         if (!q->base_gpuva) {
 853                 gk20a_err(d, "ch %d : failed to map gpu va"
 854                            "for priv cmd buffer", c->hw_chid);
 855                 err = -ENOMEM;
 856                 goto clean_up_sgt;
 857         }
 858
 859         q->size = q->mem.size / sizeof (u32);
 860
 861         INIT_LIST_HEAD(&q->head);
 862         INIT_LIST_HEAD(&q->free);
 863
 864         /* pre-alloc 25% of priv cmdbuf entries and put them on free list */
 865         for (i = 0; i < q->size / 4; i++) {
 866                 e = kzalloc(sizeof(struct priv_cmd_entry), GFP_KERNEL);
 867                 if (!e) {
 868                         gk20a_err(d, "ch %d: fail to pre-alloc cmd entry",
 869                                 c->hw_chid);
 870                         err = -ENOMEM;
 871                         goto clean_up_sgt;
 872                 }
 873                 e->pre_alloc = true;
 874                 list_add(&e->list, &q->free);
 875         }
 876
 877         gk20a_free_sgtable(&sgt);
 878
 879         return 0;
 880
 881 clean_up_sgt:
 882         gk20a_free_sgtable(&sgt);
 883 clean_up:
 884         channel_gk20a_free_priv_cmdbuf(c);
 885         return err;
 886 }
 887
 888 static void channel_gk20a_free_priv_cmdbuf(struct channel_gk20a *c)
 889 {
 890         struct device *d = dev_from_gk20a(c->g);
 891         struct vm_gk20a *ch_vm = c->vm;
 892         struct priv_cmd_queue *q = &c->priv_cmd_q;
 893         struct priv_cmd_entry *e;
 894         struct list_head *pos, *tmp, *head;
 895
 896         if (q->size == 0)
 897                 return;
 898
 899         if (q->base_gpuva)
 900                 gk20a_gmmu_unmap(ch_vm, q->base_gpuva,
 901                                 q->mem.size, gk20a_mem_flag_none);
 902         if (q->mem.base_cpuva)
 903                 dma_free_coherent(d, q->mem.size,
 904                         q->mem.base_cpuva, q->mem.base_iova);
 905         q->mem.base_cpuva = NULL;
 906         q->mem.base_iova = 0;
 907
 908         /* free used list */
 909         head = &q->head;
 910         list_for_each_safe(pos, tmp, head) {
 911                 e = container_of(pos, struct priv_cmd_entry, list);
 912                 free_priv_cmdbuf(c, e);
 913         }
 914
 915         /* free free list */
 916         head = &q->free;
 917         list_for_each_safe(pos, tmp, head) {
 918                 e = container_of(pos, struct priv_cmd_entry, list);
 919                 e->pre_alloc = false;
 920                 free_priv_cmdbuf(c, e);
 921         }
 922
 923         memset(q, 0, sizeof(struct priv_cmd_queue));
 924 }
 925
 926 /* allocate a cmd buffer with given size. size is number of u32 entries */
 927 int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 orig_size,
 928                              struct priv_cmd_entry **entry)
 929 {
 930         struct priv_cmd_queue *q = &c->priv_cmd_q;
 931         struct priv_cmd_entry *e;
 932         struct list_head *node;
 933         u32 free_count;
 934         u32 size = orig_size;
 935         bool no_retry = false;
 936
 937         gk20a_dbg_fn("size %d", orig_size);
 938
 939         *entry = NULL;
 940
 941         /* if free space in the end is less than requested, increase the size
 942          * to make the real allocated space start from beginning. */
 943         if (q->put + size > q->size)
 944                 size = orig_size + (q->size - q->put);
 945
 946         gk20a_dbg_info("ch %d: priv cmd queue get:put %d:%d",
 947                         c->hw_chid, q->get, q->put);
 948
 949 TRY_AGAIN:
 950         free_count = (q->size - (q->put - q->get) - 1) % q->size;
 951
 952         if (size > free_count) {
 953                 if (!no_retry) {
 954                         recycle_priv_cmdbuf(c);
 955                         no_retry = true;
 956                         goto TRY_AGAIN;
 957                 } else
 958                         return -EAGAIN;
 959         }
 960
 961         if (unlikely(list_empty(&q->free))) {
 962
 963                 gk20a_dbg_info("ch %d: run out of pre-alloc entries",
 964                         c->hw_chid);
 965
 966                 e = kzalloc(sizeof(struct priv_cmd_entry), GFP_KERNEL);
 967                 if (!e) {
 968                         gk20a_err(dev_from_gk20a(c->g),
 969                                 "ch %d: fail to allocate priv cmd entry",
 970                                 c->hw_chid);
 971                         return -ENOMEM;
 972                 }
 973         } else  {
 974                 node = q->free.next;
 975                 list_del(node);
 976                 e = container_of(node, struct priv_cmd_entry, list);
 977         }
 978
 979         e->size = orig_size;
 980         e->gp_get = c->gpfifo.get;
 981         e->gp_put = c->gpfifo.put;
 982         e->gp_wrap = c->gpfifo.wrap;
 983
 984         /* if we have increased size to skip free space in the end, set put
 985            to beginning of cmd buffer (0) + size */
 986         if (size != orig_size) {
 987                 e->ptr = q->mem.base_cpuva;
 988                 e->gva = q->base_gpuva;
 989                 q->put = orig_size;
 990         } else {
 991                 e->ptr = q->mem.base_cpuva + q->put;
 992                 e->gva = q->base_gpuva + q->put * sizeof(u32);
 993                 q->put = (q->put + orig_size) & (q->size - 1);
 994         }
 995
 996         /* we already handled q->put + size > q->size so BUG_ON this */
 997         BUG_ON(q->put > q->size);
 998
 999         /* add new entry to head since we free from head */
1000         list_add(&e->list, &q->head);
1001
1002         *entry = e;
1003
1004         gk20a_dbg_fn("done");
1005
1006         return 0;
1007 }
1008
1009 /* Don't call this to free an explict cmd entry.
1010  * It doesn't update priv_cmd_queue get/put */
1011 static void free_priv_cmdbuf(struct channel_gk20a *c,
1012                              struct priv_cmd_entry *e)
1013 {
1014         struct priv_cmd_queue *q = &c->priv_cmd_q;
1015
1016         if (!e)
1017                 return;
1018
1019         list_del(&e->list);
1020
1021         if (unlikely(!e->pre_alloc))
1022                 kfree(e);
1023         else {
1024                 memset(e, 0, sizeof(struct priv_cmd_entry));
1025                 e->pre_alloc = true;
1026                 list_add(&e->list, &q->free);
1027         }
1028 }
1029
1030 /* free entries if they're no longer being used */
1031 static void recycle_priv_cmdbuf(struct channel_gk20a *c)
1032 {
1033         struct priv_cmd_queue *q = &c->priv_cmd_q;
1034         struct priv_cmd_entry *e, *tmp;
1035         struct list_head *head = &q->head;
1036         bool wrap_around, found = false;
1037
1038         gk20a_dbg_fn("");
1039
1040         /* Find the most recent free entry. Free it and everything before it */
1041         list_for_each_entry(e, head, list) {
1042
1043                 gk20a_dbg_info("ch %d: cmd entry get:put:wrap %d:%d:%d "
1044                         "curr get:put:wrap %d:%d:%d",
1045                         c->hw_chid, e->gp_get, e->gp_put, e->gp_wrap,
1046                         c->gpfifo.get, c->gpfifo.put, c->gpfifo.wrap);
1047
1048                 wrap_around = (c->gpfifo.wrap != e->gp_wrap);
1049                 if (e->gp_get < e->gp_put) {
1050                         if (c->gpfifo.get >= e->gp_put ||
1051                             wrap_around) {
1052                                 found = true;
1053                                 break;
1054                         } else
1055                                 e->gp_get = c->gpfifo.get;
1056                 } else if (e->gp_get > e->gp_put) {
1057                         if (wrap_around &&
1058                             c->gpfifo.get >= e->gp_put) {
1059                                 found = true;
1060                                 break;
1061                         } else
1062                                 e->gp_get = c->gpfifo.get;
1063                 }
1064         }
1065
1066         if (found)
1067                 q->get = (e->ptr - q->mem.base_cpuva) + e->size;
1068         else {
1069                 gk20a_dbg_info("no free entry recycled");
1070                 return;
1071         }
1072
1073         list_for_each_entry_safe_continue(e, tmp, head, list) {
1074                 free_priv_cmdbuf(c, e);
1075         }
1076
1077         gk20a_dbg_fn("done");
1078 }
1079
1080
1081 static int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c,
1082                                       struct nvhost_alloc_gpfifo_args *args)
1083 {
1084         struct gk20a *g = c->g;
1085         struct device *d = dev_from_gk20a(g);
1086         struct vm_gk20a *ch_vm;
1087         u32 gpfifo_size;
1088         int err = 0;
1089         struct sg_table *sgt;
1090         dma_addr_t iova;
1091
1092         /* Kernel can insert one extra gpfifo entry before user submitted gpfifos
1093            and another one after, for internal usage. Triple the requested size. */
1094         gpfifo_size = roundup_pow_of_two(args->num_entries * 3);
1095
1096         if (args->flags & NVHOST_ALLOC_GPFIFO_FLAGS_VPR_ENABLED)
1097                 c->vpr = true;
1098
1099         /* an address space needs to have been bound at this point.   */
1100         if (!gk20a_channel_as_bound(c)) {
1101                 gk20a_err(d,
1102                             "not bound to an address space at time of gpfifo"
1103                             " allocation.  Attempting to create and bind to"
1104                             " one...");
1105                 return -EINVAL;
1106         }
1107         ch_vm = c->vm;
1108
1109         c->cmds_pending = false;
1110         c->last_submit_fence.valid = false;
1111
1112         c->ramfc.offset = 0;
1113         c->ramfc.size = ram_in_ramfc_s() / 8;
1114
1115         if (c->gpfifo.cpu_va) {
1116                 gk20a_err(d, "channel %d :"
1117                            "gpfifo already allocated", c->hw_chid);
1118                 return -EEXIST;
1119         }
1120
1121         c->gpfifo.size = gpfifo_size * sizeof(struct gpfifo);
1122         c->gpfifo.cpu_va = (struct gpfifo *)dma_alloc_coherent(d,
1123                                                 c->gpfifo.size,
1124                                                 &iova,
1125                                                 GFP_KERNEL);
1126         if (!c->gpfifo.cpu_va) {
1127                 gk20a_err(d, "%s: memory allocation failed\n", __func__);
1128                 err = -ENOMEM;
1129                 goto clean_up;
1130         }
1131
1132         c->gpfifo.iova = iova;
1133         c->gpfifo.entry_num = gpfifo_size;
1134
1135         c->gpfifo.get = c->gpfifo.put = 0;
1136
1137         err = gk20a_get_sgtable(d, &sgt,
1138                         c->gpfifo.cpu_va, c->gpfifo.iova, c->gpfifo.size);
1139         if (err) {
1140                 gk20a_err(d, "%s: failed to allocate sg table\n", __func__);
1141                 goto clean_up;
1142         }
1143
1144         c->gpfifo.gpu_va = gk20a_gmmu_map(ch_vm,
1145                                         &sgt,
1146                                         c->gpfifo.size,
1147                                         0, /* flags */
1148                                         gk20a_mem_flag_none);
1149         if (!c->gpfifo.gpu_va) {
1150                 gk20a_err(d, "channel %d : failed to map"
1151                            " gpu_va for gpfifo", c->hw_chid);
1152                 err = -ENOMEM;
1153                 goto clean_up_sgt;
1154         }
1155
1156         gk20a_dbg_info("channel %d : gpfifo_base 0x%016llx, size %d",
1157                 c->hw_chid, c->gpfifo.gpu_va, c->gpfifo.entry_num);
1158
1159         channel_gk20a_setup_ramfc(c, c->gpfifo.gpu_va, c->gpfifo.entry_num);
1160
1161         channel_gk20a_setup_userd(c);
1162         channel_gk20a_commit_userd(c);
1163
1164         /* TBD: setup engine contexts */
1165
1166         err = channel_gk20a_alloc_priv_cmdbuf(c);
1167         if (err)
1168                 goto clean_up_unmap;
1169
1170         err = channel_gk20a_update_runlist(c, true);
1171         if (err)
1172                 goto clean_up_unmap;
1173
1174         gk20a_free_sgtable(&sgt);
1175
1176         gk20a_dbg_fn("done");
1177         return 0;
1178
1179 clean_up_unmap:
1180         gk20a_gmmu_unmap(ch_vm, c->gpfifo.gpu_va,
1181                 c->gpfifo.size, gk20a_mem_flag_none);
1182 clean_up_sgt:
1183         gk20a_free_sgtable(&sgt);
1184 clean_up:
1185         dma_free_coherent(d, c->gpfifo.size,
1186                 c->gpfifo.cpu_va, c->gpfifo.iova);
1187         c->gpfifo.cpu_va = NULL;
1188         c->gpfifo.iova = 0;
1189         memset(&c->gpfifo, 0, sizeof(struct gpfifo_desc));
1190         gk20a_err(d, "fail");
1191         return err;
1192 }
1193
1194 static inline int wfi_cmd_size(void)
1195 {
1196         return 2;
1197 }
1198 void add_wfi_cmd(struct priv_cmd_entry *cmd, int *i)
1199 {
1200         /* wfi */
1201         cmd->ptr[(*i)++] = 0x2001001E;
1202         /* handle, ignored */
1203         cmd->ptr[(*i)++] = 0x00000000;
1204 }
1205
1206 static inline bool check_gp_put(struct gk20a *g,
1207                                 struct channel_gk20a *c)
1208 {
1209         u32 put;
1210         /* gp_put changed unexpectedly since last update? */
1211         put = gk20a_bar1_readl(g,
1212                c->userd_gpu_va + 4 * ram_userd_gp_put_w());
1213         if (c->gpfifo.put != put) {
1214                 /*TBD: BUG_ON/teardown on this*/
1215                 gk20a_err(dev_from_gk20a(g), "gp_put changed unexpectedly "
1216                            "since last update");
1217                 c->gpfifo.put = put;
1218                 return false; /* surprise! */
1219         }
1220         return true; /* checked out ok */
1221 }
1222
1223 /* Update with this periodically to determine how the gpfifo is draining. */
1224 static inline u32 update_gp_get(struct gk20a *g,
1225                                 struct channel_gk20a *c)
1226 {
1227         u32 new_get = gk20a_bar1_readl(g,
1228                 c->userd_gpu_va + sizeof(u32) * ram_userd_gp_get_w());
1229         if (new_get < c->gpfifo.get)
1230                 c->gpfifo.wrap = !c->gpfifo.wrap;
1231         c->gpfifo.get = new_get;
1232         return new_get;
1233 }
1234
1235 static inline u32 gp_free_count(struct channel_gk20a *c)
1236 {
1237         return (c->gpfifo.entry_num - (c->gpfifo.put - c->gpfifo.get) - 1) %
1238                 c->gpfifo.entry_num;
1239 }
1240
1241 bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch,
1242                 u32 timeout_delta_ms)
1243 {
1244         u32 gpfifo_get = update_gp_get(ch->g, ch);
1245         /* Count consequent timeout isr */
1246         if (gpfifo_get == ch->timeout_gpfifo_get) {
1247                 /* we didn't advance since previous channel timeout check */
1248                 ch->timeout_accumulated_ms += timeout_delta_ms;
1249         } else {
1250                 /* first timeout isr encountered */
1251                 ch->timeout_accumulated_ms = timeout_delta_ms;
1252         }
1253
1254         ch->timeout_gpfifo_get = gpfifo_get;
1255
1256         return ch->g->timeouts_enabled &&
1257                 ch->timeout_accumulated_ms > ch->timeout_ms_max;
1258 }
1259
1260
1261 /* Issue a syncpoint increment *preceded* by a wait-for-idle
1262  * command.  All commands on the channel will have been
1263  * consumed at the time the fence syncpoint increment occurs.
1264  */
1265 static int gk20a_channel_submit_wfi(struct channel_gk20a *c)
1266 {
1267         struct priv_cmd_entry *cmd = NULL;
1268         struct gk20a *g = c->g;
1269         u32 free_count;
1270         int err;
1271
1272         if (c->has_timedout)
1273                 return -ETIMEDOUT;
1274
1275         if (!c->sync) {
1276                 c->sync = gk20a_channel_sync_create(c);
1277                 if (!c->sync)
1278                         return -ENOMEM;
1279         }
1280
1281         update_gp_get(g, c);
1282         free_count = gp_free_count(c);
1283         if (unlikely(!free_count)) {
1284                 gk20a_err(dev_from_gk20a(g),
1285                            "not enough gpfifo space");
1286                 return -EAGAIN;
1287         }
1288
1289         err = c->sync->incr_wfi(c->sync, &cmd, &c->last_submit_fence);
1290         if (unlikely(err))
1291                 return err;
1292
1293         WARN_ON(!c->last_submit_fence.wfi);
1294
1295         c->gpfifo.cpu_va[c->gpfifo.put].entry0 = u64_lo32(cmd->gva);
1296         c->gpfifo.cpu_va[c->gpfifo.put].entry1 = u64_hi32(cmd->gva) |
1297                 pbdma_gp_entry1_length_f(cmd->size);
1298
1299         c->gpfifo.put = (c->gpfifo.put + 1) & (c->gpfifo.entry_num - 1);
1300
1301         /* save gp_put */
1302         cmd->gp_put = c->gpfifo.put;
1303
1304         gk20a_bar1_writel(g,
1305                 c->userd_gpu_va + 4 * ram_userd_gp_put_w(),
1306                 c->gpfifo.put);
1307
1308         gk20a_dbg_info("post-submit put %d, get %d, size %d",
1309                 c->gpfifo.put, c->gpfifo.get, c->gpfifo.entry_num);
1310
1311         return 0;
1312 }
1313
1314 static u32 get_gp_free_count(struct channel_gk20a *c)
1315 {
1316         update_gp_get(c->g, c);
1317         return gp_free_count(c);
1318 }
1319
1320 static void trace_write_pushbuffer(struct channel_gk20a *c, struct gpfifo *g)
1321 {
1322         void *mem = NULL;
1323         unsigned int words;
1324         u64 offset;
1325         struct dma_buf *dmabuf = NULL;
1326
1327         if (gk20a_debug_trace_cmdbuf) {
1328                 u64 gpu_va = (u64)g->entry0 |
1329                         (u64)((u64)pbdma_gp_entry1_get_hi_v(g->entry1) << 32);
1330                 int err;
1331
1332                 words = pbdma_gp_entry1_length_v(g->entry1);
1333                 err = gk20a_vm_find_buffer(c->vm, gpu_va, &dmabuf, &offset);
1334                 if (!err)
1335                         mem = dma_buf_vmap(dmabuf);
1336         }
1337
1338         if (mem) {
1339                 u32 i;
1340                 /*
1341                  * Write in batches of 128 as there seems to be a limit
1342                  * of how much you can output to ftrace at once.
1343                  */
1344                 for (i = 0; i < words; i += 128U) {
1345                         trace_gk20a_push_cmdbuf(
1346                                 c->g->dev->name,
1347                                 0,
1348                                 min(words - i, 128U),
1349                                 offset + i * sizeof(u32),
1350                                 mem);
1351                 }
1352                 dma_buf_vunmap(dmabuf, mem);
1353         }
1354 }
1355
1356 static int gk20a_channel_add_job(struct channel_gk20a *c,
1357                                  struct gk20a_channel_fence *fence)
1358 {
1359         struct vm_gk20a *vm = c->vm;
1360         struct channel_gk20a_job *job = NULL;
1361         struct mapped_buffer_node **mapped_buffers = NULL;
1362         int err = 0, num_mapped_buffers;
1363
1364         /* job needs reference to this vm */
1365         gk20a_vm_get(vm);
1366
1367         err = gk20a_vm_get_buffers(vm, &mapped_buffers, &num_mapped_buffers);
1368         if (err) {
1369                 gk20a_vm_put(vm);
1370                 return err;
1371         }
1372
1373         job = kzalloc(sizeof(*job), GFP_KERNEL);
1374         if (!job) {
1375                 gk20a_vm_put_buffers(vm, mapped_buffers, num_mapped_buffers);
1376                 gk20a_vm_put(vm);
1377                 return -ENOMEM;
1378         }
1379
1380         job->num_mapped_buffers = num_mapped_buffers;
1381         job->mapped_buffers = mapped_buffers;
1382         job->fence = *fence;
1383
1384         mutex_lock(&c->jobs_lock);
1385         list_add_tail(&job->list, &c->jobs);
1386         mutex_unlock(&c->jobs_lock);
1387
1388         return 0;
1389 }
1390
1391 void gk20a_channel_update(struct channel_gk20a *c, int nr_completed)
1392 {
1393         struct vm_gk20a *vm = c->vm;
1394         struct channel_gk20a_job *job, *n;
1395
1396         wake_up(&c->submit_wq);
1397
1398         mutex_lock(&c->jobs_lock);
1399         list_for_each_entry_safe(job, n, &c->jobs, list) {
1400                 bool completed = WARN_ON(!c->sync) ||
1401                         c->sync->is_expired(c->sync, &job->fence);
1402                 if (!completed)
1403                         break;
1404
1405                 gk20a_vm_put_buffers(vm, job->mapped_buffers,
1406                                 job->num_mapped_buffers);
1407
1408                 /* job is done. release its reference to vm */
1409                 gk20a_vm_put(vm);
1410
1411                 list_del_init(&job->list);
1412                 kfree(job);
1413                 gk20a_idle(c->g->dev);
1414         }
1415         mutex_unlock(&c->jobs_lock);
1416 }
1417
1418 static int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
1419                                 struct nvhost_gpfifo *gpfifo,
1420                                 u32 num_entries,
1421                                 struct nvhost_fence *fence,
1422                                 u32 flags)
1423 {
1424         struct gk20a *g = c->g;
1425         struct device *d = dev_from_gk20a(g);
1426         int err = 0;
1427         int i;
1428         struct priv_cmd_entry *wait_cmd = NULL;
1429         struct priv_cmd_entry *incr_cmd = NULL;
1430         /* we might need two extra gpfifo entries - one for pre fence
1431          * and one for post fence. */
1432         const int extra_entries = 2;
1433         bool need_wfi = !(flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SUPPRESS_WFI);
1434
1435         if (c->has_timedout)
1436                 return -ETIMEDOUT;
1437
1438         if ((flags & (NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT |
1439                       NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET)) &&
1440             !fence)
1441                 return -EINVAL;
1442
1443         if (!c->sync) {
1444                 c->sync = gk20a_channel_sync_create(c);
1445                 if (!c->sync)
1446                         return -ENOMEM;
1447         }
1448
1449 #ifdef CONFIG_DEBUG_FS
1450         /* update debug settings */
1451         if (g->ops.ltc.sync_debugfs)
1452                 g->ops.ltc.sync_debugfs(g);
1453 #endif
1454
1455         gk20a_dbg_info("channel %d", c->hw_chid);
1456
1457         /* gk20a_channel_update releases this ref. */
1458         err = gk20a_busy(g->dev);
1459         if (err) {
1460                 gk20a_err(d, "failed to host gk20a to submit gpfifo");
1461                 return err;
1462         }
1463
1464         trace_gk20a_channel_submit_gpfifo(c->g->dev->name,
1465                                           c->hw_chid,
1466                                           num_entries,
1467                                           flags,
1468                                           fence->syncpt_id, fence->value);
1469         check_gp_put(g, c);
1470         update_gp_get(g, c);
1471
1472         gk20a_dbg_info("pre-submit put %d, get %d, size %d",
1473                 c->gpfifo.put, c->gpfifo.get, c->gpfifo.entry_num);
1474
1475         /* Invalidate tlb if it's dirty...                                   */
1476         /* TBD: this should be done in the cmd stream, not with PRIs.        */
1477         /* We don't know what context is currently running...                */
1478         /* Note also: there can be more than one context associated with the */
1479         /* address space (vm).   */
1480         gk20a_mm_tlb_invalidate(c->vm);
1481
1482         /* Make sure we have enough space for gpfifo entries. If not,
1483          * wait for signals from completed submits */
1484         if (gp_free_count(c) < num_entries + extra_entries) {
1485                 err = wait_event_interruptible(c->submit_wq,
1486                         get_gp_free_count(c) >= num_entries + extra_entries ||
1487                         c->has_timedout);
1488         }
1489
1490         if (c->has_timedout) {
1491                 err = -ETIMEDOUT;
1492                 goto clean_up;
1493         }
1494
1495         if (err) {
1496                 gk20a_err(d, "not enough gpfifo space");
1497                 err = -EAGAIN;
1498                 goto clean_up;
1499         }
1500
1501         /*
1502          * optionally insert syncpt wait in the beginning of gpfifo submission
1503          * when user requested and the wait hasn't expired.
1504          * validate that the id makes sense, elide if not
1505          * the only reason this isn't being unceremoniously killed is to
1506          * keep running some tests which trigger this condition
1507          */
1508         if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT) {
1509                 if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE)
1510                         err = c->sync->wait_fd(c->sync, fence->syncpt_id,
1511                                         &wait_cmd);
1512                 else
1513                         err = c->sync->wait_syncpt(c->sync, fence->syncpt_id,
1514                                         fence->value, &wait_cmd);
1515         }
1516         if (err)
1517                 goto clean_up;
1518
1519
1520         /* always insert syncpt increment at end of gpfifo submission
1521            to keep track of method completion for idle railgating */
1522         if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET &&
1523                         flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE)
1524                 err = c->sync->incr_user_fd(c->sync, &incr_cmd,
1525                                             &c->last_submit_fence,
1526                                             need_wfi,
1527                                             &fence->syncpt_id);
1528         else if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET)
1529                 err = c->sync->incr_user_syncpt(c->sync, &incr_cmd,
1530                                                 &c->last_submit_fence,
1531                                                 need_wfi,
1532                                                 &fence->syncpt_id,
1533                                                 &fence->value);
1534         else
1535                 err = c->sync->incr(c->sync, &incr_cmd,
1536                                     &c->last_submit_fence);
1537         if (err)
1538                 goto clean_up;
1539
1540         if (wait_cmd) {
1541                 c->gpfifo.cpu_va[c->gpfifo.put].entry0 =
1542                         u64_lo32(wait_cmd->gva);
1543                 c->gpfifo.cpu_va[c->gpfifo.put].entry1 =
1544                         u64_hi32(wait_cmd->gva) |
1545                         pbdma_gp_entry1_length_f(wait_cmd->size);
1546                 trace_gk20a_push_cmdbuf(c->g->dev->name,
1547                         0, wait_cmd->size, 0, wait_cmd->ptr);
1548
1549                 c->gpfifo.put = (c->gpfifo.put + 1) &
1550                         (c->gpfifo.entry_num - 1);
1551
1552                 /* save gp_put */
1553                 wait_cmd->gp_put = c->gpfifo.put;
1554         }
1555
1556         for (i = 0; i < num_entries; i++) {
1557                 c->gpfifo.cpu_va[c->gpfifo.put].entry0 =
1558                         gpfifo[i].entry0; /* cmd buf va low 32 */
1559                 c->gpfifo.cpu_va[c->gpfifo.put].entry1 =
1560                         gpfifo[i].entry1; /* cmd buf va high 32 | words << 10 */
1561                 trace_write_pushbuffer(c, &c->gpfifo.cpu_va[c->gpfifo.put]);
1562                 c->gpfifo.put = (c->gpfifo.put + 1) &
1563                         (c->gpfifo.entry_num - 1);
1564         }
1565
1566         if (incr_cmd) {
1567                 c->gpfifo.cpu_va[c->gpfifo.put].entry0 =
1568                         u64_lo32(incr_cmd->gva);
1569                 c->gpfifo.cpu_va[c->gpfifo.put].entry1 =
1570                         u64_hi32(incr_cmd->gva) |
1571                         pbdma_gp_entry1_length_f(incr_cmd->size);
1572                 trace_gk20a_push_cmdbuf(c->g->dev->name,
1573                         0, incr_cmd->size, 0, incr_cmd->ptr);
1574
1575                 c->gpfifo.put = (c->gpfifo.put + 1) &
1576                         (c->gpfifo.entry_num - 1);
1577
1578                 /* save gp_put */
1579                 incr_cmd->gp_put = c->gpfifo.put;
1580         }
1581
1582         trace_gk20a_channel_submitted_gpfifo(c->g->dev->name,
1583                                              c->hw_chid,
1584                                              num_entries,
1585                                              flags,
1586                                              fence->syncpt_id, fence->value);
1587
1588         /* TODO! Check for errors... */
1589         gk20a_channel_add_job(c, &c->last_submit_fence);
1590
1591         c->cmds_pending = true;
1592         gk20a_bar1_writel(g,
1593                 c->userd_gpu_va + 4 * ram_userd_gp_put_w(),
1594                 c->gpfifo.put);
1595
1596         gk20a_dbg_info("post-submit put %d, get %d, size %d",
1597                 c->gpfifo.put, c->gpfifo.get, c->gpfifo.entry_num);
1598
1599         gk20a_dbg_fn("done");
1600         return err;
1601
1602 clean_up:
1603         gk20a_err(d, "fail");
1604         free_priv_cmdbuf(c, wait_cmd);
1605         free_priv_cmdbuf(c, incr_cmd);
1606         gk20a_idle(g->dev);
1607         return err;
1608 }
1609
1610 void gk20a_remove_channel_support(struct channel_gk20a *c)
1611 {
1612
1613 }
1614
1615 int gk20a_init_channel_support(struct gk20a *g, u32 chid)
1616 {
1617         struct channel_gk20a *c = g->fifo.channel+chid;
1618         c->g = g;
1619         c->in_use = false;
1620         c->hw_chid = chid;
1621         c->bound = false;
1622         c->remove_support = gk20a_remove_channel_support;
1623         mutex_init(&c->jobs_lock);
1624         INIT_LIST_HEAD(&c->jobs);
1625 #if defined(CONFIG_GK20A_CYCLE_STATS)
1626         mutex_init(&c->cyclestate.cyclestate_buffer_mutex);
1627 #endif
1628         INIT_LIST_HEAD(&c->dbg_s_list);
1629         mutex_init(&c->dbg_s_lock);
1630
1631         return 0;
1632 }
1633
1634 int gk20a_channel_finish(struct channel_gk20a *ch, unsigned long timeout)
1635 {
1636         int err = 0;
1637
1638         if (!ch->cmds_pending)
1639                 return 0;
1640
1641         /* Do not wait for a timedout channel */
1642         if (ch->has_timedout)
1643                 return -ETIMEDOUT;
1644
1645         if (!(ch->last_submit_fence.valid && ch->last_submit_fence.wfi)) {
1646                 gk20a_dbg_fn("issuing wfi, incr to finish the channel");
1647                 err = gk20a_channel_submit_wfi(ch);
1648         }
1649         if (err)
1650                 return err;
1651
1652         BUG_ON(!(ch->last_submit_fence.valid && ch->last_submit_fence.wfi));
1653
1654         gk20a_dbg_fn("waiting for channel to finish thresh:%d",
1655                       ch->last_submit_fence.thresh);
1656
1657         err = ch->sync->wait_cpu(ch->sync, &ch->last_submit_fence, timeout);
1658         if (WARN_ON(err))
1659                 dev_warn(dev_from_gk20a(ch->g),
1660                          "timed out waiting for gk20a channel to finish");
1661         else
1662                 ch->cmds_pending = false;
1663
1664         return err;
1665 }
1666
1667 static int gk20a_channel_wait_semaphore(struct channel_gk20a *ch,
1668                                         ulong id, u32 offset,
1669                                         u32 payload, long timeout)
1670 {
1671         struct platform_device *pdev = ch->g->dev;
1672         struct dma_buf *dmabuf;
1673         void *data;
1674         u32 *semaphore;
1675         int ret = 0;
1676         long remain;
1677
1678         /* do not wait if channel has timed out */
1679         if (ch->has_timedout)
1680                 return -ETIMEDOUT;
1681
1682         dmabuf = dma_buf_get(id);
1683         if (IS_ERR(dmabuf)) {
1684                 gk20a_err(&pdev->dev, "invalid notifier nvmap handle 0x%lx",
1685                            id);
1686                 return -EINVAL;
1687         }
1688
1689         data = dma_buf_kmap(dmabuf, offset >> PAGE_SHIFT);
1690         if (!data) {
1691                 gk20a_err(&pdev->dev, "failed to map notifier memory");
1692                 ret = -EINVAL;
1693                 goto cleanup_put;
1694         }
1695
1696         semaphore = data + (offset & ~PAGE_MASK);
1697
1698         remain = wait_event_interruptible_timeout(
1699                         ch->semaphore_wq,
1700                         *semaphore == payload || ch->has_timedout,
1701                         timeout);
1702
1703         if (remain == 0 && *semaphore != payload)
1704                 ret = -ETIMEDOUT;
1705         else if (remain < 0)
1706                 ret = remain;
1707
1708         dma_buf_kunmap(dmabuf, offset >> PAGE_SHIFT, data);
1709 cleanup_put:
1710         dma_buf_put(dmabuf);
1711         return ret;
1712 }
1713
1714 static int gk20a_channel_wait(struct channel_gk20a *ch,
1715                               struct nvhost_wait_args *args)
1716 {
1717         struct device *d = dev_from_gk20a(ch->g);
1718         struct dma_buf *dmabuf;
1719         struct notification *notif;
1720         struct timespec tv;
1721         u64 jiffies;
1722         ulong id;
1723         u32 offset;
1724         unsigned long timeout;
1725         int remain, ret = 0;
1726
1727         gk20a_dbg_fn("");
1728
1729         if (ch->has_timedout)
1730                 return -ETIMEDOUT;
1731
1732         if (args->timeout == NVHOST_NO_TIMEOUT)
1733                 timeout = MAX_SCHEDULE_TIMEOUT;
1734         else
1735                 timeout = (u32)msecs_to_jiffies(args->timeout);
1736
1737         switch (args->type) {
1738         case NVHOST_WAIT_TYPE_NOTIFIER:
1739                 id = args->condition.notifier.nvmap_handle;
1740                 offset = args->condition.notifier.offset;
1741
1742                 dmabuf = dma_buf_get(id);
1743                 if (IS_ERR(dmabuf)) {
1744                         gk20a_err(d, "invalid notifier nvmap handle 0x%lx",
1745                                    id);
1746                         return -EINVAL;
1747                 }
1748
1749                 notif = dma_buf_vmap(dmabuf);
1750                 if (!notif) {
1751                         gk20a_err(d, "failed to map notifier memory");
1752                         return -ENOMEM;
1753                 }
1754
1755                 notif = (struct notification *)((uintptr_t)notif + offset);
1756
1757                 /* user should set status pending before
1758                  * calling this ioctl */
1759                 remain = wait_event_interruptible_timeout(
1760                                 ch->notifier_wq,
1761                                 notif->status == 0 || ch->has_timedout,
1762                                 timeout);
1763
1764                 if (remain == 0 && notif->status != 0) {
1765                         ret = -ETIMEDOUT;
1766                         goto notif_clean_up;
1767                 } else if (remain < 0) {
1768                         ret = -EINTR;
1769                         goto notif_clean_up;
1770                 }
1771
1772                 /* TBD: fill in correct information */
1773                 jiffies = get_jiffies_64();
1774                 jiffies_to_timespec(jiffies, &tv);
1775                 notif->timestamp.nanoseconds[0] = tv.tv_nsec;
1776                 notif->timestamp.nanoseconds[1] = tv.tv_sec;
1777                 notif->info32 = 0xDEADBEEF; /* should be object name */
1778                 notif->info16 = ch->hw_chid; /* should be method offset */
1779
1780 notif_clean_up:
1781                 dma_buf_vunmap(dmabuf, notif);
1782                 return ret;
1783
1784         case NVHOST_WAIT_TYPE_SEMAPHORE:
1785                 ret = gk20a_channel_wait_semaphore(ch,
1786                                 args->condition.semaphore.nvmap_handle,
1787                                 args->condition.semaphore.offset,
1788                                 args->condition.semaphore.payload,
1789                                 timeout);
1790
1791                 break;
1792
1793         default:
1794                 ret = -EINVAL;
1795                 break;
1796         }
1797
1798         return ret;
1799 }
1800
1801 static int gk20a_channel_set_priority(struct channel_gk20a *ch,
1802                 u32 priority)
1803 {
1804         u32 timeslice_timeout;
1805         /* set priority of graphics channel */
1806         switch (priority) {
1807         case NVHOST_PRIORITY_LOW:
1808                 /* 64 << 3 = 512us */
1809                 timeslice_timeout = 64;
1810                 break;
1811         case NVHOST_PRIORITY_MEDIUM:
1812                 /* 128 << 3 = 1024us */
1813                 timeslice_timeout = 128;
1814                 break;
1815         case NVHOST_PRIORITY_HIGH:
1816                 /* 255 << 3 = 2048us */
1817                 timeslice_timeout = 255;
1818                 break;
1819         default:
1820                 pr_err("Unsupported priority");
1821                 return -EINVAL;
1822         }
1823         channel_gk20a_set_schedule_params(ch,
1824                         timeslice_timeout);
1825         return 0;
1826 }
1827
1828 static int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
1829                             struct nvhost_zcull_bind_args *args)
1830 {
1831         struct gk20a *g = ch->g;
1832         struct gr_gk20a *gr = &g->gr;
1833
1834         gk20a_dbg_fn("");
1835
1836         return gr_gk20a_bind_ctxsw_zcull(g, gr, ch,
1837                                 args->gpu_va, args->mode);
1838 }
1839
1840 /* in this context the "channel" is the host1x channel which
1841  * maps to *all* gk20a channels */
1842 int gk20a_channel_suspend(struct gk20a *g)
1843 {
1844         struct fifo_gk20a *f = &g->fifo;
1845         u32 chid;
1846         bool channels_in_use = false;
1847         int err;
1848
1849         gk20a_dbg_fn("");
1850
1851         /* wait for engine idle */
1852         err = gk20a_fifo_wait_engine_idle(g);
1853         if (err)
1854                 return err;
1855
1856         for (chid = 0; chid < f->num_channels; chid++) {
1857                 if (f->channel[chid].in_use) {
1858
1859                         gk20a_dbg_info("suspend channel %d", chid);
1860                         /* disable channel */
1861                         gk20a_writel(g, ccsr_channel_r(chid),
1862                                 gk20a_readl(g, ccsr_channel_r(chid)) |
1863                                 ccsr_channel_enable_clr_true_f());
1864                         /* preempt the channel */
1865                         gk20a_fifo_preempt_channel(g, chid);
1866
1867                         channels_in_use = true;
1868                 }
1869         }
1870
1871         if (channels_in_use) {
1872                 gk20a_fifo_update_runlist(g, 0, ~0, false, true);
1873
1874                 for (chid = 0; chid < f->num_channels; chid++) {
1875                         if (f->channel[chid].in_use)
1876                                 channel_gk20a_unbind(&f->channel[chid]);
1877                 }
1878         }
1879
1880         gk20a_dbg_fn("done");
1881         return 0;
1882 }
1883
1884 /* in this context the "channel" is the host1x channel which
1885  * maps to *all* gk20a channels */
1886 int gk20a_channel_resume(struct gk20a *g)
1887 {
1888         struct fifo_gk20a *f = &g->fifo;
1889         u32 chid;
1890         bool channels_in_use = false;
1891
1892         gk20a_dbg_fn("");
1893
1894         for (chid = 0; chid < f->num_channels; chid++) {
1895                 if (f->channel[chid].in_use) {
1896                         gk20a_dbg_info("resume channel %d", chid);
1897                         g->ops.fifo.bind_channel(&f->channel[chid]);
1898                         channels_in_use = true;
1899                 }
1900         }
1901
1902         if (channels_in_use)
1903                 gk20a_fifo_update_runlist(g, 0, ~0, true, true);
1904
1905         gk20a_dbg_fn("done");
1906         return 0;
1907 }
1908
1909 void gk20a_channel_semaphore_wakeup(struct gk20a *g)
1910 {
1911         struct fifo_gk20a *f = &g->fifo;
1912         u32 chid;
1913
1914         gk20a_dbg_fn("");
1915
1916         for (chid = 0; chid < f->num_channels; chid++) {
1917                 struct channel_gk20a *c = g->fifo.channel+chid;
1918                 if (c->in_use)
1919                         wake_up_interruptible_all(&c->semaphore_wq);
1920         }
1921 }
1922
1923 static int gk20a_ioctl_channel_submit_gpfifo(
1924         struct channel_gk20a *ch,
1925         struct nvhost_submit_gpfifo_args *args)
1926 {
1927         void *gpfifo;
1928         u32 size;
1929         int ret = 0;
1930
1931         gk20a_dbg_fn("");
1932
1933         if (ch->has_timedout)
1934                 return -ETIMEDOUT;
1935
1936         size = args->num_entries * sizeof(struct nvhost_gpfifo);
1937
1938         gpfifo = kzalloc(size, GFP_KERNEL);
1939         if (!gpfifo)
1940                 return -ENOMEM;
1941
1942         if (copy_from_user(gpfifo,
1943                            (void __user *)(uintptr_t)args->gpfifo, size)) {
1944                 ret = -EINVAL;
1945                 goto clean_up;
1946         }
1947
1948         ret = gk20a_submit_channel_gpfifo(ch, gpfifo, args->num_entries,
1949                                         &args->fence, args->flags);
1950
1951 clean_up:
1952         kfree(gpfifo);
1953         return ret;
1954 }
1955
1956 void gk20a_init_channel(struct gpu_ops *gops)
1957 {
1958         gops->fifo.bind_channel = channel_gk20a_bind;
1959         gops->fifo.disable_channel = channel_gk20a_disable;
1960         gops->fifo.enable_channel = channel_gk20a_enable;
1961 }
1962
1963 long gk20a_channel_ioctl(struct file *filp,
1964         unsigned int cmd, unsigned long arg)
1965 {
1966         struct channel_gk20a *ch = filp->private_data;
1967         struct platform_device *dev = ch->g->dev;
1968         u8 buf[NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE];
1969         int err = 0;
1970
1971         if ((_IOC_TYPE(cmd) != NVHOST_IOCTL_MAGIC) ||
1972                 (_IOC_NR(cmd) == 0) ||
1973                 (_IOC_NR(cmd) > NVHOST_IOCTL_CHANNEL_LAST) ||
1974                 (_IOC_SIZE(cmd) > NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE))
1975                 return -EFAULT;
1976
1977         if (_IOC_DIR(cmd) & _IOC_WRITE) {
1978                 if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd)))
1979                         return -EFAULT;
1980         }
1981
1982         switch (cmd) {
1983         case NVHOST_IOCTL_CHANNEL_OPEN:
1984         {
1985                 int fd;
1986                 struct file *file;
1987                 char *name;
1988
1989                 err = get_unused_fd_flags(O_RDWR);
1990                 if (err < 0)
1991                         break;
1992                 fd = err;
1993
1994                 name = kasprintf(GFP_KERNEL, "nvhost-%s-fd%d",
1995                                 dev_name(&dev->dev), fd);
1996                 if (!name) {
1997                         err = -ENOMEM;
1998                         put_unused_fd(fd);
1999                         break;
2000                 }
2001
2002                 file = anon_inode_getfile(name, filp->f_op, NULL, O_RDWR);
2003                 kfree(name);
2004                 if (IS_ERR(file)) {
2005                         err = PTR_ERR(file);
2006                         put_unused_fd(fd);
2007                         break;
2008                 }
2009                 fd_install(fd, file);
2010
2011                 err = __gk20a_channel_open(ch->g, file);
2012                 if (err) {
2013                         put_unused_fd(fd);
2014                         fput(file);
2015                         break;
2016                 }
2017
2018                 ((struct nvhost_channel_open_args *)buf)->channel_fd = fd;
2019                 break;
2020         }
2021         case NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD:
2022                 break;
2023         case NVHOST_IOCTL_CHANNEL_ALLOC_OBJ_CTX:
2024                 err = gk20a_busy(dev);
2025                 if (err) {
2026                         dev_err(&dev->dev,
2027                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2028                                 __func__, cmd);
2029                         return err;
2030                 }
2031                 err = gk20a_alloc_obj_ctx(ch,
2032                                 (struct nvhost_alloc_obj_ctx_args *)buf);
2033                 gk20a_idle(dev);
2034                 break;
2035         case NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX:
2036                 err = gk20a_busy(dev);
2037                 if (err) {
2038                         dev_err(&dev->dev,
2039                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2040                                 __func__, cmd);
2041                         return err;
2042                 }
2043                 err = gk20a_free_obj_ctx(ch,
2044                                 (struct nvhost_free_obj_ctx_args *)buf);
2045                 gk20a_idle(dev);
2046                 break;
2047         case NVHOST_IOCTL_CHANNEL_ALLOC_GPFIFO:
2048                 err = gk20a_busy(dev);
2049                 if (err) {
2050                         dev_err(&dev->dev,
2051                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2052                                 __func__, cmd);
2053                         return err;
2054                 }
2055                 err = gk20a_alloc_channel_gpfifo(ch,
2056                                 (struct nvhost_alloc_gpfifo_args *)buf);
2057                 gk20a_idle(dev);
2058                 break;
2059         case NVHOST_IOCTL_CHANNEL_SUBMIT_GPFIFO:
2060                 err = gk20a_ioctl_channel_submit_gpfifo(ch,
2061                                 (struct nvhost_submit_gpfifo_args *)buf);
2062                 break;
2063         case NVHOST_IOCTL_CHANNEL_WAIT:
2064                 err = gk20a_busy(dev);
2065                 if (err) {
2066                         dev_err(&dev->dev,
2067                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2068                                 __func__, cmd);
2069                         return err;
2070                 }
2071                 err = gk20a_channel_wait(ch,
2072                                 (struct nvhost_wait_args *)buf);
2073                 gk20a_idle(dev);
2074                 break;
2075         case NVHOST_IOCTL_CHANNEL_ZCULL_BIND:
2076                 err = gk20a_busy(dev);
2077                 if (err) {
2078                         dev_err(&dev->dev,
2079                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2080                                 __func__, cmd);
2081                         return err;
2082                 }
2083                 err = gk20a_channel_zcull_bind(ch,
2084                                 (struct nvhost_zcull_bind_args *)buf);
2085                 gk20a_idle(dev);
2086                 break;
2087         case NVHOST_IOCTL_CHANNEL_SET_ERROR_NOTIFIER:
2088                 err = gk20a_busy(dev);
2089                 if (err) {
2090                         dev_err(&dev->dev,
2091                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2092                                 __func__, cmd);
2093                         return err;
2094                 }
2095                 err = gk20a_init_error_notifier(ch,
2096                                 (struct nvhost_set_error_notifier *)buf);
2097                 gk20a_idle(dev);
2098                 break;
2099 #ifdef CONFIG_GK20A_CYCLE_STATS
2100         case NVHOST_IOCTL_CHANNEL_CYCLE_STATS:
2101                 err = gk20a_busy(dev);
2102                 if (err) {
2103                         dev_err(&dev->dev,
2104                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2105                                 __func__, cmd);
2106                         return err;
2107                 }
2108                 err = gk20a_channel_cycle_stats(ch,
2109                                 (struct nvhost_cycle_stats_args *)buf);
2110                 gk20a_idle(dev);
2111                 break;
2112 #endif
2113         case NVHOST_IOCTL_CHANNEL_SET_TIMEOUT:
2114         {
2115                 u32 timeout =
2116                         (u32)((struct nvhost_set_timeout_args *)buf)->timeout;
2117                 gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d",
2118                            timeout, ch->hw_chid);
2119                 ch->timeout_ms_max = timeout;
2120                 break;
2121         }
2122         case NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX:
2123         {
2124                 u32 timeout =
2125                         (u32)((struct nvhost_set_timeout_args *)buf)->timeout;
2126                 bool timeout_debug_dump = !((u32)
2127                         ((struct nvhost_set_timeout_ex_args *)buf)->flags &
2128                         (1 << NVHOST_TIMEOUT_FLAG_DISABLE_DUMP));
2129                 gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d",
2130                            timeout, ch->hw_chid);
2131                 ch->timeout_ms_max = timeout;
2132                 ch->timeout_debug_dump = timeout_debug_dump;
2133                 break;
2134         }
2135         case NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT:
2136                 ((struct nvhost_get_param_args *)buf)->value =
2137                         ch->has_timedout;
2138                 break;
2139         case NVHOST_IOCTL_CHANNEL_SET_PRIORITY:
2140                 err = gk20a_busy(dev);
2141                 if (err) {
2142                         dev_err(&dev->dev,
2143                                 "%s: failed to host gk20a for ioctl cmd: 0x%x",
2144                                 __func__, cmd);
2145                         return err;
2146                 }
2147                 gk20a_channel_set_priority(ch,
2148                         ((struct nvhost_set_priority_args *)buf)->priority);
2149                 gk20a_idle(dev);
2150                 break;
2151         default:
2152                 dev_err(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd);
2153                 err = -ENOTTY;
2154                 break;
2155         }
2156
2157         if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ))
2158                 err = copy_to_user((void __user *)arg, buf, _IOC_SIZE(cmd));
2159
2160         return err;
2161 }