arch/arm/mach-tegra/board-vcm30_t124-power.c

   1 /*
   2  * arch/arm/mach-tegra/board-vcm30_t124-power.c
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/mfd/max77663-core.h>
  21 #include <linux/regulator/max77663-regulator.h>
  22 #include <linux/regulator/max15569-regulator.h>
  23 #include <linux/gpio.h>
  24 #include <linux/i2c/pca953x.h>
  25 #include <linux/tegra-pmc.h>
  26
  27 #include "pm.h"
  28 #include "board.h"
  29 #include "gpio-names.h"
  30 #include "board-common.h"
  31 #include "board-vcm30_t124.h"
  32 #include "tegra_cl_dvfs.h"
  33 #include "devices.h"
  34 #include "tegra11_soctherm.h"
  35 #include <mach/board_id.h>
  36
  37 #define PMC_CTRL                0x0
  38 #define PMC_CTRL_INTR_LOW       (1 << 17)
  39
  40
  41 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
  42         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
  43         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
  44         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
  45 };
  46
  47 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
  48         {
  49                 .src = FPS_SRC_0,
  50                 .en_src = FPS_EN_SRC_EN0,
  51                 .time_period = FPS_TIME_PERIOD_DEF,
  52         },
  53         {
  54                 .src = FPS_SRC_1,
  55                 .en_src = FPS_EN_SRC_EN1,
  56                 .time_period = FPS_TIME_PERIOD_DEF,
  57         },
  58         {
  59                 .src = FPS_SRC_2,
  60                 .en_src = FPS_EN_SRC_EN0,
  61                 .time_period = FPS_TIME_PERIOD_DEF,
  62         },
  63 };
  64
  65 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg, \
  66                 _always_on, _boot_on, _apply_uV, \
  67                 _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
  68         static struct regulator_init_data max77663_regulator_idata_##_id = { \
  69                 .supply_regulator = _supply_reg, \
  70                 .constraints = { \
  71                         .name = max77663_rails(_id), \
  72                         .min_uV = _min_uV, \
  73                         .max_uV = _max_uV, \
  74                         .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
  75                                         REGULATOR_MODE_STANDBY), \
  76                         .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
  77                                         REGULATOR_CHANGE_STATUS | \
  78                                         REGULATOR_CHANGE_VOLTAGE), \
  79                         .always_on = _always_on, \
  80                         .boot_on = _boot_on, \
  81                         .apply_uV = _apply_uV, \
  82                 }, \
  83                 .num_consumer_supplies = \
  84                 ARRAY_SIZE(max77663_##_id##_supply), \
  85                 .consumer_supplies = max77663_##_id##_supply, \
  86         }; \
  87         static struct max77663_regulator_platform_data \
  88                 max77663_regulator_pdata_##_id = \
  89         { \
  90                 .reg_init_data = &max77663_regulator_idata_##_id, \
  91                 .id = MAX77663_REGULATOR_ID_##_rid, \
  92                 .fps_src = _fps_src, \
  93                 .fps_pu_period = _fps_pu_period, \
  94                 .fps_pd_period = _fps_pd_period, \
  95                 .fps_cfgs = max77663_fps_cfgs, \
  96                 .flags = _flags, \
  97         }
  98
  99 MAX77663_PDATA_INIT(LDO5, ldo5, 800000, 3950000, NULL, 1, 1, 0,
 100                 FPS_SRC_1, FPS_POWER_PERIOD_7, FPS_POWER_PERIOD_0, 0);
 101
 102 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
 103
 104 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
 105         MAX77663_REG(LDO5, ldo5),
 106 };
 107
 108 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
 109         {
 110                 .gpio = MAX77663_GPIO5,
 111                 .dir = GPIO_DIR_OUT,
 112                 .dout = GPIO_DOUT_HIGH,
 113                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
 114                 .alternate = GPIO_ALT_DISABLE,
 115         },
 116 };
 117
 118 static struct max77663_platform_data max77663_pdata = {
 119         .irq_base       = MAX77663_IRQ_BASE,
 120         .gpio_base      = MAX77663_GPIO_BASE,
 121
 122         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
 123         .gpio_cfgs      = max77663_gpio_cfgs,
 124
 125         .regulator_pdata = max77663_reg_pdata,
 126         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
 127
 128         .rtc_i2c_addr   = 0x68,
 129
 130         .use_power_off  = false,
 131 };
 132
 133 static struct i2c_board_info __initdata max77663_regulators[] = {
 134         {
 135                 /* The I2C address was determined by OTP factory setting */
 136                 I2C_BOARD_INFO("max77663", 0x3c),
 137                 .irq            = -1,
 138                 .platform_data  = &max77663_pdata,
 139         },
 140 };
 141
 142 /* MAX15569 switching regulator for vdd_cpu */
 143 static struct regulator_consumer_supply max15569_vddcpu_supply[] = {
 144         REGULATOR_SUPPLY("vdd_cpu", NULL),
 145 };
 146
 147 static struct regulator_init_data max15569_vddcpu_init_data = {
 148         .constraints = {
 149                 .min_uV = 500000,
 150                 .max_uV = 1520000,
 151                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
 152                                 REGULATOR_MODE_STANDBY),
 153                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
 154                                 REGULATOR_CHANGE_STATUS |
 155                                 REGULATOR_CHANGE_CONTROL |
 156                                 REGULATOR_CHANGE_VOLTAGE),
 157                 .always_on = 1,
 158                 .boot_on =  1,
 159                 .apply_uV = 0,
 160         },
 161         .num_consumer_supplies = ARRAY_SIZE(max15569_vddcpu_supply),
 162         .consumer_supplies = max15569_vddcpu_supply,
 163 };
 164
 165 static struct max15569_regulator_platform_data max15569_vddcpu_pdata = {
 166         .reg_init_data = &max15569_vddcpu_init_data,
 167         .max_voltage_uV = 1520000,
 168         .slew_rate_mv_per_us = 44,
 169 };
 170
 171 static struct i2c_board_info __initdata max15569_vddcpu_boardinfo[] = {
 172         {
 173                 I2C_BOARD_INFO("max15569", 0x3a),
 174                 .platform_data  = &max15569_vddcpu_pdata,
 175         },
 176 };
 177
 178 /* MAX15569 switching regulator for vdd_gpu */
 179 static struct regulator_consumer_supply max15569_vddgpu_supply[] = {
 180         REGULATOR_SUPPLY("vdd_gpu", NULL),
 181 };
 182
 183 static struct regulator_init_data max15569_vddgpu_init_data = {
 184         .constraints = {
 185                 .min_uV = 500000,
 186                 .max_uV = 1520000,
 187                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
 188                                 REGULATOR_MODE_STANDBY),
 189                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
 190                                 REGULATOR_CHANGE_STATUS |
 191                                 REGULATOR_CHANGE_CONTROL |
 192                                 REGULATOR_CHANGE_VOLTAGE),
 193                 .always_on = 0,
 194                 .boot_on =  0,
 195                 .apply_uV = 0,
 196         },
 197         .num_consumer_supplies = ARRAY_SIZE(max15569_vddgpu_supply),
 198         .consumer_supplies = max15569_vddgpu_supply,
 199 };
 200
 201 static struct max15569_regulator_platform_data max15569_vddgpu_pdata = {
 202         .reg_init_data = &max15569_vddgpu_init_data,
 203         .max_voltage_uV = 1400000,
 204         .slew_rate_mv_per_us = 44,
 205 };
 206
 207 static struct i2c_board_info __initdata max15569_vddgpu_boardinfo[] = {
 208         {
 209                 I2C_BOARD_INFO("max15569", 0x38),
 210                 .platform_data  = &max15569_vddgpu_pdata,
 211         },
 212 };
 213
 214 static int __init vcm30_t124_max77663_regulator_init(void)
 215 {
 216         i2c_register_board_info(4, max77663_regulators,
 217                                 ARRAY_SIZE(max77663_regulators));
 218
 219         return 0;
 220 }
 221
 222 int __init vcm30_t124_regulator_init(void)
 223 {
 224         vcm30_t124_max77663_regulator_init();
 225         i2c_register_board_info(4, max15569_vddcpu_boardinfo, 1);
 226         i2c_register_board_info(4, max15569_vddgpu_boardinfo, 1);
 227
 228         return 0;
 229 }
 230
 231 static struct tegra_suspend_platform_data vcm30_t124_suspend_data = {
 232         .cpu_timer      = 2000,
 233         .cpu_off_timer  = 2000,
 234         .suspend_mode   = TEGRA_SUSPEND_LP0,
 235         .core_timer     = 0xfefe,
 236         .core_off_timer = 2000,
 237         .corereq_high   = true,
 238         .sysclkreq_high = true,
 239         .cpu_lp2_min_residency = 1000,
 240 };
 241
 242 int __init vcm30_t124_suspend_init(void)
 243 {
 244         tegra_init_suspend(&vcm30_t124_suspend_data);
 245         return 0;
 246 }
 247
 248 static struct thermal_zone_params soctherm_tzp = {
 249         .governor_name = "pid_thermal_gov",
 250 };
 251
 252 static struct tegra_thermtrip_pmic_data tpdata_palmas = {
 253         .reset_tegra = 1,
 254         .pmu_16bit_ops = 0,
 255         .controller_type = 0,
 256         .pmu_i2c_addr = 0x58,
 257         .i2c_controller_id = 4,
 258         .poweroff_reg_addr = 0xa0,
 259         .poweroff_reg_data = 0x0,
 260 };
 261
 262 static struct tegra_thermtrip_pmic_data tpdata_max77663 = {
 263         .reset_tegra = 1,
 264         .pmu_16bit_ops = 0,
 265         .controller_type = 0,
 266         .pmu_i2c_addr = 0x3c,
 267         .i2c_controller_id = 4,
 268         .poweroff_reg_addr = 0x41,
 269         .poweroff_reg_data = 0x80,
 270 };
 271
 272 static struct soctherm_platform_data vcm30_t124_soctherm_data = {
 273         .therm = {
 274                 [THERM_CPU] = {
 275                         .zone_enable = true,
 276                         .passive_delay = 1000,
 277                         .hotspot_offset = 6000,
 278                         .num_trips = 3,
 279                         .trips = {
 280                                 {
 281                                         .cdev_type = "tegra-balanced",
 282                                         .trip_temp = 90000,
 283                                         .trip_type = THERMAL_TRIP_PASSIVE,
 284                                         .upper = THERMAL_NO_LIMIT,
 285                                         .lower = THERMAL_NO_LIMIT,
 286                                 },
 287                                 {
 288                                         .cdev_type = "tegra-heavy",
 289                                         .trip_temp = 100000,
 290                                         .trip_type = THERMAL_TRIP_HOT,
 291                                         .upper = THERMAL_NO_LIMIT,
 292                                         .lower = THERMAL_NO_LIMIT,
 293                                 },
 294                                 {
 295                                         .cdev_type = "tegra-shutdown",
 296                                         .trip_temp = 102000,
 297                                         .trip_type = THERMAL_TRIP_CRITICAL,
 298                                         .upper = THERMAL_NO_LIMIT,
 299                                         .lower = THERMAL_NO_LIMIT,
 300                                 },
 301                         },
 302                         .tzp = &soctherm_tzp,
 303                 },
 304                 [THERM_GPU] = {
 305                         .zone_enable = true,
 306                         .passive_delay = 1000,
 307                         .hotspot_offset = 6000,
 308                         .num_trips = 3,
 309                         .trips = {
 310                                 {
 311                                         .cdev_type = "tegra-balanced",
 312                                         .trip_temp = 90000,
 313                                         .trip_type = THERMAL_TRIP_PASSIVE,
 314                                         .upper = THERMAL_NO_LIMIT,
 315                                         .lower = THERMAL_NO_LIMIT,
 316                                 },
 317                                 {
 318                                         .cdev_type = "tegra-heavy",
 319                                         .trip_temp = 100000,
 320                                         .trip_type = THERMAL_TRIP_HOT,
 321                                         .upper = THERMAL_NO_LIMIT,
 322                                         .lower = THERMAL_NO_LIMIT,
 323                                 },
 324                                 {
 325                                         .cdev_type = "tegra-shutdown",
 326                                         .trip_temp = 102000,
 327                                         .trip_type = THERMAL_TRIP_CRITICAL,
 328                                         .upper = THERMAL_NO_LIMIT,
 329                                         .lower = THERMAL_NO_LIMIT,
 330                                 },
 331                         },
 332                         .tzp = &soctherm_tzp,
 333                 },
 334                 [THERM_PLL] = {
 335                         .zone_enable = true,
 336                 },
 337         },
 338         .throttle = {
 339                 [THROTTLE_HEAVY] = {
 340                         .priority = 100,
 341                         .devs = {
 342                                 [THROTTLE_DEV_CPU] = {
 343                                         .enable = true,
 344                                         .depth = 80,
 345                                 },
 346                         },
 347                 },
 348         },
 349         .tshut_pmu_trip_data = &tpdata_palmas,
 350 };
 351
 352 /* FIXME: Needed? */
 353 int __init vcm30_t124_soctherm_init(void)
 354 {
 355
 356         vcm30_t124_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
 357
 358         tegra_add_cpu_vmax_trips(vcm30_t124_soctherm_data.therm[THERM_CPU].trips,
 359                         &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips);
 360         /*tegra_add_vc_trips(vcm30_t124_soctherm_data.therm[THERM_CPU].trips,
 361                         &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips);
 362 */
 363         return tegra11_soctherm_init(&vcm30_t124_soctherm_data);
 364 }
 365
 366 /*
 367  * GPIO init table for PCA9539 MISC IO GPIOs
 368  * that have to be brought up to a known good state
 369  * except for WiFi as it is handled via the
 370  * WiFi stack.
 371  */
 372 static struct gpio vcm30_t124_system_0_gpios[] = {
 373         {MISCIO_BT_RST_GPIO,    GPIOF_OUT_INIT_HIGH, "bt_rst"},
 374 #ifdef CONFIG_TEGRA_PREPOWER_WIFI
 375         {MISCIO_WF_EN_GPIO,     GPIOF_OUT_INIT_HIGH, "wifi_en"},
 376         {MISCIO_WF_RST_GPIO,    GPIOF_OUT_INIT_HIGH, "wifi_rst"},
 377 #else
 378         {MISCIO_WF_EN_GPIO,     GPIOF_OUT_INIT_LOW,  "wifi_en"},
 379         {MISCIO_WF_RST_GPIO,    GPIOF_OUT_INIT_LOW,  "wifi_rst"},
 380 #endif
 381         {MISCIO_BT_EN_GPIO,     GPIOF_OUT_INIT_HIGH, "bt_en"},
 382         {MISCIO_BT_WAKEUP_GPIO, GPIOF_OUT_INIT_HIGH, "bt_wk"},
 383         {MISCIO_ABB_RST_GPIO,   GPIOF_OUT_INIT_HIGH, "ebb_rst"},
 384         {MISCIO_USER_LED2_GPIO, GPIOF_OUT_INIT_LOW,  "usr_led2"},
 385         {MISCIO_USER_LED1_GPIO, GPIOF_OUT_INIT_LOW,  "usr_led1"},
 386 };
 387
 388 /*
 389  * GPIO init table for PCA9539 MISC IO GPIOs
 390  * related to DAP_D_SEL and DAP_D_EN.
 391  */
 392 static struct gpio vcm30_t124_system_1_gpios[] = {
 393         {MISCIO_MUX_DAP_D_SEL,  GPIOF_OUT_INIT_LOW,     "dap_d_sel"},
 394         {MISCIO_MUX_DAP_D_EN,   GPIOF_OUT_INIT_LOW,     "dap_d_en"},
 395 };
 396
 397 static int __init vcm30_t124_system_0_gpio_init(void)
 398 {
 399         int ret, pin_count = 0;
 400         struct gpio *gpios_info = NULL;
 401         gpios_info = vcm30_t124_system_0_gpios;
 402         pin_count = ARRAY_SIZE(vcm30_t124_system_0_gpios);
 403
 404         /* Set required system GPIOs to initial bootup values */
 405         ret = gpio_request_array(gpios_info, pin_count);
 406
 407         if (ret)
 408                 pr_err("%s gpio_request_array failed(%d)\r\n",
 409                                  __func__, ret);
 410
 411         gpio_free_array(gpios_info, pin_count);
 412
 413         return ret;
 414 }
 415
 416 static int __init vcm30_t124_system_1_gpio_init(void)
 417 {
 418         int ret, pin_count = 0;
 419         struct gpio *gpios_info = NULL;
 420         gpios_info = vcm30_t124_system_1_gpios;
 421         pin_count = ARRAY_SIZE(vcm30_t124_system_1_gpios);
 422
 423         /* Set required system GPIOs to initial bootup values */
 424         ret = gpio_request_array(gpios_info, pin_count);
 425
 426         if (ret)
 427                 pr_err("%s gpio_request_array failed(%d)\r\n",
 428                                  __func__, ret);
 429
 430         gpio_free_array(gpios_info, pin_count);
 431
 432         return ret;
 433 }
 434
 435 /*
 436  * TODO: Check for the correct pca953x before invoking client
 437  *  init functions
 438  */
 439 static int pca953x_client_setup(struct i2c_client *client,
 440                                 unsigned gpio, unsigned ngpio,
 441                                 void *context)
 442 {
 443         int ret = 0;
 444         int system = (int)context;
 445
 446         switch (system) {
 447         case 0:
 448                 ret = vcm30_t124_system_0_gpio_init();
 449                 break;
 450         case 1:
 451                 ret = vcm30_t124_system_1_gpio_init();
 452                 break;
 453         default:
 454                 ret = -EINVAL;
 455         }
 456
 457         if (ret < 0)
 458                 goto fail;
 459
 460         return 0;
 461 fail:
 462         pr_err("%s failed(%d)\r\n", __func__, ret);
 463         return ret;
 464 }
 465
 466
 467 static struct pca953x_platform_data vcm30_t124_miscio_0_pca9539_data = {
 468         .gpio_base  = PCA953X_MISCIO_0_GPIO_BASE,
 469         .setup = pca953x_client_setup,
 470         .context = (void *)0,
 471 };
 472
 473 static struct pca953x_platform_data vcm30_t124_miscio_1_pca9539_data = {
 474         .gpio_base  = PCA953X_MISCIO_1_GPIO_BASE,
 475         .setup = pca953x_client_setup,
 476         .context = (void *)1,
 477 };
 478
 479 static struct i2c_board_info vcm30_t124_i2c2_board_info_pca9539_0 = {
 480         I2C_BOARD_INFO("pca9539", PCA953X_MISCIO_0_ADDR),
 481         .platform_data = &vcm30_t124_miscio_0_pca9539_data,
 482 };
 483
 484 static struct i2c_board_info vcm30_t124_i2c2_board_info_pca9539_1 = {
 485         I2C_BOARD_INFO("pca9539", PCA953X_MISCIO_1_ADDR),
 486         .platform_data = &vcm30_t124_miscio_1_pca9539_data,
 487 };
 488
 489 int __init vcm30_t124_pca953x_init(void)
 490 {
 491         int is_e1860_b00 = 0;
 492
 493         is_e1860_b00 = tegra_is_board(NULL, "61860", NULL, "300", NULL);
 494
 495         i2c_register_board_info(1, &vcm30_t124_i2c2_board_info_pca9539_0, 1);
 496
 497         if (is_e1860_b00) {
 498                 i2c_register_board_info(1,
 499                         &vcm30_t124_i2c2_board_info_pca9539_1, 1);
 500         }
 501
 502         return 0;
 503 }