arch/arm64/boot/dts/tegra210-soc-base.dtsi

   1 /*
   2  * tegra210-soc-base.dtsi: SOC specific DTSI file with all node disabled.
   3  *
   4  * Copyright (c) 2013-2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/tegra-swgroup.h>
  18 #include "tegra210-platforms/tegra210-thermal.dtsi"
  19 #include <dt-bindings/gpio/tegra-gpio.h>
  20 #include <dt-bindings/padctrl/tegra210-pads.h>
  21 #include <dt-bindings/ata/ahci-tegra.h>
  22 #include <dt-bindings/clk/tegra210-clk.h>
  23 #include <dt-bindings/soc/nvidia,tegra210-powergate.h>
  24 #include <dt-bindings/usb/tegra-usb.h>
  25
  26 / {
  27         compatible = "nvidia,tegra210";
  28         interrupt-parent = <&intc>;
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         cpus {
  33                 #address-cells = <2>;
  34                 #size-cells = <0>;
  35                 status = "disabled";
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a57-64bit", "arm,armv8";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "psci";
  42                         errata_hwcaps = <0x7>;
  43                         status = "disabled";
  44                 };
  45
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a57-64bit", "arm,armv8";
  49                         reg = <0x0 0x1>;
  50                         enable-method = "psci";
  51                         errata_hwcaps = <0x7>;
  52                         status = "disabled";
  53                 };
  54
  55                 cpu@2 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a57-64bit", "arm,armv8";
  58                         reg = <0x0 0x2>;
  59                         enable-method = "psci";
  60                         errata_hwcaps = <0x7>;
  61                         status = "disabled";
  62                 };
  63
  64                 cpu@3 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a57-64bit", "arm,armv8";
  67                         reg = <0x0 0x3>;
  68                         enable-method = "psci";
  69                         errata_hwcaps = <0x7>;
  70                         status = "disabled";
  71                 };
  72         };
  73
  74         mc_clk_pd: mc-clk-pd {
  75                 compatible = "nvidia,tegra210-mc-clk-pd";
  76                 #power-domain-cells = <0>;
  77         };
  78
  79         ape_pd: ape-pd {
  80                 compatible = "nvidia,tegra210-ape-pd";
  81                 #power-domain-cells = <0>;
  82                 power-domains = <&mc_clk_pd>;
  83                 partition-id = <TEGRA_POWERGATE_APE>;
  84         };
  85
  86         adsp_pd: adsp-pd {
  87                 compatible = "nvidia,tegra210-adsp-pd";
  88                 #power-domain-cells = <0>;
  89                 power-domains = <&ape_pd>;
  90         };
  91
  92         host1x_pd: host1x-pd {
  93                 compatible = "nvidia,tegra210-host1x-pd";
  94                 is_off;
  95                 host1x;
  96                 #power-domain-cells = <0>;
  97                 power-domains = <&mc_clk_pd>;
  98         };
  99
 100         tsec_pd: tsec-pd {
 101                 compatible = "nvidia,tegra210-tsec-pd";
 102                 is_off;
 103                 #power-domain-cells = <0>;
 104                 power-domains = <&host1x_pd>;
 105         };
 106
 107         nvdec_pd: nvdec-pd {
 108                 compatible = "nvidia,tegra210-nvdec-pd";
 109                 is_off;
 110                 #power-domain-cells = <0>;
 111                 power-domains = <&host1x_pd>;
 112                 partition-id = <TEGRA_POWERGATE_NVDEC>;
 113         };
 114
 115         ve_pd: ve-pd {
 116                 compatible = "nvidia,tegra210-ve-pd";
 117                 is_off;
 118                 #power-domain-cells = <0>;
 119                 power-domains = <&host1x_pd>;
 120                 partition-id = <TEGRA_POWERGATE_VENC>;
 121         };
 122
 123         ve2_pd: ve2-pd {
 124                 compatible = "nvidia,tegra210-ve2-pd";
 125                 is_off;
 126                 #power-domain-cells = <0>;
 127                 power-domains = <&host1x_pd>;
 128                 partition-id = <TEGRA_POWERGATE_VE2>;
 129         };
 130
 131         vic03_pd: vic03-pd {
 132                 compatible = "nvidia,tegra210-vic03-pd";
 133                 is_off;
 134                 #power-domain-cells = <0>;
 135                 power-domains = <&host1x_pd>;
 136                 partition-id = <TEGRA_POWERGATE_VIC>;
 137         };
 138
 139         msenc_pd: msenc-pd {
 140                 compatible = "nvidia,tegra210-msenc-pd";
 141                 is_off;
 142                 #power-domain-cells = <0>;
 143                 power-domains = <&host1x_pd>;
 144                 partition-id = <TEGRA_POWERGATE_MPE>;
 145         };
 146
 147         nvjpg_pd: nvjpg-pd {
 148                 compatible = "nvidia,tegra210-nvjpg-pd";
 149                 is_off;
 150                 #power-domain-cells = <0>;
 151                 power-domains = <&host1x_pd>;
 152                 partition-id = <TEGRA_POWERGATE_NVJPG>;
 153         };
 154
 155         gpu_pd: gpu-pd {
 156                 compatible = "nvidia,tegra210-gpu-pd";
 157                 is_off;
 158                 #power-domain-cells = <0>;
 159                 power-domains = <&host1x_pd>;
 160                 partition-id = <TEGRA_POWERGATE_GPU>;
 161         };
 162
 163         pcie_pd: pcie-pd {
 164                 compatible = "nvidia, tegra210-pcie-pd";
 165                 #power-domain-cells = <0>;
 166                 partition-id = <TEGRA_POWERGATE_PCIE>;
 167         };
 168
 169         sata_pd: sata-pd {
 170                 compatible = "nvidia, tegra210-sata-pd";
 171                 #power-domain-cells = <0>;
 172                 partition-id = <TEGRA_POWERGATE_SATA>;
 173         };
 174
 175         sor_pd: sor-pd {
 176                 compatible = "nvidia, tegra210-sor-pd";
 177                 #power-domain-cells = <0>;
 178                 partition-id = <TEGRA_POWERGATE_SOR>;
 179         };
 180
 181         disa_pd: disa-pd {
 182                 compatible = "nvidia, tegra210-disa-pd";
 183                 #power-domain-cells = <0>;
 184                 partition-id = <TEGRA_POWERGATE_DISA>;
 185         };
 186
 187         disb_pd: disb-pd {
 188                 compatible = "nvidia, tegra210-disb-pd";
 189                 #power-domain-cells = <0>;
 190                 partition-id = <TEGRA_POWERGATE_DISB>;
 191         };
 192
 193         xusba_pd: xusba-pd {
 194                 compatible = "nvidia, tegra210-xusba-pd";
 195                 #power-domain-cells = <0>;
 196                 partition-id = <TEGRA_POWERGATE_XUSBA>;
 197         };
 198
 199         xusbb_pd: xusbb-pd {
 200                 compatible = "nvidia, tegra210-xusbb-pd";
 201                 #power-domain-cells = <0>;
 202                 partition-id = <TEGRA_POWERGATE_XUSBB>;
 203         };
 204
 205         xusbc_pd: xusbc-pd {
 206                 compatible = "nvidia, tegra210-xusbc-pd";
 207                 #power-domain-cells = <0>;
 208                 partition-id = <TEGRA_POWERGATE_XUSBC>;
 209         };
 210
 211         psci {
 212                 compatible = "arm,psci-0.2";
 213                 status = "disabled";
 214                 method = "smc";
 215         };
 216
 217         tlk {
 218                 compatible = "nvidia,trusted-little-kernel";
 219                 logger = "enabled";
 220                 storage = "enabled";
 221         };
 222
 223         arm-pmu {
 224                 compatible = "arm,armv8-pmuv3";
 225                 status = "disabled";
 226                 interrupts = <0 144 0x4>,
 227                              <0 145 0x4>,
 228                              <0 146 0x4>,
 229                              <0 147 0x4>;
 230         };
 231
 232         tegra_car: clock {
 233                 compatible = "nvidia,tegra210-car";
 234                 reg = <0x0 0x60006000 0x0 0x1000>;
 235                 #clock-cells = <1>;
 236                 #reset-cells = <1>;
 237                 status = "disabled";
 238         };
 239
 240         reserved-memory {
 241                 #address-cells = <2>;
 242                 #size-cells = <2>;
 243                 ranges;
 244
 245                 iram: iram-carveout {
 246                         compatible = "nvidia,iram-carveout";
 247                         reg = <0x0 0x40001000 0x0 0x3F000>;
 248                         no-map;
 249                 };
 250         };
 251
 252         tegra-carveouts {
 253                 compatible = "nvidia,carveouts";
 254                 iommus = <&smmu TEGRA_SWGROUP_HC>,
 255                          <&smmu TEGRA_SWGROUP_AVPC>;
 256                 memory-region = <&iram>;
 257                 status = "okay";
 258         };
 259
 260         smmu: iommu {
 261                 compatible = "nvidia,tegra210-smmu";
 262                 reg = <0x0 0x70019000 0x0 0x1000
 263                        0x0 0x6000c000 0x0 0x1000>;
 264                 status = "disabled";
 265                 #asids = <128>;
 266                 dma-window = <0x0 0x80000000 0x0 0x7ff00000>;
 267                 #iommu-cells = <1>;
 268                 swgid-mask = <0x00000fff 0xfffccdcf>;
 269                 #num-translation-enable = <5>;
 270                 #num-asid-security = <8>;
 271
 272                 domains = <&ppcs_as TEGRA_SWGROUP_CELLS5(PPCS, PPCS1, PPCS2, SE, SE1)
 273                            &gpu_as TEGRA_SWGROUP_CELLS(GPUB)
 274                            &ape_as TEGRA_SWGROUP_CELLS(APE)
 275                            &dc_as TEGRA_SWGROUP_CELLS2(DC, DC12)
 276                            &dc_as TEGRA_SWGROUP_CELLS(DCB)
 277                            &common_as TEGRA_SWGROUP_CELLS(AFI)
 278                            &common_as TEGRA_SWGROUP_CELLS(SDMMC1A)
 279                            &common_as TEGRA_SWGROUP_CELLS(SDMMC2A)
 280                            &common_as TEGRA_SWGROUP_CELLS(SDMMC3A)
 281                            &common_as TEGRA_SWGROUP_CELLS(SDMMC4A)
 282                            &common_as TEGRA_SWGROUP_CELLS(HC)
 283                            &common_as 0xFFFFFFFF 0xFFFFFFFF>;
 284
 285                 address-space-prop {
 286                         common_as: common {
 287                                 iova-start = <0x0 0x80000000>;
 288                                 iova-size = <0x0 0x7FF00000>;
 289                                 num-pf-page = <0>;
 290                                 gap-page = <1>;
 291                         };
 292                         ppcs_as: ppcs {
 293                                 iova-start = <0x0 0x80000000>;
 294                                 iova-size = <0x0 0x7FF00000>;
 295                                 num-pf-page = <1>;
 296                                 gap-page = <1>;
 297                         };
 298                         dc_as: dc {
 299                                 iova-start = <0x0 0x00010000>;
 300                                 iova-size = <0x0 0xFFFEFFFF>;
 301                                 num-pf-page = <0>;
 302                                 gap-page = <0>;
 303                         };
 304                         gpu_as: gpu {
 305                                 iova-start = <0x0 0x00100000>;
 306                                 iova-size = <0x3 0xFFEFFFFF>;
 307                                 alignment = <0x20000>;
 308                                 num-pf-page = <0>;
 309                                 gap-page = <0>;
 310                         };
 311                         ape_as: ape {
 312                                 iova-start = <0x0 0x70300000>;
 313                                 iova-size = <0x0 0x8FC00000>;
 314                                 num-pf-page = <0>;
 315                                 gap-page = <1>;
 316                         };
 317                 };
 318         };
 319
 320         bpmp {
 321                 compatible = "nvidia,tegra210-bpmp";
 322                 carveout-start = <0x80005000>;
 323                 carveout-size = <0x10000>;
 324                 status = "disabled";
 325         };
 326
 327         mc {
 328                 compatible = "nvidia,tegra-mc";
 329
 330                 reg-ranges = <10>; /* Per channel. */
 331                 reg = <0x0 0x70019000 0x0 0x00c>,
 332                       <0x0 0x70019050 0x0 0x19c>,
 333                       <0x0 0x70019200 0x0 0x024>,
 334                       <0x0 0x7001929c 0x0 0x1b8>,
 335                       <0x0 0x70019464 0x0 0x198>,
 336                       <0x0 0x70019604 0x0 0x3b0>,
 337                       <0x0 0x700199bc 0x0 0x020>,
 338                       <0x0 0x700199f8 0x0 0x08c>,
 339                       <0x0 0x70019ae4 0x0 0x0b0>,
 340                       <0x0 0x70019ba0 0x0 0x460>,
 341
 342                       /* MC0 */
 343                       <0x0 0x7001c000 0x0 0x00c>,
 344                       <0x0 0x7001c050 0x0 0x198>,
 345                       <0x0 0x7001c200 0x0 0x024>,
 346                       <0x0 0x7001c29c 0x0 0x1b8>,
 347                       <0x0 0x7001c464 0x0 0x198>,
 348                       <0x0 0x7001c604 0x0 0x3b0>,
 349                       <0x0 0x7001c9bc 0x0 0x020>,
 350                       <0x0 0x7001c9f8 0x0 0x08c>,
 351                       <0x0 0x7001cae4 0x0 0x0b0>,
 352                       <0x0 0x7001cba0 0x0 0x460>,
 353
 354                       /* MC1 */
 355                       <0x0 0x7001d000 0x0 0x00c>,
 356                       <0x0 0x7001d050 0x0 0x198>,
 357                       <0x0 0x7001d200 0x0 0x024>,
 358                       <0x0 0x7001d29c 0x0 0x1b8>,
 359                       <0x0 0x7001d464 0x0 0x198>,
 360                       <0x0 0x7001d604 0x0 0x3b0>,
 361                       <0x0 0x7001d9bc 0x0 0x020>,
 362                       <0x0 0x7001d9f8 0x0 0x08c>,
 363                       <0x0 0x7001dae4 0x0 0x0b0>,
 364                       <0x0 0x7001dba0 0x0 0x460>;
 365
 366                 interrupts = <0 77 0x4>;
 367                 int_count  = <8>;
 368                 int_mask   = <0x23D40>;
 369
 370                 channels = <2>;
 371                 status = "disabled";
 372         };
 373
 374         intc: interrupt-controller {
 375                 compatible = "arm,cortex-a15-gic";
 376                 #interrupt-cells = <3>;
 377                 interrupt-controller;
 378                 reg = <0x0 0x50041000 0x0 0x1000
 379                        0x0 0x50042000 0x0 0x0100>;
 380                 status = "disabled";
 381         };
 382
 383         lic: interrupt-controller@60004000 {
 384                 compatible = "nvidia,tegra-gic";
 385                 interrupt-controller;
 386                 reg = <0x0 0x60004000 0x0 0x40>,
 387                       <0x0 0x60004100 0x0 0x40>,
 388                       <0x0 0x60004200 0x0 0x40>,
 389                       <0x0 0x60004300 0x0 0x40>,
 390                       <0x0 0x60004400 0x0 0x40>,
 391                       <0x0 0x60004500 0x0 0x40>;
 392                 status = "disabled";
 393         };
 394
 395         agic-controller {
 396                 compatible = "nvidia,tegra210-agic";
 397                 interrupt-controller;
 398                 no-gic-extension;
 399                 not-per-cpu;
 400                 reg = <0x0 0x702f9000 0x0 0x2000>,
 401                       <0x0 0x702fa000 0x0 0x2000>;
 402                 interrupts = <0 102 0xf04>;
 403                 status = "disabled";
 404         };
 405
 406         timer {
 407                 compatible = "arm,armv8-timer";
 408                 interrupts = <1 13 0xf01
 409                               1 14 0xf01
 410                               1 11 0xf01
 411                               1 10 0xf01>;
 412                 clock-frequency = <19200000>;
 413                 status = "disabled";
 414         };
 415
 416         timer@60005000 {
 417                 compatible = "nvidia,tegra210-timer";
 418                 reg = <0x0 0x60005000 0x0 0x400>;
 419                 interrupts = <0 176 4>,
 420                              <0 177 4>,
 421                              <0 178 4>,
 422                              <0 179 4>;
 423                 status = "disabled";
 424         };
 425
 426         rtc {
 427                 compatible = "nvidia,tegra-rtc";
 428                 reg = <0x0 0x7000e000 0x0 0x100>;
 429                 interrupts = <0 2 0x04>;
 430                 status = "disabled";
 431         };
 432
 433         apbdma: dma@60020000 {
 434                 compatible = "nvidia,tegra124-apbdma";
 435                 power-domains = <&mc_clk_pd>;
 436                 reg = <0x0 0x60020000 0x0 0x1400>;
 437                 interrupts = <0 104 0x04
 438                               0 105 0x04
 439                               0 106 0x04
 440                               0 107 0x04
 441                               0 108 0x04
 442                               0 109 0x04
 443                               0 110 0x04
 444                               0 111 0x04
 445                               0 112 0x04
 446                               0 113 0x04
 447                               0 114 0x04
 448                               0 115 0x04
 449                               0 116 0x04
 450                               0 117 0x04
 451                               0 118 0x04
 452                               0 119 0x04
 453                               0 128 0x04
 454                               0 129 0x04
 455                               0 130 0x04
 456                               0 131 0x04
 457                               0 132 0x04
 458                               0 133 0x04
 459                               0 134 0x04
 460                               0 135 0x04
 461                               0 136 0x04
 462                               0 137 0x04
 463                               0 138 0x04
 464                               0 139 0x04
 465                               0 140 0x04
 466                               0 141 0x04
 467                               0 142 0x04
 468                               0 143 0x04>;
 469                 #dma-cells = <1>;
 470                 status = "disabled";
 471         };
 472
 473         pinmux: pinmux@700008d4 {
 474                 compatible = "nvidia,tegra210-pinmux";
 475                 reg = <0x0 0x700008d4 0x0 0x2a5    /* Pad control registers */
 476                        0x0 0x70003000 0x0 0x290>; /* Mux registers */
 477                 #gpio-range-cells = <3>;
 478                 status = "disabled";
 479         };
 480
 481         gpio: gpio@6000d000 {
 482                 compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 483                 reg = <0x0 0x6000d000 0x0 0x1000>;
 484                 interrupts = <0 32 0x04
 485                                 0 33 0x04
 486                                 0 34 0x04
 487                                 0 35 0x04
 488                                 0 55 0x04
 489                                 0 87 0x04
 490                                 0 89 0x04
 491                                 0 125 0x04>;
 492                 #gpio-cells = <2>;
 493                 gpio-controller;
 494                 #interrupt-cells = <2>;
 495                 interrupt-controller;
 496                 gpio-ranges = <&pinmux 0 0 246>;
 497                 status = "disabled";
 498         };
 499
 500         xotg: xotg {
 501                 compatible = "nvidia,tegra210-xotg";
 502                 interrupts = <0 49 0x04
 503                               0 20 0x04>;
 504                 status = "disabled";
 505         };
 506
 507         xusb_padctl {
 508                 compatible = "nvidia,tegra210-padctl";
 509                 status = "disabled";
 510         };
 511
 512         xusb@70090000 {
 513                 compatible = "nvidia,tegra210-xhci";
 514                 power-domains = <&mc_clk_pd>;
 515                 reg = <0x0 0x70090000 0x0 0x8000
 516                        0x0 0x70098000 0x0 0x1000
 517                        0x0 0x70099000 0x0 0x1000
 518                        0x0 0x7009f000 0x0 0x1000>;
 519                 interrupts = <0 39 0x04
 520                               0 40 0x04
 521                               0 49 0x04
 522                               0 97 0x04
 523                               0 21 0x04>;
 524                 nvidia,hsic0 = /bits/8 <0x1 0x1 0x8 0xa 0 0 1 0x1c 0>;
 525                 iommus = <&smmu TEGRA_SWGROUP_XUSB_HOST>;
 526                 status = "disabled";
 527         };
 528
 529         uarta: serial@70006000 {
 530                 compatible = "nvidia,tegra114-hsuart";
 531                 reg = <0x0 0x70006000 0x0 0x40>;
 532                 reg-shift = <2>;
 533                 interrupts = <0 36 0x04>;
 534                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 535                 nvidia,dma-request-selector = <&apbdma 8>;
 536                 dmas = <&apbdma 8>, <&apbdma 8>;
 537                 dma-names = "rx", "tx";
 538                 status = "disabled";
 539         };
 540
 541         uartb: serial@70006040 {
 542                 compatible = "nvidia,tegra114-hsuart";
 543                 reg = <0x0 0x70006040 0x0 0x40>;
 544                 reg-shift = <2>;
 545                 interrupts = <0 37 0x04>;
 546                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 547                 nvidia,dma-request-selector = <&apbdma 9>;
 548                 dmas = <&apbdma 9>, <&apbdma 9>;
 549                 dma-names = "rx", "tx";
 550                 status = "disabled";
 551         };
 552
 553         uartc: serial@70006200 {
 554                 compatible = "nvidia,tegra114-hsuart";
 555                 reg = <0x0 0x70006200 0x0 0x40>;
 556                 reg-shift = <2>;
 557                 interrupts = <0 46 0x04>;
 558                 nvidia,dma-request-selector = <&apbdma 10>;
 559                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 560                 dmas = <&apbdma 10>, <&apbdma 10>;
 561                 dma-names = "rx", "tx";
 562                 status = "disabled";
 563         };
 564
 565         uartd: serial@70006300 {
 566                 compatible = "nvidia,tegra114-hsuart";
 567                 reg = <0x0 0x70006300 0x0 0x40>;
 568                 reg-shift = <2>;
 569                 interrupts = <0 90 0x04>;
 570                 nvidia,dma-request-selector = <&apbdma 19>;
 571                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 572                 dmas = <&apbdma 19>, <&apbdma 19>;
 573                 dma-names = "rx", "tx";
 574                 status = "disabled";
 575         };
 576
 577         sound {
 578                 iommus = <&smmu TEGRA_SWGROUP_APE>;
 579                 status = "disabled";
 580         };
 581
 582         sound_ref {
 583                 iommus = <&smmu TEGRA_SWGROUP_APE>;
 584                 status = "disabled";
 585         };
 586
 587         tegra_pwm: pwm@7000a000 {
 588                 compatible = "nvidia,tegra124-pwm";
 589                 reg = <0x0 0x7000a000 0x0 0x100>;
 590                 #pwm-cells = <2>;
 591                 status = "disabled";
 592         };
 593
 594         spi0: spi@7000d400 {
 595                 compatible = "nvidia,tegra210-spi";
 596                 reg = <0x0 0x7000d400 0x0 0x200>;
 597                 interrupts = <0 59 0x04>;
 598                 nvidia,dma-request-selector = <&apbdma 15>;
 599                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 dmas = <&apbdma 15>, <&apbdma 15>;
 603                 dma-names = "rx", "tx";
 604                 nvidia,clk-parents = "pll_p", "clk_m";
 605                 status = "disabled";
 606         };
 607
 608         spi1: spi@7000d600 {
 609                 compatible = "nvidia,tegra210-spi";
 610                 reg = <0x0 0x7000d600 0x0 0x200>;
 611                 interrupts = <0 82 0x04>;
 612                 nvidia,dma-request-selector = <&apbdma 16>;
 613                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 dmas = <&apbdma 16>, <&apbdma 16>;
 617                 dma-names = "rx", "tx";
 618                 nvidia,clk-parents = "pll_p", "clk_m";
 619                 status = "disabled";
 620         };
 621
 622         spi2: spi@7000d800 {
 623                 compatible = "nvidia,tegra210-spi";
 624                 reg = <0x0 0x7000d800 0x0 0x200>;
 625                 interrupts = <0 83 0x04>;
 626                 nvidia,dma-request-selector = <&apbdma 17>;
 627                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 dmas = <&apbdma 17>, <&apbdma 17>;
 631                 dma-names = "rx", "tx";
 632                 nvidia,clk-parents = "pll_p", "clk_m";
 633                 status = "disabled";
 634         };
 635
 636         spi3: spi@7000da00 {
 637                 compatible = "nvidia,tegra210-spi";
 638                 reg = <0x0 0x7000da00 0x0 0x200>;
 639                 interrupts = <0 93 0x04>;
 640                 nvidia,dma-request-selector = <&apbdma 18>;
 641                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 dmas = <&apbdma 18>, <&apbdma 18>;
 645                 dma-names = "rx", "tx";
 646                 nvidia,clk-parents = "pll_p", "clk_m";
 647                 status = "disabled";
 648         };
 649
 650         qspi6: spi@70410000 {
 651                 compatible = "nvidia,tegra210-qspi";
 652                 reg = <0x0 0x70410000 0x0 0x1000>;
 653                 interrupts = <0 10 0x04>;
 654                 nvidia,dma-request-selector = <&apbdma 5>;
 655                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 status = "disabled";
 659               };
 660
 661         host1x: host1x {
 662                 compatible = "nvidia,tegra210-host1x", "simple-bus";
 663                 power-domains = <&host1x_pd>;
 664                 wakeup-capable;
 665                 reg = <0x0 0x50000000 0x0 0x00034000>;
 666                 interrupts = <0 65 0x04   /* mpcore syncpt */
 667                               0 67 0x04>; /* mpcore general */
 668                 iommus = <&smmu TEGRA_SWGROUP_HC>;
 669
 670                 #address-cells = <2>;
 671                 #size-cells = <2>;
 672                 status = "disabled";
 673
 674                 ranges;
 675
 676                 nvidia,ch-base = <0>;
 677                 nvidia,nb-channels = <12>;
 678
 679                 nvidia,nb-hw-pts = <192>;
 680                 nvidia,pts-base = <0>;
 681                 nvidia,nb-pts = <192>;
 682
 683                 vi {
 684                         compatible = "nvidia,tegra210-vi", "simple-bus";
 685                         power-domains = <&ve_pd>;
 686                         reg = <0x0 0x54080000 0x0 0x40000>;
 687                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 688                         iommus = <&smmu TEGRA_SWGROUP_VI>;
 689                         status = "disabled";
 690                         clocks = <&tegra_car TEGRA210_CLK_ID_VI>,
 691                                  <&tegra_car TEGRA210_CLK_ID_CSI>,
 692                                  <&tegra_car TEGRA210_CLK_ID_PLL_D>,
 693                                  <&tegra_car TEGRA210_CLK_ID_CILAB>,
 694                                  <&tegra_car TEGRA210_CLK_ID_CILCD>,
 695                                  <&tegra_car TEGRA210_CLK_ID_CILE>;
 696                         clock-names = "vi", "csi", "pll_d",
 697                                         "cilab", "cilcd", "cile";
 698                         resets = <&tegra_car 20>;
 699                         reset-names = "vi";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                 };
 703
 704                 vi-bypass {
 705                         compatible = "nvidia,tegra210-vi-bypass";
 706                         status = "okay";
 707                 };
 708
 709                 isp@54600000 {
 710                         compatible = "nvidia,tegra210-isp";
 711                         power-domains = <&ve_pd>;
 712                         reg = <0x0 0x54600000 0x0 0x00040000>;
 713                         interrupts = <0 71 0x04>;
 714                         iommus = <&smmu TEGRA_SWGROUP_ISP>;
 715                         status = "disabled";
 716                 };
 717
 718                 isp@54680000 {
 719                         compatible = "nvidia,tegra210-isp";
 720                         power-domains = <&ve2_pd>;
 721                         reg = <0x0 0x54680000 0x0 0x00040000>;
 722                         interrupts = <0 70 0x04>;
 723                         iommus = <&smmu TEGRA_SWGROUP_ISP2B>;
 724                         status = "disabled";
 725                 };
 726
 727                 dc@54200000 {
 728                         compatible = "nvidia,tegra210-dc";
 729                         power-domains = <&mc_clk_pd>;
 730                         reg = <0x0 0x54200000 0x0 0x00040000>;
 731                         interrupts = <0 73 0x04>;
 732                         iommus = <&smmu TEGRA_SWGROUP_DC>,
 733                                  <&smmu TEGRA_SWGROUP_DC12>;
 734                         status = "disabled";
 735
 736                         rgb {
 737                                 status = "disabled";
 738                         };
 739                 };
 740
 741                 dc@54240000 {
 742                         compatible = "nvidia,tegra210-dc";
 743                         power-domains = <&mc_clk_pd>;
 744                         reg = <0x0 0x54240000 0x0 0x00040000>;
 745                         interrupts = <0 74 0x04>;
 746                         iommus = <&smmu TEGRA_SWGROUP_DCB>;
 747                         status = "disabled";
 748
 749                         rgb {
 750                                 status = "disabled";
 751                         };
 752                 };
 753
 754                 dsi {
 755                         compatible = "nvidia,tegra210-dsi";
 756                         reg = <0x0 0x54300000 0x0 0x00040000
 757                                0x0 0x54400000 0x0 0x00040000>;
 758                         status = "disabled";
 759                 };
 760
 761                 vic {
 762                         compatible = "nvidia,tegra210-vic";
 763                         power-domains = <&vic03_pd>;
 764                         reg = <0x0 0x54340000 0x0 0x00040000>;
 765                         iommus = <&smmu TEGRA_SWGROUP_VIC>;
 766                         status = "disabled";
 767                 };
 768
 769                 nvenc {
 770                         compatible = "nvidia,tegra210-nvenc";
 771                         power-domains = <&msenc_pd>;
 772                         reg = <0x0 0x544c0000 0x0 0x00040000>;
 773                         iommus = <&smmu TEGRA_SWGROUP_MPE>;
 774                         status = "disabled";
 775                 };
 776
 777                 tsec {
 778                         compatible = "nvidia,tegra210-tsec";
 779                         power-domains = <&tsec_pd>;
 780                         reg = <0x0 0x54500000 0x0 0x00040000>;
 781                         iommus = <&smmu TEGRA_SWGROUP_TSEC>;
 782                         status = "disabled";
 783                 };
 784
 785                 tsecb {
 786                         compatible = "nvidia,tegra210-tsec";
 787                         power-domains = <&tsec_pd>;
 788                         reg = <0x0 0x54100000 0x0 0x00040000>;
 789                         iommus = <&smmu TEGRA_SWGROUP_TSECB>;
 790                         status = "disabled";
 791                 };
 792
 793                 nvdec {
 794                         compatible = "nvidia,tegra210-nvdec";
 795                         power-domains = <&nvdec_pd>;
 796                         reg = <0x0 0x54480000 0x0 0x00040000>;
 797                         iommus = <&smmu TEGRA_SWGROUP_NVDEC>;
 798                         status = "disabled";
 799                 };
 800
 801                 nvjpg {
 802                         compatible = "nvidia,tegra210-nvjpg";
 803                         power-domains = <&nvjpg_pd>;
 804                         reg = <0x0 0x54380000 0x0 0x00040000>;
 805                         iommus = <&smmu TEGRA_SWGROUP_NVJPG>;
 806                         status = "disabled";
 807                 };
 808
 809                 sor {
 810                         compatible = "nvidia,tegra210-sor";
 811                         reg = <0x0 0x54540000 0x0 0x00040000>;
 812                         status = "disabled";
 813                         nvidia,xbar-ctrl = <2 1 0 3 4>;
 814                 };
 815
 816                 sor1 {
 817                         compatible = "nvidia,tegra210-sor1";
 818                         reg = <0x0 0x54580000 0x0 0x00040000>;
 819                         interrupts = <0 76 0x4>; /* INT_SOR_1 */
 820                         status = "disabled";
 821                         nvidia,xbar-ctrl = <2 1 0 3 4>;
 822                 };
 823
 824                 dpaux {
 825                         compatible = "nvidia,tegra210-dpaux";
 826                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 827                         interrupts = <0 159 0x4>; /* INT_DPAUX */
 828                         status = "disabled";
 829                 };
 830
 831                 dpaux1 {
 832                         compatible = "nvidia,tegra210-dpaux1";
 833                         reg = <0x0 0x54040000 0x0 0x00040000>;
 834                         interrupts = <0 11 0x4>; /* INT_DPAUX_1 */
 835                         status = "disabled";
 836                 };
 837                 i2c7: i2c@546c0000 {
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         compatible = "nvidia,tegra210-vii2c";
 841                         reg = <0x0 0x546C0000 0x0 0x00034000>;
 842                         iommus = <&smmu TEGRA_SWGROUP_VII2C>;
 843                         interrupts = <0 17 0x04>;
 844                         scl-gpio = <&gpio TEGRA_GPIO(S, 2) 0>;
 845                         sda-gpio = <&gpio TEGRA_GPIO(S, 3) 0>;
 846                         status = "disabled";
 847                         clock-frequency = <400000>;
 848                 };
 849         };
 850
 851         gpu {
 852                 compatible = "nvidia,tegra210-gm20b", "nvidia,gm20b";
 853                 nvidia,host1x = <&host1x>;
 854                 power-domains = <&gpu_pd>;
 855                 reg = <0x0 0x57000000 0x0 0x01000000>,
 856                     <0x0 0x58000000 0x0 0x01000000>,
 857                     <0x0 0x538f0000 0x0 0x00001000>;
 858                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 859                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 860                 interrupt-names = "stall", "nonstall";
 861                 iommus = <&smmu TEGRA_SWGROUP_GPUB>;
 862                 access-vpr-phys;
 863                 status = "disabled";
 864         };
 865
 866         mipical {
 867                 compatible = "nvidia,tegra210-mipical";
 868                 reg = <0x0 0x700e3000 0x0 0x00000100>;
 869                 clocks = <&tegra_car TEGRA210_CLK_ID_MIPI_CAL>,
 870                         <&tegra_car TEGRA210_CLK_ID_UART_MIPI_CAL>;
 871                 clock-names = "mipi_cal", "uart_mipi_cal";
 872                 status = "disabled";
 873
 874                 dsi {
 875                         dsix-cfg = <0x00000200>;
 876                         dsix-cfg2 = <0x00000002>;
 877                         bias-pad-cfg1 = <0x00000300>;
 878                         bias-pad-cfg2 = <0x00010010>;
 879                 };
 880         };
 881
 882         tegra_pmc: pmc@7000e400 {
 883                 compatible = "nvidia,tegra210-pmc";
 884                 reg = <0x0 0x7000e400 0x0 0x400>;
 885                 #padcontroller-cells = <1>;
 886                 status = "disabled";
 887                 io-pad-defaults {
 888                         audio {
 889                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 890                         };
 891
 892                         cam {
 893                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 894                         };
 895
 896                         dbg {
 897                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 898                         };
 899
 900                         dmic {
 901                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 902                         };
 903
 904                         pex-ctrl {
 905                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 906                         };
 907
 908                         spi {
 909                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 910                         };
 911
 912                         uart {
 913                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 914                         };
 915
 916                         bb {
 917                                 nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
 918                         };
 919                 };
 920         };
 921
 922         adma: adma@702e2000 {
 923                 compatible = "nvidia,tegra210-adma";
 924                 power-domains = <&ape_pd>;
 925                 reg = <0x0 0x702e2000 0x0 0x2000>;
 926                 interrupts = <0 24 0x04
 927                               0 25 0x04
 928                               0 26 0x04
 929                               0 27 0x04
 930                               0 28 0x04
 931                               0 29 0x04
 932                               0 30 0x04
 933                               0 31 0x04
 934                               0 32 0x04
 935                               0 33 0x04
 936                               0 34 0x04
 937                               0 35 0x04
 938                               0 36 0x04
 939                               0 37 0x04
 940                               0 38 0x04
 941                               0 39 0x04
 942                               0 40 0x04
 943                               0 41 0x04
 944                               0 42 0x04
 945                               0 43 0x04
 946                               0 44 0x04
 947                               0 45 0x04>;
 948                         #dma-cells = <1>;
 949                         dma-channels = <22>;
 950                 status = "disabled";
 951         };
 952
 953         se: se@70012000 {
 954                 compatible = "nvidia,tegra210-se";
 955                 power-domains = <&mc_clk_pd>;
 956                 reg = <0x0 0x70012000 0x0 0x2000 /* SE base */
 957                         0x0 0x7000e400 0x0 0x400>; /* PMC base */
 958                 interrupts = <0 58 0x04>;
 959                 status = "disabled";
 960         };
 961
 962         tegra_axbar: ahub {
 963                 compatible = "nvidia,tegra210-axbar";
 964                 power-domains = <&ape_pd>;
 965                 reg = <0x0 0x702d0800 0x0 0x800>;
 966                 status = "disabled";
 967
 968                 #address-cells = <1>;
 969                 #size-cells = <1>;
 970                 ranges = <0x702d0000 0x0 0x702d0000 0x00010000>;
 971
 972                 tegra_admaif: admaif@0x702d0000 {
 973                         compatible = "nvidia,tegra210-admaif";
 974                         reg = <0x702d0000 0x800>;
 975                         dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>,
 976                                 <&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>,
 977                                 <&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>,
 978                                 <&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>,
 979                                 <&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>;
 980                         dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3",
 981                                 "rx4", "tx4", "rx5", "tx5", "rx6", "tx6",
 982                                 "rx7", "tx7", "rx8", "tx8", "rx9", "tx9",
 983                                 "rx10", "tx10";
 984                         status = "disabled";
 985                 };
 986
 987                 tegra_sfc1: sfc@702d2000 {
 988                         compatible = "nvidia,tegra210-sfc";
 989                         reg = <0x702d2000 0x200>;
 990                         nvidia,ahub-sfc-id = <0>;
 991                         status = "disabled";
 992                 };
 993
 994                 tegra_sfc2: sfc@702d2200 {
 995                         compatible = "nvidia,tegra210-sfc";
 996                         reg = <0x702d2200 0x200>;
 997                         nvidia,ahub-sfc-id = <1>;
 998                         status = "disabled";
 999                 };
1000
1001                 tegra_sfc3: sfc@702d2400 {
1002                         compatible = "nvidia,tegra210-sfc";
1003                         reg = <0x702d2400 0x200>;
1004                         nvidia,ahub-sfc-id = <2>;
1005                         status = "disabled";
1006                 };
1007
1008                 tegra_sfc4: sfc@702d2600 {
1009                         compatible = "nvidia,tegra210-sfc";
1010                         reg = <0x702d2600 0x200>;
1011                         nvidia,ahub-sfc-id = <3>;
1012                         status = "disabled";
1013                 };
1014
1015                 spkprot@702d8c00 {
1016                         compatible = "nvidia,tegra210-spkprot";
1017                         reg = <0x702d8c00 0x400>;
1018                         nvidia,ahub-spkprot-id = <0>;
1019                         status = "disabled";
1020                 };
1021
1022                 tegra_amixer: amixer@702dbb00 {
1023                         compatible = "nvidia,tegra210-amixer";
1024                         reg = <0x702dbb00 0x800>;
1025                         nvidia,ahub-amixer-id = <0>;
1026                         status = "disabled";
1027                 };
1028
1029                 tegra_i2s1: i2s@702d1000 {
1030                         compatible = "nvidia,tegra210-i2s";
1031                         reg = <0x702d1000 0x100>;
1032                         nvidia,ahub-i2s-id = <0>;
1033                         status = "disabled";
1034                 };
1035
1036                 tegra_i2s2: i2s@702d1100 {
1037                         compatible = "nvidia,tegra210-i2s";
1038                         reg = <0x702d1100 0x100>;
1039                         nvidia,ahub-i2s-id = <1>;
1040                         status = "disabled";
1041                 };
1042
1043                 tegra_i2s3: i2s@702d1200 {
1044                         compatible = "nvidia,tegra210-i2s";
1045                         reg = <0x702d1200 0x100>;
1046                         nvidia,ahub-i2s-id = <2>;
1047                         status = "disabled";
1048                 };
1049
1050                 tegra_i2s4: i2s@702d1300 {
1051                         compatible = "nvidia,tegra210-i2s";
1052                         reg = <0x702d1300 0x100>;
1053                         nvidia,ahub-i2s-id = <3>;
1054                         status = "disabled";
1055                 };
1056
1057                 tegra_i2s5: i2s@702d1400 {
1058                         compatible = "nvidia,tegra210-i2s";
1059                         reg = <0x702d1400 0x100>;
1060                         nvidia,ahub-i2s-id = <4>;
1061                         status = "disabled";
1062                 };
1063
1064                 tegra_amx1: amx@702d3000 {
1065                         compatible = "nvidia,tegra210-amx";
1066                         reg = <0x702d3000 0x100>;
1067                         nvidia,ahub-amx-id = <0>;
1068                         status = "disabled";
1069                 };
1070
1071                 tegra_amx2: amx@702d3100 {
1072                         compatible = "nvidia,tegra210-amx";
1073                         reg = <0x702d3100 0x100>;
1074                         nvidia,ahub-amx-id = <1>;
1075                         status = "disabled";
1076                 };
1077
1078                 tegra_adx1: adx@702d3800 {
1079                         compatible = "nvidia,tegra210-adx";
1080                         reg = <0x702d3800 0x100>;
1081                         nvidia,ahub-adx-id = <0>;
1082                         status = "disabled";
1083                 };
1084
1085                 tegra_adx2: adx@702d3900 {
1086                         compatible = "nvidia,tegra210-adx";
1087                         reg = <0x702d3900 0x100>;
1088                         nvidia,ahub-adx-id = <1>;
1089                         status = "disabled";
1090                 };
1091
1092                 tegra_dmic1: dmic@702d4000 {
1093                         compatible = "nvidia,tegra210-dmic";
1094                         reg = <0x702d4000 0x100>;
1095                         nvidia,ahub-dmic-id = <0>;
1096                         status = "disabled";
1097                 };
1098
1099                 tegra_dmic2: dmic@702d4100 {
1100                         compatible = "nvidia,tegra210-dmic";
1101                         reg = <0x702d4100 0x100>;
1102                         nvidia,ahub-dmic-id = <1>;
1103                         status = "disabled";
1104                 };
1105
1106                 tegra_dmic3: dmic@702d4200 {
1107                         compatible = "nvidia,tegra210-dmic";
1108                         reg = <0x702d4200 0x100>;
1109                         nvidia,ahub-dmic-id = <2>;
1110                         status = "disabled";
1111                 };
1112
1113                 tegra_afc1: afc@702d7000 {
1114                         compatible = "nvidia,tegra210-afc";
1115                         reg = <0x702d7000 0x100>;
1116                         nvidia,ahub-afc-id = <0>;
1117                         status = "disabled";
1118                 };
1119
1120                 tegra_afc2: afc@702d7100 {
1121                         compatible = "nvidia,tegra210-afc";
1122                         reg = <0x702d7100 0x100>;
1123                         nvidia,ahub-afc-id = <1>;
1124                         status = "disabled";
1125                 };
1126
1127                 tegra_afc3: afc@702d7200 {
1128                         compatible = "nvidia,tegra210-afc";
1129                         reg = <0x702d7200 0x100>;
1130                         nvidia,ahub-afc-id = <2>;
1131                         status = "disabled";
1132                 };
1133
1134                 tegra_afc4: afc@702d7300 {
1135                         compatible = "nvidia,tegra210-afc";
1136                         reg = <0x702d7300 0x100>;
1137                         nvidia,ahub-afc-id = <3>;
1138                         status = "disabled";
1139                 };
1140
1141                 tegra_afc5: afc@702d7400 {
1142                         compatible = "nvidia,tegra210-afc";
1143                         reg = <0x702d7400 0x100>;
1144                         nvidia,ahub-afc-id = <4>;
1145                         status = "disabled";
1146                 };
1147
1148                 tegra_afc6: afc@702d7500 {
1149                         compatible = "nvidia,tegra210-afc";
1150                         reg = <0x702d7500 0x100>;
1151                         nvidia,ahub-afc-id = <5>;
1152                         status = "disabled";
1153                 };
1154
1155                 tegra_mvc1: mvc@702da000 {
1156                         compatible = "nvidia,tegra210-mvc";
1157                         reg = <0x702da000 0x200>;
1158                         nvidia,ahub-mvc-id = <0>;
1159                         status = "disabled";
1160                 };
1161
1162                 tegra_mvc2: mvc@702da200 {
1163                         compatible = "nvidia,tegra210-mvc";
1164                         reg = <0x702da200 0x200>;
1165                         nvidia,ahub-mvc-id = <1>;
1166                         status = "disabled";
1167                 };
1168
1169                 tegra_spdif: spdif@702d6000 {
1170                         compatible = "nvidia,tegra210-spdif";
1171                         reg = <0x702d6000 0x200>;
1172                         nvidia,ahub-spdif-id = <0>;
1173                         status = "disabled";
1174                 };
1175
1176                 tegra_iqc1: iqc@702de000 {
1177                         compatible = "nvidia,tegra210-iqc";
1178                         reg = <0x702de000 0x200>;
1179                         nvidia,ahub-iqc-id = <0>;
1180                         status = "disabled";
1181                 };
1182
1183                 tegra_iqc2: iqc@702de200 {
1184                         compatible = "nvidia,tegra210-iqc";
1185                         reg = <0x702de200 0x200>;
1186                         nvidia,ahub-iqc-id = <1>;
1187                         status = "disabled";
1188                 };
1189
1190                 tegra_ope1: ope@702d8000 {
1191                         compatible = "nvidia,tegra210-ope";
1192                         reg = <0x702d8000 0x100>,
1193                               <0x702d8100 0x100>,
1194                               <0x702d8200 0x200>;
1195                         nvidia,ahub-ope-id = <0>;
1196                         status = "disabled";
1197                 };
1198
1199                 tegra_ope2: ope@702d8400 {
1200                         compatible = "nvidia,tegra210-ope";
1201                         reg = <0x702d8400 0x100>,
1202                               <0x702d8500 0x100>,
1203                               <0x702d8600 0x200>;
1204                         nvidia,ahub-ope-id = <1>;
1205                         status = "disabled";
1206                 };
1207         };
1208
1209         hda@70030000 {
1210                 compatible = "nvidia,tegra30-hda";
1211                 power-domains = <&mc_clk_pd>;
1212                 reg = <0x0 0x70030000 0x0 0x10000>;
1213                 interrupts = <0 81 0x04>;
1214                 status = "disabled";
1215         };
1216
1217         tegra_adsp_audio: adsp_audio {
1218                 compatible = "nvidia,tegra210-adsp-audio";
1219                 power-domains = <&adsp_pd>;
1220                 iommus = <&smmu TEGRA_SWGROUP_APE>;
1221                 status = "disabled";
1222         };
1223
1224         adsp {
1225              compatible = "nvidia,tegra210-adsp";
1226              power-domains = <&adsp_pd>;
1227              reg = <0x0 0x702ef000 0x0 0x1000>, /* AMC */
1228                    <0x0 0x702ec000 0x0 0x2000>, /* AMISC */
1229                    <0x0 0x702ee000 0x0 0x1000>, /* ABRIDGE */
1230                    <0x0 0x702dc800 0x0 0x0>, /* FPGA RESET REG */
1231                    <0x0 0x01000000 0x0 0x6f2c0000>, /* DRAM MAP1 */
1232                    <0x0 0x70300000 0x0 0x8fd00000>; /* DRAM MAP2 */
1233              iommus = <&smmu TEGRA_SWGROUP_APE>;
1234              nvidia,adsp_mem = <0x80300000 0x01000000>, /* ADSP OS */
1235                                <0x80B00000 0x00800000>, /* ADSP APP */
1236                                <0x00400000 0x00010000>; /* ARAM ALIAS 0 */
1237              nvidia,adsp-evp-base = <0x702ef700 0x00000040>;
1238              nvidia,adsp_unit_fpga_reset = <0x0 0x00000040>;
1239              status = "disabled";
1240         };
1241
1242         pcie-controller {
1243                 compatible = "nvidia,tegra210-pcie", "nvidia,tegra124-pcie";
1244                 device_type = "pci";
1245                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
1246                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
1247                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
1248                 reg-names = "pads", "afi", "cs";
1249                 interrupts = <0 98 0x04>, /* controller interrupt */
1250                              <0 99 0x04>; /* MSI interrupt */
1251                 interrupt-names = "intr", "msi";
1252
1253                 #interrupt-cells = <1>;
1254                 interrupt-map-mask = <0 0 0 0>;
1255                 interrupt-map = <0 0 0 0 &intc 0 98 0x04>;
1256
1257                 bus-range = <0x00 0xff>;
1258                 #address-cells = <3>;
1259                 #size-cells = <2>;
1260
1261                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
1262                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
1263                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
1264                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
1265                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
1266
1267                 status = "disabled";
1268
1269                 pci@1,0 {
1270                         device_type = "pci";
1271                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
1272                         reg = <0x000800 0 0 0 0>;
1273                         status = "disabled";
1274
1275                         #address-cells = <3>;
1276                         #size-cells = <2>;
1277                         ranges;
1278
1279                         nvidia,num-lanes = <4>;
1280                 };
1281
1282                 pci@2,0 {
1283                         device_type = "pci";
1284                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
1285                         reg = <0x001000 0 0 0 0>;
1286                         status = "disabled";
1287
1288                         #address-cells = <3>;
1289                         #size-cells = <2>;
1290                         ranges;
1291
1292                         nvidia,num-lanes = <1>;
1293                 };
1294
1295         };
1296
1297         sata@70020000 {
1298                 compatible = "nvidia,tegra210-ahci-sata";
1299                 reg = <0x0 0x70021000 0x0 0x00001000>,
1300                         <0x0 0x70027000 0x0 0x00002000>,
1301                         <0x0 0x70001100 0x0 0x00000021>;
1302                 interrupts = <0 23 0x04>;
1303                 iommus = <&smmu TEGRA_SWGROUP_SATA2>;
1304                 status = "disabled";
1305         };
1306
1307         i2c1: i2c@7000c000 {
1308                 #address-cells = <1>;
1309                 #size-cells = <0>;
1310                 compatible = "nvidia,tegra210-i2c";
1311                 reg = <0x0 0x7000c000 0x0 0x100>;
1312                 interrupts = <0 38 0x04>;
1313                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1314                 status = "disabled";
1315                 clock-frequency = <400000>;
1316         };
1317
1318         i2c2: i2c@7000c400 {
1319                 #address-cells = <1>;
1320                 #size-cells = <0>;
1321                 compatible = "nvidia,tegra210-i2c";
1322                 reg = <0x0 0x7000c400 0x0 0x100>;
1323                 interrupts = <0 84 0x04>;
1324                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1325                 status = "disabled";
1326                 clock-frequency = <100000>;
1327         };
1328
1329         i2c3: i2c@7000c500 {
1330                 #address-cells = <1>;
1331                 #size-cells = <0>;
1332                 compatible = "nvidia,tegra210-i2c";
1333                 reg = <0x0 0x7000c500 0x0 0x100>;
1334                 interrupts = <0 92 0x04>;
1335                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1336                 status = "disabled";
1337                 clock-frequency = <400000>;
1338         };
1339
1340         i2c4: i2c@7000c700 {
1341                 #address-cells = <1>;
1342                 #size-cells = <0>;
1343                 compatible = "nvidia,tegra210-i2c";
1344                 reg = <0x0 0x7000c700 0x0 0x100>;
1345                 interrupts = <0 120 0x04>;
1346                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1347                 status = "disabled";
1348                 clock-frequency = <100000>;
1349         };
1350
1351         i2c5: i2c@7000d000 {
1352                 #address-cells = <1>;
1353                 #size-cells = <0>;
1354                 compatible = "nvidia,tegra210-i2c";
1355                 reg = <0x0 0x7000d000 0x0 0x100>;
1356                 interrupts = <0 53 0x04>;
1357                 scl-gpio = <&gpio 195 0>;
1358                 sda-gpio = <&gpio 196 0>;
1359                 nvidia,require-cldvfs-clock;
1360                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1361                 status = "disabled";
1362                 clock-frequency = <400000>;
1363         };
1364
1365         i2c6: i2c@7000d100 {
1366                 #address-cells = <1>;
1367                 #size-cells = <0>;
1368                 compatible = "nvidia,tegra210-i2c";
1369                 reg = <0x0 0x7000d100 0x0 0x100>;
1370                 interrupts = <0 63 0x04>;
1371                 iommus = <&smmu TEGRA_SWGROUP_PPCS>;
1372                 status = "disabled";
1373                 clock-frequency = <400000>;
1374         };
1375
1376         sdhci@700b0600 {
1377                 compatible = "nvidia,tegra210-sdhci";
1378                 reg = <0x0 0x700b0600 0x0 0x200>;
1379                 interrupts = < 0 31 0x04 >;
1380                 iommus = <&smmu TEGRA_SWGROUP_SDMMC4A>;
1381                 nvidia,runtime-pm-type = <1>;
1382                 status = "disabled";
1383         };
1384
1385         sdhci@700b0400 {
1386                 compatible = "nvidia,tegra210-sdhci";
1387                 reg = <0x0 0x700b0400 0x0 0x200>;
1388                 interrupts = < 0 19 0x04 >;
1389                 iommus = <&smmu TEGRA_SWGROUP_SDMMC3A>;
1390                 pwrdet-support;
1391                 pad-controllers = <&tegra_pmc TEGRA210_PAD_SDMMC3>;
1392                 pad-names = "sdmmc";
1393                 nvidia,runtime-pm-type = <0>;
1394                 status = "disabled";
1395         };
1396
1397         sdhci@700b0200 {
1398                 compatible = "nvidia,tegra210-sdhci";
1399                 reg = <0x0 0x700b0200 0x0 0x200>;
1400                 interrupts = < 0 15 0x04 >;
1401                 nvidia,runtime-pm-type = <1>;
1402                 status = "disabled";
1403         };
1404
1405         sdhci@700b0000 {
1406                 compatible = "nvidia,tegra210-sdhci";
1407                 reg = <0x0 0x700b0000 0x0 0x200>;
1408                 interrupts = < 0 14 0x04 >;
1409                 iommus = <&smmu TEGRA_SWGROUP_SDMMC1A>;
1410                 pwrdet-support;
1411                 pad-controllers = <&tegra_pmc TEGRA210_PAD_SDMMC1>;
1412                 pad-names = "sdmmc";
1413                 nvidia,runtime-pm-type = <1>;
1414                 status = "disabled";
1415         };
1416
1417         efuse@7000f800 {
1418                 compatible = "nvidia,tegra210-efuse";
1419                 reg = <0x0 0x7000f800 0x0 0x400>;
1420                 status = "disabled";
1421         };
1422
1423         udc: udc@7d000000 {
1424                 compatible = "nvidia,tegra210-udc";
1425                 reg = <0x0 0x7d000000 0x0 0x4000>;
1426                 interrupts = <0 20 0x04>;
1427                 status = "disabled";
1428         };
1429
1430         otg: otg@7d000000 {
1431                 compatible = "nvidia,tegra132-otg";
1432                 power-domains = <&mc_clk_pd>;
1433                 reg = <0x0 0x7d000000 0x0 0x4000>;
1434                 interrupts = <0 20 0x04>;
1435                 nvidia,hc-device = <&ehci1>;
1436                 status = "disabled";
1437         };
1438
1439         ehci1: ehci@7d000000 {
1440                 compatible = "nvidia,tegra132-ehci";
1441                 power-domains = <&mc_clk_pd>;
1442                 reg = <0x0 0x7d000000 0x0 0x4000>;
1443                 interrupts = <0 20 0x04>;
1444                 iommus = <&smmu TEGRA_SWGROUP_PPCS>,
1445                          <&smmu TEGRA_SWGROUP_PPCS1>,
1446                          <&smmu TEGRA_SWGROUP_PPCS2>;
1447                 nvidia,port-otg;
1448                 nvidia,has-hostpc;
1449                 nvidia,unaligned-dma-buf-supported;
1450                 nvidia,power-off-on-suspend;
1451                 nvidia,is-intf-utmi;
1452                 nvidia,remote-wakeup-supported;
1453                 nvidia,hssync-start-delay = <0>;
1454                 nvidia,idle-wait-delay = <17>;
1455                 nvidia,elastic-limit = <16>;
1456                 nvidia,term-range-adj = <6>;
1457                 nvidia,xcvr-setup = <8>;
1458                 nvidia,xcvr-lsfslew = <2>;
1459                 nvidia,xcvr-lsrslew = <2>;
1460                 nvidia,xcvr-use-fuses;
1461                 nvidia,vbus-oc-map = <5>;
1462                 nvidia,xcvr-setup-offset = <0>;
1463                 status = "disabled";
1464         };
1465
1466         pmc-iopower {
1467                 compatible = "nvidia,tegra210-pmc-iopower";
1468                 pad-controllers = <&tegra_pmc TEGRA210_PAD_SYS
1469                                         &tegra_pmc TEGRA210_PAD_UART
1470                                         &tegra_pmc TEGRA210_PAD_AUDIO
1471                                         &tegra_pmc TEGRA210_PAD_CAM
1472                                         &tegra_pmc TEGRA210_PAD_PEX_CTRL
1473                                         &tegra_pmc TEGRA210_PAD_SDMMC1
1474                                         &tegra_pmc TEGRA210_PAD_SDMMC3
1475                                         &tegra_pmc TEGRA210_PAD_HV
1476                                         &tegra_pmc TEGRA210_PAD_AUDIO_HV
1477                                         &tegra_pmc TEGRA210_PAD_DBG
1478                                         &tegra_pmc TEGRA210_PAD_DMIC
1479                                         &tegra_pmc TEGRA210_PAD_GPIO
1480                                         &tegra_pmc TEGRA210_PAD_SPI
1481                                         &tegra_pmc TEGRA210_PAD_SPI_HV>;
1482                 pad-names = "sys", "uart", "audio", "cam", "pex-ctrl",
1483                         "sdmmc1", "sdmmc3", "hv", "audio-hv", "debug", "dmic",
1484                         "gpio", "spi", "spi-hv";
1485                 status = "disabled";
1486         };
1487
1488         dtv@7000c300 {
1489                 compatible = "nvidia,tegra210-dtv";
1490                 reg = <0x0 0x7000c300 0x0 0x100>;
1491                 nvidia,dma-request-selector = <11>;
1492                 dmas = <&apbdma 11>;
1493                 dma-names = "rx";
1494                 status = "disabled";
1495         };
1496
1497         usb_cd: usb_cd@7009f000 {
1498                 compatible = "nvidia,tegra210-usb-cd";
1499                 reg = <0x0 0x7009f000 0x0 0x1000>;
1500                 #extcon-cells = <1>;
1501                 status = "disabled";
1502                 dt-override-status-odm-data = <0x1000000 0x1000000>;
1503         };
1504
1505         xudc: xudc@700d0000 {
1506                 compatible = "nvidia,tegra210-xudc";
1507                 reg = <0x0 0x700d0000 0x0 0x8000>,
1508                         <0x0 0x700d8000 0x0 0x1000>,
1509                         <0x0 0x700d9000 0x0 0x1000>,
1510                         <0x0 0x7009f000 0x0 0x1000>;
1511                 interrupts = <0 44 0x4
1512                                 0 49 0x4>;
1513                 status = "disabled";
1514         };
1515
1516         soctherm: soctherm@0x700E2000 {
1517                 compatible = "nvidia,tegra-soctherm";
1518                 reg =   <0x0 0x700E2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
1519                         <0x0 0x60006000 0x0 0x400>, /* 1: CAR reg_base */
1520                         <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
1521                 interrupts = <0 48 0x04
1522                               0 51 0x04>;
1523                 #thermal-sensor-cells = <1>;
1524                 status = "disabled";
1525                 interrupt-controller;
1526                 #interrupt-cells = <2>;
1527                 soctherm-clock-frequency = <51000000>;
1528                 tsensor-clock-frequency  = <400000>;
1529                 sensor-params-tall       = <16300>;
1530                 sensor-params-tiddq      = <1>;
1531                 sensor-params-ten-count  = <1>;
1532                 sensor-params-tsample    = <120>;
1533                 sensor-params-pdiv       = <8>;
1534                 sensor-params-tsamp-ate  = <480>;
1535                 sensor-params-pdiv-ate   = <8>;
1536                 fuse_war@fuse_rev_0_1 {
1537                         device_type = "fuse_war";
1538                         match_fuse_rev = <0 1>;
1539                         cpu0 = <1088700    397600 >;
1540                         cpu1 = <1077600    1073200 >;
1541                         cpu2 = <1104800    (-617000) >;
1542                         cpu3 = <1093800   (-901200)>;
1543                         mem0 = <1085300     (-98400) >;
1544                         mem1 = <1104800    (-99000) >;
1545                         gpu  = <1085800  (-1097500)>;
1546                         pllx = <1078800  (-890700)>;
1547                 };
1548                 fuse_war@fuse_rev_2 {
1549                         device_type = "fuse_war";
1550                         match_fuse_rev = <2>;
1551                         cpu0 = <1085000  3244200 >;
1552                         cpu1 = <1126200  (-67500) >;
1553                         cpu2 = <1098400  2251100 >;
1554                         cpu3 = <1108000  602700>;
1555                         mem0 = <1069200  3549900>;
1556                         mem1 = <1173700  (-6263600)>;
1557                         gpu  = <1074300  2734900>;
1558                         pllx = <1039700  6829100>;
1559                 };
1560                 /* thermctl - groups of sensors */
1561                 therm_cpu {
1562                         device_type = "thermctl";
1563                         thermal-sensor-id = <0>;
1564                         hotspot-offset = <10000>;
1565                 };
1566                 therm_gpu {
1567                         device_type = "thermctl";
1568                         thermal-sensor-id = <1>;
1569                         hotspot-offset = <5000>;
1570                 };
1571                 therm_mem {
1572                         status = "disabled";
1573                         device_type = "thermctl";
1574                         thermal-sensor-id = <2>;
1575                 };
1576                 therm_pll {
1577                         device_type = "thermctl";
1578                         thermal-sensor-id = <3>;
1579                 };
1580
1581                 /* throttlectl - hardware 'throttle' devices */
1582                 throttle@critical {
1583                         device_type = "throttlectl";
1584                         cdev-type = "tegra-shutdown";
1585                         cooling-min-state = <0>;
1586                         cooling-max-state = <3>;
1587                         #cooling-cells = <2>;
1588                 };
1589                 throttle@heavy {
1590                         device_type = "throttlectl";
1591                         cdev-type = "tegra-heavy";
1592                         cooling-min-state = <0>;
1593                         cooling-max-state = <3>;
1594                         #cooling-cells = <2>;
1595                         priority = <100>;
1596                         throttle_dev = <&{/soctherm@0x700E2000/throttle_dev@cpu_high}
1597                                         &{/soctherm@0x700E2000/throttle_dev@gpu_high}>;
1598                 };
1599                 throttle_dev@cpu_high {
1600                         depth = <85>;
1601                 };
1602                 throttle_dev@gpu_high {
1603                         level = "heavy_throttling";
1604                 };
1605         };
1606
1607         tegra-aotag {
1608                 compatible = "nvidia,tegra21x-aotag";
1609                 parent-block = <&{/pmc@7000e400}>;
1610                 /*
1611                  * interrupts =
1612                  * #interrupt-names =
1613                  */
1614                 status = "disabled";
1615                 sensor-params-tall       = <76>;
1616                 sensor-params-tiddq      = <1>;
1617                 sensor-params-ten-count  = <16>;
1618                 sensor-params-tsample    = <9>;
1619                 sensor-params-pdiv       = <8>;
1620                 sensor-params-tsamp-ate  = <39>;
1621                 sensor-params-pdiv-ate   = <8>;
1622
1623
1624                 #thermal-sensor-cells = <0>;
1625                 /* make this to '1' in case of more than one sensors */
1626
1627                 /*
1628                  * right way to do with multiple sensors is -
1629                  * sensor0 : sensor@<0x.....>
1630                  * etc.
1631                  * e.g,
1632                  * sensor@0 {
1633                  * sensor-name = "aotag0";
1634                  * sensor-id = <0>;
1635                  * };
1636                  *
1637                  */
1638                 sensor-name = "aotag0";
1639                 sensor-id = <0>;
1640                 advertised-sensor-id = <9>;
1641                 /*
1642                  * sensor-type = "nvidia,tegra21x-aotag";
1643                  * not required, use 'compatible' instead.
1644                  * keeping it as a comment
1645                  */
1646                 sensor-nominal-temp-cp = <25>;
1647                 sensor-nominal-temp-ft = <105>;
1648
1649                 sensor-compensation-a = <10632>;
1650                 sensor-compensation-b = <(-67490)>;
1651         };
1652
1653         tegra_cec {
1654                 compatible = "nvidia,tegra210-cec";
1655                 reg = <0x0 0x70015000 0x0 0x00001000>;
1656                 interrupts = <0 3 0x04>;
1657                 status = "disabled";
1658         };
1659
1660         ehci2: ehci@7d004000 {
1661                 compatible = "nvidia,tegra132-ehci";
1662                 power-domains = <&mc_clk_pd>;
1663                 reg = <0x0 0x7d004000 0x0 0x4000>;
1664                 interrupts = <0 21 0x04>;
1665                 iommus = <&smmu TEGRA_SWGROUP_PPCS>,
1666                          <&smmu TEGRA_SWGROUP_PPCS1>,
1667                          <&smmu TEGRA_SWGROUP_PPCS2>;
1668                 nvidia,has-hostpc;
1669                 nvidia,power-off-on-suspend;
1670                 nvidia,remote-wakeup-supported;
1671                 nvidia,skip_resume;
1672                 status = "disabled";
1673         };
1674
1675         tegra_watchdog: watchdog@60005100 {
1676                 compatible = "nvidia,tegra-wdt";
1677                 reg = <0x0 0x60005100 0x0 0x20              /* WDT0 registers */
1678                 0x0 0x60005070 0x0 0x8>;              /* TMR7 registers */
1679                 interrupts = <0 123 0x04>;
1680                 nvidia,expiry-count = <4>;
1681                 status = "disabled";
1682         };
1683
1684         fiq_debugger {
1685                 compatible = "nvidia,fiq-debugger";
1686                 use-console-port;
1687                 interrupts = <1 12 0x0108>;
1688         };
1689
1690         ptm {
1691                 compatible = "nvidia,ptm";
1692                 reg = <0x0 0x72010000 0x0 0x1000>, /* funnel_major */
1693                       <0x0 0x72030000 0x0 0x1000>, /* etf */
1694                       <0x0 0x72040000 0x0 0x1000>, /* replicator */
1695                       <0x0 0x72050000 0x0 0x1000>, /* etr */
1696                       <0x0 0x72060000 0x0 0x1000>, /* tpiu */
1697                       <0x0 0x73010000 0x0 0x1000>, /* funnel_bccplex */
1698                       <0x0 0x73440000 0x0 0x1000>, /* ptm0 */
1699                       <0x0 0x73540000 0x0 0x1000>, /* ptm1 */
1700                       <0x0 0x73640000 0x0 0x1000>, /* ptm2 */
1701                       <0x0 0x73740000 0x0 0x1000>, /* ptm3 */
1702                       <0x0 0x72820000 0x0 0x1000>, /* funnel_minor */
1703                       <0x0 0x72a1c000 0x0 0x1000>; /* ape */
1704         };
1705
1706         mselect {
1707                 compatible = "nvidia,tegra-mselect";
1708                 interrupts = < 0 175 0x4 >;
1709                 reg = < 0x0 0x50060000 0x0 0x1000 >;
1710                 status = "disabled";
1711         };
1712
1713         cpuidle {
1714                 compatible = "nvidia,tegra210-cpuidle";
1715         };
1716 };