drivers/video/tegra/dc/hdmivrr.h

   1 /*
   2  * drivers/video/tegra/dc/hdmivrr.h
   3  *
   4  * Copyright (c) 2015-2016, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __DRIVERS_VIDEO_TEGRA_DC_HDMIVRR_H
  18 #define __DRIVERS_VIDEO_TEGRA_DC_HDMIVRR_H
  19
  20 #define VCP_MAGIC0                      0xe0
  21 #define VCP_MAGIC1                      0xe1
  22 #define VCP_AUX_STAT                    0xe2
  23 #define VCP_AUX_STAT_IDLE               0x00
  24 #define VCP_AUX_STAT_RD                 0x01
  25 #define VCP_AUX_STAT_WR                 0x02
  26 #define VCP_AUX_ADDR_H                  0xe3
  27 #define VCP_AUX_ADDR_L                  0xe4
  28 #define VCP_AUX_LENGTH                  0xe5
  29 #define VCP_AUX_BUF                     0xe6
  30
  31 #define VCP_TEMP                        0xf9
  32 #define VCP_BOARDID                     0xfa
  33 #define VCP_DP_STATUS                   0xfb
  34 #define VCP_GFX_VER                     0xfc
  35 #define VCP_PANEL_VER                   0xfd
  36 #define VCP_NV_FW_VER                   0xfe
  37 #define NV_FW_MIN_VER                   0x400
  38 #define VCP_ERROR                       0xff
  39
  40 #define SET_VCP_LEN                     0x7
  41 #define SET_VCP_VCP_OFF                 0x3
  42 #define SET_VCP_SH_OFF                  0x4
  43 #define SET_VCP_SL_OFF                  0x5
  44
  45 #define GET_VCP_WR_LEN                  0x5
  46 #define GET_VCP_WR_VCP_OFF              0x3
  47 #define GET_VCP_RD_LEN                  0xb
  48 #define GET_VCP_RES_CODE_OFF            0x3
  49 #define GET_VCP_RES_CODE_NO_ERR         0x0
  50 #define GET_VCP_RES_CODE_UN_SUP         0x1
  51 #define GET_VCP_SH_OFF                  0x8
  52 #define GET_VCP_SL_OFF                  0x9
  53
  54 #define TABLE_WRITE_LEN                 0x17
  55 #define TABLE_WRITE_HEADER_LEN          0x6
  56 #define TABLE_WRITE_LEN_OFF             0x1
  57 #define TABLE_WRITE_VCP_OFF             0x3
  58 #define TABLE_WRITE_DATA_OFF            0x6
  59
  60 #define TABLE_READ_WR_LEN               0x7
  61 #define TABLE_READ_WR_VCP_OFF           0x3
  62 #define TABLE_READ_RD_LEN               0x16
  63 #define TABLE_READ_RD_HEADER_LEN        0x5
  64 #define TABLE_READ_RD_DATA_OFF          0x5
  65
  66 #define DPAUX_SOURCE_OUI                0x300
  67 #define DPAUX_AUTH_MAGIC                0x310
  68 #define AUTH_MAGIC_NUM                  0x56525200
  69 #define DPAUX_AUTH_PROTOCOL             0x314
  70 #define AUTH_PROTOCOL_VALID             0x1
  71 #define DPAUX_AUTH_KEYNUM               0x315
  72 #define AUTH_KEYNUM_VALUE               0x0b
  73 #define DPAUX_SERIALNUM                 0x316
  74 #define DPAUX_AUTH_CMD                  0x320
  75 #define AUTH_CMD_RESET                  0x0
  76 #define AUTH_CMD_MONAUTH                0x1
  77 #define AUTH_CMD_DRVAUTH                0x2
  78 #define DPAUX_AUTH_STATUS               0x321
  79 #define AUTH_STATUS_READY               0xff
  80 #define AUTH_STATUS_BUSY                0x01
  81 #define DPAUX_LOCK_STATUS               0x322
  82 #define LOCK_STATUS_LOCKED              0x00
  83 #define LOCK_STATUS_UNLOCKED            0x01
  84 #define DPAUX_AUTH_CHALLENGE1           0x3c0
  85 #define DPAUX_AUTH_CHALLENGE2           0x3d0
  86 #define DPAUX_AUTH_DIGEST1              0x3e0
  87 #define DPAUX_AUTH_DIGEST2              0x3f0
  88
  89 #ifdef CONFIG_TEGRA_HDMIVRR
  90 int tegra_hdmivrr_setup(struct tegra_hdmi *hdmi);
  91 void tegra_hdmivrr_update_monspecs(struct tegra_dc *dc,
  92         struct list_head *head);
  93 int tegra_hdmi_vrr_init(struct tegra_hdmi *hdmi);
  94 void te_authenticate_vrr(u8 *buf_ptr, u32 buflen);
  95 #else
  96 int tegra_hdmivrr_setup(struct tegra_hdmi *hdmi) { return -EPROTONOSUPPORT; }
  97 void tegra_hdmivrr_update_monspecs(struct tegra_dc *dc,
  98         struct list_head *head) { return; }
  99 int tegra_hdmi_vrr_init(struct tegra_hdmi *hdmi) { return -EPROTONOSUPPORT; }
 100 #endif
 101
 102 #endif