X-Git-Url: https://rtime.felk.cvut.cz/gitweb/mf624-simulink.git/blobdiff_plain/94af05c6b1740a44b2de49c2a4796259b8109ed7..f68e0aa7d1b39a46e039a8c3b7bc8cca4ae7e86c:/mf624_SIMULINK.h diff --git a/mf624_SIMULINK.h b/mf624_SIMULINK.h index c369410..2cf3dda 100644 --- a/mf624_SIMULINK.h +++ b/mf624_SIMULINK.h @@ -43,17 +43,136 @@ #define DA7_reg 0x2E /* BAR4 */ -#define CTR0MODE 0x00 -#define CTR1MODE 0x10 -#define CTR2MODE 0x20 -#define CTR3MODE 0x30 -#define CTR4MODE 0x40 -#define CTR0 0x04 -#define CTR1 0x14 -#define CTR2 0x24 -#define CTR3 0x34 -#define CTR4 0x44 -#define CTRXCTRL 0x60 +#define CTR0STATUS_reg 0x00 +#define CTR1STATUS_reg 0x10 +#define CTR2STATUS_reg 0x20 +#define CTR3STATUS_reg 0x30 +#define CTR4STATUS_reg 0x40 + +#define CTR_STATUS_RUNNING_mask 0x00000001 +#define CTR_STATUS_OUTPUT_mask 0x00000002 + +#define CTR0MODE_reg 0x00 +#define CTR1MODE_reg 0x10 +#define CTR2MODE_reg 0x20 +#define CTR3MODE_reg 0x30 +#define CTR4MODE_reg 0x40 + +#define CTR_MODE_COUNT_DIR_mask 0x00000001 +enum {CTR_MODE_COUNT_DIR_DOWN, CTR_MODE_COUNT_DIR_UP}; +#define CTR_MODE_REPETITION_mask 0x00000002 +enum {CTR_MODE_REPETITION_DISABLED, CTR_MODE_REPETITION_ENABLED}; +#define CTR_MODE_LOAD_TOGGLE_mask 0x00000004 +enum {CTR_MODE_LOAD_TOGGLE_DISABLED /* reload from A only */, + CTR_MODE_LOAD_TOGGLE_ENABLED /* alter A and B */}; +#define CTR_MODE_OUTPUT_TOGGLE_mask 0x00000008 +enum {CTR_MODE_OUTPUT_TOGGLE_DISABLED /* output changed at terminal count */, + CTR_MODE_OUTPUT_TOGGLE_ENABLED /* output is toggled at terminal count */}; +#define CTR_MODE_OUTPUT_CONTROL_mask 0x00000030 +enum {CTR_MODE_OUTPUT_CONTROL_DIRECT /* direct output */, + CTR_MODE_OUTPUT_CONTROL_INVERTED /* inverted output */, + CTR_MODE_OUTPUT_CONTROL_FORCE_LO /* force output low */, + CTR_MODE_OUTPUT_CONTROL_FORCE_HI /* force output high */}; +#define CTR_MODE_TRIGGER_SOURCE_mask 0x000000C0 +enum {CTR_MODE_TRIGGER_SOURCE_DISABLED /* trigger disabled */, + CTR_MODE_TRIGGER_SOURCE_TXIN /* trigger by counter input (TxIN) */, + CTR_MODE_TRIGGER_SOURCE_BY_PREV /* trigger by counter n-1 output */, + CTR_MODE_TRIGGER_SOURCE_BY_NEXT /* trigger by counter n+1 output */}; +#define CTR_MODE_TRIGGER_TYPE_mask 0x00000300 +enum {CTR_MODE_TRIGGER_TYPE_DISABLED /* trigger disabled */, + CTR_MODE_TRIGGER_TYPE_BY_RE /* by rising edge of trigger signal */, + CTR_MODE_TRIGGER_TYPE_BY_FE /* by falling edge of trigger signal */, + CTR_MODE_TRIGGER_TYPE_BY_BOTH /* by either edge of trigger signal */}; +#define CTR_MODE_RETRIGGER_mask 0x00000400 +enum {CTR_MODE_RETRIGGER_DISABLED /* counter can be triggered only when stopped */, + CTR_MODE_RETRIGGER_ENABLED /* counter can be retriggered when running */}; +#define CTR_MODE_GATE_SOURCE_mask 0x00001800 +enum {CTR_MODE_GATE_SOURCE_SET_HIGH /* gate set high/not gated */, + CTR_MODE_GATE_SOURCE_BY_TXIN /* gated by counter input (TxIN) */, + CTR_MODE_GATE_SOURCE_BY_PREV /* gated by counter n-1 output */, + CTR_MODE_GATE_SOURCE_BY_NEXT /* gated by counter n+1 output */}; +#define CTR_MODE_GATE_POLARITY_mask 0x00002000 +enum {CTR_MODE_GATE_POLARITY_LOW /* low level of gate signal disables counting */, + CTR_MODE_GATE_POLARITY_HIGH /* high level of gate signal disables counting */}; +#define CTR_MODE_CLOCK_SOURCE_mask 0x0003C000 +enum {CTR_MODE_CLOCK_SOURCE_50MHZ /* 50 MHz internal clock */, + CTR_MODE_CLOCK_SOURCE_10MHZ /* 10 MHz internal clock */, + CTR_MODE_CLOCK_SOURCE_1MHZ /* 1 MHz internal clock */, + CTR_MODE_CLOCK_SOURCE_100KHZ /* 100 kHz internal clock */, + CTR_MODE_CLOCK_SOURCE_res1 /* reserved */, + CTR_MODE_CLOCK_SOURCE_TXIN_RE /* counter input (TxIN) rising edge */, + CTR_MODE_CLOCK_SOURCE_TXIN_FE /* counter input (TxIN) falling edge */, + CTR_MODE_CLOCK_SOURCE_TXIN_BOTH /* counter input (TxIN) either edge */, + CTR_MODE_CLOCK_SOURCE_res2 /* reserved */, + CTR_MODE_CLOCK_SOURCE_PREV_RE /* counter n-1 output rising edge */, + CTR_MODE_CLOCK_SOURCE_PREV_FE /* counter n-1 output falling edge */, + CTR_MODE_CLOCK_SOURCE_PREV_BOTH /* counter n-1 output either edge */, + CTR_MODE_CLOCK_SOURCE_res3 /* reserved */, + CTR_MODE_CLOCK_SOURCE_NEXT_RE /* counter n+1 output rising edge */, + CTR_MODE_CLOCK_SOURCE_NEXT_FE /* counter n+1 output falling edge */, + CTR_MODE_CLOCK_SOURCE_NEXT_BOTH /* counter n+1 output either edge */}; +#define CTR_MODE_ADTRIGSRC_mask 0x40000000 /* Implemented in CTR4MODE register only */ +enum {CTR_MODE_ADTRIGSRC_OUTPUT_FE /* ADC triggers by falling edge of counter 4 output */, + CTR_MODE_ADTRIGSRC_EXTERNAL_INPUT /* triggers by falling edge of external trigger input. */}; +#define CTR_MODE_CTR4INTSRC_mask 0x80000000 /* Implemented in CTR4MODE register only */ +enum {CTR_MODE_CTR4INTSRC_OUTPUT_FE /* interrupts by falling edge of counter 4 output */, + CTR_MODE_CTR4INTSRC_EXTERNAL_INPUT/* interrupts by falling edge of external trigger input */}; + +#define CTR0_reg 0x04 +#define CTR1_reg 0x14 +#define CTR2_reg 0x24 +#define CTR3_reg 0x34 +#define CTR4_reg 0x44 + +#define CTR0A_reg 0x04 +#define CTR1A_reg 0x14 +#define CTR2A_reg 0x24 +#define CTR3A_reg 0x34 +#define CTR4A_reg 0x44 + +#define CTR0B_reg 0x08 +#define CTR1B_reg 0x18 +#define CTR2B_reg 0x28 +#define CTR3B_reg 0x38 + +#define CTRXCTRL_reg 0x60 + +#define CTRXCTRL_CHANNEL_SHIFT 6 + +#define CTRXCTRL_CTR0START_mask 0x00000001 +#define CTRXCTRL_CTR0STOP_mask 0x00000002 +#define CTRXCTRL_CTR0LOAD_mask 0x00000004 +#define CTRXCTRL_CTR0RESET_mask 0x00000008 +#define CTRXCTRL_CTR0TSET_mask 0x00000010 +#define CTRXCTRL_CTR0TRESET_mask 0x00000020 + +#define CTRXCTRL_CTR1START_mask 0x00000040 +#define CTRXCTRL_CTR1STOP_mask 0x00000080 +#define CTRXCTRL_CTR1LOAD_mask 0x00000100 +#define CTRXCTRL_CTR1RESET_mask 0x00000200 +#define CTRXCTRL_CTR1TSET_mask 0x00000400 +#define CTRXCTRL_CTR1TRESET_mask 0x00000800 + +#define CTRXCTRL_CTR2START_mask 0x00001000 +#define CTRXCTRL_CTR2STOP_mask 0x00002000 +#define CTRXCTRL_CTR2LOAD_mask 0x00004000 +#define CTRXCTRL_CTR2RESET_mask 0x00008000 +#define CTRXCTRL_CTR2TSET_mask 0x00010000 +#define CTRXCTRL_CTR2TRESET_mask 0x00020000 + +#define CTRXCTRL_CTR3START_mask 0x00040000 +#define CTRXCTRL_CTR3STOP_mask 0x00080000 +#define CTRXCTRL_CTR3LOAD_mask 0x00100000 +#define CTRXCTRL_CTR3RESET_mask 0x00200000 +#define CTRXCTRL_CTR3TSET_mask 0x00400000 +#define CTRXCTRL_CTR3TRESET_mask 0x00800000 + +#define CTRXCTRL_CTR4START_mask 0x01000000 +#define CTRXCTRL_CTR4STOP_mask 0x02000000 +#define CTRXCTRL_CTR4LOAD_mask 0x04000000 +#define CTRXCTRL_CTR4RESET_mask 0x08000000 +#define CTRXCTRL_CTR4TSET_mask 0x10000000 +#define CTRXCTRL_CTR4TRESET_mask 0x20000000 #define IRCSTATUS_reg 0x6C #define IRCCTRL_reg 0x6C