From: Martin Date: Wed, 25 May 2011 22:32:44 +0000 (+0200) Subject: Current (FEC from 2.6.31 port, no CAN, no I2C, no PCI) X-Git-Url: https://rtime.felk.cvut.cz/gitweb/mcf548x/linux.git/commitdiff_plain/db6f0eeb987ccb6db01d0ea318700368c26be7bf Current (FEC from 2.6.31 port, no CAN, no I2C, no PCI) --- diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index bc9271b85759..529362eb7769 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -9,6 +9,14 @@ config MMU bool default y +config GENERIC_TIME + bool "Enable generic timer" + default n + +config GENERIC_CLOCKEVENTS + bool "Enable generic clockevents" + default n + config RWSEM_GENERIC_SPINLOCK bool default y @@ -46,7 +54,7 @@ config ARCH_MAY_HAVE_PC_FDC default y config NO_IOPORT - def_bool y + def_bool !(M5445X || M547X_8X) config NO_DMA def_bool SUN3 @@ -105,6 +113,35 @@ config PCMCIA To compile this driver as modules, choose M here: the modules will be called pcmcia_core and ds. +config COLDFIRE + bool "ColdFire V4e support" + default y + select CFV4E + help + Say Y if you want to build a kernel to run on one of the ColdFire + V4e boards. + +config CFV4E + bool + depends on COLDFIRE + select MMU_CFV4E if MMU + default y + +config FPU + bool "ColdFire V4e FPU support" + default n + help + This enables support for CFV4E FPU feature. + +config MCD_DMA + bool "ColdFire MCD DMA support" + depends on M547X_8X + default y + help + This enables support for the ColdFire 547x/548x family + multichannel DMA support. Many drivers need it. + If you want it, say Y + config AMIGA bool "Amiga support" select MMU_MOTOROLA if MMU @@ -276,9 +313,207 @@ config M68060 If you anticipate running this kernel on a computer with a MC68060 processor, say Y. Otherwise, say N. +config M5445X + bool "MCF5445x support" + depends on COLDFIRE + select GENERIC_TIME + select USB_EHCI_FSL + select HAVE_FSL_USB_DR + help + This option will add support for the MCF544x processor with mmu. + +config M54451 + bool + depends on M5445X + default n + +config M54455 + bool + depends on M5445X + default n + +choice + prompt "Model" + depends on M5445X + default M54451EVB + config M54451EVB + bool "M54451EVB" + select M54451 + config M54455EVB + bool "M54455EVB" + select M54455 +endchoice + +config HAVE_FSL_USB_DR + bool + default n + +config M547X_8X + bool "MCF547x/MCF548x support" + depends on COLDFIRE + help + This option will add support for the MCF547x/MCF548x processor with mmu. + +config M547X + bool + depends on M547X_8X + default n + +config M548X + bool + depends on M547X_8X + default n + +choice + prompt "Model" + depends on M547X_8X + default M5485CFE + +config M5474LITE + bool "MCF5474LITE" + select M547X + +config M5475AFE + bool "MCF5475AFE" + select M547X + +config M5475BFE + bool "MCF5475BFE" + select M547X + +config M5475CFE + bool "MCF5475CFE" + select M547X + +config M5475DFE + bool "MCF5475DFE" + select M547X + +config M5475EFE + bool "MCF5475EFE" + select M547X + +config M5475FFE + bool "MCF5475FFE" + select M547X + +config M5484LITE + bool "MCF5484LITE" + select M548X + +config M5485AFE + bool "MCF5485AFE" + select M548X + +config M5485BFE + bool "MCF5485BFE" + select M548X + +config M5485CFE + bool "MCF5485CFE" + select M548X + +config M5485DFE + bool "MCF5485DFE" + select M548X + +config M5485EFE + bool "MCF5485EFE" + select M548X + +config M5485FFE + bool "MCF5485FFE" + select M548X + +endchoice + + +config MCFCLK + int + default 240000000 if M54451EVB + default 266666666 if M54455EVB + default 266000000 if M547X + default 200000000 if M548X + help + Coldfire System clock. + +config MCF_USER_HALT + bool "Coldfire User Halt Enable" + depends on M5445X || M547X_8X + default n + help + Enables the HALT instruction in User Mode. XXX: Point of this? + config MMU_MOTOROLA bool +config MMU_CFV4E + bool + +config SDRAM_BASE + hex + depends on COLDFIRE + default 0x40000000 if M5445X + default 0x00000000 if M547X_8X + +config SDRAM_SIZE + hex + depends on COLDFIRE + default 0x08000000 if M54451EVB + default 0x10000000 if M54455EVB + default 0x04000000 if M547X_8X + +config NOR_FLASH_BASE + hex "NOR Flash Base Address" + depends on COLDFIRE + default 0x00000000 if M54451EVB + default 0x00000000 if M54455EVB + default 0xE0000000 if M5475CFE + default 0xE0000000 if M5485CFE + default 0xFF800000 if M5484LITE + default 0xFF800000 if M5474LITE + +config DMA_BASE + hex + depends on COLDFIRE + default 0xef000000 + +config DMA_SIZE + hex + depends on COLDFIRE + default 0x1000000 if M5445X + default 0x800000 if M547X_8X + +config SRAM + bool "SRAM allocation APIs support on mcfv4 platform" + depends on COLDFIRE && M5445X + default y + select GENERIC_ALLOCATOR + +config SRAM_BASE + hex + depends on COLDFIRE && SRAM + default 0x8ff00000 if M5445X + +config SRAM_SIZE + hex + depends on COLDFIRE && SRAM + default 0x8000 if M5445X + +config SRAM_ALLOC_GRANULARITY + hex + depends on SRAM + default 0x200 if M5445X + +config VDSO + bool "Support VDSO page" + depends on MMU + default n + help + This will enable support for the kernel mapping a vDSO page + in process space, and subsequently handing down the entry point + to the libc through the ELF auxiliary vector. + config MMU_SUN3 bool depends on MMU && !MMU_MOTOROLA @@ -601,6 +836,8 @@ config SERIAL_CONSOLE If you don't have a VGA card installed and you say Y here, the kernel will automatically use the first serial line, /dev/ttyS0, as system console. + + TODO: For Coldfire it's CONFIG_SERIAL_MCF_CONSOLE ... If unsure, say N. diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index b06a7e3cbcd6..05a67bca4a4e 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -16,7 +16,10 @@ KBUILD_DEFCONFIG := multi_defconfig # override top level makefile +ifndef CONFIG_COLDFIRE AS += -m68020 +endif + LDFLAGS := -m m68kelf KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds ifneq ($(SUBARCH),$(ARCH)) @@ -36,6 +39,7 @@ CHECKFLAGS += -D__mc68000__ KBUILD_CFLAGS += -pipe -fno-strength-reduce -ffixed-a2 # enable processor switch if compiled only for a single cpu +ifndef CONFIG_COLDFIRE ifndef CONFIG_M68020 ifndef CONFIG_M68030 @@ -49,6 +53,17 @@ endif endif endif +endif + +ifdef CONFIG_M5445X +KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g +KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float +endif + +ifdef CONFIG_M547X_8X +KBUILD_CFLAGS += -mcfv4e -g +KBUILD_AFLAGS += -mcfv4e +endif ifdef CONFIG_KGDB # If configured for kgdb support, include debugging infos and keep the @@ -56,10 +71,12 @@ ifdef CONFIG_KGDB KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g endif -ifndef CONFIG_SUN3 -head-y := arch/m68k/kernel/head.o -else +ifdef CONFIG_SUN3 head-y := arch/m68k/kernel/sun3-head.o +else ifdef CONFIG_COLDFIRE +head-y := arch/m68k/kernel/cf-head.o +else +head-y := arch/m68k/kernel/head.o endif core-y += arch/m68k/kernel/ arch/m68k/mm/ @@ -79,6 +96,7 @@ core-$(CONFIG_SUN3) += arch/m68k/sun3/ arch/m68k/sun3/prom/ core-$(CONFIG_M68040) += arch/m68k/fpsp040/ core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ +core-$(CONFIG_COLDFIRE) += arch/m68k/coldfire/ all: zImage diff --git a/arch/m68k/coldfire/MCD_dma.h b/arch/m68k/coldfire/MCD_dma.h new file mode 100755 index 000000000000..e3e9ac93c9d9 --- /dev/null +++ b/arch/m68k/coldfire/MCD_dma.h @@ -0,0 +1,431 @@ +/* + * drivers/dma/MCD_dma.h + * + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MCD_API_H +#define _MCD_API_H + +/* + * Turn Execution Unit tasks ON (#define) or OFF (#undef) + */ +#undef MCD_INCLUDE_EU + +/* + * Number of DMA channels + */ +#define NCHANNELS 16 + +/* + * Total number of variants + */ +#ifdef MCD_INCLUDE_EU +#define NUMOFVARIANTS 6 +#else +#define NUMOFVARIANTS 4 +#endif + +/* + * Define sizes of the various tables + */ +#define TASK_TABLE_SIZE (NCHANNELS*32) +#define VAR_TAB_SIZE (128) +#define CONTEXT_SAVE_SIZE (128) +#define FUNCDESC_TAB_SIZE (256) + +#ifdef MCD_INCLUDE_EU +#define FUNCDESC_TAB_NUM 16 +#else +#define FUNCDESC_TAB_NUM 1 +#endif + + +#ifndef DEFINESONLY + +/* + * Portability typedefs + */ +typedef int s32; +typedef unsigned int u32; +typedef short s16; +typedef unsigned short u16; +typedef char s8; +typedef unsigned char u8; + +/* + * These structures represent the internal registers of the + * multi-channel DMA + */ +struct dmaRegs_s { + u32 taskbar; /* task table base address register */ + u32 currPtr; + u32 endPtr; + u32 varTablePtr; + u16 dma_rsvd0; + u16 ptdControl; /* ptd control */ + u32 intPending; /* interrupt pending register */ + u32 intMask; /* interrupt mask register */ + u16 taskControl[16]; /* task control registers */ + u8 priority[32]; /* priority registers */ + u32 initiatorMux; /* initiator mux control */ + u32 taskSize0; /* task size control register 0. */ + u32 taskSize1; /* task size control register 1. */ + u32 dma_rsvd1; /* reserved */ + u32 dma_rsvd2; /* reserved */ + u32 debugComp1; /* debug comparator 1 */ + u32 debugComp2; /* debug comparator 2 */ + u32 debugControl; /* debug control */ + u32 debugStatus; /* debug status */ + u32 ptdDebug; /* priority task decode debug */ + u32 dma_rsvd3[31]; /* reserved */ +}; +typedef volatile struct dmaRegs_s dmaRegs; + +#endif + +/* + * PTD contrl reg bits + */ +#define PTD_CTL_TSK_PRI 0x8000 +#define PTD_CTL_COMM_PREFETCH 0x0001 + +/* + * Task Control reg bits and field masks + */ +#define TASK_CTL_EN 0x8000 +#define TASK_CTL_VALID 0x4000 +#define TASK_CTL_ALWAYS 0x2000 +#define TASK_CTL_INIT_MASK 0x1f00 +#define TASK_CTL_ASTRT 0x0080 +#define TASK_CTL_HIPRITSKEN 0x0040 +#define TASK_CTL_HLDINITNUM 0x0020 +#define TASK_CTL_ASTSKNUM_MASK 0x000f + +/* + * Priority reg bits and field masks + */ +#define PRIORITY_HLD 0x80 +#define PRIORITY_PRI_MASK 0x07 + +/* + * Debug Control reg bits and field masks + */ +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 +#define DBG_CTL_AUTO_ARM 0x00008000 +#define DBG_CTL_BREAK 0x00004000 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070 +#define DBG_CTL_EXT_BREAK 0x00000004 +#define DBG_CTL_INT_BREAK 0x00000002 + +/* + * PTD Debug reg selector addresses + * This reg must be written with a value to show the contents of + * one of the desired internal register. + */ +#define PTD_DBG_REQ 0x00 +/* shows the state of 31 initiators */ +#define PTD_DBG_TSK_VLD_INIT 0x01 +/* shows which 16 tasks are valid and + * have initiators asserted */ + + +/* + * General return values + */ +#define MCD_OK 0 +#define MCD_ERROR -1 +#define MCD_TABLE_UNALIGNED -2 +#define MCD_CHANNEL_INVALID -3 + +/* + * MCD_initDma input flags + */ +#define MCD_RELOC_TASKS 0x00000001 +#define MCD_NO_RELOC_TASKS 0x00000000 +#define MCD_COMM_PREFETCH_EN 0x00000002 +/* Commbus Prefetching - MCF547x/548x ONLY */ + +/* + * MCD_dmaStatus Status Values for each channel + */ +#define MCD_NO_DMA 1 +/* No DMA has been requested since reset */ +#define MCD_IDLE 2 +/* DMA active, but the initiator is currently inactive */ +#define MCD_RUNNING 3 +/* DMA active, and the initiator is currently active */ +#define MCD_PAUSED 4 +/* DMA active but it is currently paused */ +#define MCD_HALTED 5 +/* the most recent DMA has been killed with MCD_killTask() */ +#define MCD_DONE 6 +/* the most recent DMA has completed. */ + + +/* + * MCD_startDma parameter defines + */ + +/* + * Constants for the funcDesc parameter + */ +/* Byte swapping: */ +#define MCD_NO_BYTE_SWAP 0x00045670 +/* to disable byte swapping. */ +#define MCD_BYTE_REVERSE 0x00076540 +/* to reverse the bytes of each u32 of the DMAed data. */ +#define MCD_U16_REVERSE 0x00067450 +/* to reverse the 16-bit halves of + * each 32-bit data value being DMAed.*/ +#define MCD_U16_BYTE_REVERSE 0x00054760 +/* to reverse the byte halves of each + * 16-bit half of each 32-bit data value DMAed */ +#define MCD_NO_BIT_REV 0x00000000 +/* do not reverse the bits of each byte DMAed. */ +#define MCD_BIT_REV 0x00088880 +/* reverse the bits of each byte DMAed */ +/* CRCing: */ +#define MCD_CRC16 0xc0100000 +/* to perform CRC-16 on DMAed data. */ +#define MCD_CRCCCITT 0xc0200000 +/* to perform CRC-CCITT on DMAed data. */ +#define MCD_CRC32 0xc0300000 +/* to perform CRC-32 on DMAed data. */ +#define MCD_CSUMINET 0xc0400000 +/* to perform internet checksums on DMAed data.*/ +#define MCD_NO_CSUM 0xa0000000 +/* to perform no checksumming. */ + +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) + +/* + * Constants for the flags parameter + */ +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ +#define MCD_TT_FLAGS_SP 0x00000004 +/* Speculative prefetch(XLB) MCF547x/548x ONLY */ +#define MCD_TT_FLAGS_PI 0x00000040 /* Precise Increment */ +#define MCD_TT_FLAGS_MASK 0x000000ff +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) + +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ +#define MCD_CHAIN_DMA /* TBD */ +#define MCD_EU_DMA /* TBD */ +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ + + +/* these flags are valid for MCD_startDma + * and the chained buffer descriptors */ +#define MCD_BUF_READY 0x80000000 +/* indicates that this buffer is now + * under the DMA's control */ +#define MCD_WRAP 0x20000000 +/* to tell the FEC Dmas to wrap to the first BD */ +#define MCD_INTERRUPT 0x10000000 +/* to generate an interrupt after completion of the DMA. */ +#define MCD_END_FRAME 0x08000000 +/* tell the DMA to end the frame when transferring + * last byte of data in buffer */ +#define MCD_CRC_RESTART 0x40000000 +/* to empty out the accumulated checksum + prior to performing the DMA. */ + +/* Defines for the FEC buffer descriptor control/status word*/ +#define MCD_FEC_BUF_READY 0x8000 +#define MCD_FEC_WRAP 0x2000 +#define MCD_FEC_INTERRUPT 0x1000 +#define MCD_FEC_END_FRAME 0x0800 + + +/* + * Defines for general intuitiveness + */ + +#define MCD_TRUE 1 +#define MCD_FALSE 0 + +/* + * Three different cases for destination and source. + */ +#define MINUS1 -1 +#define ZERO 0 +#define PLUS1 1 + +#ifndef DEFINESONLY + +/* Task Table Entry struct*/ +typedef struct { + u32 TDTstart; /* task descriptor table start */ + u32 TDTend; /* task descriptor table end */ + u32 varTab; /* variable table start */ + u32 FDTandFlags; /* function descriptor table start and flags */ + volatile u32 descAddrAndStatus; + volatile u32 modifiedVarTab; + u32 contextSaveSpace; /* context save space start */ + u32 literalBases; +} TaskTableEntry; + + +/* Chained buffer descriptor */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + u32 flags; +/* flags describing the DMA */ + u32 csumResult; +/* checksum from checksumming performed since last checksum reset */ + s8 *srcAddr; +/* the address to move data from */ + s8 *destAddr; +/* the address to move data to */ + s8 *lastDestAddr; +/* the last address written to */ + u32 dmaSize; +/* the number of bytes to transfer independent of the transfer size */ + MCD_bufDesc *next; +/* next buffer descriptor in chain */ + u32 info; +/* private information about this descriptor; DMA does not affect it */ +}; + +/* Progress Query struct */ +typedef volatile struct MCD_XferProg_struct { + s8 *lastSrcAddr; +/* the most-recent or last, post-increment source address */ + s8 *lastDestAddr; +/* the most-recent or last, post-increment destination address */ + u32 dmaSize; +/* the amount of data transferred for the current buffer */ + MCD_bufDesc *currBufDesc; +/* pointer to the current buffer descriptor being DMAed */ +} MCD_XferProg; + + +/* FEC buffer descriptor */ +typedef volatile struct MCD_bufDescFec_struct { + u16 statCtrl; + u16 length; + u32 dataPointer; +} MCD_bufDescFec; + + +/*************************************************************************/ +/* + * API function Prototypes - see MCD_dmaApi.c for further notes + */ + +/* + * MCD_startDma starts a particular kind of DMA . + */ +int MCD_startDma( + int channel, +/* the channel on which to run the DMA */ + s8 *srcAddr, +/* the address to move data from, or buffer-descriptor address */ + s16 srcIncr, +/* the amount to increment the source address per transfer */ + s8 *destAddr, +/* the address to move data to */ + s16 destIncr, +/* the amount to increment the destination address per transfer */ + u32 dmaSize, +/* the number of bytes to transfer independent of the transfer size */ + u32 xferSize, +/* the number bytes in of each data movement (1, 2, or 4) */ + u32 initiator, +/* what device initiates the DMA */ + int priority, +/* priority of the DMA */ + u32 flags, +/* flags describing the DMA */ + u32 funcDesc +/* a description of byte swapping, bit swapping, and CRC actions */ +); + +/* + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA + * registers, relocating and creating the appropriate task structures, and + * setting up some global settings + */ +int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); + +/* + * MCD_dmaStatus() returns the status of the DMA on the requested channel. + */ +int MCD_dmaStatus(int channel); + +/* + * MCD_XferProgrQuery() returns progress of DMA on requested channel + */ +int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep); + +/* + * MCD_killDma() halts the DMA on the requested channel, without any + * intention of resuming the DMA. + */ +int MCD_killDma(int channel); + +/* + * MCD_continDma() continues a DMA which as stopped due to encountering an + * unready buffer descriptor. + */ +int MCD_continDma(int channel); + +/* + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is + * running on that channel). + */ +int MCD_pauseDma(int channel); + +/* + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is + * running on that channel). + */ +int MCD_resumeDma(int channel); + +/* + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA + */ +int MCD_csumQuery(int channel, u32 *csum); + +/* + * MCD_getCodeSize provides the packed size required by the microcoded task + * and structures. + */ +int MCD_getCodeSize(void); + +/* + * MCD_getVersion provides a pointer to a version string and returns a + * version number. + */ +int MCD_getVersion(char **longVersion); + +/* macro for setting a location in the variable table */ +#define MCD_SET_VAR(taskTab, idx, value) \ + ((u32 *)(taskTab)->varTab)[idx] = value + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, + so I'm avoiding surrounding it with "do {} while(0)" */ + +#endif /* DEFINESONLY */ + +#endif /* _MCD_API_H */ diff --git a/arch/m68k/coldfire/MCD_dmaApi.c b/arch/m68k/coldfire/MCD_dmaApi.c new file mode 100755 index 000000000000..9609d0c6dc58 --- /dev/null +++ b/arch/m68k/coldfire/MCD_dmaApi.c @@ -0,0 +1,1045 @@ +/* + * drivers/dma/MCD_dmaApi.c + * + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "MCD_dma.h" +#include "MCD_tasksInit.h" +#include "MCD_progCheck.h" + +/********************************************************************/ +/* + * This is an API-internal pointer to the DMA's registers + */ +dmaRegs *MCD_dmaBar; + +/* + * These are the real and model task tables as generated by the + * build process + */ +extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; +extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; + +/* + * However, this (usually) gets relocated to on-chip SRAM, at which + * point we access them as these tables + */ +volatile TaskTableEntry *MCD_taskTable; +TaskTableEntry *MCD_modelTaskTable; + + +/* + * MCD_chStatus[] is an array of status indicators for remembering + * whether a DMA has ever been attempted on each channel, pausing + * status, etc. + */ +static int MCD_chStatus[NCHANNELS] = +{ + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA +}; + +/* + * Prototypes for local functions + */ +static void MCD_memcpy(int *dest, int *src, u32 size); +static void MCD_resmActions(int channel); + +/* + * Buffer descriptors used for storage of progress info for single Dmas + * Also used as storage for the DMA for CRCs for single DMAs + * Otherwise, the DMA does not parse these buffer descriptors + */ +#ifdef MCD_INCLUDE_EU +extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +#else +MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +#endif +MCD_bufDesc *MCD_relocBuffDesc; + + +/* + * Defines for the debug control register's functions + */ +#define DBG_CTL_COMP1_TASK (0x00002000) +/* have comparator 1 look for a task # */ +#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ + DBG_CTL_BREAK | \ + DBG_CTL_INT_BREAK | \ + DBG_CTL_COMP1_TASK) +#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ + DBG_CTL_INT_BREAK | \ + DBG_CTL_COMP1_TASK) +#define DBG_KILL_ALL_STAT (0xFFFFFFFF) + +/* + * Offset to context save area where progress info is stored + */ +#define CSAVE_OFFSET 10 + +/* + * Defines for Byte Swapping + */ +#define MCD_BYTE_SWAP_KILLER 0xFFF8888F +#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 + +/* + * Execution Unit Identifiers + */ +#define MAC 0 /* legacy - not used */ +#define LUAC 1 /* legacy - not used */ +#define CRC 2 /* legacy - not used */ +#define LURC 3 /* Logic Unit with CRC */ + +/* + * Task Identifiers + */ +#define TASK_CHAINNOEU 0 +#define TASK_SINGLENOEU 1 +#ifdef MCD_INCLUDE_EU +#define TASK_CHAINEU 2 +#define TASK_SINGLEEU 3 +#define TASK_FECRX 4 +#define TASK_FECTX 5 +#else +#define TASK_CHAINEU 0 +#define TASK_SINGLEEU 1 +#define TASK_FECRX 2 +#define TASK_FECTX 3 +#endif + +/* + * Structure to remember which variant is on which channel + */ +typedef struct MCD_remVariants_struct MCD_remVariant; +struct MCD_remVariants_struct { + int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ + int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ + s16 remDestIncr[NCHANNELS]; /* DestIncr */ + s16 remSrcIncr[NCHANNELS]; /* srcIncr */ + u32 remXferSize[NCHANNELS]; /* xferSize */ +}; + +/* + * Structure to remember the startDma parameters for each channel + */ +MCD_remVariant MCD_remVariants; + +/********************************************************************/ +/* + * Function: MCD_initDma + * Purpose: Initializes the DMA API by setting up a pointer to the DMA + * registers, relocating and creating the appropriate task + * structures, and setting up some global settings + * Arguments: + * dmaBarAddr - pointer to the multichannel DMA registers + * taskTableDest - location to move DMA task code and structs to + * flags - operational parameters + * Return Value: + * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned + * MCD_OK otherwise + */ +extern u32 MCD_funcDescTab0[]; + +int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) +{ + int i; + TaskTableEntry *entryPtr; + + /* Setup the local pointer to register set */ + MCD_dmaBar = dmaBarAddr; + + /* Do we need to move/create a task table */ + if ((flags & MCD_RELOC_TASKS) != 0) { + int fixedSize; + u32 *fixedPtr; + int varTabsOffset, funcDescTabsOffset; + int contextSavesOffset; + int taskDescTabsOffset; + int taskTableSize, varTabsSize; + int funcDescTabsSize, contextSavesSize; + int taskDescTabSize; + int i; + + /* Check if physical address is + * aligned on 512 byte boundary */ + if (((u32)taskTableDest & 0x000001ff) != 0) + return MCD_TABLE_UNALIGNED; + + MCD_taskTable = taskTableDest; + /* set up local pointer to task Table */ + + /* + * Create a task table: + * compute aligned base offsets for variable tables and + * function descriptor tables, then + * loop through the task table and setup the pointers + *copy over model task table with the the actual + *task descriptor tables + */ + taskTableSize = NCHANNELS * sizeof(TaskTableEntry); + /* Align variable tables to size */ + varTabsOffset = taskTableSize + (u32)taskTableDest; + if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) + varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) + & (~VAR_TAB_SIZE); + /* Align function descriptor tables */ + varTabsSize = NCHANNELS * VAR_TAB_SIZE; + funcDescTabsOffset = varTabsOffset + varTabsSize; + + if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) + funcDescTabsOffset = (funcDescTabsOffset + + FUNCDESC_TAB_SIZE) & + (~FUNCDESC_TAB_SIZE); + + funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; + contextSavesOffset = funcDescTabsOffset + + funcDescTabsSize; + contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); + fixedSize = taskTableSize + varTabsSize + + funcDescTabsSize + contextSavesSize; + + /* Zero the thing out */ + fixedPtr = (u32 *)taskTableDest; + for (i = 0; i < (fixedSize/4); i++) + fixedPtr[i] = 0; + + entryPtr = (TaskTableEntry *)MCD_taskTable; + /* Set up fixed pointers */ + for (i = 0; i < NCHANNELS; i++) { + entryPtr[i].varTab = (u32)varTabsOffset; + /* update ptr to local value */ + entryPtr[i].FDTandFlags = + (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF; + entryPtr[i].contextSaveSpace = + (u32)contextSavesOffset; + varTabsOffset += VAR_TAB_SIZE; +#ifdef MCD_INCLUDE_EU + /* if not there is only one, + * just point to the same one */ + funcDescTabsOffset += FUNCDESC_TAB_SIZE; +#endif + contextSavesOffset += CONTEXT_SAVE_SIZE; + } + /* Copy over the function descriptor table */ + for (i = 0; i < FUNCDESC_TAB_NUM; i++) { + MCD_memcpy((void *)(entryPtr[i].FDTandFlags + & ~MCD_TT_FLAGS_MASK), + (void *)MCD_funcDescTab0, + FUNCDESC_TAB_SIZE); + } + + /* Copy model task table to where the + * context save stuff leaves off */ + MCD_modelTaskTable = + (TaskTableEntry *)contextSavesOffset; + + MCD_memcpy((void *)MCD_modelTaskTable, + (void *)MCD_modelTaskTableSrc, + NUMOFVARIANTS * sizeof(TaskTableEntry)); + + /* Point to local version of model task table */ + entryPtr = MCD_modelTaskTable; + taskDescTabsOffset = (u32)MCD_modelTaskTable + + (NUMOFVARIANTS * sizeof(TaskTableEntry)); + + /* Copy actual task code and update TDT ptrs + * in local model task table */ + for (i = 0; i < NUMOFVARIANTS; i++) { + taskDescTabSize = entryPtr[i].TDTend + - entryPtr[i].TDTstart + 4; + MCD_memcpy((void *)taskDescTabsOffset, + (void *)entryPtr[i].TDTstart, + taskDescTabSize); + entryPtr[i].TDTstart = + (u32)taskDescTabsOffset; + taskDescTabsOffset += taskDescTabSize; + entryPtr[i].TDTend = + (u32)taskDescTabsOffset - 4; + } +#ifdef MCD_INCLUDE_EU + /* + * Tack single DMA BDs onto end of + * code so API controls where + * they are since DMA might write to them + */ + MCD_relocBuffDesc = (MCD_bufDesc *) + (entryPtr[NUMOFVARIANTS - 1].TDTend + 4); +#else + /* + * DMA does not touch them so they + * can be wherever and we don't need to + * waste SRAM on them + */ + MCD_relocBuffDesc = MCD_singleBufDescs; +#endif + } else { + /* + * Point the would-be relocated task tables and + * the buffer descriptors + * to the ones the linker generated + */ + if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0) + return MCD_TABLE_UNALIGNED; + + entryPtr = MCD_realTaskTableSrc; + for (i = 0; i < NCHANNELS; i++) { + if (((entryPtr[i].varTab + & (VAR_TAB_SIZE - 1)) != 0) || + ((entryPtr[i].FDTandFlags & + (FUNCDESC_TAB_SIZE - 1)) != 0)) + return MCD_TABLE_UNALIGNED; + } + + MCD_taskTable = MCD_realTaskTableSrc; + MCD_modelTaskTable = MCD_modelTaskTableSrc; + MCD_relocBuffDesc = MCD_singleBufDescs; + } + + /* Make all channels inactive, + * and remember them as such: */ + MCD_dmaBar->taskbar = (u32) MCD_taskTable; + for (i = 0; i < NCHANNELS; i++) { + MCD_dmaBar->taskControl[i] = 0x0; + MCD_chStatus[i] = MCD_NO_DMA; + } + + /* Set up pausing mechanism to inactive state: */ + MCD_dmaBar->debugComp1 = 0; + MCD_dmaBar->debugComp2 = 0; + MCD_dmaBar->debugControl = DBG_CTL_DISABLE; + MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; + + /* Enable or disable commbus prefetch */ + if ((flags & MCD_COMM_PREFETCH_EN) != 0) + MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; + else + MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; + + return MCD_OK; +} +/*********************** End of MCD_initDma() ***********************/ + +/********************************************************************/ +/* Function: MCD_dmaStatus + * Purpose: Returns the status of the DMA on the requested channel + * Arguments: channel - channel number + * Returns: Predefined status indicators + */ +int MCD_dmaStatus(int channel) +{ + u16 tcrValue; + + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + tcrValue = MCD_dmaBar->taskControl[channel]; + if ((tcrValue & TASK_CTL_EN) == 0) { + /* Nothing running if last reported + * with task enabled */ + if (MCD_chStatus[channel] == MCD_RUNNING + || MCD_chStatus[channel] == MCD_IDLE) + MCD_chStatus[channel] = MCD_DONE; + } else /* something is running */{ + /* There are three possibilities: + * paused, running or idle. */ + if (MCD_chStatus[channel] == MCD_RUNNING + || MCD_chStatus[channel] == MCD_IDLE) { + MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; + /* Determine which initiator + * is asserted. */ + if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) + MCD_chStatus[channel] = MCD_RUNNING; + else + MCD_chStatus[channel] = MCD_IDLE; + /* Do not change the status if it is already paused */ + } + } + return MCD_chStatus[channel]; +} +/******************** End of MCD_dmaStatus() ************************/ + +/********************************************************************/ +/* Function: MCD_startDma + * Ppurpose: Starts a particular kind of DMA + * Arguments: see below + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + */ + +int MCD_startDma( + int channel, +/* the channel on which to run the DMA */ + s8 *srcAddr, +/* the address to move data from, + * or physical buffer-descriptor address */ + s16 srcIncr, +/* the amount to increment the source + * address per transfer */ + s8 *destAddr, +/* the address to move data to */ + s16 destIncr, +/* the amount to increment the + * destination address per transfer */ + u32 dmaSize, +/* the number of bytes to transfer + * independent of the transfer size */ + u32 xferSize, +/* the number bytes in of each data + * movement (1, 2, or 4) */ + u32 initiator, +/* what device initiates the DMA */ + int priority, +/* priority of the DMA */ + u32 flags, +/* flags describing the DMA */ + u32 funcDesc +/* a description of byte swapping, + * bit swapping, and CRC actions */ +#ifdef MCD_NEED_ADDR_TRANS + s8 *srcAddrVirt +/* virtual buffer descriptor address TBD*/ +#endif +) +{ + int srcRsdIncr, destRsdIncr; + int *cSave; + short xferSizeIncr; + int tcrCount = 0; +#ifdef MCD_INCLUDE_EU + u32 *realFuncArray; +#endif + + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + +#ifndef MCD_INCLUDE_EU + funcDesc = MCD_FUNC_NOEU1; +#endif + +#ifdef MCD_DEBUG + printf("startDma:Setting up params\n"); +#endif + + /* Enable task-wise priority */ + MCD_dmaBar->ptdControl |= (u16) 0x8000; + + /* Calculate additional parameters + * to the regular DMA calls. */ + srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); + destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); + xferSizeIncr = (xferSize & 0xffff) | 0x20000000; + + /* Remember which variant is running for each channel */ + MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; + MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; + MCD_remVariants.remDestIncr[channel] = destIncr; + MCD_remVariants.remSrcIncr[channel] = srcIncr; + MCD_remVariants.remXferSize[channel] = xferSize; + + cSave = (int *)(MCD_taskTable[channel].contextSaveSpace) + + CSAVE_OFFSET + + CURRBD; + +#ifdef MCD_INCLUDE_EU + realFuncArray = (u32 *)(MCD_taskTable[channel].FDTandFlags + & 0xffffff00); + + /* + * Modify the LURC's normal and byte-residue-loop functions + * according to parameter. + */ + switch (xferSize) { + case 4: + realFuncArray[(LURC*16)] = funcDesc; + break; + case 2: + realFuncArray[(LURC*16)] = funcDesc & 0xfffff00f; + break; + case 1: + default: + realFuncArray[(LURC*16)] = funcDesc & 0xffff000f; + break; + } + + realFuncArray[(LURC*16 + 1)] = 0 + | (funcDesc & MCD_BYTE_SWAP_KILLER) + | MCD_NO_BYTE_SWAP_ATALL; +#endif + + /* Write the initiator field in the TCR and + * set the initiator-hold bit*/ + MCD_dmaBar->taskControl[channel] = 0 + | (initiator << 8) + | TASK_CTL_HIPRITSKEN + | TASK_CTL_HLDINITNUM; + + /* + * Current versions of the MPC8220 MCD have a hardware quirk that could + * cause the write to the TCR to collide with an MDE access to the + * initiator-register file, so we have to verify that the write occurred + * correctly by reading back the value. On MCF547x/8x devices and any + * future revisions of the MPC8220, this loop will not be entered. + */ + while (((MCD_dmaBar->taskControl[channel] & 0x1fff) != + ((initiator << 8) | TASK_CTL_HIPRITSKEN + | TASK_CTL_HLDINITNUM)) && (tcrCount < 1000)) { + tcrCount++; + MCD_dmaBar->taskControl[channel] = 0 + | (initiator << 8) + | TASK_CTL_HIPRITSKEN + | TASK_CTL_HLDINITNUM; + } + + MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK; + + if (channel < 8 && channel >= 0) { + MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4); + MCD_dmaBar->taskSize0 + |= (xferSize & 3) << (((7 - channel)*4) + 2); + MCD_dmaBar->taskSize0 + |= (xferSize & 3) << ((7 - channel)*4); + } else { + MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4); + MCD_dmaBar->taskSize1 + |= (xferSize & 3) << (((15 - channel)*4) + 2); + MCD_dmaBar->taskSize1 + |= (xferSize & 3) << ((15 - channel)*4); + } + + /* Setup task table flags/options */ + MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; + MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); + + if (flags & MCD_FECTX_DMA) { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_FECTX].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_FECTX].TDTend; + MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, + MCD_taskTable, channel); + } else if (flags & MCD_FECRX_DMA) { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_FECRX].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_FECRX].TDTend; + MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, + MCD_taskTable, channel); + } else if (flags & MCD_SINGLE_DMA) { + /* + * This buffer descriptor is used for storing off + * initial parameters for later progress query + * calculation and for the DMA to write the resulting + * checksum. The DMA does not use this to determine how + * to operate, that info is passed with the init routine + */ + MCD_relocBuffDesc[channel].srcAddr = srcAddr; + MCD_relocBuffDesc[channel].destAddr = destAddr; + MCD_relocBuffDesc[channel].lastDestAddr = destAddr; + MCD_relocBuffDesc[channel].dmaSize = dmaSize; + MCD_relocBuffDesc[channel].flags = 0; + /* not used */ + MCD_relocBuffDesc[channel].csumResult = 0; + /* not used */ + MCD_relocBuffDesc[channel].next = 0; + /* not used */ + + /* Initialize the progress-querying stuff + * to show no progress:*/ + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + SRCPTR + CSAVE_OFFSET] = (int)srcAddr; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DESTPTR + CSAVE_OFFSET] = (int)destAddr; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DCOUNT + CSAVE_OFFSET] = 0; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + CURRBD + CSAVE_OFFSET] = + (u32) &(MCD_relocBuffDesc[channel]); + + if ((funcDesc == MCD_FUNC_NOEU1) + || (funcDesc == MCD_FUNC_NOEU2)) { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; + MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, + destIncr, dmaSize, xferSizeIncr, flags, + (int *)&(MCD_relocBuffDesc[channel]), + cSave, MCD_taskTable, channel); + } else { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_SINGLEEU].TDTend; + MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, + destIncr, dmaSize, xferSizeIncr, flags, + (int *)&(MCD_relocBuffDesc[channel]), + cSave, MCD_taskTable, channel); + } + } else /* Chained DMA */ { + /* Initialize the progress-querying + * stuff to show no progress:*/ +#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */ + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + SRCPTR + CSAVE_OFFSET] + = (int)((MCD_bufDesc *) srcAddr)->srcAddr; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DESTPTR + CSAVE_OFFSET] + = (int)((MCD_bufDesc *) srcAddr)->destAddr; +#else + /* if using address translation, need the + * virtual addr of the first buffdesc */ + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + SRCPTR + CSAVE_OFFSET] + = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DESTPTR + CSAVE_OFFSET] + = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr; +#endif + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DCOUNT + CSAVE_OFFSET] = 0; + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + CURRBD + CSAVE_OFFSET] = (u32) srcAddr; + + if (funcDesc == MCD_FUNC_NOEU1 + || funcDesc == MCD_FUNC_NOEU2) { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; + MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, + destIncr, xferSize, xferSizeIncr, cSave, + MCD_taskTable, channel); + } else { + /* TDTStart and TDTEnd */ + MCD_taskTable[channel].TDTstart = + MCD_modelTaskTable[TASK_CHAINEU].TDTstart; + MCD_taskTable[channel].TDTend = + MCD_modelTaskTable[TASK_CHAINEU].TDTend; + MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, + xferSize, xferSizeIncr, cSave, + MCD_taskTable, channel); + } + } + + MCD_chStatus[channel] = MCD_IDLE; + return MCD_OK; +} + +/************************ End of MCD_startDma() *********************/ + +/********************************************************************/ +/* Function: MCD_XferProgrQuery + * Purpose: Returns progress of DMA on requested channel + * Arguments: channel - channel to retrieve progress for + * progRep - pointer to user supplied MCD_XferProg struct + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + * + * Notes: + * MCD_XferProgrQuery() upon completing or after aborting a DMA, or + * while the DMA is in progress, this function returns the first + * DMA-destination address not (or not yet) used in the DMA. When + * encountering a non-ready buffer descriptor, the information for + * the last completed descriptor is returned. + * + * MCD_XferProgQuery() has to avoid the possibility of getting + * partially-updated information in the event that we should happen + * to query DMA progress just as the DMA is updating it. It does that + * by taking advantage of the fact context is not saved frequently for + * the most part. We therefore read it at least twice until we get the + * same information twice in a row. + * + * Because a small, but not insignificant, amount of time is required + * to write out the progress-query information, especially upon + * completion of the DMA, it would be wise to guarantee some time lag + * between successive readings of the progress-query information. + */ + +/* + * How many iterations of the loop below to execute to stabilize values + */ +#define STABTIME 0 + +int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep) +{ + MCD_XferProg prevRep; + int again; + /* true if we are to try again to get consistent results */ + int i; /* used as a time-waste counter */ + int destDiffBytes; + /* Total number of bytes that we think actually got xfered. */ + int numIterations; /* number of iterations */ + int bytesNotXfered; /* bytes that did not get xfered. */ + s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; + int subModVal, addModVal; + /* Mode values to added and subtracted from the final destAddr */ + + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + /* Read a trial value for the progress-reporting values*/ + prevRep.lastSrcAddr = + (s8 *)((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + SRCPTR + CSAVE_OFFSET]; + prevRep.lastDestAddr = + (s8 *)((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DESTPTR + CSAVE_OFFSET]; + prevRep.dmaSize = + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[ + DCOUNT + CSAVE_OFFSET]; + prevRep.currBufDesc = + (MCD_bufDesc *)((volatile int *)MCD_taskTable[ + channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; + + /* Repeatedly reread those values until + * they match previous values: */ + do { + /* Take a little bit of time to ensure stability: */ + for (i = 0; i < STABTIME; i++) + i += i >> 2; + /* make sure this loop does something so that it + doesn't get optimized out */ + /* Check them again: */ + progRep->lastSrcAddr = + (s8 *)((volatile int *)MCD_taskTable[ + channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; + progRep->lastDestAddr = + (s8 *)((volatile int *)MCD_taskTable[ + channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; + progRep->dmaSize = ((volatile int *)MCD_taskTable[ + channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; + progRep->currBufDesc = + (MCD_bufDesc *)((volatile int *)MCD_taskTable[ + channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; + + /* See if they match: */ + if (prevRep.lastSrcAddr != progRep->lastSrcAddr + || prevRep.lastDestAddr != progRep->lastDestAddr + || prevRep.dmaSize != progRep->dmaSize + || prevRep.currBufDesc != progRep->currBufDesc) { + /* If they don't match, remember previous + values and try again:*/ + prevRep.lastSrcAddr = progRep->lastSrcAddr; + prevRep.lastDestAddr = progRep->lastDestAddr; + prevRep.dmaSize = progRep->dmaSize; + prevRep.currBufDesc = progRep->currBufDesc; + again = MCD_TRUE; + } else + again = MCD_FALSE; + } while (again == MCD_TRUE); + + + /* Update dmaSize and lastDestAddr */ + switch (MCD_remVariants.remDestRsdIncr[channel]) { + case MINUS1: + subModVal = ((int)progRep->lastDestAddr) + & ((MCD_remVariants.remXferSize[channel]) - 1); + addModVal = ((int)progRep->currBufDesc->destAddr) + & ((MCD_remVariants.remXferSize[channel]) - 1); + LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) + - addModVal; + LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; + destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; + bytesNotXfered = + (destDiffBytes/MCD_remVariants.remDestIncr[channel]) * + (MCD_remVariants.remDestIncr[channel] + + MCD_remVariants.remXferSize[channel]); + progRep->dmaSize = destDiffBytes - bytesNotXfered + + addModVal - subModVal; + break; + case ZERO: + progRep->lastDestAddr = progRep->currBufDesc->destAddr; + break; + case PLUS1: + /* This value has to be subtracted + from the final calculated dmaSize. */ + subModVal = ((int)progRep->currBufDesc->destAddr) + & ((MCD_remVariants.remXferSize[channel]) - 1); + /* These bytes are already in lastDestAddr. */ + addModVal = ((int)progRep->lastDestAddr) + & ((MCD_remVariants.remXferSize[channel]) - 1); + LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) + - subModVal; + LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; + destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); + numIterations = (LWAlignedCurrDestAddr - + LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel]; + bytesNotXfered = numIterations * + (MCD_remVariants.remDestIncr[channel] + - MCD_remVariants.remXferSize[channel]); + progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; + break; + default: + break; + } + + /* This covers M1,P1,Z for source */ + switch (MCD_remVariants.remSrcRsdIncr[channel]) { + case MINUS1: + progRep->lastSrcAddr = + progRep->currBufDesc->srcAddr + + (MCD_remVariants.remSrcIncr[channel] * + (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); + break; + case ZERO: + progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; + break; + case PLUS1: + progRep->lastSrcAddr = + progRep->currBufDesc->srcAddr + + (MCD_remVariants.remSrcIncr[channel] * + (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); + break; + default: + break; + } + + return MCD_OK; +} +/******************* End of MCD_XferProgrQuery() ********************/ + +/********************************************************************/ +/* MCD_resmActions() does the majority of the actions of a DMA resume. + * It is called from MCD_killDma() and MCD_resumeDma(). It has to be + * a separate function because the kill function has to negate the task + * enable before resuming it, but the resume function has to do nothing + * if there is no DMA on that channel (i.e., if the enable bit is 0). + */ +static void MCD_resmActions(int channel) +{ + MCD_dmaBar->debugControl = DBG_CTL_DISABLE; + MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; + + /* Determine which initiators are asserted */ + MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; + + if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) + MCD_chStatus[channel] = MCD_RUNNING; + else + MCD_chStatus[channel] = MCD_IDLE; +} +/********************* End of MCD_resmActions() *********************/ + +/********************************************************************/ +/* Function: MCD_killDma + * Purpose: Halt the DMA on the requested channel, without any + * intention of resuming the DMA. + * Arguments: channel - requested channel + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + * + * Notes: + * A DMA may be killed from any state, including paused state, and it + * always goes to the MCD_HALTED state even if it is killed while in + * the MCD_NO_DMA or MCD_IDLE states. + */ +int MCD_killDma(int channel) +{ + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + MCD_dmaBar->taskControl[channel] = 0x0; + + /* Clean up after a paused task */ + if (MCD_chStatus[channel] == MCD_PAUSED) { + MCD_dmaBar->debugControl = DBG_CTL_DISABLE; + MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; + } + + MCD_chStatus[channel] = MCD_HALTED; + + return MCD_OK; +} +/************************ End of MCD_killDma() **********************/ + +/********************************************************************/ +/* Function: MCD_continDma + * Purpose: Continue a DMA which as stopped due to encountering an + * unready buffer descriptor. + * Arguments: channel - channel to continue the DMA on + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + * + * Notes: + * This routine does not check to see if there is a task which can + * be continued. Also this routine should not be used with single DMAs. + */ +int MCD_continDma(int channel) +{ + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; + MCD_chStatus[channel] = MCD_RUNNING; + + return MCD_OK; +} +/********************** End of MCD_continDma() **********************/ + +/********************************************************************* + * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit + * to freeze a task and resume it. We freeze a task by breakpointing + * on the stated task. That is, not any specific place in the task, + * but any time that task executes. In particular, when that task + * executes, we want to freeze that task and only that task. + * + * The bits of the debug control register influence interrupts vs. + * breakpoints as follows: + * - Bits 14 and 0 enable or disable debug functions. If enabled, you + * will get the interrupt but you may or may not get a breakpoint. + * - Bits 2 and 1 decide whether you also get a breakpoint in addition + * to an interrupt. + * + * The debug unit can do these actions in response to either internally + * detected breakpoint conditions from the comparators, or in response + * to the external breakpoint pin, or both. + * - Bits 14 and 1 perform the above-described functions for + * internally-generated conditions, i.e., the debug comparators. + * - Bits 0 and 2 perform the above-described functions for external + * conditions, i.e., the breakpoint external pin. + * + * Note that, although you "always" get the interrupt when you turn + * the debug functions, the interrupt can nevertheless, if desired, be + * masked by the corresponding bit in the PTD's IMR. Note also that + * this means that bits 14 and 0 must enable debug functions before + * bits 1 and 2, respectively, have any effect. + * + * NOTE: It's extremely important to not pause more than one DMA channel + * at a time. + ********************************************************************/ + +/********************************************************************/ +/* Function: MCD_pauseDma + * Purpose: Pauses the DMA on a given channel (if any DMA is running + * on that channel). + * Arguments: channel + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + */ +int MCD_pauseDma(int channel) +{ + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) { + MCD_dmaBar->debugComp1 = channel; + MCD_dmaBar->debugControl = + DBG_CTL_ENABLE | (1 << (channel + 16)); + MCD_chStatus[channel] = MCD_PAUSED; + } + + return MCD_OK; +} +/************************* End of MCD_pauseDma() ********************/ + +/********************************************************************/ +/* Function: MCD_resumeDma + * Purpose: Resumes the DMA on a given channel (if any DMA is + * running on that channel). + * Arguments: channel - channel on which to resume DMA + * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK + */ +int MCD_resumeDma(int channel) +{ + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) + MCD_resmActions(channel); + + return MCD_OK; +} +/************************ End of MCD_resumeDma() ********************/ + +/********************************************************************/ +/* Function: MCD_csumQuery + * Purpose: Provide the checksum after performing a non-chained DMA + * Arguments: channel - channel to report on + * csum - pointer to where to write the checksum/CRC + * Returns: MCD_ERROR if the channel is invalid, else MCD_OK + * + * Notes: + * + */ +int MCD_csumQuery(int channel, u32 *csum) +{ +#ifdef MCD_INCLUDE_EU + if ((channel < 0) || (channel >= NCHANNELS)) + return MCD_CHANNEL_INVALID; + + *csum = MCD_relocBuffDesc[channel].csumResult; + return MCD_OK; +#else + return MCD_ERROR; +#endif +} +/*********************** End of MCD_resumeDma() *********************/ + +/********************************************************************/ +/* Function: MCD_getCodeSize + * Purpose: Provide the size requirements of the microcoded tasks + * Returns: Size in bytes + */ +int MCD_getCodeSize(void) +{ +#ifdef MCD_INCLUDE_EU + return 0x2b64; +#else + return 0x1744; +#endif +} +/********************** End of MCD_getCodeSize() ********************/ + +/********************************************************************/ +/* Function: MCD_getVersion + * Purpose: Provide the version string and number + * Arguments: longVersion - user supplied pointer to a pointer to a char + * which points to the version string + * Returns: Version number and version string (by reference) + */ +char MCD_versionString[] = "Multi-channel DMA API v1.0"; +#define MCD_REV_MAJOR 0x01 +#define MCD_REV_MINOR 0x00 + +int MCD_getVersion(char **longVersion) +{ + int ret = 0; + *longVersion = MCD_versionString; + ret = (MCD_REV_MAJOR << 8) | MCD_REV_MINOR; + return ret; +} +/********************** End of MCD_getVersion() *********************/ + +/********************************************************************/ +/* Private version of memcpy() + * Note that everything this is used for is longword-aligned. + */ +static void MCD_memcpy(int *dest, int *src, u32 size) +{ + u32 i; + + for (i = 0; i < size; i += sizeof(int), dest++, src++) + *dest = *src; +} +/********************************************************************/ diff --git a/arch/m68k/coldfire/MCD_progCheck.h b/arch/m68k/coldfire/MCD_progCheck.h new file mode 100755 index 000000000000..136f4dfdbe7d --- /dev/null +++ b/arch/m68k/coldfire/MCD_progCheck.h @@ -0,0 +1,29 @@ +/* + * drivers/dma/MCD_progCheck.h + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is autogenerated. Do not change */ + +#define CURRBD 4 +#define DCOUNT 6 +#define DESTPTR 5 +#define SRCPTR 7 diff --git a/arch/m68k/coldfire/MCD_tasks.c b/arch/m68k/coldfire/MCD_tasks.c new file mode 100755 index 000000000000..00b4b35bba82 --- /dev/null +++ b/arch/m68k/coldfire/MCD_tasks.c @@ -0,0 +1,2466 @@ +/* + * drivers/dma/MCD_tasks.c + * + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "MCD_dma.h" + +u32 MCD_varTab0[]; +u32 MCD_varTab1[]; +u32 MCD_varTab2[]; +u32 MCD_varTab3[]; +u32 MCD_varTab4[]; +u32 MCD_varTab5[]; +u32 MCD_varTab6[]; +u32 MCD_varTab7[]; +u32 MCD_varTab8[]; +u32 MCD_varTab9[]; +u32 MCD_varTab10[]; +u32 MCD_varTab11[]; +u32 MCD_varTab12[]; +u32 MCD_varTab13[]; +u32 MCD_varTab14[]; +u32 MCD_varTab15[]; + +u32 MCD_funcDescTab0[]; +#ifdef MCD_INCLUDE_EU +u32 MCD_funcDescTab1[]; +u32 MCD_funcDescTab2[]; +u32 MCD_funcDescTab3[]; +u32 MCD_funcDescTab4[]; +u32 MCD_funcDescTab5[]; +u32 MCD_funcDescTab6[]; +u32 MCD_funcDescTab7[]; +u32 MCD_funcDescTab8[]; +u32 MCD_funcDescTab9[]; +u32 MCD_funcDescTab10[]; +u32 MCD_funcDescTab11[]; +u32 MCD_funcDescTab12[]; +u32 MCD_funcDescTab13[]; +u32 MCD_funcDescTab14[]; +u32 MCD_funcDescTab15[]; +#endif + +u32 MCD_contextSave0[]; +u32 MCD_contextSave1[]; +u32 MCD_contextSave2[]; +u32 MCD_contextSave3[]; +u32 MCD_contextSave4[]; +u32 MCD_contextSave5[]; +u32 MCD_contextSave6[]; +u32 MCD_contextSave7[]; +u32 MCD_contextSave8[]; +u32 MCD_contextSave9[]; +u32 MCD_contextSave10[]; +u32 MCD_contextSave11[]; +u32 MCD_contextSave12[]; +u32 MCD_contextSave13[]; +u32 MCD_contextSave14[]; +u32 MCD_contextSave15[]; + +u32 MCD_realTaskTableSrc[] = +{ + 0x00000000, + 0x00000000, + (u32)MCD_varTab0, /* Task 0 Variable Table */ + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ + 0x00000000, + 0x00000000, + (u32)MCD_contextSave0, /* Task 0 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab1, /* Task 1 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave1, /* Task 1 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab2, /* Task 2 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave2, /* Task 2 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab3, /* Task 3 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave3, /* Task 3 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab4, /* Task 4 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave4, /* Task 4 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab5, /* Task 5 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave5, /* Task 5 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab6, /* Task 6 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave6, /* Task 6 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab7, /* Task 7 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave7, /* Task 7 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab8, /* Task 8 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave8, /* Task 8 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab9, /* Task 9 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave9, /* Task 9 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab10, /* Task 10 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave10, /* Task 10 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab11, /* Task 11 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave11, /* Task 11 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab12, /* Task 12 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave12, /* Task 12 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab13, /* Task 13 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave13, /* Task 13 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab14, /* Task 14 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave14, /* Task 14 context save space */ + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_varTab15, /* Task 15 Variable Table */ +#ifdef MCD_INCLUDE_EU + (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ +#else + (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +#endif + 0x00000000, + 0x00000000, + (u32)MCD_contextSave15, /* Task 15 context save space */ + 0x00000000, +}; + + +u32 MCD_varTab0[] = +{ /* Task 0 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + + +u32 MCD_varTab1[] = +{ /* Task 1 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab2[] = +{ /* Task 2 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab3[] = +{ /* Task 3 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab4[] = +{ /* Task 4 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab5[] = +{ /* Task 5 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab6[] = +{ /* Task 6 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab7[] = +{ /* Task 7 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab8[] = +{ /* Task 8 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab9[] = +{ /* Task 9 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab10[] = +{ /* Task 10 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab11[] = +{ /* Task 11 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab12[] = +{ /* Task 12 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab13[] = +{ /* Task 13 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab14[] = +{ /* Task 14 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_varTab15[] = +{ /* Task 15 Variable Table */ + 0x00000000, /* var[0] */ + 0x00000000, /* var[1] */ + 0x00000000, /* var[2] */ + 0x00000000, /* var[3] */ + 0x00000000, /* var[4] */ + 0x00000000, /* var[5] */ + 0x00000000, /* var[6] */ + 0x00000000, /* var[7] */ + 0x00000000, /* var[8] */ + 0x00000000, /* var[9] */ + 0x00000000, /* var[10] */ + 0x00000000, /* var[11] */ + 0x00000000, /* var[12] */ + 0x00000000, /* var[13] */ + 0x00000000, /* var[14] */ + 0x00000000, /* var[15] */ + 0x00000000, /* var[16] */ + 0x00000000, /* var[17] */ + 0x00000000, /* var[18] */ + 0x00000000, /* var[19] */ + 0x00000000, /* var[20] */ + 0x00000000, /* var[21] */ + 0x00000000, /* var[22] */ + 0x00000000, /* var[23] */ + 0xe0000000, /* inc[0] */ + 0x20000000, /* inc[1] */ + 0x2000ffff, /* inc[2] */ + 0x00000000, /* inc[3] */ + 0x00000000, /* inc[4] */ + 0x00000000, /* inc[5] */ + 0x00000000, /* inc[6] */ + 0x00000000, /* inc[7] */ +}; + +u32 MCD_funcDescTab0[] = +{ /* Task 0 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +#ifdef MCD_INCLUDE_EU +u32 MCD_funcDescTab1[] = +{ /* Task 1 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab2[] = +{ /* Task 2 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab3[] = +{ /* Task 3 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab4[] = +{ /* Task 4 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab5[] = +{ /* Task 5 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab6[] = +{ /* Task 6 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab7[] = +{ /* Task 7 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab8[] = +{ /* Task 8 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab9[] = +{ /* Task 9 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab10[] = +{ /* Task 10 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab11[] = +{ /* Task 11 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab12[] = +{ /* Task 12 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab13[] = +{ /* Task 13 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab14[] = +{ /* Task 14 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; + +u32 MCD_funcDescTab15[] = +{ /* Task 15 Function Descriptor Table */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xa0045670, /* mainFunc(), EU# 3 */ + 0xa0000000, /* rsduFunc(), EU# 3 */ + 0xa0000000, /* crcAccumVal(), EU# 3 */ + 0x20000000, /* setCrcAccum(), EU# 3 */ + 0x21800000, /* and(), EU# 3 */ + 0x21e00000, /* or(), EU# 3 */ + 0x20400000, /* add(), EU# 3 */ + 0x20500000, /* sub(), EU# 3 */ + 0x205a0000, /* andNot(), EU# 3 */ + 0x20a00000, /* shiftR(), EU# 3 */ + 0x202fa000, /* andReadyBit(), EU# 3 */ + 0x202f9000, /* andNotReadyBit(), EU# 3 */ + 0x202ea000, /* andWrapBit(), EU# 3 */ + 0x202da000, /* andLastBit(), EU# 3 */ + 0x202e2000, /* andInterruptBit(), EU# 3 */ + 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +}; +#endif /*MCD_INCLUDE_EU*/ + +u32 MCD_contextSave0[128]; /* Task 0 context save space */ +u32 MCD_contextSave1[128]; /* Task 1 context save space */ +u32 MCD_contextSave2[128]; /* Task 2 context save space */ +u32 MCD_contextSave3[128]; /* Task 3 context save space */ +u32 MCD_contextSave4[128]; /* Task 4 context save space */ +u32 MCD_contextSave5[128]; /* Task 5 context save space */ +u32 MCD_contextSave6[128]; /* Task 6 context save space */ +u32 MCD_contextSave7[128]; /* Task 7 context save space */ +u32 MCD_contextSave8[128]; /* Task 8 context save space */ +u32 MCD_contextSave9[128]; /* Task 9 context save space */ +u32 MCD_contextSave10[128]; /* Task 10 context save space */ +u32 MCD_contextSave11[128]; /* Task 11 context save space */ +u32 MCD_contextSave12[128]; /* Task 12 context save space */ +u32 MCD_contextSave13[128]; /* Task 13 context save space */ +u32 MCD_contextSave14[128]; /* Task 14 context save space */ +u32 MCD_contextSave15[128]; /* Task 15 context save space */ + +u32 MCD_ChainNoEu_TDT[]; +u32 MCD_SingleNoEu_TDT[]; +#ifdef MCD_INCLUDE_EU +u32 MCD_ChainEu_TDT[]; +u32 MCD_SingleEu_TDT[]; +#endif +u32 MCD_ENetRcv_TDT[]; +u32 MCD_ENetXmit_TDT[]; + +u32 MCD_modelTaskTableSrc[] = +{ + (u32)MCD_ChainNoEu_TDT, + (u32)&((u8 *)MCD_ChainNoEu_TDT)[0x0000016c], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_SingleNoEu_TDT, + (u32)&((u8 *)MCD_SingleNoEu_TDT)[0x000000d4], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +#ifdef MCD_INCLUDE_EU + (u32)MCD_ChainEu_TDT, + (u32)&((u8 *)MCD_ChainEu_TDT)[0x000001b4], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_SingleEu_TDT, + (u32)&((u8 *)MCD_SingleEu_TDT)[0x00000124], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +#endif + (u32)MCD_ENetRcv_TDT, + (u32)&((u8 *)MCD_ENetRcv_TDT)[0x000000a4], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + (u32)MCD_ENetXmit_TDT, + (u32)&((u8 *)MCD_ENetXmit_TDT)[0x000000d0], + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +u32 MCD_ChainNoEu_TDT[] = +{ + 0x80004000, + 0x8118801b, + 0xb8c60018, + 0x10002b10, + 0x7000000d, + 0x018cf89f, + 0x6000000a, + 0x080cf89f, + 0x000001f8, + 0x98180364, + 0x8118801b, + 0xf8c6001a, + 0xb8c6601b, + 0x10002710, + 0x00000f18, + 0xb8c6001d, + 0x10001310, + 0x60000007, + 0x014cf88b, + 0x98c6001c, + 0x00000710, + 0x98c70018, + 0x10001f10, + 0x0000c818, + 0x000001f8, /* 0060(:0): NOP */ + 0xc1476018, + 0xc003231d, + 0x811a601b, + 0xc1862102, + 0x849be009, + 0x03fed7b8, + 0xda9b001b, + 0x9b9be01b, + 0x1000cb20, + 0x70000006, + 0x088cf88f, + 0x1000cb28, + 0x70000006, + 0x088cf88f, + 0x1000cb30, + 0x70000006, + 0x088cf88f, + 0x1000cb38, + 0x0000c728, + 0x000001f8, /* 00B0(:0): NOP */ + 0xc1476018, + 0xc003241d, + 0x811a601b, + 0xda9b001b, + 0x9b9be01b, + 0x0000d3a0, + 0xc1862102, + 0x849be009, + 0x0bfed7b8, + 0xda9b001b, + 0x9b9be01b, + 0x1000cb20, + 0x70000006, + 0x088cf88f, + 0x1000cb28, + 0x70000006, + 0x088cf88f, + 0x1000cb30, + 0x70000006, + 0x088cf88f, + 0x1000cb38, + 0x0000c728, + 0x000001f8, /* 010C(:0): NOP */ + 0x8118801b, + 0xd8c60018, + 0x98c6601c, + 0x6000000b, + 0x0c8cfc9f, + 0x000001f8, /* 0124(:0): NOP */ + 0xa146001e, + 0x10000b08, + 0x10002050, + 0xb8c60018, + 0x10002b10, + 0x7000000a, + 0x080cf89f, + 0x6000000d, + 0x018cf89f, + 0x000001f8, /* 014C(:0): NOP */ + 0x8618801b, + 0x7000000e, + 0x084cf21f, + 0xd8990336, + 0x8019801b, + 0x040001f8, + 0x000001f8, /* 0168(:0): NOP */ + 0x000001f8, /* 016C(:0): NOP */ +}; +u32 MCD_SingleNoEu_TDT[] = +{ + 0x8198001b, + 0x7000000d, + 0x080cf81f, + 0x8198801b, + 0x6000000e, + 0x084cf85f, + 0x000001f8, /* 0018(:0): NOP */ + 0x8298001b, + 0x7000000d, + 0x010cf81f, + 0x6000000e, + 0x018cf81f, + 0xc202601b, + 0xc002221c, + 0x809a601b, + 0xc10420c2, + 0x839be009, + 0x03fed7b8, + 0xda9b001b, + 0x9b9be01b, + 0x70000006, + 0x088cf889, + 0x1000cb28, + 0x70000006, + 0x088cf889, + 0x1000cb30, + 0x70000006, + 0x088cf889, + 0x0000cb38, + 0x000001f8, /* 0074(:0): NOP */ + 0xc202601b, + 0xc002229c, + 0x809a601b, + 0xda9b001b, + 0x9b9be01b, + 0x0000d3a0, + 0xc10420c2, + 0x839be009, + 0x0bfed7b8, + 0xda9b001b, + 0x9b9be01b, + 0x70000006, + 0x088cf889, + 0x1000cb28, + 0x70000006, + 0x088cf889, + 0x1000cb30, + 0x70000006, + 0x088cf889, + 0x0000cb38, + 0x000001f8, /* 00C8(:0): NOP */ + 0xc318022d, + 0x8018801b, + 0x040001f8, +}; +#ifdef MCD_INCLUDE_EU +u32 MCD_ChainEu_TDT[] = +{ + 0x80004000, + 0x8198801b, + 0xb8c68018, + 0x10002f10, + 0x7000000d, + 0x01ccf89f, + 0x6000000a, + 0x080cf89f, + 0x000001f8, + 0x981803a4, + 0x8198801b, + 0xf8c6801a, + 0xb8c6e01b, + 0x10002b10, + 0x00001318, + 0xb8c6801d, + 0x10001710, + 0x60000007, + 0x018cf88c, + 0x98c6801c, + 0x00000b10, + 0x98c78018, + 0x10002310, + 0x0000c820, + 0x000001f8, /* 0060(:0): NOP */ + 0x8698801b, + 0x7000000f, + 0x084cf2df, + 0xd899042d, + 0x8019801b, + 0x60000003, + 0x2cd7c7df, /* 007C(:979): DRD2B2: EU3(var13) */ + 0xd8990364, + 0x8019801b, + 0x60000003, + 0x2c17c7df, /* 008C(:981): DRD2B2: EU3(var1) */ + 0x000001f8, /* 0090(:0): NOP */ + 0xc1c7e018, + 0xc003a35e, + 0x819a601b, + 0xc206a142, + 0x851be009, + 0x63fe0000, + 0x0d4cfddf, + 0xda9b001b, + 0x9b9be01b, + 0x70000002, + 0x004cf81f, + 0x1000cb20, + 0x70000006, + 0x088cf891, + 0x1000cb28, + 0x70000006, + 0x088cf891, + 0x1000cb30, + 0x70000006, + 0x088cf891, + 0x1000cb38, + 0x0000c728, + 0x000001f8, /* 00EC(:0): NOP */ + 0xc1c7e018, + 0xc003a49e, + 0x819a601b, + 0xda9b001b, + 0x9b9be01b, + 0x0000d3a0, + 0xc206a142, + 0x851be009, + 0x6bfe0000, + 0x0d4cfddf, + 0xda9b001b, + 0x9b9be01b, + 0x70000002, + 0x004cf81f, + 0x1000cb20, + 0x70000006, + 0x088cf891, + 0x1000cb28, + 0x70000006, + 0x088cf891, + 0x1000cb30, + 0x70000006, + 0x088cf891, + 0x1000cb38, + 0x0000c728, + 0x000001f8, /* 0154(:0): NOP */ + 0x8198801b, + 0xd8c68018, + 0x98c6e01c, + 0x6000000b, + 0x0c8cfc9f, + 0x0000cc08, + 0xa1c6801e, + 0x10000f08, + 0x10002458, + 0xb8c68018, + 0x10002f10, + 0x7000000a, + 0x080cf89f, + 0x6000000d, + 0x01ccf89f, + 0x000001f8, /* 0194(:0): NOP */ + 0x8698801b, + 0x7000000e, + 0x084cf25f, + 0xd899037f, + 0x8019801b, + 0x040001f8, + 0x000001f8, /* 01B0(:0): NOP */ + 0x000001f8, /* 01B4(:0): NOP */ +}; +u32 MCD_SingleEu_TDT[] = +{ + 0x8218001b, + 0x7000000d, + 0x080cf81f, + 0x8218801b, + 0x6000000e, + 0x084cf85f, + 0x000001f8, /* 0018(:0): NOP */ + 0x8318001b, + 0x7000000d, + 0x014cf81f, + 0x6000000e, + 0x01ccf81f, + 0x8498001b, + 0x7000000f, + 0x080cf19f, + 0xd81882a4, + 0x8019001b, + 0x60000003, + 0x2c97c7df, + 0xd818826d, + 0x8019001b, + 0x60000003, + 0x2c17c7df, + 0x000001f8, /* 005C(:0): NOP */ + 0xc282e01b, + 0xc002a25e, + 0x811a601b, + 0xc184a102, + 0x841be009, + 0x63fe0000, + 0x0d4cfddf, + 0xda9b001b, + 0x9b9be01b, + 0x70000002, + 0x004cf99f, + 0x70000006, + 0x088cf88b, + 0x1000cb28, + 0x70000006, + 0x088cf88b, + 0x1000cb30, + 0x70000006, + 0x088cf88b, + 0x0000cb38, + 0x000001f8, /* 00B0(:0): NOP */ + 0xc282e01b, + 0xc002a31e, + 0x811a601b, + 0xda9b001b, + 0x9b9be01b, + 0x0000d3a0, + 0xc184a102, + 0x841be009, + 0x6bfe0000, + 0x0d4cfddf, + 0xda9b001b, + 0x9b9be01b, + 0x70000002, + 0x004cf99f, + 0x70000006, + 0x088cf88b, + 0x1000cb28, + 0x70000006, + 0x088cf88b, + 0x1000cb30, + 0x70000006, + 0x088cf88b, + 0x0000cb38, + 0x000001f8, /* 0110(:0): NOP */ + 0x8144801c, + 0x0000c008, + 0xc398027f, + 0x8018801b, + 0x040001f8, +}; +#endif +u32 MCD_ENetRcv_TDT[] = +{ + 0x80004000, + 0x81988000, + 0x10000788, + 0x6000000a, + 0x080cf05f, + 0x98180209, + 0x81c40004, + 0x7000000e, + 0x010cf05f, + 0x7000000c, + 0x01ccf05f, + 0x70000004, + 0x014cf049, + 0x70000004, + 0x004cf04a, + 0x00000b88, + 0xc4030150, + 0x8119e012, + 0x03e0cf90, + 0x81188000, + 0x000ac788, + 0xc4030000, + 0x8199e000, + 0x63e00004, + 0x084cfc8b, + 0xd8990000, + 0x9999e000, + 0x60000005, + 0x0cccf841, + 0x81c60000, + 0xc399021b, + 0x80198000, + 0x00008400, + 0x00000f08, + 0x81988000, + 0x10000788, + 0x6000000a, + 0x080cf05f, + 0xc2188209, + 0x80190000, + 0x040001f8, + 0x000001f8, +}; +u32 MCD_ENetXmit_TDT[] = +{ + 0x80004000, + 0x81988000, + 0x10000788, + 0x6000000a, + 0x080cf05f, + 0x98180309, + 0x80004003, + 0x81c60004, + 0x7000000e, + 0x014cf05f, + 0x7000000c, + 0x028cf05f, + 0x7000000d, + 0x018cf05f, + 0x70000004, + 0x01ccf04d, + 0x10000b90, + 0x60000004, + 0x020cf0a1, + 0xc3188312, + 0x83c70000, + 0x00001f10, + 0xc583a3c3, + 0x81042325, + 0x03e0c798, + 0xd8990000, + 0x9999e000, + 0x000acf98, + 0xd8992306, + 0x9999e03f, + 0x03eac798, + 0xd8990000, + 0x9999e000, + 0x000acf98, + 0xd8990000, + 0x99832302, + 0x0beac798, + 0x81988000, + 0x6000000b, + 0x0c4cfc5f, + 0x81c80000, + 0xc5190312, + 0x80198000, + 0x00008400, + 0x00000f08, + 0x81988000, + 0x10000788, + 0x6000000a, + 0x080cf05f, + 0xc2988309, + 0x80190000, + 0x040001f8, + 0x000001f8, +}; + +#ifdef MCD_INCLUDE_EU +MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +#endif diff --git a/arch/m68k/coldfire/MCD_tasksInit.c b/arch/m68k/coldfire/MCD_tasksInit.c new file mode 100755 index 000000000000..f9b46bc35f72 --- /dev/null +++ b/arch/m68k/coldfire/MCD_tasksInit.c @@ -0,0 +1,275 @@ +/* + * drivers/dma/MCD_tasksInit.c + * + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Autogenerated - Do not edit! + */ + +#include "MCD_dma.h" + +extern dmaRegs *MCD_dmaBar; + + +/* + * Task 0 + */ + +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, + short destIncr, int xferSize, short xferSizeIncr, + int *cSave, volatile TaskTableEntry *taskTable, + int channel) +{ + + MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 25, + (u32)(0xe000 << 16) | (0xffff & srcIncr)); + /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 24, + (u32)(0xe000 << 16) | (0xffff & destIncr)); + /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 26, + (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); + /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} + + +/* + * Task 1 + */ + +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, + char *destAddr, short destIncr, int dmaSize, + short xferSizeIncr, int flags, int *currBD, int *cSave, + volatile TaskTableEntry *taskTable, int channel) +{ + + MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 25, + (u32)(0xe000 << 16) | (0xffff & srcIncr)); + /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 24, + (u32)(0xe000 << 16) | (0xffff & destIncr)); + /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 26, + (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); + /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} + + +/* + * Task 2 + */ + +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry *taskTable, int channel) +{ + + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 25, + (u32)(0xe000 << 16) | (0xffff & srcIncr)); + /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 24, + (u32)(0xe000 << 16) | (0xffff & destIncr)); + /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); + /* var[12] */ + MCD_SET_VAR(taskTable+channel, 26, + (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); + /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */ + MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} + + +/* + * Task 3 + */ + +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, + char *destAddr, short destIncr, int dmaSize, + short xferSizeIncr, int flags, int *currBD, int *cSave, + volatile TaskTableEntry *taskTable, int channel) +{ + + MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 25, + (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 24, + (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 26, + (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} + + +/* + * Task 4 + */ + +void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, + volatile TaskTableEntry *taskTable, int channel) +{ + + MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} + + +/* + * Task 5 + */ + +void MCD_startDmaENetXmit(char *bDBase, char *currBD, + char *xmitFifoPtr, volatile TaskTableEntry *taskTable, + int channel) +{ + + MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ + MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ + MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */ + MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ + MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ + MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ + MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ + MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ + MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ + MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ + MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ + MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ + MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ + MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */ + MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */ + MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ + MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */ + MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ + MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ + MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */ + MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */ + MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */ + MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ + MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */ + MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */ + + /* Set the task's Enable bit in its Task Control Register */ + MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +} diff --git a/arch/m68k/coldfire/MCD_tasksInit.h b/arch/m68k/coldfire/MCD_tasksInit.h new file mode 100755 index 000000000000..14fac2537140 --- /dev/null +++ b/arch/m68k/coldfire/MCD_tasksInit.h @@ -0,0 +1,84 @@ +/* + * drivers/dma/MCD_tasksInit.h + * + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Kurt Mahan + * Shrek Wu b16972@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef MCD_TSK_INIT_H +#define MCD_TSK_INIT_H 1 + +/* + * Autogenerated - Do not edit! + */ + +/* + * Task 0 + */ +void MCD_startDmaChainNoEu(int *currBD, short srcIncr, + short destIncr, int xferSize, + short xferSizeIncr, int *cSave, + volatile TaskTableEntry *taskTable, + int channel); + + +/* + * Task 1 + */ +void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, + char *destAddr, short destIncr, int dmaSize, + short xferSizeIncr, int flags, int *currBD, + int *cSave, volatile TaskTableEntry *taskTable, + int channel); + + +/* + * Task 2 + */ +void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, + int xferSize, short xferSizeIncr, int *cSave, + volatile TaskTableEntry *taskTable, + int channel); + + +/* + * Task 3 + */ +void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, + char *destAddr, short destIncr, int dmaSize, + short xferSizeIncr, int flags, int *currBD, + int *cSave, volatile TaskTableEntry *taskTable, + int channel); + + +/* + * Task 4 + */ +void MCD_startDmaENetRcv(char *bDBase, char *currBD, + char *rcvFifoPtr, + volatile TaskTableEntry *taskTable, int channel); + + +/* + * Task 5 + */ +void MCD_startDmaENetXmit(char *bDBase, char *currBD, + char *xmitFifoPtr, + volatile TaskTableEntry *taskTable, int channel); + +#endif /* MCD_TSK_INIT_H */ diff --git a/arch/m68k/coldfire/Makefile b/arch/m68k/coldfire/Makefile new file mode 100644 index 000000000000..342462bc99a9 --- /dev/null +++ b/arch/m68k/coldfire/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for Linux arch/m68k/coldfire source directory +# + +obj-y:= config.o cache.o signal.o muldi3.o traps.o ints.o +ifdef CONFIG_M5445X +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),) + obj-y += usb.o usb/ +endif +endif + +obj-$(CONFIG_M5445X) += mcf5445x-devices.o +obj-$(CONFIG_M547X_8X) += m547x_8x-devices.o +obj-$(CONFIG_M547X_8X) += mcf548x-devices.o +obj-$(CONFIG_MCD_DMA) += m547x_8x-dma.o MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o diff --git a/arch/m68k/coldfire/cache.c b/arch/m68k/coldfire/cache.c index d5cdce2edaf3..86e58791bc2a 100644 --- a/arch/m68k/coldfire/cache.c +++ b/arch/m68k/coldfire/cache.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include diff --git a/arch/m68k/coldfire/config.c b/arch/m68k/coldfire/config.c index aac09391a04c..23be9d435865 100644 --- a/arch/m68k/coldfire/config.c +++ b/arch/m68k/coldfire/config.c @@ -21,10 +21,10 @@ #include #include #include -#include +#include #include #include -#include +#include #include #include #include @@ -35,16 +35,6 @@ #include -#ifdef CONFIG_UBOOT - -#if defined(CONFIG_M5445X) -#define UBOOT_EXTRA_CLOCKS -#elif defined(CONFIG_M547X_8X) -#define UBOOT_PCI -#endif - -#endif - #include #ifdef CONFIG_M5445X @@ -56,7 +46,7 @@ #endif #ifdef CONFIG_M547X_8X -#include +#include #endif extern int get_irq_list(struct seq_file *p, void *v); @@ -67,6 +57,7 @@ extern unsigned long availmem; #if CONFIG_UBOOT extern char m68k_command_line[CL_SIZE]; +struct mem_info m68k_ramdisk; #endif static int irq_enable[NR_IRQS]; @@ -111,11 +102,22 @@ int __init uboot_commandline(char *bootargs) int len = 0, cmd_line_len; unsigned long cmd_line_stop, cmd_line_start; + unsigned long initrd_start, initrd_stop; u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET; //uboot_init_sp parameters - must add offset to them !! cmd_line_start = uboot_init_sp + 16 + offset; - cmd_line_start = uboot_init_sp + 20 + offset; + cmd_line_stop = uboot_init_sp + 20 + offset; + + initrd_start = uboot_init_sp + 8 + offset; + + if ( *((unsigned long*)initrd_start) != 0) + { + initrd_stop = uboot_init_sp + 12 + offset; + + m68k_ramdisk.addr = initrd_start; + m68k_ramdisk.size = *((unsigned long*)initrd_stop) - *((unsigned long*)initrd_start); + } /* copy command line */ cmd_line_len = cmd_line_stop - cmd_line_start; diff --git a/arch/m68k/coldfire/m547x_8x-devices.c b/arch/m68k/coldfire/m547x_8x-devices.c new file mode 100644 index 000000000000..a7c6c3e6f2b5 --- /dev/null +++ b/arch/m68k/coldfire/m547x_8x-devices.c @@ -0,0 +1,163 @@ +/* + * arch/m68k/coldfire/m547x_8x-devices.c + * + * Coldfire M547x/M548x Platform Device Configuration + * + * Copyright (c) 2008 Freescale Semiconductor, Inc. + * Kurt Mahan + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +#ifdef CONFIG_SPI +/* + * + * DSPI + * + */ + +/* number of supported SPI selects */ +#define SPI_NUM_CHIPSELECTS 8 + +void coldfire_spi_cs_control(u8 cs, u8 command) +{ + /* nothing special required */ +} + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +static struct coldfire_spi_chip spidev_chip_info = { + .bits_per_word = 8, +}; +#endif + +static struct spi_board_info spi_board_info[] = { +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + { + .modalias = "spidev", + .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 0, /* CS0 */ + .controller_data = &spidev_chip_info, + } +#endif +}; + +static int spi_irq_list[] = { + /* IRQ, ICR Offset, ICR Val,Mask */ + 64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW, 0x18, 0, + 64 + ISC_DSPI_RFOF, ISC_DSPI_RFOF, 0x18, 0, + 64 + ISC_DSPI_RFDF, ISC_DSPI_RFDF, 0x18, 0, + 64 + ISC_DSPI_TFUF, ISC_DSPI_TFUF, 0x18, 0, + 64 + ISC_DSPI_TCF, ISC_DSPI_TCF, 0x18, 0, + 64 + ISC_DSPI_TFFF, ISC_DSPI_TFFF, 0x18, 0, + 64 + ISC_DSPI_EOQF, ISC_DSPI_EOQF, 0x18, 0, + 0,0,0,0, +}; + +static struct coldfire_spi_master coldfire_master_info = { + .bus_num = 1, + .num_chipselect = SPI_NUM_CHIPSELECTS, + .irq_list = spi_irq_list, + .irq_source = 0, /* not used */ + .irq_vector = 0, /* not used */ + .irq_mask = 0, /* not used */ + .irq_lp = 0, /* not used */ + .par_val = 0, /* not used */ + .cs_control = coldfire_spi_cs_control, +}; + +static struct resource coldfire_spi_resources[] = { + [0] = { + .name = "spi-par", + .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ + .end = MCF_MBAR + 0x00000a50, /* PAR_DSPI */ + .flags = IORESOURCE_MEM + }, + + [1] = { + .name = "spi-module", + .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */ + .end = MCF_MBAR + 0x00008ab8, /* DSPI mem map end */ + .flags = IORESOURCE_MEM + }, + + [2] = { + .name = "spi-int-level", + .start = MCF_MBAR + 0x740, /* ICR start */ + .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */ + .flags = IORESOURCE_MEM + }, + + [3] = { + .name = "spi-int-mask", + .start = MCF_MBAR + 0x70c, /* IMRL */ + .end = MCF_MBAR + 0x70c, /* IMRL */ + .flags = IORESOURCE_MEM + } +}; + +static struct platform_device coldfire_spi = { + .name = "spi_coldfire", + .id = -1, + .resource = coldfire_spi_resources, + .num_resources = ARRAY_SIZE(coldfire_spi_resources), + .dev = { + .platform_data = &coldfire_master_info, + } +}; + +/** + * m547x_8x_spi_init - Initialize SPI + */ +static int __init m547x_8x_spi_init(void) +{ + int retval; + + /* initialize the DSPI PAR */ + MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 | + MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS | + MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS | + MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS | + MCF_GPIO_PAR_DSPI_PAR_SCK_SCK | + MCF_GPIO_PAR_DSPI_PAR_SIN_SIN | + MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT); + + /* register device */ + retval = platform_device_register(&coldfire_spi); + if (retval < 0) { + goto out; + } + + /* register board info */ + if (ARRAY_SIZE(spi_board_info)) + retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + +out: + return retval; +} +#endif + + +/** + * m547x_8x_init_devices - Initialize M547X_8X devices + * + * Returns 0 on success. + */ +static int __init m547x_8x_init_devices(void) +{ +#ifdef CONFIG_SPI + m547x_8x_spi_init(); +#endif + + return 0; +} +arch_initcall(m547x_8x_init_devices); diff --git a/arch/m68k/coldfire/m547x_8x-dma.c b/arch/m68k/coldfire/m547x_8x-dma.c new file mode 100644 index 000000000000..4f103d4f1ced --- /dev/null +++ b/arch/m68k/coldfire/m547x_8x-dma.c @@ -0,0 +1,516 @@ +/* + * arch/m68k/coldfire/m547x_8x-dma.c + * + * Coldfire M547x/M548x DMA + * + * Copyright (c) 2008 Freescale Semiconductor, Inc. + * Kurt Mahan + * + * This code is based on patches from the Freescale M547x_8x BSP + * release mcf547x_8x-20070107-ltib.iso + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This global keeps track of which initiators have been + * used of the available assignments. Initiators 0-15 are + * hardwired. Initiators 16-31 are multiplexed and controlled + * via the Initiatior Mux Control Registe (IMCR). The + * assigned requestor is stored with the associated initiator + * number. + */ +static int used_reqs[32] = { + DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0, + DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1, + DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX, + DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +/* + * This global keeps track of which channels have been assigned + * to tasks. This methology assumes that no single initiator + * will be tied to more than one task/channel + */ +static char used_channel[16] = { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1 +}; + +unsigned int connected_channel[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/** + * dma_set_initiator - enable initiator + * @initiator: initiator identifier + * + * Returns 0 of successful, non-zero otherwise + * + * Attempt to enable the provided Initiator in the Initiator + * Mux Control Register. + */ +int dma_set_initiator(int initiator) +{ + switch (initiator) { + case DMA_ALWAYS: + case DMA_DSPI_RX: + case DMA_DSPI_TX: + case DMA_DREQ0: + case DMA_PSC0_RX: + case DMA_PSC0_TX: + case DMA_USBEP0: + case DMA_USBEP1: + case DMA_USBEP2: + case DMA_USBEP3: + case DMA_PCI_TX: + case DMA_PCI_RX: + case DMA_PSC1_RX: + case DMA_PSC1_TX: + case DMA_I2C_RX: + case DMA_I2C_TX: + /* + * These initiators are always active + */ + break; + + case DMA_FEC0_RX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3)) + | MCF_DMA_IMCR_SRC16_FEC0RX; + used_reqs[16] = DMA_FEC0_RX; + break; + + case DMA_FEC0_TX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3)) + | MCF_DMA_IMCR_SRC17_FEC0TX; + used_reqs[17] = DMA_FEC0_TX; + break; + + case DMA_FEC1_RX: + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3)) + | MCF_DMA_IMCR_SRC20_FEC1RX; + used_reqs[20] = DMA_FEC1_RX; + break; + + case DMA_FEC1_TX: + if (used_reqs[21] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) + | MCF_DMA_IMCR_SRC21_FEC1TX; + used_reqs[21] = DMA_FEC1_TX; + } else if (used_reqs[25] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) + | MCF_DMA_IMCR_SRC25_FEC1TX; + used_reqs[25] = DMA_FEC1_TX; + } else if (used_reqs[31] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) + | MCF_DMA_IMCR_SRC31_FEC1TX; + used_reqs[31] = DMA_FEC1_TX; + } else /* No empty slots */ + return 1; + break; + + case DMA_DREQ1: + if (used_reqs[29] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) + | MCF_DMA_IMCR_SRC29_DREQ1; + used_reqs[29] = DMA_DREQ1; + } else if (used_reqs[21] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) + | MCF_DMA_IMCR_SRC21_DREQ1; + used_reqs[21] = DMA_DREQ1; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM0: + if (used_reqs[24] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3)) + | MCF_DMA_IMCR_SRC24_CTM0; + used_reqs[24] = DMA_CTM0; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM1: + if (used_reqs[25] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) + | MCF_DMA_IMCR_SRC25_CTM1; + used_reqs[25] = DMA_CTM1; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM2: + if (used_reqs[26] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) + | MCF_DMA_IMCR_SRC26_CTM2; + used_reqs[26] = DMA_CTM2; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM3: + if (used_reqs[27] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) + | MCF_DMA_IMCR_SRC27_CTM3; + used_reqs[27] = DMA_CTM3; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM4: + if (used_reqs[28] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) + | MCF_DMA_IMCR_SRC28_CTM4; + used_reqs[28] = DMA_CTM4; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM5: + if (used_reqs[29] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) + | MCF_DMA_IMCR_SRC29_CTM5; + used_reqs[29] = DMA_CTM5; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM6: + if (used_reqs[30] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) + | MCF_DMA_IMCR_SRC30_CTM6; + used_reqs[30] = DMA_CTM6; + } else /* No empty slots */ + return 1; + break; + + case DMA_CTM7: + if (used_reqs[31] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) + | MCF_DMA_IMCR_SRC31_CTM7; + used_reqs[31] = DMA_CTM7; + } else /* No empty slots */ + return 1; + break; + + case DMA_USBEP4: + if (used_reqs[26] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) + | MCF_DMA_IMCR_SRC26_USBEP4; + used_reqs[26] = DMA_USBEP4; + } else /* No empty slots */ + return 1; + break; + + case DMA_USBEP5: + if (used_reqs[27] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) + | MCF_DMA_IMCR_SRC27_USBEP5; + used_reqs[27] = DMA_USBEP5; + } else /* No empty slots */ + return 1; + break; + + case DMA_USBEP6: + if (used_reqs[28] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) + | MCF_DMA_IMCR_SRC28_USBEP6; + used_reqs[28] = DMA_USBEP6; + } else /* No empty slots */ + return 1; + break; + + case DMA_PSC2_RX: + if (used_reqs[28] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) + | MCF_DMA_IMCR_SRC28_PSC2RX; + used_reqs[28] = DMA_PSC2_RX; + } else /* No empty slots */ + return 1; + break; + + case DMA_PSC2_TX: + if (used_reqs[29] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) + | MCF_DMA_IMCR_SRC29_PSC2TX; + used_reqs[29] = DMA_PSC2_TX; + } else /* No empty slots */ + return 1; + break; + + case DMA_PSC3_RX: + if (used_reqs[30] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) + | MCF_DMA_IMCR_SRC30_PSC3RX; + used_reqs[30] = DMA_PSC3_RX; + } else /* No empty slots */ + return 1; + break; + + case DMA_PSC3_TX: + if (used_reqs[31] == 0) { + MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) + | MCF_DMA_IMCR_SRC31_PSC3TX; + used_reqs[31] = DMA_PSC3_TX; + } else /* No empty slots */ + return 1; + break; + + default: + return 1; + } + return 0; +} + +/** + * dma_get_initiator - get the initiator for the given requestor + * @requestor: initiator identifier + * + * Returns initiator number (0-31) if assigned or just 0 + */ +unsigned int dma_get_initiator(int requestor) +{ + u32 i; + + for (i = 0; i < sizeof(used_reqs); ++i) { + if (used_reqs[i] == requestor) + return i; + } + return 0; +} + +/** + * dma_remove_initiator - remove the given initiator from active list + * @requestor: requestor to remove + */ +void dma_remove_initiator(int requestor) +{ + u32 i; + + for (i = 0; i < sizeof(used_reqs); ++i) { + if (used_reqs[i] == requestor) { + used_reqs[i] = -1; + break; + } + } +} + +/** + * dma_set_channel_fec: find available channel for fec and mark + * @requestor: initiator/requestor identifier + * + * Returns first avaialble channel (0-5) or -1 if all occupied + */ +int dma_set_channel_fec(int requestor) +{ + u32 i, t; + +#ifdef CONFIG_FEC_548x_ENABLE_FEC2 + t = 4; +#else + t = 2; +#endif + + for (i = 0; i < t ; ++i) { + if (used_channel[i] == -1) { + used_channel[i] = requestor; + return i; + } + } + /* All channels taken */ + return -1; +} + +/** + * dma_set_channel - find an available channel and mark as used + * @requestor: initiator/requestor identifier + * + * Returns first available channel (6-15) or -1 if all occupied + */ +int dma_set_channel(int requestor) +{ + u32 i; +#ifdef CONFIG_NET_FEC2 + i = 4; +#else + i = 2; +#endif + + for (; i < 16; ++i) + if (used_channel[i] == -1) { + used_channel[i] = requestor; + return i; + } + + /* All channels taken */ + return -1; +} + +/** + * dma_get_channel - get the channel being initiated by the requestor + * @requestor: initiator/requestor identifier + * + * Returns Initiator for requestor or -1 if not found + */ +int dma_get_channel(int requestor) +{ + u32 i; + + for (i = 0; i < sizeof(used_channel); ++i) { + if (used_channel[i] == requestor) + return i; + } + return -1; +} + +/** + * dma_connect - connect a channel with reference on data + * @channel: channel number + * @address: reference address of data + * + * Returns 0 if success or -1 if invalid channel + */ +int dma_connect(int channel, int address) +{ + if ((channel < 16) && (channel >= 0)) { + connected_channel[channel] = address; + return 0; + } + return -1; +} + +/** + * dma_disconnect - disconnect a channel + * @channel: channel number + * + * Returns 0 if success or -1 if invalid channel + */ +int dma_disconnect(int channel) +{ + if ((channel < 16) && (channel >= 0)) { + connected_channel[channel] = 0; + return 0; + } + return -1; +} + +/** + * dma_remove_channel - remove channel from the active list + * @requestor: initiator/requestor identifier + */ +void dma_remove_channel(int requestor) +{ + u32 i; + + for (i = 0; i < sizeof(used_channel); ++i) { + if (used_channel[i] == requestor) { + used_channel[i] = -1; + break; + } + } +} + +/** + * dma_interrupt_handler - dma interrupt handler + * @irq: interrupt number + * @dev_id: data + * + * Returns IRQ_HANDLED + */ +irqreturn_t dma_interrupt_handler(int irq, void *dev_id) +{ + u32 i, interrupts; + + /* + * Determine which interrupt(s) triggered by AND'ing the + * pending interrupts with those that aren't masked. + */ + interrupts = MCF_DMA_DIPR; + MCF_DMA_DIPR = interrupts; + + for (i = 0; i < 16; ++i, interrupts >>= 1) { + if (interrupts & 0x1) + if (connected_channel[i] != 0) + ((void (*)(void)) (connected_channel[i])) (); + } + + return IRQ_HANDLED; +} + +/** + * dma_remove_channel_by_number - clear dma channel + * @channel: channel number to clear + */ +void dma_remove_channel_by_number(int channel) +{ + if ((channel < sizeof(used_channel)) && (channel >= 0)) + used_channel[channel] = -1; +} + +/** + * dma_init - initialize the dma subsystem + * + * Returns 0 if success non-zero if failure + * + * Handles the DMA initialization during device setup. + */ +int __devinit dma_init() +{ + int result; + char *dma_version_str; + + MCD_getVersion(&dma_version_str); + printk(KERN_INFO "m547x_8x DMA: Initialize %s\n", dma_version_str); + + /* attempt to setup dma interrupt handler */ + if (request_irq(64 + ISC_DMA, dma_interrupt_handler, IRQF_DISABLED, + "MCD-DMA", NULL)) { + printk(KERN_ERR "MCD-DMA: Cannot allocate the DMA IRQ(48)\n"); + return 1; + } + + MCF_DMA_DIMR = 0; + MCF_DMA_DIPR = 0xFFFFFFFF; + + MCF_ICR(ISC_DMA) = ILP_DMA; + + result = MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000), + (void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS); + if (result != MCD_OK) { + printk(KERN_ERR "MCD-DMA: Cannot perform DMA initialization\n"); + free_irq(64 + ISC_DMA, NULL); + return 1; + } + + return 0; +} +device_initcall(dma_init); diff --git a/arch/m68k/coldfire/mcf5445x-devices.c b/arch/m68k/coldfire/mcf5445x-devices.c new file mode 100644 index 000000000000..e65bb03351f5 --- /dev/null +++ b/arch/m68k/coldfire/mcf5445x-devices.c @@ -0,0 +1,136 @@ +/* + * arch/m68k/coldfire/mcf5445x-devices.c + * + * Coldfire M5445x Platform Device Configuration + * + * Based on the Freescale MXC devices.c + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * Kurt Mahan + */ +#include +#include +#include +#include +#include + +#include +#include + +/* ATA Interrupt */ +#define IRQ_ATA (64 + 64 + 54) + +/* ATA Base */ +#define BASE_IO_ATA 0x90000000 + +#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */ +#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */ + +/* + * On-chip PATA + */ +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +static int ata_init(struct platform_device *pdev) +{ + /* clear ints */ + ATA_IER = 0x00; + ATA_ICR = 0xff; + + /* setup shared pins */ + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) | + MCF_GPIO_PAR_FEC_FEC1_ATA; + + MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C & + (MCF_GPIO_PAR_FECI2C_MDC1_MASK & + MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) | + MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR | + MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW; + + MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN | + MCF_GPIO_PAR_ATA_CS1 | + MCF_GPIO_PAR_ATA_CS0 | + MCF_GPIO_PAR_ATA_DA2 | + MCF_GPIO_PAR_ATA_DA1 | + MCF_GPIO_PAR_ATA_DA0 | + MCF_GPIO_PAR_ATA_RESET_RESET | + MCF_GPIO_PAR_ATA_DMARQ_DMARQ | + MCF_GPIO_PAR_ATA_IORDY_IORDY; + + MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI & + (MCF_GPIO_PAR_PCI_GNT3_MASK & + MCF_GPIO_PAR_PCI_REQ3_MASK)) | + MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK | + MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ; + + return 0; +} + +static void ata_exit(void) +{ + printk(KERN_INFO "** ata_exit\n"); +} + +static int ata_get_clk_rate(void) +{ + return MCF_BUSCLK; +} + +/* JKM -- move these to a header file */ +#define MCF_IDE_DMA_WATERMARK 32 /* DMA watermark level in bytes */ +#define MCF_IDE_DMA_BD_NR (512/3/4) /* number of BDs per channel */ + +static struct fsl_ata_platform_data ata_data = { + .init = ata_init, + .exit = ata_exit, + .get_clk_rate = ata_get_clk_rate, +#ifdef CONFIG_PATA_FSL_USE_DMA + .udma_mask = 0x0F, /* the board handles up to UDMA3 */ + .fifo_alarm = MCF_IDE_DMA_WATERMARK / 2, + .max_sg = MCF_IDE_DMA_BD_NR, +#endif +}; + +static struct resource pata_fsl_resources[] = { + [0] = { /* I/O */ + .start = BASE_IO_ATA, + .end = BASE_IO_ATA + 0x000000d8, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = IRQ_ATA, + .end = IRQ_ATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .platform_data = &ata_data, + .coherent_dma_mask = ~0, /* $$$ REVISIT */ + }, +}; + +static inline void mcf5445x_init_pata(void) +{ + (void)platform_device_register(&pata_fsl_device); +} +#else +static inline void mcf5445x_init_pata(void) +{ +} +#endif + +static int __init mcf5445x_init_devices(void) +{ + printk(KERN_INFO "MCF5445x INIT_DEVICES\n"); +#if 0 + mcf5445x_init_pata(); +#endif + + return 0; +} +arch_initcall(mcf5445x_init_devices); diff --git a/arch/m68k/coldfire/mcf548x-devices.c b/arch/m68k/coldfire/mcf548x-devices.c new file mode 100644 index 000000000000..eadd1a32553b --- /dev/null +++ b/arch/m68k/coldfire/mcf548x-devices.c @@ -0,0 +1,94 @@ +/* + * arch/m68k/coldfire/mcf5445x-devices.c + * + * Coldfire M5445x Platform Device Configuration + * + * Based on the Freescale MXC devices.c + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * Kurt Mahan + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct resource coldfire_i2c_resources[] = { + [0] = { /* I/O */ + .start = MCF_MBAR + 0x008F00, + .end = MCF_MBAR + 0x008F20, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = 40, + .end = 40, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device coldfire_i2c_device = { + .name = "MCF548X-i2c", + .id = -1, + .num_resources = ARRAY_SIZE(coldfire_i2c_resources), + .resource = coldfire_i2c_resources, +}; + +static struct resource coldfire_sec_resources[] = { + [0] = { /* I/O */ + .start = MCF_MBAR + 0x00020000, + .end = MCF_MBAR + 0x00033000, + .flags = IORESOURCE_MEM, + }, + [2] = { /* IRQ */ + .start = ISC_SEC, + .end = ISC_SEC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device coldfire_sec_device = { + .name = "fsl-sec1", + .id = -1, + .num_resources = ARRAY_SIZE(coldfire_sec_resources), + .resource = coldfire_sec_resources, +}; + +#if defined(CONFIG_MTD_PHYSMAP) +static struct physmap_flash_data mcf5485_flash_data = { + .width = 2, +}; + +static struct resource mcf5485_flash_resource = { + .start = 0xf8000000, + .end = 0xf80fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mcf5485_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mcf5485_flash_data, + }, + .num_resources = 1, + .resource = &mcf5485_flash_resource, +}; +#endif + +static int __init mcf5485_init_devices(void) +{ + printk(KERN_INFO "MCF5485x INIT_DEVICES\n"); + + platform_device_register(&coldfire_i2c_device); + platform_device_register(&coldfire_sec_device); +/*#if defined(CONFIG_MTD_PHYSMAP) + platform_device_register(&mcf5485_flash_device); +#endif*/ + return 0; +} +arch_initcall(mcf5485_init_devices); diff --git a/arch/m68k/coldfire/traps.c b/arch/m68k/coldfire/traps.c new file mode 100644 index 000000000000..38784a553662 --- /dev/null +++ b/arch/m68k/coldfire/traps.c @@ -0,0 +1,455 @@ +/* + * linux/arch/m68knommu/kernel/traps.c + * + * Copyright (C) 1993, 1994 by Hamish Macdonald + * + * 68040 fixes by Michael Rausch + * 68040 fixes by Martin Apel + * 68060 fixes by Roman Hodek + * 68060 fixes by Jesper Skov + * Coldfire fixes by Kurt Mahan + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +/* + * Sets up all exception vectors + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +static char const * const vec_names[] = { + "RESET SP", "RESET PC", "BUS ERROR", "ADDRESS ERROR", + "ILLEGAL INSTRUCTION", "ZERO DIVIDE", "CHK", "TRAPcc", + "PRIVILEGE VIOLATION", "TRACE", "LINE 1010", "LINE 1111", + "UNASSIGNED RESERVED 12", "COPROCESSOR PROTOCOL VIOLATION", + "FORMAT ERROR", "UNINITIALIZED INTERRUPT", + "UNASSIGNED RESERVED 16", "UNASSIGNED RESERVED 17", + "UNASSIGNED RESERVED 18", "UNASSIGNED RESERVED 19", + "UNASSIGNED RESERVED 20", "UNASSIGNED RESERVED 21", + "UNASSIGNED RESERVED 22", "UNASSIGNED RESERVED 23", + "SPURIOUS INTERRUPT", "LEVEL 1 INT", "LEVEL 2 INT", "LEVEL 3 INT", + "LEVEL 4 INT", "LEVEL 5 INT", "LEVEL 6 INT", "LEVEL 7 INT", + "SYSCALL", "TRAP #1", "TRAP #2", "TRAP #3", + "TRAP #4", "TRAP #5", "TRAP #6", "TRAP #7", + "TRAP #8", "TRAP #9", "TRAP #10", "TRAP #11", + "TRAP #12", "TRAP #13", "TRAP #14", "TRAP #15", + "FPCP BSUN", "FPCP INEXACT", "FPCP DIV BY 0", "FPCP UNDERFLOW", + "FPCP OPERAND ERROR", "FPCP OVERFLOW", "FPCP SNAN", + "FPCP UNSUPPORTED OPERATION", + "MMU CONFIGURATION ERROR" +}; + +asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, + unsigned long error_code); +asmlinkage void trap_c(struct frame *fp); +extern void __init coldfire_trap_init(void); + +void __init trap_init(void) +{ + coldfire_trap_init(); +} + +/* The following table converts the FS encoding of a ColdFire + exception stack frame into the error_code value needed by + do_fault. */ + +static const unsigned char fs_err_code[] = { + 0, /* 0000 */ + 0, /* 0001 */ + 0, /* 0010 */ + 0, /* 0011 */ + 1, /* 0100 */ + 0, /* 0101 */ + 0, /* 0110 */ + 0, /* 0111 */ + 2, /* 1000 */ + 3, /* 1001 */ + 2, /* 1010 */ + 0, /* 1011 */ + 1, /* 1100 */ + 1, /* 1101 */ + 0, /* 1110 */ + 0 /* 1111 */ +}; + +#ifdef DEBUG +static const char *fs_err_msg[16] = { + "Normal", + "Reserved", + "Interrupt during debug service routine", + "Reserved", + "X Protection", + "TLB X miss (opword)", + "TLB X miss (ext. word)", + "IFP in emulator mode", + "W Protection", + "Write error", + "TLB W miss", + "Reserved", + "R Protection", + "R/RMW Protection", + "TLB R miss", + "OEP in emulator mode", +}; +#endif + +static inline void access_errorCF(struct frame *fp) +{ + unsigned long int mmusr, complainingAddress; + unsigned int err_code, fs; + int need_page_fault; + + mmusr = fp->ptregs.mmusr; + complainingAddress = fp->ptregs.mmuar; +#ifdef DEBUG + printk(KERN_DEBUG "pc %#lx, mmusr %#lx, complainingAddress %#lx\n", \ + fp->ptregs.pc, mmusr, complainingAddress); +#endif + + /* + * error_code: + * bit 0 == 0 means no page found, 1 means protection fault + * bit 1 == 0 means read, 1 means write + */ + + fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1; + switch (fs) { + case 5: /* 0101 TLB opword X miss */ + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 0); + complainingAddress = fp->ptregs.pc; + break; + case 6: /* 0110 TLB extension word X miss */ + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 0, 1); + complainingAddress = fp->ptregs.pc + sizeof(long); + break; + case 10: /* 1010 TLB W miss */ + need_page_fault = cf_tlb_miss(&fp->ptregs, 1, 1, 0); + break; + case 14: /* 1110 TLB R miss */ + need_page_fault = cf_tlb_miss(&fp->ptregs, 0, 1, 0); + break; + default: + /* 0000 Normal */ + /* 0001 Reserved */ + /* 0010 Interrupt during debug service routine */ + /* 0011 Reserved */ + /* 0100 X Protection */ + /* 0111 IFP in emulator mode */ + /* 1000 W Protection*/ + /* 1001 Write error*/ + /* 1011 Reserved*/ + /* 1100 R Protection*/ + /* 1101 R Protection*/ + /* 1111 OEP in emulator mode*/ + need_page_fault = 1; + break; + } + + if (need_page_fault) { + err_code = fs_err_code[fs]; + if ((fs == 13) && (mmusr & MMUSR_WF)) /* rd-mod-wr access */ + err_code |= 2; /* bit1 - write, bit0 - protection */ + do_page_fault(&fp->ptregs, complainingAddress, err_code); + } +} + +void die_if_kernel(char *str, struct pt_regs *fp, int nr) +{ + if (!(fp->sr & PS_S)) + return; + + console_verbose(); + printk(KERN_EMERG "%s: %08x\n", str, nr); + printk(KERN_EMERG "PC: [<%08lx>]", fp->pc); + print_symbol(" %s", fp->pc); + printk(KERN_EMERG "\nSR: %04x SP: %p a2: %08lx\n", + fp->sr, fp, fp->a2); + printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", + fp->d0, fp->d1, fp->d2, fp->d3); + printk(KERN_EMERG "d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n", + fp->d4, fp->d5, fp->a0, fp->a1); + + printk(KERN_EMERG "Process %s (pid: %d, stackpage=%08lx)\n", + current->comm, current->pid, PAGE_SIZE+(unsigned long)current); + show_stack(NULL, (unsigned long *)fp); + do_exit(SIGSEGV); +} + +asmlinkage void buserr_c(struct frame *fp) +{ + unsigned int fs; + + /* Only set esp0 if coming from user mode */ + if (user_mode(&fp->ptregs)) + current->thread.esp0 = (unsigned long) fp; + + fs = (fp->ptregs.fs2 << 2) | fp->ptregs.fs1; +#if defined(DEBUG) + printk(KERN_DEBUG "*** Bus Error *** (%x)%s\n", fs, + fs_err_msg[fs & 0xf]); +#endif + switch (fs) { + case 0x5: + case 0x6: + case 0x7: + case 0x9: + case 0xa: + case 0xd: + case 0xe: + case 0xf: + access_errorCF(fp); + break; + default: + die_if_kernel("bad frame format", &fp->ptregs, 0); +#if defined(DEBUG) + printk(KERN_DEBUG "Unknown SIGSEGV - 4\n"); +#endif + force_sig(SIGSEGV, current); + } +} + + +int kstack_depth_to_print = 48; + +void show_stack(struct task_struct *task, unsigned long *stack) +{ + unsigned long *endstack, addr, symaddr; + extern char _start, _etext; + int i; + + if (!stack) { + if (task) + stack = (unsigned long *)task->thread.ksp; + else + stack = (unsigned long *)&stack; + } + + addr = (unsigned long) stack; + endstack = (unsigned long *) PAGE_ALIGN(addr); + + printk(KERN_EMERG "Stack from %08lx:", (unsigned long)stack); + for (i = 0; i < kstack_depth_to_print; i++) { + if (stack + 1 > endstack) + break; + if (i % 8 == 0) + printk("\n" KERN_EMERG " "); + symaddr = *stack; + printk(KERN_EMERG " %08lx", *stack++); + if ((symaddr >= 0xc0000000) && (symaddr < 0xc1000000)) + print_symbol("(%s)", symaddr); + } + printk("\n"); + + printk(KERN_EMERG "Call Trace:"); + i = 0; + while (stack + 1 <= endstack) { + addr = *stack++; + /* + * If the address is either in the text segment of the + * kernel, or in the region which contains vmalloc'ed + * memory, it *may* be the address of a calling + * routine; if so, print it so that someone tracing + * down the cause of the crash will be able to figure + * out the call path that was taken. + */ + if (((addr >= (unsigned long) &_start) && + (addr <= (unsigned long) &_etext))) { + if (i % 4 == 0) + printk("\n" KERN_EMERG " "); + printk(KERN_EMERG " [<%08lx>]", addr); + i++; + } + } + printk("\n"); +} + +void bad_super_trap(struct frame *fp) +{ + console_verbose(); + if (fp->ptregs.vector < sizeof(vec_names)/sizeof(vec_names[0])) + printk(KERN_WARNING "*** %s *** FORMAT=%X\n", + vec_names[fp->ptregs.vector], + fp->ptregs.format); + else + printk(KERN_WARNING "*** Exception %d *** FORMAT=%X\n", + fp->ptregs.vector, + fp->ptregs.format); + printk(KERN_WARNING "Current process id is %d\n", current->pid); + die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0); +} + +asmlinkage void trap_c(struct frame *fp) +{ + int sig; + siginfo_t info; + + if (fp->ptregs.sr & PS_S) { + if (fp->ptregs.vector == VEC_TRACE) { + /* traced a trapping instruction */ + current->ptrace |= PT_DTRACE; + } else + bad_super_trap(fp); + return; + } + + /* send the appropriate signal to the user program */ + switch (fp->ptregs.vector) { + case VEC_ADDRERR: + info.si_code = BUS_ADRALN; + sig = SIGBUS; + break; + case VEC_ILLEGAL: + case VEC_LINE10: + case VEC_LINE11: + info.si_code = ILL_ILLOPC; + sig = SIGILL; + break; + case VEC_PRIV: + info.si_code = ILL_PRVOPC; + sig = SIGILL; + break; + case VEC_COPROC: + info.si_code = ILL_COPROC; + sig = SIGILL; + break; + case VEC_TRAP1: /* gdbserver breakpoint */ + fp->ptregs.pc -= 2; + info.si_code = TRAP_TRACE; + sig = SIGTRAP; + break; + case VEC_TRAP2: + case VEC_TRAP3: + case VEC_TRAP4: + case VEC_TRAP5: + case VEC_TRAP6: + case VEC_TRAP7: + case VEC_TRAP8: + case VEC_TRAP9: + case VEC_TRAP10: + case VEC_TRAP11: + case VEC_TRAP12: + case VEC_TRAP13: + case VEC_TRAP14: + info.si_code = ILL_ILLTRP; + sig = SIGILL; + break; + case VEC_FPBRUC: + case VEC_FPOE: + case VEC_FPNAN: + info.si_code = FPE_FLTINV; + sig = SIGFPE; + break; + case VEC_FPIR: + info.si_code = FPE_FLTRES; + sig = SIGFPE; + break; + case VEC_FPDIVZ: + info.si_code = FPE_FLTDIV; + sig = SIGFPE; + break; + case VEC_FPUNDER: + info.si_code = FPE_FLTUND; + sig = SIGFPE; + break; + case VEC_FPOVER: + info.si_code = FPE_FLTOVF; + sig = SIGFPE; + break; + case VEC_ZERODIV: + info.si_code = FPE_INTDIV; + sig = SIGFPE; + break; + case VEC_CHK: + case VEC_TRAP: + info.si_code = FPE_INTOVF; + sig = SIGFPE; + break; + case VEC_TRACE: /* ptrace single step */ + info.si_code = TRAP_TRACE; + sig = SIGTRAP; + break; + case VEC_TRAP15: /* breakpoint */ + info.si_code = TRAP_BRKPT; + sig = SIGTRAP; + break; + default: + info.si_code = ILL_ILLOPC; + sig = SIGILL; + break; + } + info.si_signo = sig; + info.si_errno = 0; + switch (fp->ptregs.format) { + default: + info.si_addr = (void *) fp->ptregs.pc; + break; + case 2: + info.si_addr = (void *) fp->un.fmt2.iaddr; + break; + case 7: + info.si_addr = (void *) fp->un.fmt7.effaddr; + break; + case 9: + info.si_addr = (void *) fp->un.fmt9.iaddr; + break; + case 10: + info.si_addr = (void *) fp->un.fmta.daddr; + break; + case 11: + info.si_addr = (void *) fp->un.fmtb.daddr; + break; + } + force_sig_info(sig, &info, current); +} + +asmlinkage void set_esp0(unsigned long ssp) +{ + current->thread.esp0 = ssp; +} + +/* + * The architecture-independent backtrace generator + */ +void dump_stack(void) +{ + unsigned long stack; + + show_stack(current, &stack); +} +EXPORT_SYMBOL(dump_stack); + +#ifdef CONFIG_M68KFPU_EMU +asmlinkage void fpemu_signal(int signal, int code, void *addr) +{ + siginfo_t info; + + info.si_signo = signal; + info.si_errno = 0; + info.si_code = code; + info.si_addr = addr; + force_sig_info(signal, &info, current); +} +#endif diff --git a/arch/m68k/coldfire/usb.c b/arch/m68k/coldfire/usb.c new file mode 100644 index 000000000000..fd56433bf4a8 --- /dev/null +++ b/arch/m68k/coldfire/usb.c @@ -0,0 +1,182 @@ +/* + * + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * otg_{get,set}_transceiver() are from arm/plat-omap/usb.c. + * which is Copyright (C) 2004 Texas Instruments, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* The dmamask must be set for EHCI to work */ +static u64 ehci_dmamask = ~(u32) 0; + +struct fsl_xcvr_ops *xc_ops[3] = { NULL }; + +void fsl_usb_enable_clk(void) +{ +} +EXPORT_SYMBOL(fsl_usb_enable_clk); + +void fsl_usb_disable_clk(void) +{ +} +EXPORT_SYMBOL(fsl_usb_disable_clk); + +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) +{ + pr_debug("%s ctrlr=%d\n", __FUNCTION__, xcvr_ops->ctrlr); + xc_ops[xcvr_ops->ctrlr] = xcvr_ops; + +} +EXPORT_SYMBOL(fsl_usb_xcvr_register); + +void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr) +{ + pr_debug("%s ctrlr=%d\n", __FUNCTION__, ctrlr); + xc_ops[ctrlr] = NULL; +} +EXPORT_SYMBOL(fsl_usb_xcvr_unregister); + +/*! + * Register an instance of a USB host platform device. + * + * @param res: resource pointer + * @param n_res: number of resources + * @param config: config pointer + * + * @return newly-registered platform_device + * + * DDD fix this comment: + * The USB controller supports 3 host interfaces, and the + * kernel can be configured to support some number of them. + * Each supported host interface is registered as an instance + * of the "fsl-ehci" device. Call this function multiple times + * to register each host interface. + */ +static int instance_id; +struct platform_device *host_pdev_register(struct resource *res, int n_res, + struct fsl_usb2_platform_data *config) +{ + struct platform_device *pdev; + + pr_debug("register host res=0x%p, size=%d\n", res, n_res); + + pdev = platform_device_register_simple("fsl-ehci", + instance_id, res, n_res); + if (IS_ERR(pdev)) { + printk(KERN_ERR "usb: can't register %s Host, %ld\n", + config->name, PTR_ERR(pdev)); + return NULL; + } + + pdev->dev.coherent_dma_mask = 0xffffffff; + pdev->dev.dma_mask = &ehci_dmamask; + + /* + * platform_device_add_data() makes a copy of + * the platform_data passed in. That makes it + * impossible to share the same config struct for + * all OTG devices (host,gadget,otg). So, just + * set the platform_data pointer ourselves. + */ + pdev->dev.platform_data = config; + + printk(KERN_INFO "usb: %s Host registered\n", config->name); + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); + + instance_id++; + + return pdev; +} + + +int fsl_usb_mem_init(struct platform_device *pdev) +{ + struct resource *res; + struct fsl_usb2_platform_data *pdata; + + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __FUNCTION__, pdev, pdata); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no MEM resource.\n"); + return -ENODEV; + } + + pdata->r_start = res->start; + pdata->r_len = res->end - res->start + 1; + pr_debug("%s: MEM resource start=0x%x len=0x%x\n", pdata->name, + res->start, pdata->r_len); + + if (!request_mem_region(pdata->r_start, pdata->r_len, "OTG")) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + return -EBUSY; + } + pdata->regs = ioremap(pdata->r_start, pdata->r_len); + pr_debug("ioremapped to 0x%p\n", pdata->regs); + + if (pdata->regs == NULL) { + dev_err(&pdev->dev, "ioremap failed\n"); + release_mem_region(pdata->r_start, pdata->r_len); + return -EFAULT; + } + + pr_debug("%s: success\n", __FUNCTION__); + return 0; +} + + +#if defined(CONFIG_USB_OTG) +static struct otg_transceiver *xceiv; + +/** + * otg_get_transceiver - find the (single) OTG transceiver driver + * + * Returns the transceiver driver, after getting a refcount to it; or + * null if there is no such transceiver. The caller is responsible for + * releasing that count. + */ +struct otg_transceiver *otg_get_transceiver(void) +{ + pr_debug("%s xceiv=0x%p\n", __FUNCTION__, xceiv); + if (xceiv) + get_device(xceiv->dev); + return xceiv; +} +EXPORT_SYMBOL(otg_get_transceiver); + +int otg_set_transceiver(struct otg_transceiver *x) +{ + pr_debug("%s xceiv=0x%p x=0x%p\n", __FUNCTION__, xceiv, x); + if (xceiv && x) + return -EBUSY; + xceiv = x; + return 0; +} +EXPORT_SYMBOL(otg_set_transceiver); +#endif diff --git a/arch/m68k/coldfire/usb/Makefile b/arch/m68k/coldfire/usb/Makefile new file mode 100644 index 000000000000..f40c136b773b --- /dev/null +++ b/arch/m68k/coldfire/usb/Makefile @@ -0,0 +1,28 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +ifneq ($(CONFIG_USB_EHCI_HCD),) + obj-y += otg_host.o +endif + +ifneq ($(CONFIG_USB_GADGET_MCF5445X),) + obj-y += otg_device.o +endif + +ifneq ($(strip $(CONFIG_USB_GADGET_MCF5445X) $(CONFIG_USB_EHCI_HCD)),) + obj-y += otg_cmn.o +endif + +ifneq ($(CONFIG_USB_OTG),) + obj-y += otg_otg.o +endif + + +# USB Transceiver driver: +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),) + obj-y += xcvr.o +endif + diff --git a/arch/m68k/coldfire/usb/otg_cmn.c b/arch/m68k/coldfire/usb/otg_cmn.c new file mode 100644 index 000000000000..e1975fab0340 --- /dev/null +++ b/arch/m68k/coldfire/usb/otg_cmn.c @@ -0,0 +1,106 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern void fsl_usb_enable_clk(void); +extern void fsl_usb_disable_clk(void); +extern int fsl_usb_mem_init(struct platform_device *pdev); + +extern struct fsl_xcvr_ops *xc_ops[]; + +static int otg_used; + +int usbotg_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata; + struct fsl_xcvr_ops *xops = xc_ops[USB_CTRLR_OTG]; + int rc; + + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __FUNCTION__, pdev, pdata); + + if (!xops) { + printk(KERN_ERR "OTG transceiver ops missing\n"); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + + if (!otg_used) { + /* request_mem_region and ioremap registers */ + rc = fsl_usb_mem_init(pdev); + if (rc) + return rc; + + fsl_usb_enable_clk(); + + if (xops->init) + xops->init(pdev); + } + + otg_used++; + pr_debug("%s: success\n", __FUNCTION__); + return 0; +} + +void usbotg_uninit(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata; + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data; + + pr_debug("%s\n", __FUNCTION__); + + otg_used--; + if (!otg_used) { + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdev); + + iounmap(pdata->regs); + release_mem_region(pdata->r_start, pdata->r_len); + + pdata->regs = NULL; + pdata->r_start = pdata->r_len = 0; + + fsl_usb_disable_clk(); + } +} + +struct fsl_usb2_platform_data mxc_otg_config = { + .name = "OTG", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .es = 1, + .big_endian_mmio = 1, + .big_endian_desc = 1, + .le_setup_buf = 1, + .does_otg = 1, + .power_budget = 500, /* 500 mA max power */ + .max_ep_nr = 4, /* DDD read from a register ? */ + .phy_mode = FSL_USB2_PHY_ULPI, /* DDD redundant with xcvr_type */ +}; diff --git a/arch/m68k/coldfire/usb/otg_device.c b/arch/m68k/coldfire/usb/otg_device.c new file mode 100644 index 000000000000..3795f933c187 --- /dev/null +++ b/arch/m68k/coldfire/usb/otg_device.c @@ -0,0 +1,89 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000) +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */ +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern struct fsl_usb2_platform_data mxc_otg_config; + +struct platform_device otg_udc_device; + +/*! + * OTG Gadget device + */ + +static void usb_release(struct device *dev) +{ + /* normally not freed */ +} + +static u64 udc_dmamask = ~(u32) 0; +static struct resource otg_udc_resources[] = { + [0] = { + .start = (u32) (&USB_OTGREGS_BASE), + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + + +struct platform_device otg_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = usb_release, + .dma_mask = &udc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mxc_otg_config, + }, + .resource = otg_udc_resources, + .num_resources = ARRAY_SIZE(otg_udc_resources), +}; + +static int __init udc_init(void) +{ + int rc __attribute((unused)); + + rc = platform_device_register(&otg_udc_device); + if (rc) + printk(KERN_ERR "usb: can't register OTG Gadget, rc=%d\n", rc); + else + printk(KERN_INFO "usb: OTG Gadget registered\n"); + return rc; +} + +subsys_initcall(udc_init); diff --git a/arch/m68k/coldfire/usb/otg_host.c b/arch/m68k/coldfire/usb/otg_host.c new file mode 100644 index 000000000000..506a3faad4e5 --- /dev/null +++ b/arch/m68k/coldfire/usb/otg_host.c @@ -0,0 +1,68 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000) +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */ +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */ + +struct platform_device *otg_host_device; + +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, + struct fsl_usb2_platform_data + *config); + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern struct fsl_usb2_platform_data mxc_otg_config; + +/*! + * OTG host config + */ +static struct resource otg_host_resources[] = { + [0] = { + .start = (u32) (&USB_OTGREGS_BASE), + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init otg_host_init(void) +{ + otg_host_device = host_pdev_register(otg_host_resources, + ARRAY_SIZE(otg_host_resources), + &mxc_otg_config); + return 0; +} + +subsys_initcall(otg_host_init); diff --git a/arch/m68k/coldfire/usb/otg_otg.c b/arch/m68k/coldfire/usb/otg_otg.c new file mode 100644 index 000000000000..b1ca8bb1280e --- /dev/null +++ b/arch/m68k/coldfire/usb/otg_otg.c @@ -0,0 +1,96 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * platform_device registration for ULPI OTG device + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000) +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */ +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern struct fsl_usb2_platform_data mxc_otg_config; + +static void otg_otg_release(struct device *dev) +{ + /* normally not freed */ +} + +/* *INDENT-OFF* */ +static struct resource otg_otg_resources[] = { + [0] = { + .start = (u32) (&USB_OTGREGS_BASE), + .end = (u32) (&USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! + * OTG device + */ +static u64 otg_otg_dmamask = ~(u32) 0; +static struct platform_device otg_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = otg_otg_release, + .dma_mask = &otg_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mxc_otg_config, + }, + .resource = otg_otg_resources, + .num_resources = ARRAY_SIZE(otg_otg_resources), +}; +/* *INDENT-ON* */ + +static int __init mx31_otg_otg_init(void) +{ + int rc = 0; + + pr_debug("register OTG otg res=0x%p, size=%d\n", + otg_otg_device.resource, otg_otg_device.num_resources); + + rc = platform_device_register(&otg_otg_device); + if (rc) { + pr_debug("can't register ULPI OTG dvc, %d\n", rc); + } else { + printk(KERN_INFO "usb: OTG ULPI transceiver registered\n"); + pr_debug("otg_otg_device=0x%p resources=0x%p.\n", + &otg_otg_device, otg_otg_device.resource); + } + + return rc; +} + +subsys_initcall(mx31_otg_otg_init); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ULPI OTG device registration"); +MODULE_LICENSE("GPL"); diff --git a/arch/m68k/coldfire/usb/xcvr.c b/arch/m68k/coldfire/usb/xcvr.c new file mode 100644 index 000000000000..dd4c84f11ad4 --- /dev/null +++ b/arch/m68k/coldfire/usb/xcvr.c @@ -0,0 +1,156 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); +extern void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr); + +#define MCF_SCM_BCR MCF_REG32(0xFC040024) +#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */ +#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */ +#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */ + + +#ifdef ULPI_DEBUG +void print_ulpi_regs(void) +{ + pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x " + "MCF_GPIO_PAR_DMA=0x%08x MCF_GPIO_PAR_USB=08%08x " + "MCF_GPIO_PAR_FEC=08%08x\n", + MCF_SCM_BCR, MCF_CCM_MISCCR, MCF_GPIO_PAR_DMA, + MCF_GPIO_PAR_USB, MCF_GPIO_PAR_FEC); +} +EXPORT_SYMBOL(print_ulpi_regs); +#endif + + +static void xcvr_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *this = pdata->xcvr_ops; + struct fsl_usb_host_regs *regs = pdata->regs; + + pr_debug("%s: ctrlr=%d pdata=0x%p regs=0x%p\n", __FUNCTION__, + this->ctrlr, pdata, pdata->regs); + + /* enable USB read, write and slave bursts */ + MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL; + + /* Use external clock source if PLL isn't a multiple of 60MHz */ + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC; + + /* Initialize the USB Clock: use USB input clock */ + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & MCF_GPIO_PAR_DMA_DREQ1_MASK) | + MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN; + + switch (this->xcvr_type) { + case PORTSCX_PTS_ULPI: + /* Enable the required ULPI signals */ + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & + MCF_GPIO_PAR_DMA_DACK1_MASK) | + MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR; + + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT | + MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP; + + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & + MCF_GPIO_PAR_FEC_FEC0_MASK) | + MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI; + break; + case PORTSCX_PTS_ONCHIP: + /* Enable VBUS_EN and VBUS_OC signals */ + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_VBUSEN | + MCF_GPIO_PAR_USB_VBUSOC_VBUSOC; + + /* Setup USB_VBUS_OC signal to be active-low */ + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBOC; + + break; + } + + pr_debug("®s->portsc1=0x%p old portsc1=0x%x \n", ®s->portsc1, + regs->portsc1); + + regs->portsc1 &= ~PORTSCX_PTS_MASK; + regs->portsc1 |= this->xcvr_type; + + /* + * need to reset the controller here so that the ID pin + * is correctly detected. + */ + regs->usbcmd |= USB_CMD_CTRL_RESET; + + /* + * allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + mdelay(10); + + pr_debug("DDD %s: done. portsc1=0x%x\n", __FUNCTION__, regs->portsc1); +} + +static void xcvr_uninit(struct platform_device *pdev) +{ + pr_debug("%s: pdev=0x%p\n", __FUNCTION__, pdev); +} + + +struct fsl_xcvr_ops xcvr_ops_otg = { + .ctrlr = USB_CTRLR_OTG, + .init = xcvr_init, + .uninit = xcvr_uninit, + +#ifdef CONFIG_USB_M5445X_ULPI + .xcvr_type = PORTSCX_PTS_ULPI, +#elif defined CONFIG_USB_M5445X_FSLS + .xcvr_type = PORTSCX_PTS_ONCHIP, +#else +#error "Invalid USB transceiver selection." +#endif +}; + +static int __init usb_xcvr_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&xcvr_ops_otg); + + pr_debug("%s done\n", __FUNCTION__); + return 0; +} + +static void __exit usb_xcvr_exit(void) +{ + fsl_usb_xcvr_unregister(USB_CTRLR_OTG); +} + +module_init(usb_xcvr_init); +module_exit(usb_xcvr_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("External ULPI xcvr driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/m68k/configs/m5484lite_defconfig b/arch/m68k/configs/m5484lite_defconfig new file mode 100644 index 000000000000..e9b5edcc6a82 --- /dev/null +++ b/arch/m68k/configs/m5484lite_defconfig @@ -0,0 +1,117 @@ +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_START=0xff800000 +# CONFIG_MTD_PHYSMAP_COMPAT=y +# CONFIG_MTD_PHYSMAP_LEN=0x400000 +# CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_DMADEVICES=y +CONFIG_CFDMA=y +CONFIG_FPU=y +# CONFIG_M5474LITE is not set +CONFIG_M5484LITE=y +# CONFIG_M5441X is not set +# CONFIG_VDSO is not set +CONFIG_BROADCOM5222_PHY=y +# CONFIG_8139TOO is not set +CONFIG_ADVANCED=y +# CONFIG_AMIGA is not set +# CONFIG_APOLLO is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_AOUT=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ATARI is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BITREVERSE=y +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="console=ttyS0,115200 mtdparts=phys_mapped_flash:4m(Boot)" +CONFIG_BOUNCE=y +CONFIG_CFV4E=y +CONFIG_CLASSIC_RCU=y +# CONFIG_COLDFIRE_EDMA is not set +# CONFIG_COLDFIRE_WATCHDOG is not set +CONFIG_COLDFIRE=y +CONFIG_FEC_DMA_AUTO_NEGOTIATION=y +CONFIG_FEC_DMA_ENABLE_FEC2=y +CONFIG_FEC_DMA=y +CONFIG_FEC_DMA_SHARED_PHY=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_GENERIC_IOMAP=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GEN_RTC is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_IDE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HP300 is not set +CONFIG_HW_RANDOM=y +# CONFIG_IDE is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LEDS_ALIX is not set +# CONFIG_M5445X is not set +# CONFIG_M5475AFE is not set +# CONFIG_M5475BFE is not set +# CONFIG_M5475CFE is not set +# CONFIG_M5475DFE is not set +# CONFIG_M5475EFE is not set +# CONFIG_M5475FFE is not set +CONFIG_M547X_8X=y +# CONFIG_M547X is not set +# CONFIG_M5485AFE is not set +# CONFIG_M5485BFE is not set +# CONFIG_M5485CFE is not set +# CONFIG_M5485DFE is not set +# CONFIG_M5485EFE is not set +# CONFIG_M5485FFE is not set +CONFIG_M548X=y +# CONFIG_M68020 is not set +# CONFIG_M68030 is not set +# CONFIG_M68040 is not set +# CONFIG_M68060 is not set +# CONFIG_M68KFPU_EMU is not set +CONFIG_M68K=y +# CONFIG_MAC is not set +CONFIG_MCD_DMA=y +CONFIG_MCFCLK=200000000 +CONFIG_MCF_USER_HALT=y +# CONFIG_MEMSTICK is not set +CONFIG_MMU_CFV4E=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_NE2K_PCI is not set +CONFIG_NEED_MULTIPLE_NODES=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NO_DMA is not set +# CONFIG_NO_IOPORT is not set +CONFIG_NOR_FLASH_BASE=0xFF800000 +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PROC_HARDWARE is not set +# CONFIG_Q40 is not set +# CONFIG_R6040 is not set +# CONFIG_RMW_INSNS is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SDRAM_BASE=0x00000000 +CONFIG_SDRAM_SIZE=0x04000000 +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_COLDFIRE_IRDA is not set +# CONFIG_SERIAL_COLDFIRE is not set +# CONFIG_SERIAL_CONSOLE is not set +CONFIG_SERIAL_MCF=y +# CONFIG_SERIAL_COLDFIRE_EDMA is not set +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +CONFIG_SINGLE_MEMORY_CHUNK=y +CONFIG_SLABINFO=y +# CONFIG_SUN3 is not set +# CONFIG_SUN3X is not set +CONFIG_TIME_LOW_RES=y +CONFIG_UID16=y +# CONFIG_VGASTATE is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VME is not set +CONFIG_UBOOT=y diff --git a/arch/m68k/configs/mcf5484lite_defconfig b/arch/m68k/configs/mcf5484lite_defconfig new file mode 100644 index 000000000000..aa021b4439c9 --- /dev/null +++ b/arch/m68k/configs/mcf5484lite_defconfig @@ -0,0 +1,179 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="-mcf" +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_START=0xff800000 +# CONFIG_MTD_PHYSMAP_COMPAT=y +# CONFIG_MTD_PHYSMAP_LEN=0x400000 +# CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_DMADEVICES=y +CONFIG_CFDMA=y +CONFIG_FPU=y +# CONFIG_M5474LITE is not set +CONFIG_M5484LITE=y +# CONFIG_M5441X is not set +# CONFIG_VDSO is not set +CONFIG_BROADCOM5222_PHY=y +# CONFIG_8139TOO is not set +CONFIG_ADVANCED=y +# CONFIG_AMIGA is not set +# CONFIG_APOLLO is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_AOUT=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ATARI is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BITREVERSE=y +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="console=ttyS0,115200 mtdparts=phys_mapped_flash:4m(Boot)" +CONFIG_BOUNCE=y +CONFIG_CFV4E=y +CONFIG_CLASSIC_RCU=y +# CONFIG_COLDFIRE_EDMA is not set +# CONFIG_COLDFIRE_WATCHDOG is not set +CONFIG_COLDFIRE=y +CONFIG_FEC_DMA_AUTO_NEGOTIATION=y +CONFIG_FEC_DMA_ENABLE_FEC2=y +CONFIG_FEC_DMA=y +CONFIG_FEC_DMA_SHARED_PHY=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_GENERIC_IOMAP=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GEN_RTC is not set +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_IDE=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_OPROFILE is not set +# CONFIG_HP300 is not set +CONFIG_HW_RANDOM=y +# CONFIG_IDE is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_LEDS_ALIX is not set +# CONFIG_M5445X is not set +# CONFIG_M5475AFE is not set +# CONFIG_M5475BFE is not set +# CONFIG_M5475CFE is not set +# CONFIG_M5475DFE is not set +# CONFIG_M5475EFE is not set +# CONFIG_M5475FFE is not set +CONFIG_M547X_8X=y +# CONFIG_M547X is not set +# CONFIG_M5485AFE is not set +# CONFIG_M5485BFE is not set +# CONFIG_M5485CFE is not set +# CONFIG_M5485DFE is not set +# CONFIG_M5485EFE is not set +# CONFIG_M5485FFE is not set +CONFIG_M548X=y +# CONFIG_M68020 is not set +# CONFIG_M68030 is not set +# CONFIG_M68040 is not set +# CONFIG_M68060 is not set +# CONFIG_M68KFPU_EMU is not set +CONFIG_M68K=y +# CONFIG_MAC is not set +CONFIG_MCD_DMA=y +CONFIG_MCFCLK=200000000 +CONFIG_MCF_USER_HALT=y +# CONFIG_MEMSTICK is not set +CONFIG_MMU_CFV4E=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_NE2K_PCI is not set +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NO_DMA is not set +# CONFIG_NO_IOPORT is not set +CONFIG_NOR_FLASH_BASE=0xFF800000 +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PROC_HARDWARE is not set +# CONFIG_Q40 is not set +# CONFIG_R6040 is not set +# CONFIG_RMW_INSNS is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SDRAM_BASE=0x00000000 +CONFIG_SDRAM_SIZE=0x04000000 +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_COLDFIRE_IRDA is not set +# CONFIG_SERIAL_COLDFIRE is not set +# CONFIG_SERIAL_CONSOLE is not set +CONFIG_SERIAL_MCF=y +# CONFIG_SERIAL_COLDFIRE_EDMA is not set +CONFIG_SERIAL_MCF_BAUDRATE=115200 +CONFIG_SERIAL_MCF_CONSOLE=y +CONFIG_SINGLE_MEMORY_CHUNK=y +CONFIG_SLABINFO=y +# CONFIG_SUN3 is not set +# CONFIG_SUN3X is not set +CONFIG_TIME_LOW_RES=y +CONFIG_UBOOT=y +CONFIG_UID16=y +# CONFIG_VGASTATE is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VME is not set diff --git a/arch/m68k/include/asm/MCD_dma.h b/arch/m68k/include/asm/MCD_dma.h new file mode 100644 index 000000000000..963bf6eade59 --- /dev/null +++ b/arch/m68k/include/asm/MCD_dma.h @@ -0,0 +1,408 @@ +/********************************************************************* + * + * Copyright (C) 2004 Motorola, Inc. + * MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use + * the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + ********************************************************************/ + +/* + * File: MCD_dma.h + * Purpose: Main header file for multi-channel DMA API. + * + * Notes: + * + * Modifications: + */ +#ifndef _MCD_API_H +#define _MCD_API_H + +#include + +/* + * Turn Execution Unit tasks ON (#define) or OFF (#undef) + */ +#undef MCD_INCLUDE_EU + +/* + * Number of DMA channels + */ +#define NCHANNELS 16 + +/* + * Total number of variants + */ +#ifdef MCD_INCLUDE_EU +#define NUMOFVARIANTS 6 +#else +#define NUMOFVARIANTS 4 +#endif + +/* + * Define sizes of the various tables + */ +#define TASK_TABLE_SIZE (NCHANNELS*32) +#define VAR_TAB_SIZE (128) +#define CONTEXT_SAVE_SIZE (128) +#define FUNCDESC_TAB_SIZE (256) + +#ifdef MCD_INCLUDE_EU +#define FUNCDESC_TAB_NUM 16 +#else +#define FUNCDESC_TAB_NUM 1 +#endif + + +#ifndef DEFINESONLY + +/* + * Portability typedefs + */ + /* +#ifndef s32 +typedef int s32; +#endif +#ifndef u32 +typedef unsigned int u32; +#endif +#ifndef s16 +typedef short s16; +#endif +#ifndef u16 +typedef unsigned short u16; +#endif +#ifndef s8 +typedef char s8; +#endif +#ifndef u8 +typedef unsigned char u8; +#endif +*/ +/* + * These structures represent the internal registers of the + * multi-channel DMA + */ +struct dmaRegs_s { + u32 taskbar; /* task table base address register */ + u32 currPtr; + u32 endPtr; + u32 varTablePtr; + u16 dma_rsvd0; + u16 ptdControl; /* ptd control */ + u32 intPending; /* interrupt pending register */ + u32 intMask; /* interrupt mask register */ + u16 taskControl[16]; /* task control registers */ + u8 priority[32]; /* priority registers */ + u32 initiatorMux; /* initiator mux control */ + u32 taskSize0; /* task size control register 0. */ + u32 taskSize1; /* task size control register 1. */ + u32 dma_rsvd1; /* reserved */ + u32 dma_rsvd2; /* reserved */ + u32 debugComp1; /* debug comparator 1 */ + u32 debugComp2; /* debug comparator 2 */ + u32 debugControl; /* debug control */ + u32 debugStatus; /* debug status */ + u32 ptdDebug; /* priority task decode debug */ + u32 dma_rsvd3[31]; /* reserved */ +}; +typedef volatile struct dmaRegs_s dmaRegs; + +#endif + +/* + * PTD contrl reg bits + */ +#define PTD_CTL_TSK_PRI 0x8000 +#define PTD_CTL_COMM_PREFETCH 0x0001 + +/* + * Task Control reg bits and field masks + */ +#define TASK_CTL_EN 0x8000 +#define TASK_CTL_VALID 0x4000 +#define TASK_CTL_ALWAYS 0x2000 +#define TASK_CTL_INIT_MASK 0x1f00 +#define TASK_CTL_ASTRT 0x0080 +#define TASK_CTL_HIPRITSKEN 0x0040 +#define TASK_CTL_HLDINITNUM 0x0020 +#define TASK_CTL_ASTSKNUM_MASK 0x000f + +/* + * Priority reg bits and field masks + */ +#define PRIORITY_HLD 0x80 +#define PRIORITY_PRI_MASK 0x07 + +/* + * Debug Control reg bits and field masks + */ +#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 +#define DBG_CTL_AUTO_ARM 0x00008000 +#define DBG_CTL_BREAK 0x00004000 +#define DBG_CTL_COMP1_TYP_MASK 0x00003800 +#define DBG_CTL_COMP2_TYP_MASK 0x00000070 +#define DBG_CTL_EXT_BREAK 0x00000004 +#define DBG_CTL_INT_BREAK 0x00000002 + +/* + * PTD Debug reg selector addresses + * This reg must be written with a value to show the contents of + * one of the desired internal register. + */ +#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ +#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and + have initiators asserted */ + + +/* + * General return values + */ +#define MCD_OK 0 +#define MCD_ERROR -1 +#define MCD_TABLE_UNALIGNED -2 +#define MCD_CHANNEL_INVALID -3 + +/* + * MCD_initDma input flags + */ +#define MCD_RELOC_TASKS 0x00000001 +#define MCD_NO_RELOC_TASKS 0x00000000 +#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ + +/* + * MCD_dmaStatus Status Values for each channel + */ +#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ +#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ +#define MCD_PAUSED 4 /* DMA active but it is currently paused */ +#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ +#define MCD_DONE 6 /* the most recent DMA has completed. */ + + +/* + * MCD_startDma parameter defines + */ + +/* + * Constants for the funcDesc parameter + */ +/* Byte swapping: */ +#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ +#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ +#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of + each 32-bit data value being DMAed.*/ +#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each + 16-bit half of each 32-bit data value DMAed */ +#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ +#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ +/* CRCing: */ +#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ +#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ +#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ +#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ +#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ + +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) + +/* + * Constants for the flags parameter + */ +#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ +#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ +#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ +#define MCD_TT_FLAGS_MASK 0x000000ff +#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) + +#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ +#define MCD_CHAIN_DMA /* TBD */ +#define MCD_EU_DMA /* TBD */ +#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ +#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ + + +/* these flags are valid for MCD_startDma and the chained buffer descriptors */ +#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ +#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ +#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ +#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring + last byte of data in buffer */ +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum + prior to performing the DMA. */ + +/* Defines for the FEC buffer descriptor control/status word*/ +#define MCD_FEC_BUF_READY 0x8000 +#define MCD_FEC_WRAP 0x2000 +#define MCD_FEC_INTERRUPT 0x1000 +#define MCD_FEC_END_FRAME 0x0800 + + +/* + * Defines for general intuitiveness + */ + +#define MCD_TRUE 1 +#define MCD_FALSE 0 + +/* + * Three different cases for destination and source. + */ +#define MINUS1 -1 +#define ZERO 0 +#define PLUS1 1 + +#ifndef DEFINESONLY + +/* Task Table Entry struct*/ +typedef struct { + u32 TDTstart; /* task descriptor table start */ + u32 TDTend; /* task descriptor table end */ + u32 varTab; /* variable table start */ + u32 FDTandFlags; /* function descriptor table start and flags */ + volatile u32 descAddrAndStatus; + volatile u32 modifiedVarTab; + u32 contextSaveSpace; /* context save space start */ + u32 literalBases; +} TaskTableEntry; + + +/* Chained buffer descriptor */ +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +struct MCD_bufDesc_struct { + u32 flags; /* flags describing the DMA */ + u32 csumResult; /* checksum from checksumming performed since last checksum reset */ + s8 *srcAddr; /* the address to move data from */ + s8 *destAddr; /* the address to move data to */ + s8 *lastDestAddr; /* the last address written to */ + u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ + MCD_bufDesc *next; /* next buffer descriptor in chain */ + u32 info; /* private information about this descriptor; DMA does not affect it */ +}; + +/* Progress Query struct */ +typedef volatile struct MCD_XferProg_struct { + s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ + s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ + u32 dmaSize; /* the amount of data transferred for the current buffer */ + MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ +} MCD_XferProg; + + +/* FEC buffer descriptor */ +typedef volatile struct MCD_bufDescFec_struct { + u16 statCtrl; + u16 length; + u32 dataPointer; +} MCD_bufDescFec; + + +/*************************************************************************/ +/* + * API function Prototypes - see MCD_dmaApi.c for further notes + */ + +/* + * MCD_startDma starts a particular kind of DMA . + */ +int MCD_startDma ( + int channel, /* the channel on which to run the DMA */ + s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ + s16 srcIncr, /* the amount to increment the source address per transfer */ + s8 *destAddr, /* the address to move data to */ + s16 destIncr, /* the amount to increment the destination address per transfer */ + u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ + u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ + u32 initiator, /* what device initiates the DMA */ + int priority, /* priority of the DMA */ + u32 flags, /* flags describing the DMA */ + u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +); + +/* + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA + * registers, relocating and creating the appropriate task structures, and + * setting up some global settings + */ +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); + +/* + * MCD_dmaStatus() returns the status of the DMA on the requested channel. + */ +int MCD_dmaStatus (int channel); + +/* + * MCD_XferProgrQuery() returns progress of DMA on requested channel + */ +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); + +/* + * MCD_killDma() halts the DMA on the requested channel, without any + * intention of resuming the DMA. + */ +int MCD_killDma (int channel); + +/* + * MCD_continDma() continues a DMA which as stopped due to encountering an + * unready buffer descriptor. + */ +int MCD_continDma (int channel); + +/* + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is + * running on that channel). + */ +int MCD_pauseDma (int channel); + +/* + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is + * running on that channel). + */ +int MCD_resumeDma (int channel); + +/* + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA + */ +int MCD_csumQuery (int channel, u32 *csum); + +/* + * MCD_getCodeSize provides the packed size required by the microcoded task + * and structures. + */ +int MCD_getCodeSize(void); + +/* + * MCD_getVersion provides a pointer to a version string and returns a + * version number. + */ +int MCD_getVersion(char **longVersion); + +/* macro for setting a location in the variable table */ +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value + /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, + so I'm avoiding surrounding it with "do {} while(0)" */ + +#endif /* DEFINESONLY */ + +#endif /* _MCD_API_H */ diff --git a/arch/m68k/include/asm/bitops_coldfire.h b/arch/m68k/include/asm/bitops_coldfire.h index b974269141b9..54fc46c44ca9 100644 --- a/arch/m68k/include/asm/bitops_coldfire.h +++ b/arch/m68k/include/asm/bitops_coldfire.h @@ -322,6 +322,11 @@ found_middle: #ifdef __KERNEL__ +/* + * fls: find last bit set. + */ + + /* Ported from include/linux/bitops.h */ static __inline__ int fls(int x) { @@ -352,6 +357,12 @@ static __inline__ int fls(int x) return r; } +static inline int __fls(int x) +{ + return fls(x) - 1; +} + + #include #include #include diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h index e5a28c67c45e..6957995282f9 100644 --- a/arch/m68k/include/asm/cacheflush.h +++ b/arch/m68k/include/asm/cacheflush.h @@ -6,9 +6,9 @@ # ifdef CONFIG_COLDFIRE # ifdef CONFIG_M5445X -# include "mcf_5445x_cacheflush.h" +# include "mcf_cacheflush_5445x.h" # else -# include "mcf_548x_cacheflush.h" +# include "mcf_cacheflush_m547x_8x.h" # endif # else //CONFIG_COLDFIRE # include "cacheflush_mm.h" diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 7085bd51668b..d9c8b6894e4c 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -29,7 +29,7 @@ static inline void __flush_cache_all(void) { -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) /* * Use cpushl to push and invalidate all cache lines. * Gas doesn't seem to know how to generate the ColdFire diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h index 3b0a34d0fe33..b60896840a03 100644 --- a/arch/m68k/include/asm/coldfire.h +++ b/arch/m68k/include/asm/coldfire.h @@ -20,25 +20,76 @@ * at config time too. */ #ifdef CONFIG_CLOCK_SET + #define MCF_CLK CONFIG_CLOCK_FREQ #define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) + #else -#error "Don't know what your ColdFire CPU clock frequency is??" + +#define MCF_CLK CONFIG_MCFCLK +#define MCF_BUSCLK (CONFIG_MCFCLK/2) + #endif -/* - * Define the processor support peripherals base address. - * This is generally setup by the boards start up code. - */ -#define MCF_MBAR 0x10000000 -#define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M548x) +#if defined(CONFIG_M547X_8X) #define MCF_IPSBAR MCF_MBAR #elif defined(CONFIG_M520x) #define MCF_IPSBAR 0xFC000000 #else #define MCF_IPSBAR 0x40000000 #endif + +#if defined(CONFIG_M5445X) +#define MCF_MBAR 0x0 +/* + * Even though RAMBAR1 macro should be in the 0x8xxxxxxx range, + * here set the CONFIG_SDRAM_BASE value to it to use + * SDRAM memory, not SRAM memory. + */ +#define MCF_RAMBAR1 (CONFIG_SDRAM_BASE) +#elif defined(CONFIG_M547X_8X) +#define MCF_MBAR 0xF0000000 +#define MCF_MMUBAR 0xF1000000 +#define MCF_RAMBAR0 0xF3000000 +#define MCF_RAMBAR1 0xF3001000 +#else +/* +* Define the processor support peripherals base address. +* This is generally setup by the boards start up code. +*/ +#define MCF_MBAR 0x10000000 +#define MCF_MBAR2 0x80000000 +#endif + +#ifdef __ASSEMBLY__ +#define REG32 +#define REG16 +#define REG08 +#else /* __ASSEMBLY__ */ +#define REG32(x) ((volatile unsigned long *)(x)) +#define REG16(x) ((volatile unsigned short *)(x)) +#define REG08(x) ((volatile unsigned char *)(x)) + +#define MCF_REG32(x) *(volatile unsigned long *)(MCF_MBAR+(x)) +#define MCF_REG16(x) *(volatile unsigned short *)(MCF_MBAR+(x)) +#define MCF_REG08(x) *(volatile unsigned char *)(MCF_MBAR+(x)) + +void cacr_set(unsigned long); +unsigned long cacr_get(void); + +#define coldfire_enable_irq0(irq) MCF_INTC0_CIMR = (irq); + +#define coldfire_enable_irq1(irq) MCF_INTC1_CIMR = (irq); + +#define coldfire_disable_irq0(irq) MCF_INTC0_SIMR = (irq); + +#define coldfire_disable_irq1(irq) MCF_INTC1_SIMR = (irq); + +#define getiprh() MCF_INTC0_IPRH + +#endif /* __ASSEMBLY__ */ + + #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h index edb66148a71d..ba62e1789dfe 100644 --- a/arch/m68k/include/asm/div64.h +++ b/arch/m68k/include/asm/div64.h @@ -1,7 +1,8 @@ #ifndef _M68K_DIV64_H #define _M68K_DIV64_H -#ifdef CONFIG_MMU +//no support in Coldfire +#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE) #include diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h index 6fbdfe895104..34a429bd9132 100644 --- a/arch/m68k/include/asm/dma.h +++ b/arch/m68k/include/asm/dma.h @@ -479,13 +479,109 @@ static __inline__ int get_dma_residue(unsigned int dmanr) /* it's useless on the m68k, but unfortunately needed by the new bootmem allocator (but this should do it for this) */ + +#if defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X) +#define MAX_DMA_ADDRESS 0xEFFFFFFF +#else #define MAX_DMA_ADDRESS PAGE_OFFSET +#endif + +#ifndef CONFIG_COLDFIRE #define MAX_DMA_CHANNELS 8 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ extern void free_dma(unsigned int dmanr); /* release it again */ +#else /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) + || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */ +/************************************************ + * Multichannel DMA definitions * + ************************************************/ +#ifdef CONFIG_MCD_DMA +#include +#include + +struct scatterlist; + +#define MAX_DMA_CHANNELS NCHANNELS +/* + * identifiers for each initiator/requestor + */ +#define DMA_ALWAYS (0) +#define DMA_DSPI_RX (1) +#define DMA_DSPI_TX (2) +#define DMA_DREQ0 (3) +#define DMA_PSC0_RX (4) +#define DMA_PSC0_TX (5) +#define DMA_USBEP0 (6) +#define DMA_USBEP1 (7) +#define DMA_USBEP2 (8) +#define DMA_USBEP3 (9) +#define DMA_PCI_TX (10) +#define DMA_PCI_RX (11) +#define DMA_PSC1_RX (12) +#define DMA_PSC1_TX (13) +#define DMA_I2C_RX (14) +#define DMA_I2C_TX (15) +#define DMA_FEC0_RX (16) +#define DMA_FEC0_TX (17) +#define DMA_FEC1_RX (18) +#define DMA_FEC1_TX (19) +#define DMA_DREQ1 (20) +#define DMA_CTM0 (21) +#define DMA_CTM1 (22) +#define DMA_CTM2 (23) +#define DMA_CTM3 (24) +#define DMA_CTM4 (25) +#define DMA_CTM5 (26) +#define DMA_CTM6 (27) +#define DMA_CTM7 (28) +#define DMA_USBEP4 (29) +#define DMA_USBEP5 (30) +#define DMA_USBEP6 (31) +#define DMA_PSC2_RX (32) +#define DMA_PSC2_TX (33) +#define DMA_PSC3_RX (34) +#define DMA_PSC3_TX (35) +#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX) +#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX) + +int dma_set_initiator(int); +unsigned int dma_get_initiator(int); +void dma_remove_initiator(int); +int dma_set_channel(int); +int dma_get_channel(int); +void dma_remove_channel(int); +int dma_set_channel_fec(int requestor); +int dma_connect(int channel, int address); +int dma_disconnect(int channel); +void dma_remove_channel_by_number(int channel); +int dma_init(void); +#endif /* CONFIG_MCD_DMA */ + +extern spinlock_t dma_spin_lock; + +static __inline__ unsigned long claim_dma_lock(void) +{ + unsigned long flags; + spin_lock_irqsave(&dma_spin_lock, flags); + return flags; +} + +static __inline__ void release_dma_lock(unsigned long flags) +{ + spin_unlock_irqrestore(&dma_spin_lock, flags); +} + + + +#define clear_dma_ff(channel) + +#endif + + #define isa_dma_bridge_buggy (0) + #endif /* _M68K_DMA_H */ diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h index 36c099db73fd..b3425053410c 100644 --- a/arch/m68k/include/asm/elf.h +++ b/arch/m68k/include/asm/elf.h @@ -34,7 +34,26 @@ #define R_68K_GLOB_DAT 20 #define R_68K_JMP_SLOT 21 #define R_68K_RELATIVE 22 - +/* TLS static relocations */ +#define R_68K_TLS_GD32 25 +#define R_68K_TLS_GD16 26 +#define R_68K_TLS_GD8 27 +#define R_68K_TLS_LDM32 28 +#define R_68K_TLS_LDM16 29 +#define R_68K_TLS_LDM8 30 +#define R_68K_TLS_LDO32 31 +#define R_68K_TLS_LDO16 32 +#define R_68K_TLS_LDO8 33 +#define R_68K_TLS_IE32 34 +#define R_68K_TLS_IE16 35 +#define R_68K_TLS_IE8 36 +#define R_68K_TLS_LE32 37 +#define R_68K_TLS_LE16 38 +#define R_68K_TLS_LE8 39 +/* TLS dynamic relocations */ +#define R_68K_TLS_DTPMOD32 40 +#define R_68K_TLS_DTPREL32 41 +#define R_68K_TLS_TPREL32 42 typedef unsigned long elf_greg_t; #define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) @@ -117,4 +136,36 @@ typedef struct user_m68kfp_struct elf_fpregset_t; #define SET_PERSONALITY(ex) set_personality(PER_LINUX) +/* + * VDSO + */ +#ifdef CONFIG_VSYSCALL +extern unsigned int vdso_enabled; + +#define VDSO_BASE ((unsigned long)current->mm->context.vdso) +#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x)) + +#define VSYSCALL_AUX_ENT \ + if (vdso_enabled) \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); + +/* additional pages */ +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 + +struct linux_binprm; +extern int arch_setup_additional_pages(struct linux_binprm *bprm, + int executable_stack); + +#else +/* no VSYSCALL_AUX_ENT */ +#define VSYSCALL_AUX_ENT +#endif + +#define ARCH_DLINFO \ +do { \ + /* vsyscall entry */ \ + VSYSCALL_AUX_ENT; \ +} while (0); + + #endif diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 1b57adbafad5..8f54b58c0212 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h @@ -37,7 +37,7 @@ #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M548x) + defined(CONFIG_M532x) /* These parts have GPIO organized by 8 bit ports */ diff --git a/arch/m68k/include/asm/m5485sim.h b/arch/m68k/include/asm/m5485sim.h new file mode 100644 index 000000000000..0893d179ace9 --- /dev/null +++ b/arch/m68k/include/asm/m5485sim.h @@ -0,0 +1,221 @@ +/* + * m5485sim.h -- ColdFire 547x/548x System Integration Unit support. + */ + +#ifndef m5485sim_h +#define m5485sim_h + + +/* + * System Integration Unit Registers + */ +#define MCF_SDRAMDS MCF_REG32(0x000004) /* SDRAM Drive Strength */ +#define MCF_SBCR MCF_REG32(0x000010) /* System Breakpoint Control */ +#define MCF_CSnCFG(x) MCF_REG32(0x000020+(x*4))/* SDRAM Chip Select X */ +#define MCF_SECSACR MCF_REG32(0x000038) /* Sequential Access Control */ +#define MCF_RSR MCF_REG32(0x000044) /* Reset Status */ +#define MCF_JTAGID MCF_REG32(0x000050) /* JTAG Device Identification */ + +/* + * FlexBus Chip Selects Registers + */ +#define MCF_CSARn(x) MCF_REG32(0x000500+(x*0xC)) +#define MCF_CSMRn(x) MCF_REG32(0x000504+(x*0xC)) +#define MCF_CSCRn(x) MCF_REG32(0x000508+(x*0xC)) + +/* + * Interrupt Controller Registers + */ +#define MCF_IPRH MCF_REG32(0x000700) +#define MCF_IPRL MCF_REG32(0x000704) +#define MCF_IMRH MCF_REG32(0x000708) +#define MCF_IMRL MCF_REG32(0x00070C) +#define MCF_INTFRCH MCF_REG32(0x000710) +#define MCF_INTFRCL MCF_REG32(0x000714) +#define MCF_IRLR MCF_REG08(0x000718) +#define MCF_IACKLPR MCF_REG08(0x000719) +#define MCF_SWIACK MCF_REG08(0x0007E0) +#define MCF_LnIACK(x) MCF_REG08(0x0007E4+((x)*0x004)) +#define MCF_ICR(x) MCF_REG08(0x000740+((x)*0x001)) + +/* + * Slice Timers Registers + */ +#define MCF_SLTCNT(x) MCF_REG32(0x000900+((x)*0x010)) +#define MCF_SCR(x) MCF_REG32(0x000904+((x)*0x010)) +#define MCF_SCNT(x) MCF_REG32(0x000908+((x)*0x010)) +#define MCF_SSR(x) MCF_REG32(0x00090C+((x)*0x010)) + +/* + * Interrupt sources + */ +#define ISC_EPORT_Fn(x) (x) /* EPORT Interrupts */ +#define ISC_USB_EPn(x) (15+(x)) /* USB Endopint */ +#define ISC_USB_ISR (22) /* USB General source */ +#define ISC_USB_AISR (22) /* USB core source */ +#define ISC_DSPI_OVRFW (25) /* DSPI overflow */ +#define ISC_DSPI_RFOF (26) +#define ISC_DSPI_RFDF (27) +#define ISC_DSPI_TFUF (28) +#define ISC_DSPI_TCF (29) +#define ISC_DSPI_TFFF (30) +#define ISC_DSPI_EOQF (31) +#define ISC_PSCn(x) (35-(x)) +#define ISC_COMM_TIM (36) +#define ISC_SEC (37) +#define ISC_FEC1 (38) +#define ISC_FEC0 (39) +#define ISC_I2C (40) +#define ISC_PCI_ARB (41) +#define ISC_PCI_CB (42) +#define ISC_PCI_XLB (43) +#define ISC_DMA (48) +#define ISC_CANn_ERR(x) (49+(6*(x))) +#define ISC_CANn_BUSOFF(x) (50+(6*(x))) +#define ISC_CANn_MBOR(x) (51+(6*(x))) +#define ISC_CAN0_WAKEIN (52) +#define ISC_SLTn(x) (54-(x)) +#define ISC_GPTn(x) (62-(x)) + +/* + * Interrupt level and priorities + */ +#define ILP_TOP (MCF_ICR_IL(5) | MCF_ICR_IP(3)) +#define ILP_SLT0 (MCF_ICR_IL(5) | MCF_ICR_IP(2)) +#define ILP_SLT1 (MCF_ICR_IL(5) | MCF_ICR_IP(1)) +#define ILP_DMA (MCF_ICR_IL(5) | MCF_ICR_IP(0)) +#define ILP_SEC (MCF_ICR_IL(4) | MCF_ICR_IP(7)) +#define ILP_FEC0 (MCF_ICR_IL(4) | MCF_ICR_IP(6)) +#define ILP_FEC1 (MCF_ICR_IL(4) | MCF_ICR_IP(5)) +#define ILP_PCI_XLB (MCF_ICR_IL(4) | MCF_ICR_IP(4)) +#define ILP_PCI_ARB (MCF_ICR_IL(4) | MCF_ICR_IP(3)) +#define ILP_PCI_CB (MCF_ICR_IL(4) | MCF_ICR_IP(2)) +#define ILP_I2C (MCF_ICR_IL(4) | MCF_ICR_IP(1)) + +#define ILP_USB_EPn(x) (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x))) +#define ILP_USB_EP0 (MCF_ICR_IL(3) | MCF_ICR_IP(7)) +#define ILP_USB_EP1 (MCF_ICR_IL(3) | MCF_ICR_IP(6)) +#define ILP_USB_EP2 (MCF_ICR_IL(3) | MCF_ICR_IP(5)) +#define ILP_USB_EP3 (MCF_ICR_IL(3) | MCF_ICR_IP(4)) +#define ILP_USB_EP4 (MCF_ICR_IL(3) | MCF_ICR_IP(3)) +#define ILP_USB_EP5 (MCF_ICR_IL(3) | MCF_ICR_IP(2)) +#define ILP_USB_EP6 (MCF_ICR_IL(3) | MCF_ICR_IP(1)) +#define ILP_USB_ISR (MCF_ICR_IL(3) | MCF_ICR_IP(0)) + +#define ILP_USB_AISR (MCF_ICR_IL(2) | MCF_ICR_IP(7)) +#define ILP_DSPI_OVRFW (MCF_ICR_IL(2) | MCF_ICR_IP(6)) +#define ILP_DSPI_RFOF (MCF_ICR_IL(2) | MCF_ICR_IP(5)) +#define ILP_DSPI_RFDF (MCF_ICR_IL(2) | MCF_ICR_IP(4)) +#define ILP_DSPI_TFUF (MCF_ICR_IL(2) | MCF_ICR_IP(3)) +#define ILP_DSPI_TCF (MCF_ICR_IL(2) | MCF_ICR_IP(2)) +#define ILP_DSPI_TFFF (MCF_ICR_IL(2) | MCF_ICR_IP(1)) +#define ILP_DSPI_EOQF (MCF_ICR_IL(2) | MCF_ICR_IP(0)) + +#define ILP_COMM_TIM (MCF_ICR_IL(1) | MCF_ICR_IP(7)) +#define ILP_PSCn(x) (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3))) +#define ILP_PSC0 (MCF_ICR_IL(1) | MCF_ICR_IP(3)) +#define ILP_PSC1 (MCF_ICR_IL(1) | MCF_ICR_IP(2)) +#define ILP_PSC2 (MCF_ICR_IL(1) | MCF_ICR_IP(1)) +#define ILP_PSC3 (MCF_ICR_IL(1) | MCF_ICR_IP(0)) + + + + + +/********************************************************************/ + +/* + * System Integration Unit Bitfields + */ + +/* SBCR */ +#define MCF_SBCR_PIN2DSPI (0x08000000) +#define MCF_SBCR_DMA2CPU (0x10000000) +#define MCF_SBCR_CPU2DMA (0x20000000) +#define MCF_SBCR_PIN2DMA (0x40000000) +#define MCF_SBCR_PIN2CPU (0x80000000) + +/* SECSACR */ +#define MCF_SECSACR_SEQEN (0x00000001) + +/* RSR */ +#define MCF_RSR_RST (0x00000001) +#define MCF_RSR_RSTWD (0x00000002) +#define MCF_RSR_RSTJTG (0x00000008) + +/* JTAGID */ +#define MCF_JTAGID_REV (0xF0000000) +#define MCF_JTAGID_PROCESSOR (0x0FFFFFFF) +#define MCF_JTAGID_MCF5485 (0x0800C01D) +#define MCF_JTAGID_MCF5484 (0x0800D01D) +#define MCF_JTAGID_MCF5483 (0x0800E01D) +#define MCF_JTAGID_MCF5482 (0x0800F01D) +#define MCF_JTAGID_MCF5481 (0x0801001D) +#define MCF_JTAGID_MCF5480 (0x0801101D) +#define MCF_JTAGID_MCF5475 (0x0801201D) +#define MCF_JTAGID_MCF5474 (0x0801301D) +#define MCF_JTAGID_MCF5473 (0x0801401D) +#define MCF_JTAGID_MCF5472 (0x0801501D) +#define MCF_JTAGID_MCF5471 (0x0801601D) +#define MCF_JTAGID_MCF5470 (0x0801701D) + + +/* + * Interrupt Controller Bitfields + */ +#define MCF_IRLR_IRQ(x) (((x)&0x7F)<<1) +#define MCF_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_IACKLPR_LEVEL(x) (((x)&0x07)<<4) +#define MCF_ICR_IP(x) (((x)&0x07)<<0) +#define MCF_ICR_IL(x) (((x)&0x07)<<3) + +/* + * Slice Timers Bitfields + */ +#define MCF_SCR_TEN (0x01000000) +#define MCF_SCR_IEN (0x02000000) +#define MCF_SCR_RUN (0x04000000) +#define MCF_SSR_ST (0x01000000) +#define MCF_SSR_BE (0x02000000) + + +/* + * Some needed coldfire registers + */ +#define MCF_PAR_PCIBG MCF_REG16(0x000A48) +#define MCF_PAR_PCIBR MCF_REG16(0x000A4A) +#define MCF_PAR_PSCn(x) MCF_REG08(0x000A4F-((x)&0x3)) +#define MCF_PAR_FECI2CIRQ MCF_REG16(0x000A44) +#define MCF_PAR_DSPI MCF_REG16(0x000A50) +#define MCF_PAR_TIMER MCF_REG08(0X000A52) +#define MCF_EPPAR MCF_REG16(0x000F00) +#define MCF_EPIER MCF_REG08(0x000F05) +#define MCF_EPFR MCF_REG08(0x000F0C) + +/* + * Some GPIO bitfields + */ +#define MCF_PAR_SDA (0x0008) +#define MCF_PAR_SCL (0x0004) +#define MCF_PAR_PSC_TXD (0x04) +#define MCF_PAR_PSC_RXD (0x08) +#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4) +#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6) +#define MCF_PAR_PSC_CTS_GPIO (0x00) +#define MCF_PAR_PSC_CTS_BCLK (0x80) +#define MCF_PAR_PSC_CTS_CTS (0xC0) +#define MCF_PAR_PSC_RTS_GPIO (0x00) +#define MCF_PAR_PSC_RTS_FSYNC (0x20) +#define MCF_PAR_PSC_RTS_RTS (0x30) +#define MCF_PAR_PSC_CANRX (0x40) + + +/* + * Some used coldfire values + */ +#define MCF_EPIER_EPIE(x) (0x01 << (x)) +#define MCF_EPPAR_EPPAx_FALLING (2) +#define MCF_EPPAR_EPPA(n,x) (((x)&0x0003) << (2*n)) + + +#endif /* m5485sim_h */ diff --git a/arch/m68k/include/asm/m548xdma.h b/arch/m68k/include/asm/m548xdma.h new file mode 100644 index 000000000000..59b7e80877b2 --- /dev/null +++ b/arch/m68k/include/asm/m548xdma.h @@ -0,0 +1,97 @@ +/* + * m5485dma.h -- ColdFire 547x/548x DMA controller support. + */ +#ifndef __MCF548X_DMA_H__ +#define __MCF548X_DMA_H__ + + +/* Register read/write macros */ +#define MCF_DMA_DIPR (*(volatile u32*)(void*)(MCF_MBAR+0x008014)) +#define MCF_DMA_DIMR (*(volatile u32*)(void*)(MCF_MBAR+0x008018)) +#define MCF_DMA_IMCR (*(volatile u32*)(void*)(MCF_MBAR+0x00805C)) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK0 (0x00000001) +#define MCF_DMA_DIPR_TASK1 (0x00000002) +#define MCF_DMA_DIPR_TASK2 (0x00000004) +#define MCF_DMA_DIPR_TASK3 (0x00000008) +#define MCF_DMA_DIPR_TASK4 (0x00000010) +#define MCF_DMA_DIPR_TASK5 (0x00000020) +#define MCF_DMA_DIPR_TASK6 (0x00000040) +#define MCF_DMA_DIPR_TASK7 (0x00000080) +#define MCF_DMA_DIPR_TASK8 (0x00000100) +#define MCF_DMA_DIPR_TASK9 (0x00000200) +#define MCF_DMA_DIPR_TASK10 (0x00000400) +#define MCF_DMA_DIPR_TASK11 (0x00000800) +#define MCF_DMA_DIPR_TASK12 (0x00001000) +#define MCF_DMA_DIPR_TASK13 (0x00002000) +#define MCF_DMA_DIPR_TASK14 (0x00004000) +#define MCF_DMA_DIPR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK0 (0x00000001) +#define MCF_DMA_DIMR_TASK1 (0x00000002) +#define MCF_DMA_DIMR_TASK2 (0x00000004) +#define MCF_DMA_DIMR_TASK3 (0x00000008) +#define MCF_DMA_DIMR_TASK4 (0x00000010) +#define MCF_DMA_DIMR_TASK5 (0x00000020) +#define MCF_DMA_DIMR_TASK6 (0x00000040) +#define MCF_DMA_DIMR_TASK7 (0x00000080) +#define MCF_DMA_DIMR_TASK8 (0x00000100) +#define MCF_DMA_DIMR_TASK9 (0x00000200) +#define MCF_DMA_DIMR_TASK10 (0x00000400) +#define MCF_DMA_DIMR_TASK11 (0x00000800) +#define MCF_DMA_DIMR_TASK12 (0x00001000) +#define MCF_DMA_DIMR_TASK13 (0x00002000) +#define MCF_DMA_DIMR_TASK14 (0x00004000) +#define MCF_DMA_DIMR_TASK15 (0x00008000) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) +#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) +#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) +#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) +#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) +#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) +#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) +#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) +#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) +#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) +#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) +#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) +#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) +#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) +#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) +#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) +#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) +#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) +#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) +#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) +#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) +#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) +#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) +#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) +#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) +#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) +#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) +#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) +#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) +#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) +#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) +#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) +#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) +#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) +#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) +#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) +#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) +#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) +#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) +#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) +#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) +#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) +#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) +#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) +#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) +#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) + +#endif /* __MCF548X_DMA_H__ */ diff --git a/arch/m68k/include/asm/m548xdspi.h b/arch/m68k/include/asm/m548xdspi.h new file mode 100644 index 000000000000..824025750639 --- /dev/null +++ b/arch/m68k/include/asm/m548xdspi.h @@ -0,0 +1,144 @@ +/* + * File: mcf548x_dspi.h + * Purpose: Register and bit definitions for the MCF548X + * + * Notes: + * + */ + +#ifndef _M548XDSPI_H_ +#define _M548XDSPI_H_ + +/* + * + * DMA Serial Peripheral Interface (DSPI) + * + */ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR MCF_REG32(0x008A00) +#define MCF_DSPI_DTCR MCF_REG32(0x008A08) +#define MCF_DSPI_DCTAR0 MCF_REG32(0x008A0C) +#define MCF_DSPI_DCTAR1 MCF_REG32(0x008A10) +#define MCF_DSPI_DCTAR2 MCF_REG32(0x008A14) +#define MCF_DSPI_DCTAR3 MCF_REG32(0x008A18) +#define MCF_DSPI_DCTAR4 MCF_REG32(0x008A1C) +#define MCF_DSPI_DCTAR5 MCF_REG32(0x008A20) +#define MCF_DSPI_DCTAR6 MCF_REG32(0x008A24) +#define MCF_DSPI_DCTAR7 MCF_REG32(0x008A28) +#define MCF_DSPI_DCTARn(x) MCF_REG32(0x008A0C+(x*4)) +#define MCF_DSPI_DSR MCF_REG32(0x008A2C) +#define MCF_DSPI_DRSER MCF_REG32(0x008A30) +#define MCF_DSPI_DTFR MCF_REG32(0x008A34) +#define MCF_DSPI_DRFR MCF_REG32(0x008A38) +#define MCF_DSPI_DTFDR0 MCF_REG32(0x008A3C) +#define MCF_DSPI_DTFDR1 MCF_REG32(0x008A40) +#define MCF_DSPI_DTFDR2 MCF_REG32(0x008A44) +#define MCF_DSPI_DTFDR3 MCF_REG32(0x008A48) +#define MCF_DSPI_DTFDRn(x) MCF_REG32(0x008A3C+(x*4)) +#define MCF_DSPI_DRFDR0 MCF_REG32(0x008A7C) +#define MCF_DSPI_DRFDR1 MCF_REG32(0x008A80) +#define MCF_DSPI_DRFDR2 MCF_REG32(0x008A84) +#define MCF_DSPI_DRFDR3 MCF_REG32(0x008A88) +#define MCF_DSPI_DRFDRn(x) MCF_REG32(0x008A7C+(x*4)) + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x00000001) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +#define MCF_DSPI_DMCR_CRXF (0x00000400) +#define MCF_DSPI_DMCR_CTXF (0x00000800) +#define MCF_DSPI_DMCR_DRXF (0x00001000) +#define MCF_DSPI_DMCR_DTXF (0x00002000) +#define MCF_DSPI_DMCR_CSIS0 (0x00010000) +#define MCF_DSPI_DMCR_CSIS2 (0x00040000) +#define MCF_DSPI_DMCR_CSIS3 (0x00080000) +#define MCF_DSPI_DMCR_CSIS5 (0x00200000) +#define MCF_DSPI_DMCR_ROOE (0x01000000) +#define MCF_DSPI_DMCR_PCSSE (0x02000000) +#define MCF_DSPI_DMCR_MTFE (0x04000000) +#define MCF_DSPI_DMCR_FRZ (0x08000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_DSPI_DCTARn */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) +#define MCF_DSPI_DCTAR_LSBFE (0x01000000) +#define MCF_DSPI_DCTAR_CPHA (0x02000000) +#define MCF_DSPI_DCTAR_CPOL (0x04000000) +/* #define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27) */ +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00A00000) +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000A0000) +#define MCF_DSPI_DCTAR_PBR_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +#define MCF_DSPI_DSR_RFDF (0x00020000) +#define MCF_DSPI_DSR_RFOF (0x00080000) +#define MCF_DSPI_DSR_TFFF (0x02000000) +#define MCF_DSPI_DSR_TFUF (0x08000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRSER */ +#define MCF_DSPI_DRSER_RFDFS (0x00010000) +#define MCF_DSPI_DRSER_RFDFE (0x00020000) +#define MCF_DSPI_DRSER_RFOFE (0x00080000) +#define MCF_DSPI_DRSER_TFFFS (0x01000000) +#define MCF_DSPI_DRSER_TFFFE (0x02000000) +#define MCF_DSPI_DRSER_TFUFE (0x08000000) +#define MCF_DSPI_DRSER_EOQFE (0x10000000) +#define MCF_DSPI_DRSER_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x00010000) +#define MCF_DSPI_DTFR_CS2 (0x00040000) +#define MCF_DSPI_DTFR_CS3 (0x00080000) +#define MCF_DSPI_DTFR_CS5 (0x00200000) +#define MCF_DSPI_DTFR_CTCNT (0x04000000) +#define MCF_DSPI_DTFR_EOQ (0x08000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDRn */ +#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_DSPI_DRFDRn */ +#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) + +/********************************************************************/ + +#endif /* _M548XDSPI_H_ */ diff --git a/arch/m68k/include/asm/m548xgpio.h b/arch/m68k/include/asm/m548xgpio.h new file mode 100644 index 000000000000..47f487ebc4cf --- /dev/null +++ b/arch/m68k/include/asm/m548xgpio.h @@ -0,0 +1,694 @@ +/* + * File: mcf548x_gpio.h + * Purpose: Register and bit definitions for the MCF548X + * + * Notes: + * + */ + +#ifndef _M548XGPIO_H_ +#define _M548XGPIO_H_ + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL MCF_REG08(0x000A00) +#define MCF_GPIO_PODR_FBCS MCF_REG08(0x000A01) +#define MCF_GPIO_PODR_DMA MCF_REG08(0x000A02) +#define MCF_GPIO_PODR_FEC0H MCF_REG08(0x000A04) +#define MCF_GPIO_PODR_FEC0L MCF_REG08(0x000A05) +#define MCF_GPIO_PODR_FEC1H MCF_REG08(0x000A06) +#define MCF_GPIO_PODR_FEC1L MCF_REG08(0x000A07) +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0x000A08) +#define MCF_GPIO_PODR_PCIBG MCF_REG08(0x000A09) +#define MCF_GPIO_PODR_PCIBR MCF_REG08(0x000A0A) +#define MCF_GPIO_PODR_PSC3PSC2 MCF_REG08(0x000A0C) +#define MCF_GPIO_PODR_PSC1PSC0 MCF_REG08(0x000A0D) +#define MCF_GPIO_PODR_DSPI MCF_REG08(0x000A0E) +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0x000A10) +#define MCF_GPIO_PDDR_FBCS MCF_REG08(0x000A11) +#define MCF_GPIO_PDDR_DMA MCF_REG08(0x000A12) +#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0x000A14) +#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0x000A15) +#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0x000A16) +#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0x000A17) +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0x000A18) +#define MCF_GPIO_PDDR_PCIBG MCF_REG08(0x000A19) +#define MCF_GPIO_PDDR_PCIBR MCF_REG08(0x000A1A) +#define MCF_GPIO_PDDR_PSC3PSC2 MCF_REG08(0x000A1C) +#define MCF_GPIO_PDDR_PSC1PSC0 MCF_REG08(0x000A1D) +#define MCF_GPIO_PDDR_DSPI MCF_REG08(0x000A1E) +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0x000A20) +#define MCF_GPIO_PPDSDR_FBCS MCF_REG08(0x000A21) +#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0x000A22) +#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0x000A24) +#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0x000A25) +#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0x000A26) +#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0x000A27) +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0x000A28) +#define MCF_GPIO_PPDSDR_PCIBG MCF_REG08(0x000A29) +#define MCF_GPIO_PPDSDR_PCIBR MCF_REG08(0x000A2A) +#define MCF_GPIO_PPDSDR_PSC3PSC2 MCF_REG08(0x000A2C) +#define MCF_GPIO_PPDSDR_PSC1PSC0 MCF_REG08(0x000A2D) +#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0x000A2E) +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0x000A30) +#define MCF_GPIO_PCLRR_FBCS MCF_REG08(0x000A31) +#define MCF_GPIO_PCLRR_DMA MCF_REG08(0x000A32) +#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0x000A34) +#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0x000A35) +#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0x000A36) +#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0x000A37) +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0x000A38) +#define MCF_GPIO_PCLRR_PCIBG MCF_REG08(0x000A39) +#define MCF_GPIO_PCLRR_PCIBR MCF_REG08(0x000A3A) +#define MCF_GPIO_PCLRR_PSC3PSC2 MCF_REG08(0x000A3C) +#define MCF_GPIO_PCLRR_PSC1PSC0 MCF_REG08(0x000A3D) +#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0x000A3E) +#define MCF_GPIO_PAR_FBCTL MCF_REG16(0x000A40) +#define MCF_GPIO_PAR_FBCS MCF_REG08(0x000A42) +#define MCF_GPIO_PAR_DMA MCF_REG08(0x000A43) +#define MCF_GPIO_PAR_FECI2CIRQ MCF_REG16(0x000A44) +#define MCF_GPIO_PAR_PCIBG MCF_REG16(0x000A48) +#define MCF_GPIO_PAR_PCIBR MCF_REG16(0x000A4A) +#define MCF_GPIO_PAR_PSC3 MCF_REG08(0x000A4C) +#define MCF_GPIO_PAR_PSC2 MCF_REG08(0x000A4D) +#define MCF_GPIO_PAR_PSC1 MCF_REG08(0x000A4E) +#define MCF_GPIO_PAR_PSC0 MCF_REG08(0x000A4F) +#define MCF_GPIO_PAR_DSPI MCF_REG16(0x000A50) +#define MCF_GPIO_PAR_TIMER MCF_REG08(0x000A52) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0 (0x01) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1 (0x02) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2 (0x04) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3 (0x08) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODRFBCS1 (0x02) +#define MCF_GPIO_PODR_FBCS_PODRFBCS2 (0x04) +#define MCF_GPIO_PODR_FBCS_PODRFBCS3 (0x08) +#define MCF_GPIO_PODR_FBCS_PODRFBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODRFBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODRDMA0 (0x01) +#define MCF_GPIO_PODR_DMA_PODRDMA1 (0x02) +#define MCF_GPIO_PODR_DMA_PODRDMA2 (0x04) +#define MCF_GPIO_PODR_DMA_PODRDMA3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0 (0x01) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1 (0x02) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2 (0x04) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3 (0x08) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0 (0x01) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1 (0x02) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2 (0x04) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3 (0x08) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0 (0x01) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1 (0x02) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2 (0x04) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3 (0x08) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0 (0x01) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1 (0x02) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2 (0x04) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3 (0x08) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0 (0x01) +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1 (0x02) +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2 (0x04) +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0 (0x01) +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1 (0x02) +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2 (0x04) +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3 (0x08) +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0 (0x01) +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1 (0x02) +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2 (0x04) +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3 (0x08) +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20 (0x01) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21 (0x02) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22 (0x04) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23 (0x08) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00 (0x01) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01 (0x02) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02 (0x04) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03 (0x08) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODRDSPI0 (0x01) +#define MCF_GPIO_PODR_DSPI_PODRDSPI1 (0x02) +#define MCF_GPIO_PODR_DSPI_PODRDSPI2 (0x04) +#define MCF_GPIO_PODR_DSPI_PODRDSPI3 (0x08) +#define MCF_GPIO_PODR_DSPI_PODRDSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODRDSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODRDSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0 (0x01) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1 (0x02) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2 (0x04) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3 (0x08) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1 (0x02) +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2 (0x04) +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3 (0x08) +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDRDMA0 (0x01) +#define MCF_GPIO_PDDR_DMA_PDDRDMA1 (0x02) +#define MCF_GPIO_PDDR_DMA_PDDRDMA2 (0x04) +#define MCF_GPIO_PDDR_DMA_PDDRDMA3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0 (0x01) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1 (0x02) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2 (0x04) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3 (0x08) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0 (0x01) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1 (0x02) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2 (0x04) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3 (0x08) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0 (0x01) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1 (0x02) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2 (0x04) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3 (0x08) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0 (0x01) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1 (0x02) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2 (0x04) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3 (0x08) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0 (0x01) +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1 (0x02) +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2 (0x04) +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0 (0x01) +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1 (0x02) +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2 (0x04) +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3 (0x08) +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0 (0x01) +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1 (0x02) +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2 (0x04) +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3 (0x08) +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20 (0x01) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21 (0x02) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22 (0x04) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23 (0x08) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00 (0x01) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02 (0x04) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0 (0x01) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1 (0x02) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2 (0x04) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3 (0x08) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0 (0x01) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1 (0x02) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2 (0x04) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3 (0x08) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1 (0x02) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2 (0x04) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3 (0x08) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0 (0x01) +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1 (0x02) +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2 (0x04) +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0 (0x01) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1 (0x02) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2 (0x04) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3 (0x08) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0 (0x01) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1 (0x02) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2 (0x04) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3 (0x08) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0 (0x01) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1 (0x02) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2 (0x04) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3 (0x08) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0 (0x01) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1 (0x02) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2 (0x04) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3 (0x08) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0 (0x01) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1 (0x02) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2 (0x04) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0 (0x01) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1 (0x02) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2 (0x04) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3 (0x08) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0 (0x01) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1 (0x02) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2 (0x04) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3 (0x08) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20 (0x01) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21 (0x02) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22 (0x04) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23 (0x08) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00 (0x01) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01 (0x02) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02 (0x04) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03 (0x08) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0 (0x01) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1 (0x02) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2 (0x04) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3 (0x08) +#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0 (0x01) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1 (0x02) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2 (0x04) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3 (0x08) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1 (0x02) +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2 (0x04) +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3 (0x08) +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0 (0x01) +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1 (0x02) +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2 (0x04) +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0 (0x01) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1 (0x02) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2 (0x04) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3 (0x08) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0 (0x01) +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1 (0x02) +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2 (0x04) +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3 (0x08) +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0 (0x01) +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1 (0x02) +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2 (0x04) +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3 (0x08) +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0 (0x01) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1 (0x02) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2 (0x04) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3 (0x08) +#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0 (0x01) +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1 (0x02) +#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2 (0x04) +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0 (0x01) +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1 (0x02) +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2 (0x04) +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3 (0x08) +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0 (0x01) +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1 (0x02) +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2 (0x04) +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3 (0x08) +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20 (0x01) +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21 (0x02) +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22 (0x04) +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23 (0x08) +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00 (0x01) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01 (0x02) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02 (0x04) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03 (0x08) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0 (0x01) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1 (0x02) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2 (0x04) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3 (0x08) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ +#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) +#define MCF_GPIO_PAR_FBCTL_PAR_RWB (0x0010) +#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) +#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) +#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) +#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) +#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) + +/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ +#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) +#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) +#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) +#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ +#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) +#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) +#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) +#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) +#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) +#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) + +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) + +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) + +/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ +#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) +#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) +#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) + +/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ +#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) +#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX (0x40) + +/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ +#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) +#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) +#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) + +/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ +#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) +#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) +#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) + +/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ +#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) +#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) +#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) +#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) +#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) +#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) +#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) +#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) +#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) +#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) +#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) +#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) +#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) +#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) +#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) + +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ +#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) +#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) + +/********************************************************************/ + +#endif /* _M548XGPIO_H_ */ diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h index c8ef158a1c4e..b68273bcb5b2 100644 --- a/arch/m68k/include/asm/m548xgpt.h +++ b/arch/m68k/include/asm/m548xgpt.h @@ -6,8 +6,8 @@ * */ -#ifndef m548xgpt_h -#define m548xgpt_h +#ifndef _M548XGPT_H_ +#define _M548XGPT_H_ /********************************************************************* * @@ -85,4 +85,4 @@ /********************************************************************/ -#endif /* m548xgpt_h */ +#endif /* _M548XGPT_H_ */ diff --git a/arch/m68k/include/asm/m548xi2c.h b/arch/m68k/include/asm/m548xi2c.h new file mode 100644 index 000000000000..af59b42e5c6a --- /dev/null +++ b/arch/m68k/include/asm/m548xi2c.h @@ -0,0 +1,45 @@ +/* + * m5485i2c.h -- ColdFire 547x/548x i2c controller support. + */ +#ifndef _M548X_I2C_H +#define _M548X_I2C_H + +/* Register read/write macros */ +#define MCF_I2AR MCF_REG08(0x008F00) /* I2C Address */ +#define MCF_I2FDR MCF_REG08(0x008F04) /* I2C Frequency Divider */ +#define MCF_I2CR MCF_REG08(0x008F08) /* I2C Control */ +#define MCF_I2SR MCF_REG08(0x008F0C) /* I2C Status */ +#define MCF_I2DR MCF_REG08(0x008F10) /* I2C Data I/O */ +#define MCF_I2ICR MCF_REG08(0x008F20) /* I2C Interrupt Control */ + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2CR_RSTA (0x04) +#define MCF_I2CR_TXAK (0x08) +#define MCF_I2CR_MTX (0x10) +#define MCF_I2CR_MSTA (0x20) +#define MCF_I2CR_IIEN (0x40) +#define MCF_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2SR_RXAK (0x01) +#define MCF_I2SR_IIF (0x02) +#define MCF_I2SR_SRW (0x04) +#define MCF_I2SR_IAL (0x10) +#define MCF_I2SR_IBB (0x20) +#define MCF_I2SR_IAAS (0x40) +#define MCF_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2ICR_IE (0x01) +#define MCF_I2ICR_RE (0x02) +#define MCF_I2ICR_TE (0x04) +#define MCF_I2ICR_BNBE (0x08) + +/********************************************************************/ +#endif diff --git a/arch/m68k/include/asm/m548xpsc.h b/arch/m68k/include/asm/m548xpsc.h new file mode 100644 index 000000000000..b39ff778b6ab --- /dev/null +++ b/arch/m68k/include/asm/m548xpsc.h @@ -0,0 +1,648 @@ +/* + * File: mcf548x_psc.h + * Purpose: Register and bit definitions for the MCF548X + * + * Notes: + * + */ + +#ifndef __MCF548X_PSC_H__ +#define __MCF548X_PSC_H__ + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC_MR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600)) +#define MCF_PSC_SR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604)) +#define MCF_PSC_CSR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604)) +#define MCF_PSC_CR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608)) +#define MCF_PSC_RB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) +#define MCF_PSC_TB0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) +#define MCF_PSC_TB_8BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) +#define MCF_PSC_TB_16BIT0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) +#define MCF_PSC_TB_AC970 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C)) +#define MCF_PSC_IPCR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610)) +#define MCF_PSC_ACR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610)) +#define MCF_PSC_ISR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614)) +#define MCF_PSC_IMR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614)) +#define MCF_PSC_CTUR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618)) +#define MCF_PSC_CTLR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C)) +#define MCF_PSC_IP0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634)) +#define MCF_PSC_OPSET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638)) +#define MCF_PSC_OPRESET0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C)) +#define MCF_PSC_SICR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640)) +#define MCF_PSC_IRCR10 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644)) +#define MCF_PSC_IRCR20 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648)) +#define MCF_PSC_IRSDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C)) +#define MCF_PSC_IRMDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650)) +#define MCF_PSC_IRFDR0 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654)) +#define MCF_PSC_RFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658)) +#define MCF_PSC_TFCNT0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C)) +#define MCF_PSC_RFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664)) +#define MCF_PSC_TFSR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684)) +#define MCF_PSC_RFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668)) +#define MCF_PSC_TFCR0 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688)) +#define MCF_PSC_RFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00866E)) +#define MCF_PSC_TFAR0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00868E)) +#define MCF_PSC_RFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672)) +#define MCF_PSC_TFRP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692)) +#define MCF_PSC_RFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676)) +#define MCF_PSC_TFWP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696)) +#define MCF_PSC_RLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A)) +#define MCF_PSC_TLRFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A)) +#define MCF_PSC_RLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E)) +#define MCF_PSC_TLWFP0 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E)) +#define MCF_PSC_MR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008700)) +#define MCF_PSC_SR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008704)) +#define MCF_PSC_CSR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008704)) +#define MCF_PSC_CR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008708)) +#define MCF_PSC_RB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) +#define MCF_PSC_TB1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) +#define MCF_PSC_TB_8BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) +#define MCF_PSC_TB_16BIT1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) +#define MCF_PSC_TB_AC971 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C)) +#define MCF_PSC_IPCR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710)) +#define MCF_PSC_ACR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710)) +#define MCF_PSC_ISR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714)) +#define MCF_PSC_IMR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714)) +#define MCF_PSC_CTUR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008718)) +#define MCF_PSC_CTLR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00871C)) +#define MCF_PSC_IP1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008734)) +#define MCF_PSC_OPSET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008738)) +#define MCF_PSC_OPRESET1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00873C)) +#define MCF_PSC_SICR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008740)) +#define MCF_PSC_IRCR11 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008744)) +#define MCF_PSC_IRCR21 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008748)) +#define MCF_PSC_IRSDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00874C)) +#define MCF_PSC_IRMDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008750)) +#define MCF_PSC_IRFDR1 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008754)) +#define MCF_PSC_RFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008758)) +#define MCF_PSC_TFCNT1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00875C)) +#define MCF_PSC_RFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008764)) +#define MCF_PSC_TFSR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008784)) +#define MCF_PSC_RFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008768)) +#define MCF_PSC_TFCR1 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008788)) +#define MCF_PSC_RFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00876E)) +#define MCF_PSC_TFAR1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00878E)) +#define MCF_PSC_RFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008772)) +#define MCF_PSC_TFRP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008792)) +#define MCF_PSC_RFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008776)) +#define MCF_PSC_TFWP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008796)) +#define MCF_PSC_RLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877A)) +#define MCF_PSC_TLRFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879A)) +#define MCF_PSC_RLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877E)) +#define MCF_PSC_TLWFP1 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879E)) +#define MCF_PSC_MR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008800)) +#define MCF_PSC_SR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008804)) +#define MCF_PSC_CSR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008804)) +#define MCF_PSC_CR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008808)) +#define MCF_PSC_RB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) +#define MCF_PSC_TB2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) +#define MCF_PSC_TB_8BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) +#define MCF_PSC_TB_16BIT2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) +#define MCF_PSC_TB_AC972 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C)) +#define MCF_PSC_IPCR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810)) +#define MCF_PSC_ACR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810)) +#define MCF_PSC_ISR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814)) +#define MCF_PSC_IMR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814)) +#define MCF_PSC_CTUR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008818)) +#define MCF_PSC_CTLR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00881C)) +#define MCF_PSC_IP2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008834)) +#define MCF_PSC_OPSET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008838)) +#define MCF_PSC_OPRESET2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00883C)) +#define MCF_PSC_SICR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008840)) +#define MCF_PSC_IRCR12 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008844)) +#define MCF_PSC_IRCR22 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008848)) +#define MCF_PSC_IRSDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00884C)) +#define MCF_PSC_IRMDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008850)) +#define MCF_PSC_IRFDR2 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008854)) +#define MCF_PSC_RFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008858)) +#define MCF_PSC_TFCNT2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00885C)) +#define MCF_PSC_RFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008864)) +#define MCF_PSC_TFSR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008884)) +#define MCF_PSC_RFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008868)) +#define MCF_PSC_TFCR2 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008888)) +#define MCF_PSC_RFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00886E)) +#define MCF_PSC_TFAR2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00888E)) +#define MCF_PSC_RFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008872)) +#define MCF_PSC_TFRP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008892)) +#define MCF_PSC_RFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008876)) +#define MCF_PSC_TFWP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008896)) +#define MCF_PSC_RLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887A)) +#define MCF_PSC_TLRFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889A)) +#define MCF_PSC_RLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887E)) +#define MCF_PSC_TLWFP2 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889E)) +#define MCF_PSC_MR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008900)) +#define MCF_PSC_SR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008904)) +#define MCF_PSC_CSR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008904)) +#define MCF_PSC_CR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008908)) +#define MCF_PSC_RB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) +#define MCF_PSC_TB3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) +#define MCF_PSC_TB_8BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) +#define MCF_PSC_TB_16BIT3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) +#define MCF_PSC_TB_AC973 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C)) +#define MCF_PSC_IPCR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910)) +#define MCF_PSC_ACR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910)) +#define MCF_PSC_ISR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914)) +#define MCF_PSC_IMR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914)) +#define MCF_PSC_CTUR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008918)) +#define MCF_PSC_CTLR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00891C)) +#define MCF_PSC_IP3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008934)) +#define MCF_PSC_OPSET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008938)) +#define MCF_PSC_OPRESET3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00893C)) +#define MCF_PSC_SICR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008940)) +#define MCF_PSC_IRCR13 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008944)) +#define MCF_PSC_IRCR23 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008948)) +#define MCF_PSC_IRSDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00894C)) +#define MCF_PSC_IRMDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008950)) +#define MCF_PSC_IRFDR3 (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008954)) +#define MCF_PSC_RFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008958)) +#define MCF_PSC_TFCNT3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00895C)) +#define MCF_PSC_RFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008964)) +#define MCF_PSC_TFSR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008984)) +#define MCF_PSC_RFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008968)) +#define MCF_PSC_TFCR3 (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008988)) +#define MCF_PSC_RFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00896E)) +#define MCF_PSC_TFAR3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00898E)) +#define MCF_PSC_RFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008972)) +#define MCF_PSC_TFRP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008992)) +#define MCF_PSC_RFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008976)) +#define MCF_PSC_TFWP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008996)) +#define MCF_PSC_RLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897A)) +#define MCF_PSC_TLRFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899A)) +#define MCF_PSC_RLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897E)) +#define MCF_PSC_TLWFP3 (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899E)) +#define MCF_PSC_MR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600+((x)*0x100))) +#define MCF_PSC_SR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604+((x)*0x100))) +#define MCF_PSC_CSR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604+((x)*0x100))) +#define MCF_PSC_CR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608+((x)*0x100))) +#define MCF_PSC_RB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) +#define MCF_PSC_TB(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) +#define MCF_PSC_TB_8BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) +#define MCF_PSC_TB_16BIT(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) +#define MCF_PSC_TB_AC97(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100))) +#define MCF_PSC_IPCR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100))) +#define MCF_PSC_ACR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100))) +#define MCF_PSC_ISR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100))) +#define MCF_PSC_IMR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100))) +#define MCF_PSC_CTUR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618+((x)*0x100))) +#define MCF_PSC_CTLR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C+((x)*0x100))) +#define MCF_PSC_IP(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634+((x)*0x100))) +#define MCF_PSC_OPSET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638+((x)*0x100))) +#define MCF_PSC_OPRESET(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C+((x)*0x100))) +#define MCF_PSC_SICR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640+((x)*0x100))) +#define MCF_PSC_IRCR1(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644+((x)*0x100))) +#define MCF_PSC_IRCR2(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648+((x)*0x100))) +#define MCF_PSC_IRSDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C+((x)*0x100))) +#define MCF_PSC_IRMDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650+((x)*0x100))) +#define MCF_PSC_IRFDR(x) (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654+((x)*0x100))) +#define MCF_PSC_RFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658+((x)*0x100))) +#define MCF_PSC_TFCNT(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C+((x)*0x100))) +#define MCF_PSC_RFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664+((x)*0x100))) +#define MCF_PSC_TFSR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684+((x)*0x100))) +#define MCF_PSC_RFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668+((x)*0x100))) +#define MCF_PSC_TFCR(x) (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688+((x)*0x100))) +#define MCF_PSC_RFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00866E)+((x)*0x100))) +#define MCF_PSC_TFAR(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00868E)+((x)*0x100))) +#define MCF_PSC_RFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672+((x)*0x100))) +#define MCF_PSC_TFRP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692+((x)*0x100))) +#define MCF_PSC_RFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676+((x)*0x100))) +#define MCF_PSC_TFWP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696+((x)*0x100))) +#define MCF_PSC_RLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A+((x)*0x100))) +#define MCF_PSC_TLRFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A+((x)*0x100))) +#define MCF_PSC_RLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E+((x)*0x100))) +#define MCF_PSC_TLWFP(x) (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E+((x)*0x100))) + +/* Bit definitions and macros for MCF_PSC_MR */ +#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) +#define MCF_PSC_MR_PT (0x04) +#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) +#define MCF_PSC_MR_ERR (0x20) +#define MCF_PSC_MR_RXIRQ (0x40) +#define MCF_PSC_MR_RXRTS (0x80) +#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) +#define MCF_PSC_MR_TXCTS (0x10) +#define MCF_PSC_MR_TXRTS (0x20) +#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) +#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_MR_PM_MULTI_DATA (0x18) +#define MCF_PSC_MR_PM_NONE (0x10) +#define MCF_PSC_MR_PM_FORCE_HI (0x0C) +#define MCF_PSC_MR_PM_FORCE_LO (0x08) +#define MCF_PSC_MR_PM_ODD (0x04) +#define MCF_PSC_MR_PM_EVEN (0x00) +#define MCF_PSC_MR_BC_5 (0x00) +#define MCF_PSC_MR_BC_6 (0x01) +#define MCF_PSC_MR_BC_7 (0x02) +#define MCF_PSC_MR_BC_8 (0x03) +#define MCF_PSC_MR_CM_NORMAL (0x00) +#define MCF_PSC_MR_CM_ECHO (0x40) +#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) +#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) +#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_PSC_SR */ +#define MCF_PSC_SR_ERR (0x0040) +#define MCF_PSC_SR_CDE_DEOF (0x0080) +#define MCF_PSC_SR_RXRDY (0x0100) +#define MCF_PSC_SR_FU (0x0200) +#define MCF_PSC_SR_TXRDY (0x0400) +#define MCF_PSC_SR_TXEMP_URERR (0x0800) +#define MCF_PSC_SR_OE (0x1000) +#define MCF_PSC_SR_PE_CRCERR (0x2000) +#define MCF_PSC_SR_FE_PHYERR (0x4000) +#define MCF_PSC_SR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_CSR */ +#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) +#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) +#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_CSR_RCSEL_CTM (0xF0) +#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_CSR_TCSEL_CTM (0x0F) + +/* Bit definitions and macros for MCF_PSC_CR */ +#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) +#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) +#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) +#define MCF_PSC_CR_NONE (0x00) +#define MCF_PSC_CR_STOP_BREAK (0x70) +#define MCF_PSC_CR_START_BREAK (0x60) +#define MCF_PSC_CR_BKCHGINT (0x50) +#define MCF_PSC_CR_RESET_ERROR (0x40) +#define MCF_PSC_CR_RESET_TX (0x30) +#define MCF_PSC_CR_RESET_RX (0x20) +#define MCF_PSC_CR_RESET_MR (0x10) +#define MCF_PSC_CR_TX_DISABLED (0x08) +#define MCF_PSC_CR_TX_ENABLED (0x04) +#define MCF_PSC_CR_RX_DISABLED (0x02) +#define MCF_PSC_CR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_PSC_TB_8BIT */ +#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) +#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) +#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) +#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_PSC_TB_16BIT */ +#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) +#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_PSC_TB_AC97 */ +#define MCF_PSC_TB_AC97_SOF (0x00000800) +#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) + +/* Bit definitions and macros for MCF_PSC_IPCR */ +#define MCF_PSC_IPCR_RESERVED (0x0C) +#define MCF_PSC_IPCR_CTS (0x0D) +#define MCF_PSC_IPCR_D_CTS (0x1C) +#define MCF_PSC_IPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_ACR */ +#define MCF_PSC_ACR_IEC0 (0x01) +#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) +#define MCF_PSC_ACR_BRG (0x80) + +/* Bit definitions and macros for MCF_PSC_ISR */ +#define MCF_PSC_ISR_ERR (0x0040) +#define MCF_PSC_ISR_DEOF (0x0080) +#define MCF_PSC_ISR_TXRDY (0x0100) +#define MCF_PSC_ISR_RXRDY_FU (0x0200) +#define MCF_PSC_ISR_DB (0x0400) +#define MCF_PSC_ISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_IMR */ +#define MCF_PSC_IMR_ERR (0x0040) +#define MCF_PSC_IMR_DEOF (0x0080) +#define MCF_PSC_IMR_TXRDY (0x0100) +#define MCF_PSC_IMR_RXRDY_FU (0x0200) +#define MCF_PSC_IMR_DB (0x0400) +#define MCF_PSC_IMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_IP */ +#define MCF_PSC_IP_CTS (0x01) +#define MCF_PSC_IP_TGL (0x40) +#define MCF_PSC_IP_LWPR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_OPSET */ +#define MCF_PSC_OPSET_RTS (0x01) + +/* Bit definitions and macros for MCF_PSC_OPRESET */ +#define MCF_PSC_OPRESET_RTS (0x01) + +/* Bit definitions and macros for MCF_PSC_SICR */ +#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) +#define MCF_PSC_SICR_SHDIR (0x10) +#define MCF_PSC_SICR_DTS (0x20) +#define MCF_PSC_SICR_AWR (0x40) +#define MCF_PSC_SICR_ACRB (0x80) +#define MCF_PSC_SICR_SIM_UART (0x00) +#define MCF_PSC_SICR_SIM_MODEM8 (0x01) +#define MCF_PSC_SICR_SIM_MODEM16 (0x02) +#define MCF_PSC_SICR_SIM_AC97 (0x03) +#define MCF_PSC_SICR_SIM_SIR (0x04) +#define MCF_PSC_SICR_SIM_MIR (0x05) +#define MCF_PSC_SICR_SIM_FIR (0x06) + +/* Bit definitions and macros for MCF_PSC_IRCR1 */ +#define MCF_PSC_IRCR1_SPUL (0x01) +#define MCF_PSC_IRCR1_SIPEN (0x02) +#define MCF_PSC_IRCR1_FD (0x04) + +/* Bit definitions and macros for MCF_PSC_IRCR2 */ +#define MCF_PSC_IRCR2_NXTEOF (0x01) +#define MCF_PSC_IRCR2_ABORT (0x02) +#define MCF_PSC_IRCR2_SIPREQ (0x04) + +/* Bit definitions and macros for MCF_PSC_IRMDR */ +#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_IRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_IRFDR */ +#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_PSC_RFCNT */ +#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TFCNT */ +#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_RFSR */ +#define MCF_PSC_RFSR_EMT (0x0001) +#define MCF_PSC_RFSR_ALARM (0x0002) +#define MCF_PSC_RFSR_FU (0x0004) +#define MCF_PSC_RFSR_FRMRY (0x0008) +#define MCF_PSC_RFSR_OF (0x0010) +#define MCF_PSC_RFSR_UF (0x0020) +#define MCF_PSC_RFSR_RXW (0x0040) +#define MCF_PSC_RFSR_FAE (0x0080) +#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF_PSC_RFSR_TAG (0x1000) +#define MCF_PSC_RFSR_TXW (0x4000) +#define MCF_PSC_RFSR_IP (0x8000) +#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) +#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) +#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) +#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF_PSC_TFSR */ +#define MCF_PSC_TFSR_EMT (0x0001) +#define MCF_PSC_TFSR_ALARM (0x0002) +#define MCF_PSC_TFSR_FU (0x0004) +#define MCF_PSC_TFSR_FRMRY (0x0008) +#define MCF_PSC_TFSR_OF (0x0010) +#define MCF_PSC_TFSR_UF (0x0020) +#define MCF_PSC_TFSR_RXW (0x0040) +#define MCF_PSC_TFSR_FAE (0x0080) +#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) +#define MCF_PSC_TFSR_TAG (0x1000) +#define MCF_PSC_TFSR_TXW (0x4000) +#define MCF_PSC_TFSR_IP (0x8000) +#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) +#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) +#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) +#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) + +/* Bit definitions and macros for MCF_PSC_RFCR */ +#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF_PSC_RFCR_TXW_MSK (0x00040000) +#define MCF_PSC_RFCR_OF_MSK (0x00080000) +#define MCF_PSC_RFCR_UF_MSK (0x00100000) +#define MCF_PSC_RFCR_RXW_MSK (0x00200000) +#define MCF_PSC_RFCR_FAE_MSK (0x00400000) +#define MCF_PSC_RFCR_IP_MSK (0x00800000) +#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF_PSC_RFCR_FRMEN (0x08000000) +#define MCF_PSC_RFCR_TIMER (0x10000000) +#define MCF_PSC_RFCR_WRITETAG (0x20000000) +#define MCF_PSC_RFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF_PSC_TFCR */ +#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +#define MCF_PSC_TFCR_TXW_MSK (0x00040000) +#define MCF_PSC_TFCR_OF_MSK (0x00080000) +#define MCF_PSC_TFCR_UF_MSK (0x00100000) +#define MCF_PSC_TFCR_RXW_MSK (0x00200000) +#define MCF_PSC_TFCR_FAE_MSK (0x00400000) +#define MCF_PSC_TFCR_IP_MSK (0x00800000) +#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) +#define MCF_PSC_TFCR_FRMEN (0x08000000) +#define MCF_PSC_TFCR_TIMER (0x10000000) +#define MCF_PSC_TFCR_WRITETAG (0x20000000) +#define MCF_PSC_TFCR_SHADOW (0x80000000) + +/* Bit definitions and macros for MCF_PSC_RFAR */ +#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TFAR */ +#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_RFRP */ +#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TFRP */ +#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_RFWP */ +#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TFWP */ +#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_RLRFP */ +#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TLRFP */ +#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_RLWFP */ +#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) + +/* Bit definitions and macros for MCF_PSC_TLWFP */ +#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) + +/******************************************************************* + * SECURITY + ******************************************************************/ +//FIXME - not all Coldfires supports this, like MCF5484LITE + + +#define SEC_EUACR_U MCF_REG32(0x21000) +#define SEC_EUACR_L MCF_REG32(0x21004) +#define SEC_EUASR_U MCF_REG32(0x21028) +#define SEC_EUASR_L MCF_REG32(0x2102C) +#define SEC_SMCR MCF_REG32(0x21030) +#define SEC_SISR_U MCF_REG32(0x21010) +#define SEC_SISR_L MCF_REG32(0x21014) +#define SEC_SICR_U MCF_REG32(0x21018) +#define SEC_SICR_L MCF_REG32(0x2101C) +#define SEC_SIMR_U MCF_REG32(0x21008) +#define SEC_SIMR_L MCF_REG32(0x2100C) +#define SEC_SID MCF_REG32(0x21020) + +#define SEC_SMCR_RESET 0x01000000 +#define SEC_SIMR_MASK_U 0x00000000 +#define SEC_SIMR_MASK_L 0x03333340 + +#define SEC_CC0_FR MCF_REG32(0x2204C) +#define SEC_CC0_CR MCF_REG32(0x2200C) +#define SEC_CC0_CDPR MCF_REG32(0x22044) +#define SEC_CC0_PSR_U MCF_REG32(0x22010) +#define SEC_CC0_PSR_L MCF_REG32(0x22014) +#define SEC_CC1_FR MCF_REG32(0x2304C) +#define SEC_CC1_CR MCF_REG32(0x2300C) +#define SEC_CC1_CDPR MCF_REG32(0x23044) +#define SEC_CC1_PSR_U MCF_REG32(0x23010) +#define SEC_CC1_PSR_L MCF_REG32(0x23014) + +#define SEC_CC_CR_RESET 0x00000001 +#define SEC_CC_CR_CONFIGURATION 0x0000001E +#define SEC_CC_PSR_U_ERR_CH0 0x20000000 +#define SEC_CC_PSR_U_ERR_CH1 0x80000000 +#define SEC_CC_PSR_U_DN_CH0 0x10000000 +#define SEC_CC_PSR_U_DN_CH1 0x40000000 + +#define SEC_DEU_DRCR MCF_REG32(0x2A018) +#define SEC_DEU_DSR MCF_REG32(0x2A028) +#define SEC_DEU_DISR MCF_REG32(0x2A030) +#define SEC_DEU_DIMR MCF_REG32(0x2A038) + +#define SEC_DEU_DRCR_RESET 0x01000000 +#define SEC_DEU_DSR_RD 0x01000000 +#define SEC_DEU_DIMR_MASK 0xF63F0000 + +#define SEC_AFEU_AFRCR MCF_REG32(0x28018) +#define SEC_AFEU_AFSR MCF_REG32(0x28028) +#define SEC_AFEU_AFISR MCF_REG32(0x28030) +#define SEC_AFEU_AFIMR MCF_REG32(0x28038) + +#define SEC_AFEU_AFRCR_RESET 0x01000000 +#define SEC_AFEU_AFSR_RD 0x01000000 +#define SEC_AFEU_AFIMR_MASK 0xF61F0000 + + +#define SEC_MDEU_MDRCR MCF_REG32(0x2C018) +#define SEC_MDEU_MDSR MCF_REG32(0x2C028) +#define SEC_MDEU_MDISR MCF_REG32(0x2C030) +#define SEC_MDEU_MDIMR MCF_REG32(0x2C038) + +#define SEC_MDEU_MDRCR_RESET 0x01000000 +#define SEC_MDEU_MDSR_RD 0x01000000 +#define SEC_MDEU_MDIMR_MASK 0xC41F0000 + + +#define SEC_RNG_RNGRCR MCF_REG32(0x2E018) +#define SEC_RNG_RNGSR MCF_REG32(0x2E028) +#define SEC_RNG_RNGISR MCF_REG32(0x2E030) +#define SEC_RNG_RNGIMR MCF_REG32(0x2E038) + +#define SEC_RNG_RNGRCR_RESET 0x01000000 +#define SEC_RNG_RNGSR_RD 0x01000000 +#define SEC_RNG_RNGIMR_MASK 0xC2100000 + +#define SEC_AESU_AESRCR MCF_REG32(0x32018) +#define SEC_AESU_AESSR MCF_REG32(0x32028) +#define SEC_AESU_AESISR MCF_REG32(0x32030) +#define SEC_AESU_AESIMR MCF_REG32(0x32038) + +#define SEC_AESU_AESRCR_RESET 0x01000000 +#define SEC_AESU_AESSR_RD 0x01000000 +#define SEC_AESU_AESIMR_MASK 0xF61F0000 + + +#define SEC_DESC_NUM 20 +#define SEC_CHANNEL_NUMBER 2 +#define SEC_MAX_BUF_SIZE 32*1024 +#define SEC_INIT_TIMEOUT 1*HZ +#define SEC_INTERRUPT 37 + +/* Header descriptor values*/ +#define SEC_ALG_ENCR_DES_ECB_SINGLE 0x20100010 +#define SEC_ALG_DECR_DES_ECB_SINGLE 0x20000010 +#define SEC_ALG_ENCR_DES_ECB_TRIPLE 0x20300010 +#define SEC_ALG_DECR_DES_ECB_TRIPLE 0x20200010 +#define SEC_ALG_ENCR_DES_CBC_SINGLE 0x20500010 +#define SEC_ALG_DECR_DES_CBC_SINGLE 0x20400010 +#define SEC_ALG_ENCR_DES_CBC_TRIPLE 0x20700010 +#define SEC_ALG_DECR_DES_CBC_TRIPLE 0x20600010 + +#define SEC_ALG_MDEU_SHA256 0x30500010 +#define SEC_ALG_MDEU_MD5 0x30600010 +#define SEC_ALG_MDEU_SHA 0x30400010 +#define SEC_ALG_MDEU_SHA256_HMAC 0x31D00010 +#define SEC_ALG_MDEU_MD5_HMAC 0x31E00010 +#define SEC_ALG_MDEU_SHA_HMAC 0x31C00010 + +#define SEC_ALG_RNG 0x40000010 + + +#define SEC_ALG_AFEU_KEY 0x10200050 +#define SEC_ALG_AFEU_CONTEXT 0x10700050 + +#define SEC_ALG_ENCR_AESU_CBC 0x60300010 +#define SEC_ALG_DECR_AESU_CBC 0x60200010 +#define SEC_ALG_ENCR_AESU_ECB 0x60100010 +#define SEC_ALG_DECR_AESU_ECB 0x60000010 +#define SEC_ALG_AESU_CTR 0x60600010 + + + +#define SEC_DESCHEAD_ERROR 0xFE000000 +#define SEC_DESCHEAD_COMPLETED 0xFF000000 + +#define SEC_DEVICE_NAME "cfsec" + +/*!!! This number must be changed*/ +#define SEC_MAJOR 130 + +#define SEC_DEV_BUF 1024 +#define SEC_DEV_KEY_LEN 64 +#define SEC_DEV_VECTOR_LEN 259 + +#define SEC_AES_BLCK_LEN 16 +#define SEC_DES_BLCK_LEN 8 + + +/* Descriptor structure of SEC*/ +struct sec_descriptor { + volatile unsigned long secdesc_header; + unsigned long secdesc_len1; + void *secdesc_ptr1; + unsigned long secdesc_iv_in_len; + void *secdesc_iv_in_ptr; + unsigned long secdesc_key_len; + void *secdesc_key_ptr; + unsigned long secdesc_data_in_len; + void *secdesc_data_in_ptr; + unsigned long secdesc_data_out_len; + void *secdesc_data_out_ptr; + unsigned long secdesc_iv_out_len; + void *secdesc_iv_out_ptr; + unsigned long secdesc_len7; + void *secdesc_ptr7; + void *secdesc_ptrnext; +}; + +struct sec_device_data { + unsigned char secdev_inbuf[SEC_DEV_BUF]; + unsigned char secdev_outbuf[SEC_DEV_BUF]; + unsigned char secdev_key[SEC_DEV_KEY_LEN]; + unsigned char secdev_iv[SEC_DEV_VECTOR_LEN]; + unsigned char secdev_ov[SEC_DEV_VECTOR_LEN]; + struct sec_descriptor *secdev_desc; +}; + +struct sec_descriptor *sec_desc_alloc(void); +inline void sec_desc_free(struct sec_descriptor *desc); +int sec_execute(int channel, struct sec_descriptor *desc, int timeout); +int sec_nonblock_execute(struct sec_descriptor *desc); + +#endif /* __MCF548X_PSC_H__ */ diff --git a/arch/m68k/include/asm/m548xsram.h b/arch/m68k/include/asm/m548xsram.h new file mode 100644 index 000000000000..e663c8e3ff99 --- /dev/null +++ b/arch/m68k/include/asm/m548xsram.h @@ -0,0 +1,12 @@ +#ifndef _M548X_SRAM_H +#define _M548X_SRAM_H + + +#define SYS_SRAM_DMA_START MCF_MBAR + 0x10000 +#define SYS_SRAM_DMA_SIZE 8192 +#define SYS_SRAM_FEC_START SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE +#define SYS_SRAM_FEC_SIZE 2048 +#define SYS_SRAM_SEC_START SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE +#define SYS_SRAM_SEC_SIZE 1280 + +#endif /* _M548X_SRAM_H */ diff --git a/arch/m68k/include/asm/mcf5445x_ccm.h b/arch/m68k/include/asm/mcf5445x_ccm.h new file mode 100644 index 000000000000..76f2f501abe4 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_ccm.h @@ -0,0 +1,163 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_CCM_H__ +#define __MCF5445X_CCM_H__ + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) /* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */ +#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) /* Reset Configuration (Read-only) (256 or 360 TEPBGA) */ +#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) /* Chip Identification Register (Read-only) */ +#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) /* Miscellaneous Control Register */ +#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */ +#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) /* USB On-the-Go Controller Status Register */ +#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) /* Serial Boot Facility Status Register (Read Only) */ +#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) /* Serial Boot Facility Control Register */ + +/* Bit definitions and macros for CCR_360 */ +#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) /* 2-Bit PLL clock mode */ +#define MCF_CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */ +#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */ +#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL Clock Mode */ +#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */ +#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0) +#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003) +#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007) +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000) +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020) +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040) +#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060) +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080) +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0) +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0) +#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0) +#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000) +#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001) +#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002) +#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003) +#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000) +#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001) +#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002) +#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003) +#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004) +#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005) +#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006) +#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for CCR_256 */ +#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL clock mode */ +#define MCF_CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */ +#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */ +#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0) +#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000) +#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020) +#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040) +#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080) +#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0) +#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0) +#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007) +#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000) +#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001) +#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002) +#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003) +#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004) +#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005) +#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006) +#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007) + +/* Bit definitions and macros for RCON_360 */ +#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */ +#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */ +#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */ +#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */ +#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for RCON_256 */ +#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */ +#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */ +#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */ +#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */ + +/* Bit definitions and macros for CIR */ +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) /* Part revision number */ +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) /* Part identification number */ +#define MCF_CCM_CIR_PIN_MASK (0xFFC0) +#define MCF_CCM_CIR_PRN_MASK (0x003F) +#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6) +#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6) +#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6) +#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6) +#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6) +#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6) + +/* Bit definitions and macros for MISCCR */ +#define MCF_CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ +#define MCF_CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */ +#define MCF_CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */ +#define MCF_CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define MCF_CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define MCF_CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define MCF_CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) /* Bus monitor timing field */ +#define MCF_CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */ +#define MCF_CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ +#define MCF_CCM_MISCCR_BMT_65536 (0 << 8) +#define MCF_CCM_MISCCR_BMT_32768 (1 << 8) +#define MCF_CCM_MISCCR_BMT_16384 (2 << 8) +#define MCF_CCM_MISCCR_BMT_8192 (3 << 8) +#define MCF_CCM_MISCCR_BMT_4096 (4 << 8) +#define MCF_CCM_MISCCR_BMT_2048 (5 << 8) +#define MCF_CCM_MISCCR_BMT_1024 (6 << 8) +#define MCF_CCM_MISCCR_BMT_512 (7 << 8) +#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7) +#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7) +#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6) +#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6) +#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5) +#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5) +#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4) +#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4) +#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1) +#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1) +#define MCF_CCM_MISCCR_USBSRC_CLKIN (0) +#define MCF_CCM_MISCCR_USBSRC_PLL (1) + +/* Bit definitions and macros for CDR */ +#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) /* SSI oversampling clock divider */ +#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) /* Low power clock divider */ + +/* Bit definitions and macros for UOCSR */ +#define MCF_CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */ +#define MCF_CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */ +#define MCF_CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define MCF_CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */ +#define MCF_CCM_UOCSR_SEND (0x0010) /* Session end */ +#define MCF_CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define MCF_CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define MCF_CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define MCF_CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */ +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */ +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */ +#define MCF_CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */ +#define MCF_CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */ + +/********************************************************************/ + +#endif /* __MCF5445X_CCM_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_dspi.h b/arch/m68k/include/asm/mcf5445x_dspi.h new file mode 100644 index 000000000000..16b2b0897eab --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_dspi.h @@ -0,0 +1,402 @@ +/* + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_DSPI_H__ +#define __MCF5445X_DSPI_H__ + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) /* DSPI Module Configuration Register */ +#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) /* DSPI Transfer Count Register */ +#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) /* DSPI Status Register */ +#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) /* DSPI DMA/Interrupt Request Select and Enable Register */ +#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) /* DSPI Transmit FIFO Register */ +#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) /* DSPI Receive FIFO Register */ +#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) /* DSPI Transmit FIFO Debugging Registers */ +#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) /* DSPI Transmit FIFO Debugging Registers */ +#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) /* DSPI Transmit FIFO Debugging Registers */ +#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) /* DSPI Transmit FIFO Debugging Registers */ +#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) /* DSPI Receive FIFO Debugging Registers */ +#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) /* DSPI Receive FIFO Debugging Registers */ +#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) /* DSPI Receive FIFO Debugging Registers */ +#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) /* DSPI Receive FIFO Debugging Registers */ + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) /* DSPI Clock and Transfer Attributes Register */ +#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) /* DSPI Transmit FIFO Debugging Registers */ +#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) /* DSPI Receive FIFO Debugging Registers */ + +/* Bit definitions and macros for DMCR */ +#define MCF_DSPI_DMCR_HALT (0x00000001) /* Halt -- stops and starts DSPI transfers */ +#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) /* Sample point selection */ +#define MCF_DSPI_DMCR_CLRRXF (0x00000400) /* Clear receive FIFO */ +#define MCF_DSPI_DMCR_CLRTXF (0x00000800) /* Clear transmit FIFO */ +#define MCF_DSPI_DMCR_DISRXF (0x00001000) /* Disable receive FIFO */ +#define MCF_DSPI_DMCR_DISTXF (0x00002000) /* Disable transmit FIFO */ +#define MCF_DSPI_DMCR_MDIS (0x00004000) /* Module Disable */ +#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) /* Peripheral chip-select 0 inactive state */ +#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) /* Peripheral chip-select 1 inactive state */ +#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) /* Peripheral chip-select 2 inactive state */ +#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) /* Peripheral chip-select 3 inactive state */ +#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) /* Peripheral chip-select 4 inactive state */ +#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) /* Peripheral chip-select 5 inactive state */ +#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) /* Peripheral chip-select 6 inactive state */ +#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) /* Peripheral chip-select 7 inactive state */ +#define MCF_DSPI_DMCR_ROOE (0x01000000) /* Receive FIFO overflow overwrite enable */ +#define MCF_DSPI_DMCR_PCSSE (0x02000000) /* Peripheral chip select strobe enable */ +#define MCF_DSPI_DMCR_MTFE (0x04000000) /* Modified timing format enable */ +#define MCF_DSPI_DMCR_FRZ (0x08000000) /* Freeze */ +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) /* DSPI configuration */ +#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) /* Continuous SCK enable */ +#define MCF_DSPI_DMCR_MSTR (0x80000000) /* Master/Slave mode select */ +#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000) +#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000) +#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000) +#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000) +#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000) +#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000) +#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000) +#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000) +#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000) +#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000) + +/* Bit definitions and macros for DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) /* SPI transfer count */ + +/* Bit definitions and macros for DCTAR group */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR_DBR (0x80000000) /* Double baud rate */ +#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000) +#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000) +#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000) +#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000) +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000) +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000) +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000) +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000) +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000) +#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for DCTAR0 */ +#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR0_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR0_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR0_DBR (0x80000000) /* Double baud rate */ +#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000) +#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000) +#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000) +#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000) +#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000) +#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000) +#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000) +#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000) +#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000) +#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000) +#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000) +#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000) +#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000) +#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000) +#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000) +#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000) +#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000) +#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000) +#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000) +#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000) + +/* Bit definitions and macros for DCTAR1 */ +#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR1_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR1_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR1_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR2 */ +#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR2_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR2_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR2_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR3 */ +#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR3_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR3_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR3_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR4 */ +#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR4_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR4_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR4_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR5 */ +#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR5_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR5_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR5_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR6 */ +#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR6_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR6_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR6_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DCTAR7 */ +#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */ +#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */ +#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */ +#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */ +#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */ +#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */ +#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */ +#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */ +#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) /* LSB first enable */ +#define MCF_DSPI_DCTAR7_CPHA (0x02000000) /* Clock phase */ +#define MCF_DSPI_DCTAR7_CPOL (0x04000000) /* Clock polarity */ +#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */ +#define MCF_DSPI_DCTAR7_DBR (0x80000000) /* Double baud rate */ + +/* Bit definitions and macros for DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) /* Receive next pointer */ +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) /* Receive FIFO counter */ +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) /* Transmit next pointer */ +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) /* Transmit FIFO counter */ +#define MCF_DSPI_DSR_RFDF (0x00020000) /* Receive FIFO drain flag */ +#define MCF_DSPI_DSR_RFOF (0x00080000) /* Receive FIFO overflow flag */ +#define MCF_DSPI_DSR_TFFF (0x02000000) /* Transmit FIFO fill flag */ +#define MCF_DSPI_DSR_TFUF (0x08000000) /* Transmit FIFO underflow flag */ +#define MCF_DSPI_DSR_EOQF (0x10000000) /* End of queue flag */ +#define MCF_DSPI_DSR_TXRXS (0x40000000) /* Tx and Rx status (enabled | disabled) */ +#define MCF_DSPI_DSR_TCF (0x80000000) /* Transfer complete flag */ + +/* Bit definitions and macros for DRSER */ +#define MCF_DSPI_DRSER_RFDFS (0x00010000) /* Receive FIFO drain DMA or interrupt select */ +#define MCF_DSPI_DRSER_RFDFE (0x00020000) /* Receive FIFO drain request enable */ +#define MCF_DSPI_DRSER_RFOFE (0x00080000) /* Receive FIFO overflow request enable */ +#define MCF_DSPI_DRSER_TFFFS (0x01000000) /* Transmit FIFO fill DMA or interrupt select */ +#define MCF_DSPI_DRSER_TFFFE (0x02000000) /* Transmit FIFO fill request enable */ +#define MCF_DSPI_DRSER_TFUFE (0x08000000) /* Transmit FIFO underflow request enable */ +#define MCF_DSPI_DRSER_EOQFE (0x10000000) /* DSPI finished request enable */ +#define MCF_DSPI_DRSER_TCFE (0x80000000) /* Transmission complete request enable */ + +/* Bit definitions and macros for DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFR_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFR_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFR_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFR_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFR_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFR_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFR_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFR_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFR_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFR_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFR_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/* Bit definitions and macros for DTFDR group */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFDR_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFDR_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFDR_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFDR_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFDR_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFDR_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFDR_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFDR_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFDR_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFDR_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFDR_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DTFDR0 */ +#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFDR0_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFDR0_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DTFDR1 */ +#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFDR1_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFDR1_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DTFDR2 */ +#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFDR2_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFDR2_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DTFDR3 */ +#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */ +#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) /* Peripheral chip select 0 */ +#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) /* Peripheral chip select 1 */ +#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) /* Peripheral chip select 2 */ +#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) /* Peripheral chip select 3 */ +#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) /* Peripheral chip select 4 */ +#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) /* Peripheral chip select 5 */ +#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) /* Peripheral chip select 6 */ +#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) /* Peripheral chip select 7 */ +#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) /* Clear SPI transfer counter */ +#define MCF_DSPI_DTFDR3_EOQ (0x08000000) /* End of queue */ +#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */ +#define MCF_DSPI_DTFDR3_CONT (0x80000000) /* Continuous peripheral chip-select enable */ + +/* Bit definitions and macros for DRFDR group */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/* Bit definitions and macros for DRFDR0 */ +#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/* Bit definitions and macros for DRFDR1 */ +#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/* Bit definitions and macros for DRFDR2 */ +#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/* Bit definitions and macros for DRFDR3 */ +#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */ + +/********************************************************************/ + +#endif /* __MCF5445X_DSPI_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_dtim.h b/arch/m68k/include/asm/mcf5445x_dtim.h new file mode 100644 index 000000000000..27288595938d --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_dtim.h @@ -0,0 +1,87 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_DTIM_H__ +#define __MCF5445X_DTIM_H__ + +/********************************************************************* +* +* DMA Timers (DTIM) +* +*********************************************************************/ +/* Register read/write macros */ +#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */ +#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */ +#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */ +#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */ +#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */ +#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */ +#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */ +#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */ +#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */ +#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */ +#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */ +#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */ +#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */ +#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */ +#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */ +#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */ +#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */ +#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */ +#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */ +#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */ +#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */ +#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */ +#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */ +#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */ + +/* Parameterized register read/write macros for multiple modules */ +#define MCF_DTIM_DTMR(x) 0xFC070000+((x)*0x4000) /* DMA Timer Mode Register */ +#define MCF_DTIM_DTXMR(x) 0xFC070002+((x)*0x4000) /* DMA Timer Extended Mode Register */ +#define MCF_DTIM_DTER(x) 0xFC070003+((x)*0x4000) /* DMA Timer Event Register */ +#define MCF_DTIM_DTRR(x) 0xFC070004+((x)*0x4000) /* DMA Timer Reference Register */ +#define MCF_DTIM_DTCR(x) 0xFC070008+((x)*0x4000) /* DMA Timer Capture Register */ +#define MCF_DTIM_DTCN(x) 0xFC07000C+((x)*0x4000) /* DMA Timer Counter Register */ + +/* Bit definitions and macros for DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */ +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */ +#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */ +#define MCF_DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */ +#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */ +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */ +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */ +#define MCF_DTIM_DTMR_RST_EN (0x0001) +#define MCF_DTIM_DTMR_RST_RST (0x0000) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */ +#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */ + +/* Bit definitions and macros for DTER */ +#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */ +#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */ + +/* Interrupts used for system timers */ +#define MCFSIM_ICR_TIMER1 (0xFC048040+32) +#define MCFSIM_ICR_TIMER2 (0xFC048040+33) + +/********************************************************************/ + +#endif /* __MCF5445X_DTIM_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_edma.h b/arch/m68k/include/asm/mcf5445x_edma.h new file mode 100644 index 000000000000..8f34ef26bf2c --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_edma.h @@ -0,0 +1,1472 @@ +/* + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __MCF5445X_EDMA_H__ +#define __MCF5445X_EDMA_H__ + +/* + * Enhanced DMA (EDMA) + */ + +/* Channels */ +#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */ +#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */ +#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */ +#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */ +#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */ +#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */ +#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */ +#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */ +#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */ +#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */ +#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */ +#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */ +#define MCF_EDMA_CHAN_DSPI_RX 12 /* DSPI Receive */ +#define MCF_EDMA_CHAN_DSPI_TX 13 /* DSPI Transmit */ +#define MCF_EDMA_CHAN_ATA_RX 14 /* ATA Receive */ +#define MCF_EDMA_CHAN_ATA_TX 15 /* ATA Transmit */ + +/* Register read/write macros */ +#define MCF_EDMA_CR MCF_REG32(0xFC044000) +#define MCF_EDMA_ES MCF_REG32(0xFC044004) +#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E) +#define MCF_EDMA_EEI MCF_REG16(0xFC044016) +#define MCF_EDMA_SERQ MCF_REG08(0xFC044018) +#define MCF_EDMA_CERQ MCF_REG08(0xFC044019) +#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A) +#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B) +#define MCF_EDMA_CINT MCF_REG08(0xFC04401C) +#define MCF_EDMA_CERR MCF_REG08(0xFC04401D) +#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E) +#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F) +#define MCF_EDMA_INTR MCF_REG16(0xFC044026) +#define MCF_EDMA_ERR MCF_REG16(0xFC04402E) +#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100) +#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101) +#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102) +#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103) +#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104) +#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105) +#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106) +#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107) +#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108) +#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109) +#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A) +#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B) +#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C) +#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D) +#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E) +#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F) +#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000) +#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004) +#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006) +#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008) +#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C) +#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010) +#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014) +#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014) +#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016) +#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018) +#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C) +#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C) +#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E) +#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020) +#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024) +#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026) +#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028) +#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C) +#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030) +#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034) +#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034) +#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036) +#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038) +#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C) +#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C) +#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E) +#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040) +#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044) +#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046) +#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048) +#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C) +#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050) +#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054) +#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054) +#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056) +#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058) +#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C) +#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C) +#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E) +#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060) +#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064) +#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066) +#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068) +#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C) +#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070) +#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074) +#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074) +#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076) +#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078) +#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C) +#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C) +#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E) +#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080) +#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084) +#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086) +#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088) +#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C) +#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090) +#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094) +#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094) +#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096) +#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098) +#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C) +#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C) +#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E) +#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0) +#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4) +#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6) +#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8) +#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC) +#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0) +#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4) +#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4) +#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6) +#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8) +#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC) +#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC) +#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE) +#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0) +#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4) +#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6) +#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8) +#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC) +#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0) +#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4) +#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4) +#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6) +#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8) +#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC) +#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC) +#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE) +#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0) +#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4) +#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6) +#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8) +#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC) +#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0) +#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4) +#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4) +#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6) +#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8) +#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC) +#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC) +#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE) +#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100) +#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104) +#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106) +#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108) +#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C) +#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110) +#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114) +#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114) +#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116) +#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118) +#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C) +#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C) +#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E) +#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120) +#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124) +#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126) +#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128) +#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C) +#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130) +#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134) +#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134) +#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136) +#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138) +#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C) +#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C) +#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E) +#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140) +#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144) +#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146) +#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148) +#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C) +#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150) +#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154) +#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154) +#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156) +#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158) +#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C) +#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C) +#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E) +#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160) +#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164) +#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166) +#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168) +#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C) +#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170) +#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174) +#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174) +#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176) +#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178) +#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C) +#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C) +#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E) +#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180) +#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184) +#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186) +#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188) +#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C) +#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190) +#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194) +#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194) +#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196) +#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198) +#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C) +#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C) +#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E) +#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0) +#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4) +#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6) +#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8) +#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC) +#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0) +#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4) +#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4) +#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6) +#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8) +#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC) +#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC) +#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE) +#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0) +#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4) +#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6) +#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8) +#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC) +#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0) +#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4) +#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4) +#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6) +#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8) +#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC) +#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC) +#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE) +#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0) +#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4) +#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6) +#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8) +#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC) +#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0) +#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4) +#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4) +#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6) +#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8) +#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC) +#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC) +#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE) + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001)) +#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020)) +#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020)) +#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020)) +#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020)) +#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020)) +#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020)) +#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020)) +#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020)) +#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020)) +#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020)) +#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020)) +#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020)) +#define MCF_EDMA_TCD_CSR(x) MCF_REG16(0xFC04501e +((x)*0x020)) + +/* Bit definitions and macros for CR */ +#define MCF_EDMA_CR_EDBG (0x00000002) +#define MCF_EDMA_CR_ERCA (0x00000004) + +/* Bit definitions and macros for ES */ +#define MCF_EDMA_ES_DBE (0x00000001) +#define MCF_EDMA_ES_SBE (0x00000002) +#define MCF_EDMA_ES_SGE (0x00000004) +#define MCF_EDMA_ES_NCE (0x00000008) +#define MCF_EDMA_ES_DOE (0x00000010) +#define MCF_EDMA_ES_DAE (0x00000020) +#define MCF_EDMA_ES_SOE (0x00000040) +#define MCF_EDMA_ES_SAE (0x00000080) +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8) +#define MCF_EDMA_ES_CPE (0x00004000) +#define MCF_EDMA_ES_VLD (0x80000000) + +/* Bit definitions and macros for ERQ */ +#define MCF_EDMA_ERQ_ERQ0 (0x0001) +#define MCF_EDMA_ERQ_ERQ1 (0x0002) +#define MCF_EDMA_ERQ_ERQ2 (0x0004) +#define MCF_EDMA_ERQ_ERQ3 (0x0008) +#define MCF_EDMA_ERQ_ERQ4 (0x0010) +#define MCF_EDMA_ERQ_ERQ5 (0x0020) +#define MCF_EDMA_ERQ_ERQ6 (0x0040) +#define MCF_EDMA_ERQ_ERQ7 (0x0080) +#define MCF_EDMA_ERQ_ERQ8 (0x0100) +#define MCF_EDMA_ERQ_ERQ9 (0x0200) +#define MCF_EDMA_ERQ_ERQ10 (0x0400) +#define MCF_EDMA_ERQ_ERQ11 (0x0800) +#define MCF_EDMA_ERQ_ERQ12 (0x1000) +#define MCF_EDMA_ERQ_ERQ13 (0x2000) +#define MCF_EDMA_ERQ_ERQ14 (0x4000) +#define MCF_EDMA_ERQ_ERQ15 (0x8000) + +/* Bit definitions and macros for EEI */ +#define MCF_EDMA_EEI_EEI0 (0x0001) +#define MCF_EDMA_EEI_EEI1 (0x0002) +#define MCF_EDMA_EEI_EEI2 (0x0004) +#define MCF_EDMA_EEI_EEI3 (0x0008) +#define MCF_EDMA_EEI_EEI4 (0x0010) +#define MCF_EDMA_EEI_EEI5 (0x0020) +#define MCF_EDMA_EEI_EEI6 (0x0040) +#define MCF_EDMA_EEI_EEI7 (0x0080) +#define MCF_EDMA_EEI_EEI8 (0x0100) +#define MCF_EDMA_EEI_EEI9 (0x0200) +#define MCF_EDMA_EEI_EEI10 (0x0400) +#define MCF_EDMA_EEI_EEI11 (0x0800) +#define MCF_EDMA_EEI_EEI12 (0x1000) +#define MCF_EDMA_EEI_EEI13 (0x2000) +#define MCF_EDMA_EEI_EEI14 (0x4000) +#define MCF_EDMA_EEI_EEI15 (0x8000) + +/* Bit definitions and macros for SERQ */ +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F)) +#define MCF_EDMA_SERQ_SAER (0x40) + +/* Bit definitions and macros for CERQ */ +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F)) +#define MCF_EDMA_CERQ_CAER (0x40) + +/* Bit definitions and macros for SEEI */ +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F)) +#define MCF_EDMA_SEEI_SAEE (0x40) + +/* Bit definitions and macros for CEEI */ +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F)) +#define MCF_EDMA_CEEI_CAEE (0x40) + +/* Bit definitions and macros for CINT */ +#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F)) +#define MCF_EDMA_CINT_CAIR (0x40) + +/* Bit definitions and macros for CERR */ +#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F)) +#define MCF_EDMA_CERR_CAER (0x40) + +/* Bit definitions and macros for SSRT */ +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F)) +#define MCF_EDMA_SSRT_SAST (0x40) + +/* Bit definitions and macros for CDNE */ +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F)) +#define MCF_EDMA_CDNE_CADN (0x40) + +/* Bit definitions and macros for INTR */ +#define MCF_EDMA_INTR_INT0 (0x0001) +#define MCF_EDMA_INTR_INT1 (0x0002) +#define MCF_EDMA_INTR_INT2 (0x0004) +#define MCF_EDMA_INTR_INT3 (0x0008) +#define MCF_EDMA_INTR_INT4 (0x0010) +#define MCF_EDMA_INTR_INT5 (0x0020) +#define MCF_EDMA_INTR_INT6 (0x0040) +#define MCF_EDMA_INTR_INT7 (0x0080) +#define MCF_EDMA_INTR_INT8 (0x0100) +#define MCF_EDMA_INTR_INT9 (0x0200) +#define MCF_EDMA_INTR_INT10 (0x0400) +#define MCF_EDMA_INTR_INT11 (0x0800) +#define MCF_EDMA_INTR_INT12 (0x1000) +#define MCF_EDMA_INTR_INT13 (0x2000) +#define MCF_EDMA_INTR_INT14 (0x4000) +#define MCF_EDMA_INTR_INT15 (0x8000) + +/* Bit definitions and macros for ERR */ +#define MCF_EDMA_ERR_ERR0 (0x0001) +#define MCF_EDMA_ERR_ERR1 (0x0002) +#define MCF_EDMA_ERR_ERR2 (0x0004) +#define MCF_EDMA_ERR_ERR3 (0x0008) +#define MCF_EDMA_ERR_ERR4 (0x0010) +#define MCF_EDMA_ERR_ERR5 (0x0020) +#define MCF_EDMA_ERR_ERR6 (0x0040) +#define MCF_EDMA_ERR_ERR7 (0x0080) +#define MCF_EDMA_ERR_ERR8 (0x0100) +#define MCF_EDMA_ERR_ERR9 (0x0200) +#define MCF_EDMA_ERR_ERR10 (0x0400) +#define MCF_EDMA_ERR_ERR11 (0x0800) +#define MCF_EDMA_ERR_ERR12 (0x1000) +#define MCF_EDMA_ERR_ERR13 (0x2000) +#define MCF_EDMA_ERR_ERR14 (0x4000) +#define MCF_EDMA_ERR_ERR15 (0x8000) + +/* Bit definitions and macros for DCHPRI group */ +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI_ECP (0x80) + +/* Bit definitions and macros for DCHPRI0 */ +#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI0_ECP (0x80) + +/* Bit definitions and macros for DCHPRI1 */ +#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI1_ECP (0x80) + +/* Bit definitions and macros for DCHPRI2 */ +#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI2_ECP (0x80) + +/* Bit definitions and macros for DCHPRI3 */ +#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI3_ECP (0x80) + +/* Bit definitions and macros for DCHPRI4 */ +#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI4_ECP (0x80) + +/* Bit definitions and macros for DCHPRI5 */ +#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI5_ECP (0x80) + +/* Bit definitions and macros for DCHPRI6 */ +#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI6_ECP (0x80) + +/* Bit definitions and macros for DCHPRI7 */ +#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI7_ECP (0x80) + +/* Bit definitions and macros for DCHPRI8 */ +#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI8_ECP (0x80) + +/* Bit definitions and macros for DCHPRI9 */ +#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI9_ECP (0x80) + +/* Bit definitions and macros for DCHPRI10 */ +#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI10_ECP (0x80) + +/* Bit definitions and macros for DCHPRI11 */ +#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI11_ECP (0x80) + +/* Bit definitions and macros for DCHPRI12 */ +#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI12_ECP (0x80) + +/* Bit definitions and macros for DCHPRI13 */ +#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI13_ECP (0x80) + +/* Bit definitions and macros for DCHPRI14 */ +#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI14_ECP (0x80) + +/* Bit definitions and macros for DCHPRI15 */ +#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F)) +#define MCF_EDMA_DCHPRI15_ECP (0x80) + +/* Bit definitions and macros for TCD_SADDR group */ +#define MCF_EDMA_TCD_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD0_SADDR */ +#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD_ATTR group */ +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11) +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400) +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004) + +/* Bit definitions and macros for TCD0_ATTR */ +#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11) +#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100) +#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200) +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400) +#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000) +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001) +#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002) +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004) + +/* Bit definitions and macros for TCD_SOFF group */ +#define MCF_EDMA_TCD_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD0_SOFF */ +#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD_NBYTES group */ +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD0_NBYTES */ +#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD_SLAST group */ +#define MCF_EDMA_TCD_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD0_SLAST */ +#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD_DADDR group */ +#define MCF_EDMA_TCD_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD0_DADDR */ +#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD_CITER_ELINK group */ +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD0_CITER_ELINK */ +#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD_CITER group */ +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD0_CITER */ +#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD_DOFF group */ +#define MCF_EDMA_TCD_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD0_DOFF */ +#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD_DLAST_SGA group */ +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD0_DLAST_SGA */ +#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD_BITER_ELINK group */ +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD0_BITER_ELINK */ +#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD_BITER group */ +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD0_BITER */ +#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD_CSR group */ +#define MCF_EDMA_TCD_CSR_START (0x0001) +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD_CSR_DONE (0x0080) +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14) +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000) +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000) +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000) + +/* Bit definitions and macros for TCD0_CSR */ +#define MCF_EDMA_TCD0_CSR_START (0x0001) +#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD0_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD0_CSR_DONE (0x0080) +#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14) +#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000) +#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000) +#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000) + +/* Bit definitions and macros for TCD1_SADDR */ +#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD1_ATTR */ +#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD1_SOFF */ +#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD1_NBYTES */ +#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD1_SLAST */ +#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD1_DADDR */ +#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD1_CITER_ELINK */ +#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD1_CITER */ +#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD1_DOFF */ +#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD1_DLAST_SGA */ +#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD1_BITER */ +#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD1_BITER_ELINK */ +#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD1_CSR */ +#define MCF_EDMA_TCD1_CSR_START (0x0001) +#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD1_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD1_CSR_DONE (0x0080) +#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD2_SADDR */ +#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD2_ATTR */ +#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD2_SOFF */ +#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD2_NBYTES */ +#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD2_SLAST */ +#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD2_DADDR */ +#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD2_CITER */ +#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD2_CITER_ELINK */ +#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD2_DOFF */ +#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD2_DLAST_SGA */ +#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD2_BITER_ELINK */ +#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD2_BITER */ +#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD2_CSR */ +#define MCF_EDMA_TCD2_CSR_START (0x0001) +#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD2_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD2_CSR_DONE (0x0080) +#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD3_SADDR */ +#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD3_ATTR */ +#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD3_SOFF */ +#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD3_NBYTES */ +#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD3_SLAST */ +#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD3_DADDR */ +#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD3_CITER */ +#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD3_CITER_ELINK */ +#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD3_DOFF */ +#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD3_DLAST_SGA */ +#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD3_BITER_ELINK */ +#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD3_BITER */ +#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD3_CSR */ +#define MCF_EDMA_TCD3_CSR_START (0x0001) +#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD3_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD3_CSR_DONE (0x0080) +#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD4_SADDR */ +#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD4_ATTR */ +#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD4_SOFF */ +#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD4_NBYTES */ +#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD4_SLAST */ +#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD4_DADDR */ +#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD4_CITER */ +#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD4_CITER_ELINK */ +#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD4_DOFF */ +#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD4_DLAST_SGA */ +#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD4_BITER */ +#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD4_BITER_ELINK */ +#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD4_CSR */ +#define MCF_EDMA_TCD4_CSR_START (0x0001) +#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD4_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD4_CSR_DONE (0x0080) +#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD5_SADDR */ +#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD5_ATTR */ +#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD5_SOFF */ +#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD5_NBYTES */ +#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD5_SLAST */ +#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD5_DADDR */ +#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD5_CITER */ +#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD5_CITER_ELINK */ +#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD5_DOFF */ +#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD5_DLAST_SGA */ +#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD5_BITER_ELINK */ +#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD5_BITER */ +#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD5_CSR */ +#define MCF_EDMA_TCD5_CSR_START (0x0001) +#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD5_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD5_CSR_DONE (0x0080) +#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD6_SADDR */ +#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD6_ATTR */ +#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD6_SOFF */ +#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD6_NBYTES */ +#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD6_SLAST */ +#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD6_DADDR */ +#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD6_CITER */ +#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD6_CITER_ELINK */ +#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD6_DOFF */ +#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD6_DLAST_SGA */ +#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD6_BITER_ELINK */ +#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD6_BITER */ +#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD6_CSR */ +#define MCF_EDMA_TCD6_CSR_START (0x0001) +#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD6_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD6_CSR_DONE (0x0080) +#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD7_SADDR */ +#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD7_ATTR */ +#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD7_SOFF */ +#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD7_NBYTES */ +#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD7_SLAST */ +#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD7_DADDR */ +#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD7_CITER */ +#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD7_CITER_ELINK */ +#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD7_DOFF */ +#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD7_DLAST_SGA */ +#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD7_BITER_ELINK */ +#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD7_BITER */ +#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD7_CSR */ +#define MCF_EDMA_TCD7_CSR_START (0x0001) +#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD7_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD7_CSR_DONE (0x0080) +#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD8_SADDR */ +#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD8_ATTR */ +#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD8_SOFF */ +#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD8_NBYTES */ +#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD8_SLAST */ +#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD8_DADDR */ +#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD8_CITER */ +#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD8_CITER_ELINK */ +#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD8_DOFF */ +#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD8_DLAST_SGA */ +#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD8_BITER_ELINK */ +#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD8_BITER */ +#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD8_CSR */ +#define MCF_EDMA_TCD8_CSR_START (0x0001) +#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD8_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD8_CSR_DONE (0x0080) +#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD9_SADDR */ +#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD9_ATTR */ +#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD9_SOFF */ +#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD9_NBYTES */ +#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD9_SLAST */ +#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD9_DADDR */ +#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD9_CITER_ELINK */ +#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD9_CITER */ +#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD9_DOFF */ +#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD9_DLAST_SGA */ +#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD9_BITER_ELINK */ +#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD9_BITER */ +#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD9_CSR */ +#define MCF_EDMA_TCD9_CSR_START (0x0001) +#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD9_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD9_CSR_DONE (0x0080) +#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD10_SADDR */ +#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD10_ATTR */ +#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD10_SOFF */ +#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD10_NBYTES */ +#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD10_SLAST */ +#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD10_DADDR */ +#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD10_CITER_ELINK */ +#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD10_CITER */ +#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD10_DOFF */ +#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD10_DLAST_SGA */ +#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD10_BITER */ +#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD10_BITER_ELINK */ +#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD10_CSR */ +#define MCF_EDMA_TCD10_CSR_START (0x0001) +#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD10_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD10_CSR_DONE (0x0080) +#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD11_SADDR */ +#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD11_ATTR */ +#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD11_SOFF */ +#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD11_NBYTES */ +#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD11_SLAST */ +#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD11_DADDR */ +#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD11_CITER */ +#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD11_CITER_ELINK */ +#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD11_DOFF */ +#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD11_DLAST_SGA */ +#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD11_BITER */ +#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD11_BITER_ELINK */ +#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD11_CSR */ +#define MCF_EDMA_TCD11_CSR_START (0x0001) +#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD11_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD11_CSR_DONE (0x0080) +#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD12_SADDR */ +#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD12_ATTR */ +#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD12_SOFF */ +#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD12_NBYTES */ +#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD12_SLAST */ +#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD12_DADDR */ +#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD12_CITER */ +#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD12_CITER_ELINK */ +#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD12_DOFF */ +#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD12_DLAST_SGA */ +#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD12_BITER */ +#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD12_BITER_ELINK */ +#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD12_CSR */ +#define MCF_EDMA_TCD12_CSR_START (0x0001) +#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD12_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD12_CSR_DONE (0x0080) +#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD13_SADDR */ +#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD13_ATTR */ +#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD13_SOFF */ +#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD13_NBYTES */ +#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD13_SLAST */ +#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD13_DADDR */ +#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD13_CITER_ELINK */ +#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD13_CITER */ +#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD13_DOFF */ +#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD13_DLAST_SGA */ +#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD13_BITER_ELINK */ +#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD13_BITER */ +#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD13_CSR */ +#define MCF_EDMA_TCD13_CSR_START (0x0001) +#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD13_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD13_CSR_DONE (0x0080) +#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD14_SADDR */ +#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD14_ATTR */ +#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD14_SOFF */ +#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD14_NBYTES */ +#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD14_SLAST */ +#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD14_DADDR */ +#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD14_CITER */ +#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD14_CITER_ELINK */ +#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD14_DOFF */ +#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD14_DLAST_SGA */ +#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD14_BITER_ELINK */ +#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD14_BITER */ +#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD14_CSR */ +#define MCF_EDMA_TCD14_CSR_START (0x0001) +#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD14_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD14_CSR_DONE (0x0080) +#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for TCD15_SADDR */ +#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x) + +/* Bit definitions and macros for TCD15_ATTR */ +#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007)) +#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3) +#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8) +#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11) + +/* Bit definitions and macros for TCD15_SOFF */ +#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x) + +/* Bit definitions and macros for TCD15_NBYTES */ +#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x) + +/* Bit definitions and macros for TCD15_SLAST */ +#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x) + +/* Bit definitions and macros for TCD15_DADDR */ +#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x) + +/* Bit definitions and macros for TCD15_CITER_ELINK */ +#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD15_CITER */ +#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD15_DOFF */ +#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x) + +/* Bit definitions and macros for TCD15_DLAST_SGA */ +#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x) + +/* Bit definitions and macros for TCD15_BITER */ +#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF)) +#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000) + +/* Bit definitions and macros for TCD15_BITER_ELINK */ +#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF)) +#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9) +#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000) + +/* Bit definitions and macros for TCD15_CSR */ +#define MCF_EDMA_TCD15_CSR_START (0x0001) +#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002) +#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004) +#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008) +#define MCF_EDMA_TCD15_CSR_E_SG (0x0010) +#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020) +#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040) +#define MCF_EDMA_TCD15_CSR_DONE (0x0080) +#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8) +#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14) + +#endif /* __MCF5445X_EDMA_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_eport.h b/arch/m68k/include/asm/mcf5445x_eport.h new file mode 100644 index 000000000000..046500120e2e --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_eport.h @@ -0,0 +1,117 @@ +/* + * Kurt Mahan kmahan@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_EPORT_H__ +#define __MCF5445X_EPORT_H__ + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) +#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) +#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) +#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) +#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) + +/* Bit definitions and macros for EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************/ + +#endif /* __MCF5445X_EPORT_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_fbcs.h b/arch/m68k/include/asm/mcf5445x_fbcs.h new file mode 100644 index 000000000000..b9a8c9e4f91c --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_fbcs.h @@ -0,0 +1,182 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_FBCS_H__ +#define __MCF5445X_FBCS_H__ + +/********************************************************************* +* +* FlexBus Chip Selects (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */ +#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */ +#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */ +#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */ +#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */ +#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */ +#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */ +#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */ +#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */ +#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */ +#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */ +#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */ + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) /* Chip-select Addr Register */ +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) /* Chip-select Mask Register */ +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) /* Chip-select Cntl Register */ + +/* Bit definitions and macros for CSAR group */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for CSAR0 */ +#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for CSMR group */ +#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */ +#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */ +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for CSMR0 */ +#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */ +#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */ +#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */ +#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000) +#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000) +#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000) +#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000) +#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000) +#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000) +#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000) +#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000) +#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000) +#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000) +#define MCF_FBCS_CSMR0_BAM_512K (0x00070000) +#define MCF_FBCS_CSMR0_BAM_256K (0x00030000) +#define MCF_FBCS_CSMR0_BAM_128K (0x00010000) +#define MCF_FBCS_CSMR0_BAM_64K (0x00000000) + +/* Bit definitions and macros for CSCR group */ +#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ +#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ +#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ +#define MCF_FBCS_CSCR_PS_8 (0x00000040) +#define MCF_FBCS_CSCR_PS_16 (0x00000080) +#define MCF_FBCS_CSCR_PS_32 (0x00000000) + +/* Bit definitions and macros for CSCR0 */ +#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */ +#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */ +#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */ +#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */ +#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */ +#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ +#define MCF_FBCS_CSCR0_PS_8 (0x00000040) +#define MCF_FBCS_CSCR0_PS_16 (0x00000080) +#define MCF_FBCS_CSCR0_PS_32 (0x00000000) + +/* Bit definitions and macros for CSMR1 */ +#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */ +#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */ +#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ + +/* Bit definitions and macros for CSCR1 */ +#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */ +#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */ +#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */ +#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */ +#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */ +#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +/* Bit definitions and macros for CSMR2 */ +#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */ +#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */ +#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ + +/* Bit definitions and macros for CSCR2 */ +#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */ +#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */ +#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */ +#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */ +#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */ +#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +/* Bit definitions and macros for CSMR3 */ +#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */ +#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */ +#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ + +/* Bit definitions and macros for CSCR3 */ +#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */ +#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */ +#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */ +#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */ +#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */ +#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ +#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ +#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ +#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ +#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */ +#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ + +/********************************************************************/ + +#endif /* __MCF5445X_FBCS_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_gpio.h b/arch/m68k/include/asm/mcf5445x_gpio.h new file mode 100644 index 000000000000..b53701e2beea --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_gpio.h @@ -0,0 +1,1257 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_GPIO_H__ +#define __MCF5445X_GPIO_H__ + +/********************************************************************* +* +* General Purpose I/O Module (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FEC0H MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */ +#define MCF_GPIO_PODR_FEC0L MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */ +#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */ +#define MCF_GPIO_PODR_FBCTL MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */ +#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) /* Flexbus Byte Enable Port Output Data Register */ +#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) /* Flexbus Chip-Select Port Output Data Register */ +#define MCF_GPIO_PODR_DMA MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */ +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */ +#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */ +#define MCF_GPIO_PODR_DSPI MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */ +#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */ +#define MCF_GPIO_PODR_PCI MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */ +#define MCF_GPIO_PODR_USB MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */ +#define MCF_GPIO_PODR_ATAH MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */ +#define MCF_GPIO_PODR_ATAL MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */ +#define MCF_GPIO_PODR_FEC1H MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */ +#define MCF_GPIO_PODR_FEC1L MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */ +#define MCF_GPIO_PODR_FBADH MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */ +#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) /* Flexbus AD Med-High Port Output Data Register */ +#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) /* Flexbus AD Med-Low Port Output Data Register */ +#define MCF_GPIO_PODR_FBADL MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */ +#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */ +#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */ +#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */ +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) /* Flexbus Control Port Data Direction Register */ +#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) /* Flexbus Byte Enable Port Data Direction Register */ +#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) /* Flexbus Chip-Select Port Data Direction Register */ +#define MCF_GPIO_PDDR_DMA MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */ +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */ +#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */ +#define MCF_GPIO_PDDR_DSPI MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */ +#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */ +#define MCF_GPIO_PDDR_PCI MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */ +#define MCF_GPIO_PDDR_USB MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */ +#define MCF_GPIO_PDDR_ATAH MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */ +#define MCF_GPIO_PDDR_ATAL MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */ +#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */ +#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */ +#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) /* Flexbus AD High Port Data Direction Register */ +#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) /* Flexbus AD Med-High Port Data Direction Register */ +#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) /* Flexbus AD Med-Low Port Data Direction Register */ +#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) /* Flexbus AD Low Port Data Direction Register */ +#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */ +#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) /* Flexbus Control Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) /* Flexbus Byte Enable Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) /* Flexbus Chip-Select Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_PCI MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_USB MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_ATAH MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_ATAL MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) /* Flexbus AD High Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) /* Flexbus AD Med-High Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ +#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) /* Flexbus AD Low Port Pin Data/Set Data Register */ +#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */ +#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) /* Flexbus Control Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) /* Flexbus Byte Enable Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) /* Flexbus Chip-Select Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_DMA MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_PCI MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_USB MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_ATAH MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_ATAL MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) /* Flexbus AD High Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) /* Flexbus AD Med-High Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) /* Flexbus AD Med-Low Port Clear Output Data Register */ +#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) /* Flexbus AD Low Port Clear Output Data Register */ +#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */ +#define MCF_GPIO_PAR_DMA MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */ +#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */ +#define MCF_GPIO_PAR_DSPI MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */ +#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) /* Flexbus Byte-Enable Pin Assignment Register */ +#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) /* Flexbus Chip-Select Pin Assignment Register */ +#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */ +#define MCF_GPIO_PAR_USB MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */ +#define MCF_GPIO_PAR_UART MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */ +#define MCF_GPIO_PAR_FECI2C MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */ +#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */ +#define MCF_GPIO_PAR_ATA MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */ +#define MCF_GPIO_PAR_IRQ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */ +#define MCF_GPIO_PAR_PCI MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */ +#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */ +#define MCF_GPIO_MSCR_PCI MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */ +#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */ +#define MCF_GPIO_DSCR_FLEXBUS MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */ +#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */ +#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */ +#define MCF_GPIO_DSCR_DSPI MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */ +#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */ +#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */ +#define MCF_GPIO_DSCR_DMA MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */ +#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */ +#define MCF_GPIO_DSCR_RESET MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */ +#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */ +#define MCF_GPIO_DSCR_USB MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */ +#define MCF_GPIO_DSCR_ATA MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */ + +/* Bit definitions and macros for PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ +#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ +#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ +#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ +#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ +#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ +#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ +#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */ + +/* Bit definitions and macros for PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ +#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ +#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ +#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ +#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ +#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ +#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ +#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ + +/* Bit definitions and macros for PODR_SSI */ +#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */ +#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */ +#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */ +#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */ +#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */ + +/* Bit definitions and macros for PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ +#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */ +#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */ +#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */ + +/* Bit definitions and macros for PODR_BE */ +#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ +#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ +#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ +#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ + +/* Bit definitions and macros for PODR_CS */ +#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */ +#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */ +#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */ + +/* Bit definitions and macros for PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */ +#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */ +#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */ +#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */ + +/* Bit definitions and macros for PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */ +#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */ +#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */ +#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */ +#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ +#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */ + +/* Bit definitions and macros for PODR_UART */ +#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */ +#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */ +#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */ +#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */ +#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */ +#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */ +#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */ +#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */ + +/* Bit definitions and macros for PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */ +#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */ +#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */ +#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */ +#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */ +#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */ +#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */ + +/* Bit definitions and macros for PODR_TIMER */ +#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */ +#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */ +#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */ +#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */ + +/* Bit definitions and macros for PODR_PCI */ +#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ +#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */ +#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */ +#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */ +#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ +#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */ +#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */ +#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ + +/* Bit definitions and macros for PODR_USB */ +#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ +#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */ + +/* Bit definitions and macros for PODR_ATAH */ +#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */ +#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */ +#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */ +#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */ +#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */ +#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */ + +/* Bit definitions and macros for PODR_ATAL */ +#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */ +#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */ +#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */ + +/* Bit definitions and macros for PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ +#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ +#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ +#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ +#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */ +#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ +#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ +#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ + +/* Bit definitions and macros for PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */ +#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */ +#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ +#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ +#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ +#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */ +#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ +#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ + +/* Bit definitions and macros for PODR_FBADH */ +#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */ +#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */ +#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */ +#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */ +#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */ +#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */ +#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */ +#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */ + +/* Bit definitions and macros for PODR_FBADMH */ +#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */ +#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */ +#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */ +#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */ +#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */ +#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */ +#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */ +#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */ + +/* Bit definitions and macros for PODR_FBADML */ +#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */ +#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */ +#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */ +#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */ +#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */ +#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */ +#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */ +#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */ + +/* Bit definitions and macros for PODR_FBADL */ +#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */ +#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */ +#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */ +#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */ +#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */ +#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */ +#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */ +#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */ + +/* Bit definitions and macros for PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ +#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ +#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ +#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ +#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ +#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ +#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ +#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */ + +/* Bit definitions and macros for PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ +#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ +#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ + +/* Bit definitions and macros for PDDR_SSI */ +#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */ +#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */ +#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */ +#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */ +#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */ + +/* Bit definitions and macros for PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ +#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */ +#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */ +#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */ + +/* Bit definitions and macros for PDDR_BE */ +#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ +#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ +#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ +#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ + +/* Bit definitions and macros for PDDR_CS */ +#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */ +#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */ +#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */ + +/* Bit definitions and macros for PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */ +#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */ +#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */ +#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */ + +/* Bit definitions and macros for PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */ +#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */ +#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */ +#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */ +#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ +#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ + +/* Bit definitions and macros for PDDR_UART */ +#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */ +#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */ +#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */ +#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */ +#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */ +#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */ +#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */ +#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */ + +/* Bit definitions and macros for PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */ +#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */ +#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */ +#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */ +#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ +#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */ +#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */ + +/* Bit definitions and macros for PDDR_TIMER */ +#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */ +#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */ +#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */ +#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */ + +/* Bit definitions and macros for PDDR_PCI */ +#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ +#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */ +#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */ +#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ +#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ +#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */ +#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */ +#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ + +/* Bit definitions and macros for PDDR_USB */ +#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ +#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */ + +/* Bit definitions and macros for PDDR_ATAH */ +#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */ +#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */ +#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */ +#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */ +#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */ +#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */ + +/* Bit definitions and macros for PDDR_ATAL */ +#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */ +#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */ +#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */ + +/* Bit definitions and macros for PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ +#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ + +/* Bit definitions and macros for PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ +#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ + +/* Bit definitions and macros for PDDR_FBADH */ +#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */ +#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */ +#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */ +#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */ +#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */ +#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */ +#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */ +#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */ + +/* Bit definitions and macros for PDDR_FBADMH */ +#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */ +#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */ + +/* Bit definitions and macros for PDDR_FBADML */ +#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */ +#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */ +#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */ +#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */ +#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */ +#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */ +#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */ +#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */ + +/* Bit definitions and macros for PDDR_FBADL */ +#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */ +#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */ +#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */ +#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */ +#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */ +#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */ +#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */ +#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */ + +/* Bit definitions and macros for PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV / FEC0_RMII_CRS_DV */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */ + +/* Bit definitions and macros for PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ + +/* Bit definitions and macros for PPDSDR_SSI */ +#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */ +#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */ +#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */ +#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */ +#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */ + +/* Bit definitions and macros for PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */ + +/* Bit definitions and macros for PPDSDR_BE */ +#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ +#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ +#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ +#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ + +/* Bit definitions and macros for PPDSDR_CS */ +#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */ +#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */ +#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */ + +/* Bit definitions and macros for PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */ +#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */ +#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */ +#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */ + +/* Bit definitions and macros for PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */ + +/* Bit definitions and macros for PPDSDR_UART */ +#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */ +#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */ +#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */ +#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */ +#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */ +#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */ +#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */ +#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */ + +/* Bit definitions and macros for PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */ +#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */ + +/* Bit definitions and macros for PPDSDR_TIMER */ +#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */ +#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */ +#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */ +#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */ + +/* Bit definitions and macros for PPDSDR_PCI */ +#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ +#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */ +#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */ +#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */ +#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ +#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */ +#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */ +#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ + +/* Bit definitions and macros for PPDSDR_USB */ +#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ +#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */ + +/* Bit definitions and macros for PPDSDR_ATAH */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */ +#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */ + +/* Bit definitions and macros for PPDSDR_ATAL */ +#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */ +#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */ +#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */ + +/* Bit definitions and macros for PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ + +/* Bit definitions and macros for PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ + +/* Bit definitions and macros for PPDSDR_FBADH */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */ +#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */ + +/* Bit definitions and macros for PPDSDR_FBADMH */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */ +#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */ + +/* Bit definitions and macros for PPDSDR_FBADML */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */ +#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */ + +/* Bit definitions and macros for PPDSDR_FBADL */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */ +#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */ + +/* Bit definitions and macros for PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */ + +/* Bit definitions and macros for PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */ +#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */ + +/* Bit definitions and macros for PCLRR_SSI */ +#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */ +#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */ +#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */ +#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */ +#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */ + +/* Bit definitions and macros for PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */ + +/* Bit definitions and macros for PCLRR_BE */ +#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */ +#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */ +#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */ +#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */ + +/* Bit definitions and macros for PCLRR_CS */ +#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */ +#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */ +#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */ + +/* Bit definitions and macros for PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */ +#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */ +#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */ +#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */ + +/* Bit definitions and macros for PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */ + +/* Bit definitions and macros for PCLRR_UART */ +#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */ +#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */ +#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */ +#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */ +#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */ +#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */ +#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */ +#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */ + +/* Bit definitions and macros for PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */ + +/* Bit definitions and macros for PCLRR_TIMER */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */ + +/* Bit definitions and macros for PCLRR_PCI */ +#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */ +#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */ +#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */ +#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */ +#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */ +#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */ +#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */ +#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */ + +/* Bit definitions and macros for PCLRR_USB */ +#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */ +#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */ + +/* Bit definitions and macros for PCLRR_ATAH */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */ +#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */ + +/* Bit definitions and macros for PCLRR_ATAL */ +#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */ +#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */ +#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */ + +/* Bit definitions and macros for PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */ + +/* Bit definitions and macros for PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */ + +/* Bit definitions and macros for PCLRR_FBADH */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */ +#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */ + +/* Bit definitions and macros for PCLRR_FBADMH */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */ +#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */ + +/* Bit definitions and macros for PCLRR_FBADML */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */ +#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */ + +/* Bit definitions and macros for PCLRR_FBADL */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */ +#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */ + +/* Bit definitions and macros for PAR_FEC */ +#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07)) +#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4) +#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F) +#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70) +#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30) +#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20) +#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10) +#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00) +#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8) +#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07) +#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03) +#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02) +#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01) +#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00) + +/* Bit definitions and macros for PAR_DMA */ +#define MCF_GPIO_PAR_DMA_DREQ0 (0x01) +#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F) +#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0) +#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40) +#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00) +#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF) +#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30) +#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10) +#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00) +#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3) +#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C) +#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04) +#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00) +#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01) +#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00) + +/* Bit definitions and macros for PAR_FBCTL */ +#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3) +#define MCF_GPIO_PAR_FBCTL_RW (0x20) +#define MCF_GPIO_PAR_FBCTL_TA (0x40) +#define MCF_GPIO_PAR_FBCTL_OE (0x80) +#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80) +#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40) +#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00) +#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20) +#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00) +#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18) +#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10) +#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08) +#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80) + +/* Bit definitions and macros for PAR_DSPI */ +#define MCF_GPIO_PAR_DSPI_SCK (0x01) +#define MCF_GPIO_PAR_DSPI_SOUT (0x02) +#define MCF_GPIO_PAR_DSPI_SIN (0x04) +#define MCF_GPIO_PAR_DSPI_PCS0 (0x08) +#define MCF_GPIO_PAR_DSPI_PCS1 (0x10) +#define MCF_GPIO_PAR_DSPI_PCS2 (0x20) +#define MCF_GPIO_PAR_DSPI_PCS5 (0x40) +#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40) +#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20) +#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10) +#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08) +#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04) +#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02) +#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01) +#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_BE */ +#define MCF_GPIO_PAR_BE_BE0 (0x01) +#define MCF_GPIO_PAR_BE_BE1 (0x04) +#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F) +#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0) +#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80) +#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00) +#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF) +#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30) +#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20) +#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00) +#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04) +#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00) +#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01) +#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define MCF_GPIO_PAR_CS_CS1 (0x02) +#define MCF_GPIO_PAR_CS_CS2 (0x04) +#define MCF_GPIO_PAR_CS_CS3 (0x08) +#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08) +#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00) +#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04) +#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00) +#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02) +#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03)) +#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40) +#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10) +#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04) +#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01) +#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for PAR_USB */ +#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03)) +#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3) +#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C) +#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08) +#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04) +#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00) +#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC) +#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03) +#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01) +#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define MCF_GPIO_PAR_UART_U0TXD (0x01) +#define MCF_GPIO_PAR_UART_U0RXD (0x02) +#define MCF_GPIO_PAR_UART_U0RTS (0x04) +#define MCF_GPIO_PAR_UART_U0CTS (0x08) +#define MCF_GPIO_PAR_UART_U1TXD (0x10) +#define MCF_GPIO_PAR_UART_U1RXD (0x20) +#define MCF_GPIO_PAR_UART_U1RTS (0x40) +#define MCF_GPIO_PAR_UART_U1CTS (0x80) +#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80) +#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40) +#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20) +#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10) +#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08) +#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04) +#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02) +#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00) +#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01) +#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003)) +#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003)) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010) +#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040) +#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF) +#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00) +#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800) +#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000) +#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF) +#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300) +#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200) +#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000) +#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040) +#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000) +#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010) +#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000) +#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3) +#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C) +#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004) +#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000) +#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC) +#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003) +#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001) +#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000) + +/* Bit definitions and macros for PAR_SSI */ +#define MCF_GPIO_PAR_SSI_MCLK (0x0001) +#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF) +#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300) +#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200) +#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000) +#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F) +#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0) +#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080) +#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000) +#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF) +#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030) +#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020) +#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000) +#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3) +#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C) +#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008) +#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000) +#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001) +#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000) + +/* Bit definitions and macros for PAR_ATA */ +#define MCF_GPIO_PAR_ATA_IORDY (0x0001) +#define MCF_GPIO_PAR_ATA_DMARQ (0x0002) +#define MCF_GPIO_PAR_ATA_RESET (0x0004) +#define MCF_GPIO_PAR_ATA_DA0 (0x0020) +#define MCF_GPIO_PAR_ATA_DA1 (0x0040) +#define MCF_GPIO_PAR_ATA_DA2 (0x0080) +#define MCF_GPIO_PAR_ATA_CS0 (0x0100) +#define MCF_GPIO_PAR_ATA_CS1 (0x0200) +#define MCF_GPIO_PAR_ATA_BUFEN (0x0400) +#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400) +#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200) +#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100) +#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080) +#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040) +#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020) +#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004) +#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002) +#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000) +#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001) +#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000) + +/* Bit definitions and macros for PAR_IRQ */ +#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02) +#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10) +#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10) +#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02) +#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for PAR_PCI */ +#define MCF_GPIO_PAR_PCI_REQ0 (0x0001) +#define MCF_GPIO_PAR_PCI_REQ1 (0x0004) +#define MCF_GPIO_PAR_PCI_REQ2 (0x0010) +#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_PCI_GNT0 (0x0100) +#define MCF_GPIO_PAR_PCI_GNT1 (0x0400) +#define MCF_GPIO_PAR_PCI_GNT2 (0x1000) +#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF) +#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000) +#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000) +#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000) +#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400) +#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100) +#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F) +#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0) +#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080) +#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010) +#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040) +#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000) +#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001) +#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03)) +#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2) +#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4) +#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6) +#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F) +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0) +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80) +#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40) +#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00) +#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF) +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30) +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20) +#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10) +#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00) +#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C) +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08) +#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04) +#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00) +#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03) +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02) +#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01) +#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00) + +/* Bit definitions and macros for MSCR_PCI */ +#define MCF_GPIO_MSCR_PCI_PCI (0x01) +#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01) +#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00) + +/* Bit definitions and macros for DSCR_I2C */ +#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FLEXBUS */ +#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2) +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4) +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6) +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0) +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80) +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40) +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00) +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30) +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20) +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10) +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00) +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C) +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08) +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04) +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00) +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_FEC */ +#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2) +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C) +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08) +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04) +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00) +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_UART */ +#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2) +#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C) +#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08) +#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04) +#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00) +#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DSPI */ +#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_TIMER */ +#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_SSI */ +#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DMA */ +#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_DEBUG */ +#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_RESET */ +#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_IRQ */ +#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_USB */ +#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00) + +/* Bit definitions and macros for DSCR_ATA */ +#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03)) +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03) +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02) +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01) +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00) + +/********************************************************************/ + +#endif /* __MCF5445X_GPIO_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_i2c.h b/arch/m68k/include/asm/mcf5445x_i2c.h new file mode 100644 index 000000000000..823ed501779a --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_i2c.h @@ -0,0 +1,39 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_I2C_H__ +#define __MCF5445X_I2C_H__ + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (volatile u8 *)(0xFC058000) +#define MCF_I2C_I2FDR (volatile u8 *)(0xFC058004) +#define MCF_I2C_I2CR (volatile u8 *)(0xFC058008) +#define MCF_I2C_I2SR (volatile u8 *)(0xFC05800C) +#define MCF_I2C_I2DR (volatile u8 *)(0xFC058010) + +/* Bit definitions and macros for I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)) + +/* Bit definitions and macros for I2DR */ +#define MCF_I2C_I2DR_DATA(x) (x) + +/********************************************************************/ + +#endif /* __MCF5445X_I2C_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_intc.h b/arch/m68k/include/asm/mcf5445x_intc.h new file mode 100644 index 000000000000..7bde2064bf02 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_intc.h @@ -0,0 +1,724 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_INTC_H__ +#define __MCF5445X_INTC_H__ + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8 +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001)) +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004)) +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001)) +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004)) + +/* Parameterized register read/write macros for multiple modules */ +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) + +/* Bit definitions and macros for IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for IPRL */ +#define MCF_INTC_IPRL_INT0 (0x00000001) +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for IMRL */ +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for ICONFIG */ +#define MCF_INTC_ICONFIG_EMASK (0x0020) +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for SIMR */ +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CIMR */ +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CLMASK */ +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for SLMASK */ +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for ICR group */ +#define MCF_INTC_ICR_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR1 */ +#define MCF_INTC_ICR1_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR2 */ +#define MCF_INTC_ICR2_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR3 */ +#define MCF_INTC_ICR3_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR4 */ +#define MCF_INTC_ICR4_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR5 */ +#define MCF_INTC_ICR5_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR6 */ +#define MCF_INTC_ICR6_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR7 */ +#define MCF_INTC_ICR7_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR8 */ +#define MCF_INTC_ICR8_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR9 */ +#define MCF_INTC_ICR9_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR10 */ +#define MCF_INTC_ICR10_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR11 */ +#define MCF_INTC_ICR11_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR12 */ +#define MCF_INTC_ICR12_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR13 */ +#define MCF_INTC_ICR13_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR14 */ +#define MCF_INTC_ICR14_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR15 */ +#define MCF_INTC_ICR15_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR16 */ +#define MCF_INTC_ICR16_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR17 */ +#define MCF_INTC_ICR17_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR18 */ +#define MCF_INTC_ICR18_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR19 */ +#define MCF_INTC_ICR19_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR20 */ +#define MCF_INTC_ICR20_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR21 */ +#define MCF_INTC_ICR21_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR22 */ +#define MCF_INTC_ICR22_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR23 */ +#define MCF_INTC_ICR23_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR24 */ +#define MCF_INTC_ICR24_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR25 */ +#define MCF_INTC_ICR25_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR26 */ +#define MCF_INTC_ICR26_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR27 */ +#define MCF_INTC_ICR27_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR28 */ +#define MCF_INTC_ICR28_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR29 */ +#define MCF_INTC_ICR29_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR30 */ +#define MCF_INTC_ICR30_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR31 */ +#define MCF_INTC_ICR31_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR32 */ +#define MCF_INTC_ICR32_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR33 */ +#define MCF_INTC_ICR33_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR34 */ +#define MCF_INTC_ICR34_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR35 */ +#define MCF_INTC_ICR35_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR36 */ +#define MCF_INTC_ICR36_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR37 */ +#define MCF_INTC_ICR37_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR38 */ +#define MCF_INTC_ICR38_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR39 */ +#define MCF_INTC_ICR39_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR40 */ +#define MCF_INTC_ICR40_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR41 */ +#define MCF_INTC_ICR41_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR42 */ +#define MCF_INTC_ICR42_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR43 */ +#define MCF_INTC_ICR43_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR44 */ +#define MCF_INTC_ICR44_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR45 */ +#define MCF_INTC_ICR45_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR46 */ +#define MCF_INTC_ICR46_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR47 */ +#define MCF_INTC_ICR47_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR48 */ +#define MCF_INTC_ICR48_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR49 */ +#define MCF_INTC_ICR49_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR50 */ +#define MCF_INTC_ICR50_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR51 */ +#define MCF_INTC_ICR51_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR52 */ +#define MCF_INTC_ICR52_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR53 */ +#define MCF_INTC_ICR53_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR54 */ +#define MCF_INTC_ICR54_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR55 */ +#define MCF_INTC_ICR55_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR56 */ +#define MCF_INTC_ICR56_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR57 */ +#define MCF_INTC_ICR57_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR58 */ +#define MCF_INTC_ICR58_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR59 */ +#define MCF_INTC_ICR59_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR60 */ +#define MCF_INTC_ICR60_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR61 */ +#define MCF_INTC_ICR61_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR62 */ +#define MCF_INTC_ICR62_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for ICR63 */ +#define MCF_INTC_ICR63_IL(x) (((x)&0x07)) + +/* Bit definitions and macros for SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (x) + +/* Bit definitions and macros for LIACK group */ +#define MCF_INTC_LIACK_VECTOR(x) (x) + +/* Bit definitions and macros for L1IACK */ +#define MCF_INTC_L1IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L2IACK */ +#define MCF_INTC_L2IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L3IACK */ +#define MCF_INTC_L3IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L4IACK */ +#define MCF_INTC_L4IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L5IACK */ +#define MCF_INTC_L5IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L6IACK */ +#define MCF_INTC_L6IACK_VECTOR(x) (x) + +/* Bit definitions and macros for L7IACK */ +#define MCF_INTC_L7IACK_VECTOR(x) (x) + +/********************************************************************/ + +#endif /* __MCF5445X_INTC_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_pci.h b/arch/m68k/include/asm/mcf5445x_pci.h new file mode 100644 index 000000000000..3ce3d3a61eb4 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_pci.h @@ -0,0 +1,238 @@ +/* + * Kurt Mahan kmahan@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_PCI_H__ +#define __MCF5445X_PCI_H__ + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000) +#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004) +#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008) +#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C) +#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010) +#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014) +#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018) +#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C) +#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020) +#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024) +#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C) +#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C) +#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060) +#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064) +#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068) +#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C) +#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070) +#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074) +#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078) +#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080) +#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084) +#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088) +#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C) +#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090) +#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094) +#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098) +#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C) +#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0) +#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4) +#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8) + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004)) + +/* Bit definitions and macros for PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for PCISCR */ +#define MCF_PCI_PCISCR_M (0x00000002) +#define MCF_PCI_PCISCR_B (0x00000004) +#define MCF_PCI_PCISCR_SP (0x00000008) +#define MCF_PCI_PCISCR_MW (0x00000010) +#define MCF_PCI_PCISCR_PER (0x00000040) +#define MCF_PCI_PCISCR_S (0x00000100) +#define MCF_PCI_PCISCR_F (0x00000200) +#define MCF_PCI_PCISCR_C (0x00100000) +#define MCF_PCI_PCISCR_66M (0x00200000) +#define MCF_PCI_PCISCR_R (0x00400000) +#define MCF_PCI_PCISCR_FC (0x00800000) +#define MCF_PCI_PCISCR_DP (0x01000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) +#define MCF_PCI_PCISCR_TS (0x08000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) + +/* Bit definitions and macros for PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IO (0x00000001) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) +#define MCF_PCI_PCIBAR0_PREF (0x00000008) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IO (0x00000001) +#define MCF_PCI_PCIBAR1_PREF (0x00000008) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20) + +/* Bit definitions and macros for PCIBAR2 */ +#define MCF_PCI_PCIBAR2_IO (0x00000001) +#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1) +#define MCF_PCI_PCIBAR2_PREF (0x00000008) +#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22) + +/* Bit definitions and macros for PCIBAR3 */ +#define MCF_PCI_PCIBAR3_IO (0x00000001) +#define MCF_PCI_PCIBAR3_PREF (0x00000008) +#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for PCIBAR4 */ +#define MCF_PCI_PCIBAR4_IO (0x00000001) +#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1) +#define MCF_PCI_PCIBAR4_PREF (0x00000008) +#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27) + +/* Bit definitions and macros for PCIBAR5 */ +#define MCF_PCI_PCIBAR5_IO (0x00000001) +#define MCF_PCI_PCIBAR5_PREF (0x00000008) +#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF)) +#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x00000001) +#define MCF_PCI_PCIGSCR_SEE (0x00001000) +#define MCF_PCI_PCIGSCR_PEE (0x00002000) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for PCITBATR0A */ +#define MCF_PCI_PCITBATR0A_EN (0x00000001) +#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for PCITBATR1A */ +#define MCF_PCI_PCITBATR1A_EN (0x00000001) +#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20) + +/* Bit definitions and macros for PCITCR */ +#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF)) +#define MCF_PCI_PCITCR_WCD (0x00000100) +#define MCF_PCI_PCITCR_P (0x00010000) +#define MCF_PCI_PCITCR_PID (0x00020000) +#define MCF_PCI_PCITCR_LD (0x01000000) + +/* Bit definitions and macros for PCIIWBTAR group */ +#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000))) +#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000) +#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000) + +/* Bit definitions and macros for PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000))) +#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000) +#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000) + +/* Bit definitions and macros for PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) +#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) +#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) +#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) +#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) +#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) + +/* Bit definitions and macros for PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)) +#define MCF_PCI_PCIICR_TAE (0x01000000) +#define MCF_PCI_PCIICR_IAE (0x02000000) +#define MCF_PCI_PCIICR_REE (0x04000000) + +/* Bit definitions and macros for PCIISR */ +#define MCF_PCI_PCIISR_TA (0x01000000) +#define MCF_PCI_PCIISR_IA (0x02000000) +#define MCF_PCI_PCIISR_RE (0x04000000) + +/* Bit definitions and macros for PCITCR2 */ +#define MCF_PCI_PCITCR2_CR (0x00000001) +#define MCF_PCI_PCITCR2_B0E (0x00000100) +#define MCF_PCI_PCITCR2_B1E (0x00000200) +#define MCF_PCI_PCITCR2_B2E (0x00000400) +#define MCF_PCI_PCITCR2_B3E (0x00000800) +#define MCF_PCI_PCITCR2_B4E (0x00001000) +#define MCF_PCI_PCITCR2_B5E (0x00002000) + +/* Bit definitions and macros for PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x00000001) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x00000001) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20) + +/* Bit definitions and macros for PCITBATR2 */ +#define MCF_PCI_PCITBATR2_EN (0x00000001) +#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22) + +/* Bit definitions and macros for PCITBATR3 */ +#define MCF_PCI_PCITBATR3_EN (0x00000001) +#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for PCITBATR4 */ +#define MCF_PCI_PCITBATR4_EN (0x00000001) +#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27) + +/* Bit definitions and macros for PCITBATR5 */ +#define MCF_PCI_PCITBATR5_EN (0x00000001) +#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) +#define MCF_PCI_PCICAR_E (0x80000000) + +/********************************************************************/ + +#endif /* __MCF5445X_PCI_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_pciarb.h b/arch/m68k/include/asm/mcf5445x_pciarb.h new file mode 100644 index 000000000000..53dd7b696759 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_pciarb.h @@ -0,0 +1,40 @@ +/* + * Kurt Mahan kmahan@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_PCIARB_H__ +#define __MCF5445X_PCIARB_H__ + +/********************************************************************* +* +* PCI Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000) +#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004) + +/* Bit definitions and macros for PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x00000001) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) +#define MCF_PCIARB_PACR_RA (0x00008000) +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) +#define MCF_PCIARB_PACR_PKMD (0x40000000) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x00010000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) + +/********************************************************************/ + +#endif /* __MCF5445X_PCIARB_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_sdramc.h b/arch/m68k/include/asm/mcf5445x_sdramc.h new file mode 100644 index 000000000000..a17275e30bde --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_sdramc.h @@ -0,0 +1,115 @@ +/* + * Matt Waddel Matt.Waddel@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_SDRAMC_H__ +#define __MCF5445X_SDRAMC_H__ + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */ +#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */ +#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */ +#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */ +#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */ +#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */ + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004))) /* SDRAM Chip Select Register */ + +/* Bit definitions and macros for SDMR */ +#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00) + +/* Bit definitions and macros for SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/* Bit definitions and macros for SDCS0 */ +#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000) +#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000) +#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013) +#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014) +#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015) +#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016) +#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017) +#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018) +#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019) +#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A) +#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B) +#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C) +#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D) +#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E) +#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F) + +/* Bit definitions and macros for SDCS1 */ +#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ + +/********************************************************************/ + +#endif /* __MCF5445X_SDRAMC_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_ssi.h b/arch/m68k/include/asm/mcf5445x_ssi.h new file mode 100644 index 000000000000..85b755c03cc0 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_ssi.h @@ -0,0 +1,187 @@ +/* + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_SSI_H__ +#define __MCF5445X_SSI_H__ + +/********************************************************************* +* +* Synchronous Serial Interface (SSI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000) +#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004) +#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008) +#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C) +#define MCF_SSI_CR MCF_REG32(0xFC0BC010) +#define MCF_SSI_ISR MCF_REG32(0xFC0BC014) +#define MCF_SSI_IER MCF_REG32(0xFC0BC018) +#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C) +#define MCF_SSI_RCR MCF_REG32(0xFC0BC020) +#define MCF_SSI_CCR MCF_REG32(0xFC0BC024) +#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C) +#define MCF_SSI_ACR MCF_REG32(0xFC0BC038) +#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C) +#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040) +#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044) +#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048) +#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C) + +/* Parameterized register read/write macros for multiple registers */ +#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004)) +#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004)) + +/* Bit definitions and macros for TX group */ +#define MCF_SSI_TX_SSI_TX(x) (x) + +/* Bit definitions and macros for TX0 */ +#define MCF_SSI_TX0_SSI_TX(x) (x) + +/* Bit definitions and macros for TX1 */ +#define MCF_SSI_TX1_SSI_TX(x) (x) + +/* Bit definitions and macros for RX group */ +#define MCF_SSI_RX_SSI_RX(x) (x) + +/* Bit definitions and macros for RX0 */ +#define MCF_SSI_RX0_SSI_RX(x) (x) + +/* Bit definitions and macros for RX1 */ +#define MCF_SSI_RX1_SSI_RX(x) (x) + +/* Bit definitions and macros for CR */ +#define MCF_SSI_CR_SSI_EN (0x00000001) +#define MCF_SSI_CR_TE (0x00000002) +#define MCF_SSI_CR_RE (0x00000004) +#define MCF_SSI_CR_NET (0x00000008) +#define MCF_SSI_CR_SYN (0x00000010) +#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5) +#define MCF_SSI_CR_MCE (0x00000080) +#define MCF_SSI_CR_TCH (0x00000100) +#define MCF_SSI_CR_CIS (0x00000200) +#define MCF_SSI_CR_I2S_NORMAL (0x00000000) +#define MCF_SSI_CR_I2S_MASTER (0x00000020) +#define MCF_SSI_CR_I2S_SLAVE (0x00000040) + +/* Bit definitions and macros for ISR */ +#define MCF_SSI_ISR_TFE0 (0x00000001) +#define MCF_SSI_ISR_TFE1 (0x00000002) +#define MCF_SSI_ISR_RFF0 (0x00000004) +#define MCF_SSI_ISR_RFF1 (0x00000008) +#define MCF_SSI_ISR_RLS (0x00000010) +#define MCF_SSI_ISR_TLS (0x00000020) +#define MCF_SSI_ISR_RFS (0x00000040) +#define MCF_SSI_ISR_TFS (0x00000080) +#define MCF_SSI_ISR_TUE0 (0x00000100) +#define MCF_SSI_ISR_TUE1 (0x00000200) +#define MCF_SSI_ISR_ROE0 (0x00000400) +#define MCF_SSI_ISR_ROE1 (0x00000800) +#define MCF_SSI_ISR_TDE0 (0x00001000) +#define MCF_SSI_ISR_TDE1 (0x00002000) +#define MCF_SSI_ISR_RDR0 (0x00004000) +#define MCF_SSI_ISR_RDR1 (0x00008000) +#define MCF_SSI_ISR_RXT (0x00010000) +#define MCF_SSI_ISR_CMDDU (0x00020000) +#define MCF_SSI_ISR_CMDAU (0x00040000) + +/* Bit definitions and macros for IER */ +#define MCF_SSI_IER_TFE0 (0x00000001) +#define MCF_SSI_IER_TFE1 (0x00000002) +#define MCF_SSI_IER_RFF0 (0x00000004) +#define MCF_SSI_IER_RFF1 (0x00000008) +#define MCF_SSI_IER_RLS (0x00000010) +#define MCF_SSI_IER_TLS (0x00000020) +#define MCF_SSI_IER_RFS (0x00000040) +#define MCF_SSI_IER_TFS (0x00000080) +#define MCF_SSI_IER_TUE0 (0x00000100) +#define MCF_SSI_IER_TUE1 (0x00000200) +#define MCF_SSI_IER_ROE0 (0x00000400) +#define MCF_SSI_IER_ROE1 (0x00000800) +#define MCF_SSI_IER_TDE0 (0x00001000) +#define MCF_SSI_IER_TDE1 (0x00002000) +#define MCF_SSI_IER_RDR0 (0x00004000) +#define MCF_SSI_IER_RDR1 (0x00008000) +#define MCF_SSI_IER_RXT (0x00010000) +#define MCF_SSI_IER_CMDU (0x00020000) +#define MCF_SSI_IER_CMDAU (0x00040000) +#define MCF_SSI_IER_TIE (0x00080000) +#define MCF_SSI_IER_TDMAE (0x00100000) +#define MCF_SSI_IER_RIE (0x00200000) +#define MCF_SSI_IER_RDMAE (0x00400000) + +/* Bit definitions and macros for TCR */ +#define MCF_SSI_TCR_TEFS (0x00000001) +#define MCF_SSI_TCR_TFSL (0x00000002) +#define MCF_SSI_TCR_TFSI (0x00000004) +#define MCF_SSI_TCR_TSCKP (0x00000008) +#define MCF_SSI_TCR_TSHFD (0x00000010) +#define MCF_SSI_TCR_TXDIR (0x00000020) +#define MCF_SSI_TCR_TFDIR (0x00000040) +#define MCF_SSI_TCR_TFEN0 (0x00000080) +#define MCF_SSI_TCR_TFEN1 (0x00000100) +#define MCF_SSI_TCR_TXBIT0 (0x00000200) + +/* Bit definitions and macros for RCR */ +#define MCF_SSI_RCR_REFS (0x00000001) +#define MCF_SSI_RCR_RFSL (0x00000002) +#define MCF_SSI_RCR_RFSI (0x00000004) +#define MCF_SSI_RCR_RSCKP (0x00000008) +#define MCF_SSI_RCR_RSHFD (0x00000010) +#define MCF_SSI_RCR_RFEN0 (0x00000080) +#define MCF_SSI_RCR_RFEN1 (0x00000100) +#define MCF_SSI_RCR_RXBIT0 (0x00000200) +#define MCF_SSI_RCR_RXEXT (0x00000400) + +/* Bit definitions and macros for CCR */ +#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)) +#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8) +#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13) +#define MCF_SSI_CCR_PSR (0x00020000) +#define MCF_SSI_CCR_DIV2 (0x00040000) + +/* Bit definitions and macros for FCSR */ +#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)) +#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4) +#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8) +#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12) +#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16) +#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20) +#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24) +#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for ACR */ +#define MCF_SSI_ACR_AC97EN (0x00000001) +#define MCF_SSI_ACR_FV (0x00000002) +#define MCF_SSI_ACR_TIF (0x00000004) +#define MCF_SSI_ACR_RD (0x00000008) +#define MCF_SSI_ACR_WR (0x00000010) +#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5) + +/* Bit definitions and macros for ACADD */ +#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ACDAT */ +#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)) + +/* Bit definitions and macros for ATAG */ +#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)) + +/* Bit definitions and macros for TMASK */ +#define MCF_SSI_TMASK_SSI_TMASK(x) (x) + +/* Bit definitions and macros for RMASK */ +#define MCF_SSI_RMASK_SSI_RMASK(x) (x) + +/********************************************************************/ + +#endif /* __MCF5445X_SSI_H__ */ diff --git a/arch/m68k/include/asm/mcf5445x_usb.h b/arch/m68k/include/asm/mcf5445x_usb.h new file mode 100644 index 000000000000..af26ae2659c0 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_usb.h @@ -0,0 +1,50 @@ +/* + * Duck Schmid duck@freescale.com + * + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +/* ehci_arc_hc_driver.flags value */ +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY) + +static inline int fsl_platform_verify(struct platform_device *pdev) +{ + return 0; +} + +static inline void fsl_platform_usb_setup(struct usb_hcd *hcd) +{ +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + struct fsl_usb_host_regs *regs; + + pdata = hcd->self.controller->platform_data; + regs = pdata->regs; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode and select "big endian" */ + temp = fsl_readl(®s->usbmode); + temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); + fsl_writel(temp, ®s->usbmode); + + pr_debug("%s: set usbmode to 0x%x\n\n", __FUNCTION__, + fsl_readl(®s->usbmode)); + +} diff --git a/arch/m68k/include/asm/mcf5445x_xbs.h b/arch/m68k/include/asm/mcf5445x_xbs.h new file mode 100644 index 000000000000..beeba6591aa0 --- /dev/null +++ b/arch/m68k/include/asm/mcf5445x_xbs.h @@ -0,0 +1,81 @@ +/* + * Kurt Mahan kmahan@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MCF5445X_XBS_H__ +#define __MCF5445X_XBS_H__ + +/* + * Crossbar Switch (XBS) + */ + +/* Register read/write macros */ +#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */ +#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */ +#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */ +#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */ +#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */ +#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */ +#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */ +#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */ +#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */ +#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */ +#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */ +#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */ +#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */ +#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */ + +/* Priorities */ +#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */ +#define MCF_XBS_PRI_2 1 /* Level 2 */ +#define MCF_XBS_PRI_3 2 /* Level 3 */ +#define MCF_XBS_PRI_4 3 /* Level 4 */ +#define MCF_XBS_PRI_5 4 /* Level 5 */ +#define MCF_XBS_PRI_6 5 /* Level 6 */ +#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */ +#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */ + +/* Priority Register (PRSn) Defs */ +#define MCF_XBS_PRS_MACRO(m,p) ((p)<<((m)<<2)) +#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */ +#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */ +#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */ +#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */ +#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */ +#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */ +#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */ +#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */ + +/* Control Register (CRSn) Defs */ +#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */ +#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */ +#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */ +#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */ + +/* MCF_XBS_CRS_ARB Defs */ +#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */ +#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */ + +/* MCF_XBS_CRS_PCTL Defs */ +#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */ +#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */ +#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */ + +/* MCF_XBS_CRS_PARK Defs */ +#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */ +#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */ +#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */ +#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */ +#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */ +#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */ +#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */ +#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */ + +#endif /* __MCF5445X_XBS_H__ */ diff --git a/arch/m68k/include/asm/mcf_cacheflush_5445x.h b/arch/m68k/include/asm/mcf_cacheflush_5445x.h new file mode 100644 index 000000000000..f09b3eb04c28 --- /dev/null +++ b/arch/m68k/include/asm/mcf_cacheflush_5445x.h @@ -0,0 +1,453 @@ +/* + * arch/m68k/include/asm/mcf_cacheflush_5445x.h - Coldfire 5445x Cache + * + * Based on arch/m68k/include/asm/cacheflush.h + * + * Coldfire pieces by: + * Kurt Mahan kmahan@freescale.com + * + * Copyright Freescale Semiconductor, Inc. 2007, 2008 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef M68K_CF_5445x_CACHEFLUSH_H +#define M68K_CF_5445x_CACHEFLUSH_H + +#include + +/* + * Coldfire Cache Model + * + * The Coldfire processors use a Harvard architecture cache configured + * as four-way set associative. The cache does not implement bus snooping + * so cache coherency with other masters must be maintained in software. + * + * The cache is managed via the CPUSHL instruction in conjunction with + * bits set in the CACR (cache control register). Currently the code + * uses the CPUSHL enhancement which adds the ability to + * invalidate/clear/push a cacheline by physical address. This feature + * is designated in the Hardware Configuration Register [D1-CPES]. + * + * CACR Bits: + * DPI[28] cpushl invalidate disable for d-cache + * IDPI[12] cpushl invalidate disable for i-cache + * SPA[14] cpushl search by physical address + * IVO[20] cpushl invalidate only + * + * Random Terminology: + * * invalidate = reset the cache line's valid bit + * * push = generate a line-sized store of the data if its contents are marked + * as modifed (the modified flag is cleared after the store) + * * clear = push + invalidate + */ + +/** + * flush_icache - Flush all of the instruction cache + */ +static inline void flush_icache(void) +{ + asm volatile("nop\n" + "moveq%.l #0,%%d0\n" + "moveq%.l #0,%%d1\n" + "move%.l %%d0,%%a0\n" + "1:\n" + "cpushl %%ic,(%%a0)\n" + "add%.l #0x0010,%%a0\n" + "addq%.l #1,%%d1\n" + "cmpi%.l %0,%%d1\n" + "bne 1b\n" + "moveq%.l #0,%%d1\n" + "addq%.l #1,%%d0\n" + "move%.l %%d0,%%a0\n" + "cmpi%.l #4,%%d0\n" + "bne 1b\n" + : : "i" (CACHE_SETS) + : "a0", "d0", "d1"); +} + +/** + * flush_dcache - Flush all of the data cache + */ +static inline void flush_dcache(void) +{ + asm volatile("nop\n" + "moveq%.l #0,%%d0\n" + "moveq%.l #0,%%d1\n" + "move%.l %%d0,%%a0\n" + "1:\n" + "cpushl %%dc,(%%a0)\n" + "add%.l #0x0010,%%a0\n" + "addq%.l #1,%%d1\n" + "cmpi%.l %0,%%d1\n" + "bne 1b\n" + "moveq%.l #0,%%d1\n" + "addq%.l #1,%%d0\n" + "move%.l %%d0,%%a0\n" + "cmpi%.l #4,%%d0\n" + "bne 1b\n" + : : "i" (CACHE_SETS) + : "a0", "d0", "d1"); +} + +/** + * flush_bcache - Flush all of both caches + */ +static inline void flush_bcache(void) +{ + asm volatile("nop\n" + "moveq%.l #0,%%d0\n" + "moveq%.l #0,%%d1\n" + "move%.l %%d0,%%a0\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "add%.l #0x0010,%%a0\n" + "addq%.l #1,%%d1\n" + "cmpi%.l %0,%%d1\n" + "bne 1b\n" + "moveq%.l #0,%%d1\n" + "addq%.l #1,%%d0\n" + "move%.l %%d0,%%a0\n" + "cmpi%.l #4,%%d0\n" + "bne 1b\n" + : : "i" (CACHE_SETS) + : "a0", "d0", "d1"); +} + +/** + * cf_cache_clear - invalidate cache + * @paddr: starting physical address + * @len: number of bytes + * + * Invalidate cache lines starting at paddr for len bytes. + * Those lines are not pushed. + */ +static inline void cf_cache_clear(unsigned long paddr, int len) +{ + /* number of lines */ + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; + if (len == 0) + return; + + /* align on set boundary */ + paddr &= 0xfffffff0; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%d0\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "subq%.l #1,%%d0\n" + "bne%.b 1b\n" + "movec %2,%%cacr\n" + : : "a" (paddr), "r" (len), + "r" (shadow_cacr), + "i" (CF_CACR_SPA+CF_CACR_IVO) + : "a0", "d0"); +} + +/** + * cf_cache_push - Push dirty cache out with no invalidate + * @paddr: starting physical address + * @len: number of bytes + * + * Push the any dirty lines starting at paddr for len bytes. + * Those lines are not invalidated. + */ +static inline void cf_cache_push(unsigned long paddr, int len) +{ + /* number of lines */ + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; + if (len == 0) + return; + + /* align on set boundary */ + paddr &= 0xfffffff0; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%d0\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "subq%.l #1,%%d0\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : : "a" (paddr), "r" (len), + "r" (shadow_cacr), + "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI) + : "a0", "d0"); +} + +/** + * cf_cache_flush - Push dirty cache out and invalidate + * @paddr: starting physical address + * @len: number of bytes + * + * Push the any dirty lines starting at paddr for len bytes and + * invalidate those lines. + */ +static inline void cf_cache_flush(unsigned long paddr, int len) +{ + /* number of lines */ + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE; + if (len == 0) + return; + + /* align on set boundary */ + paddr &= 0xfffffff0; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%d0\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "subq%.l #1,%%d0\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : : "a" (paddr), "r" (len), + "r" (shadow_cacr), + "i" (CF_CACR_SPA) + : "a0", "d0"); +} + +/** + * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate + * @vstart - starting virtual address + * @vend: ending virtual address + * + * Push the any dirty data/instr lines starting at paddr for len bytes and + * invalidate those lines. + */ +static inline void cf_cache_flush_range(unsigned long vstart, unsigned long vend) +{ + int len; + + /* align on set boundary */ + vstart &= 0xfffffff0; + vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0; + len = vend - vstart; + if (len == 0) + return; + vstart = __pa(vstart); + vend = vstart + len; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%a1\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "cmpa%.l %%a0,%%a1\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : /* no return */ + : "a" (vstart), "a" (vend), + "r" (shadow_cacr), + "i" (CF_CACR_SPA) + : "a0", "a1", "d0"); +} + +/** + * cf_dcache_flush_range - Push dirty data cache in range out and invalidate + * @vstart - starting virtual address + * @vend: ending virtual address + * + * Push the any dirty data lines starting at paddr for len bytes and + * invalidate those lines. + */ +static inline void cf_dcache_flush_range(unsigned long vstart, unsigned long vend) +{ + /* align on set boundary */ + vstart &= 0xfffffff0; + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%a1\n" + "1:\n" + "cpushl %%dc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "cmpa%.l %%a0,%%a1\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : /* no return */ + : "a" (__pa(vstart)), "a" (__pa(vend)), + "r" (shadow_cacr), + "i" (CF_CACR_SPA) + : "a0", "a1", "d0"); +} + +/** + * cf_icache_flush_range - Push dirty inst cache in range out and invalidate + * @vstart - starting virtual address + * @vend: ending virtual address + * + * Push the any dirty instr lines starting at paddr for len bytes and + * invalidate those lines. This should just be an invalidate since you + * shouldn't be able to have dirty instruction cache. + */ +static inline void cf_icache_flush_range(unsigned long vstart, unsigned long vend) +{ + /* align on set boundary */ + vstart &= 0xfffffff0; + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0; + + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%a0\n" + "move%.l %1,%%a1\n" + "1:\n" + "cpushl %%ic,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "cmpa%.l %%a0,%%a1\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : /* no return */ + : "a" (__pa(vstart)), "a" (__pa(vend)), + "r" (shadow_cacr), + "i" (CF_CACR_SPA) + : "a0", "a1", "d0"); +} + +/** + * flush_cache_mm - Flush an mm_struct + * @mm: mm_struct to flush + */ +static inline void flush_cache_mm(struct mm_struct *mm) +{ + if (mm == current->mm) + flush_bcache(); +} + +#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + +/** + * flush_cache_range - Flush a cache range + * @vma: vma struct + * @start: Starting address + * @end: Ending address + * + * flush_cache_range must be a macro to avoid a dependency on + * linux/mm.h which includes this file. + */ +static inline void flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (vma->vm_mm == current->mm) + cf_cache_flush_range(start, end); +} + +/** + * flush_cache_page - Flush a page of the cache + * @vma: vma struct + * @vmaddr: + * @pfn: page numer + * + * flush_cache_page must be a macro to avoid a dependency on + * linux/mm.h which includes this file. + */ +static inline void flush_cache_page(struct vm_area_struct *vma, + unsigned long vmaddr, unsigned long pfn) +{ + if (vma->vm_mm == current->mm) + cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE); +} + +/** + * __flush_page_to_ram - Push a page out of the cache + * @vaddr: Virtual address at start of page + * + * Push the page at kernel virtual address *vaddr* and clear + * the icache. + */ +static inline void __flush_page_to_ram(void *vaddr) +{ + asm volatile("nop\n" + "move%.l %2,%%d0\n" + "or%.l %3,%%d0\n" + "movec %%d0,%%cacr\n" + "move%.l %0,%%d0\n" + "and%.l #0xfffffff0,%%d0\n" + "move%.l %%d0,%%a0\n" + "move%.l %1,%%d0\n" + "1:\n" + "cpushl %%bc,(%%a0)\n" + "lea 0x10(%%a0),%%a0\n" + "subq%.l #1,%%d0\n" + "bne.b 1b\n" + "movec %2,%%cacr\n" + : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE), + "r" (shadow_cacr), "i" (CF_CACR_SPA) + : "a0", "d0"); +} + +/* + * Various defines for the kernel. + */ + +extern void cache_clear(unsigned long paddr, int len); +extern void cache_push(unsigned long paddr, int len); + +static inline void flush_icache_range(unsigned long address, unsigned long endaddr) +{ +// JKM -- hack until new cpushl stuff is in +// cf_icache_flush_range(address, endaddr); + flush_icache(); +} + +#define flush_cache_all() flush_bcache() +#define flush_cache_vmap(start, end) flush_bcache() +#define flush_cache_vunmap(start, end) flush_bcache() + +#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend) +#define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) + +#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) + +/** + * copy_to_user_page - Copy memory to user page + */ +static inline void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + memcpy(dst, src, len); + cf_cache_flush(page_to_phys(page), PAGE_SIZE); +} + +/** + * copy_from_user_page - Copy memory from user page + */ +static inline void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, + void *dst, void *src, int len) +{ + cf_cache_flush(page_to_phys(page), PAGE_SIZE); + memcpy(dst, src, len); +} + +#endif /* M68K_CF_5445x_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/mcf_cacheflush_m547x_8x.h b/arch/m68k/include/asm/mcf_cacheflush_m547x_8x.h index 7898c82ad683..7143f39bcbf8 100644 --- a/arch/m68k/include/asm/mcf_cacheflush_m547x_8x.h +++ b/arch/m68k/include/asm/mcf_cacheflush_m547x_8x.h @@ -16,6 +16,8 @@ #ifndef _M68K_MCF_M547X_8X_CACHEFLUSH_H #define _M68K_MCF_M547X_8X_CACHEFLUSH_H +#include + /* * Cache handling functions */ @@ -190,6 +192,8 @@ extern inline void __flush_page_to_ram(void *address) } } +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 + /* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */ #define flush_dcache_page(page) \ __flush_page_to_ram((void *) page_address(page)) @@ -201,7 +205,7 @@ extern inline void __flush_page_to_ram(void *address) /* Push n pages at kernel virtual address and clear the icache */ /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ -extern inline void flush_icache_range (unsigned long address, +static inline void flush_icache_range (unsigned long address, unsigned long endaddr) { unsigned long set; diff --git a/arch/m68k/include/asm/mcf_pgalloc.h b/arch/m68k/include/asm/mcf_pgalloc.h new file mode 100644 index 000000000000..88089c72280a --- /dev/null +++ b/arch/m68k/include/asm/mcf_pgalloc.h @@ -0,0 +1,103 @@ +#ifndef _MCF_PGALLOC_H +#define _MCF_PGALLOC_H + +#include +#include +#include +#include + +extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_page((unsigned long) pte); +} + +extern const char bad_pmd_string[]; + +extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) +{ + unsigned long page = __get_free_page(GFP_DMA|__GFP_REPEAT); + + if (!page) + return NULL; + + memset((void *)page, 0, PAGE_SIZE); + return (pte_t *) (page); +} + +extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address) +{ + return (pmd_t *) pgd; +} + +#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); }) +#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); }) + +#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr) + +#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \ + (unsigned long)(page_address(page))) + +#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte)) + +#define pmd_pgtable(pmd) pmd_page(pmd) + +static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page) +{ + __free_page(page); +} + +#define __pmd_free_tlb(tlb, pmd) do { } while (0) + +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long address) +{ + struct page *page = alloc_pages(GFP_DMA|__GFP_REPEAT, 0); + pte_t *pte; + + if (!page) + return NULL; + + pte = kmap(page); + if (pte) { + clear_page(pte); + __flush_page_to_ram(pte); + flush_tlb_kernel_page(pte); + nocache_page(pte); + } + kunmap(pte); + + return page; +} + +extern inline void pte_free(struct mm_struct *mm, struct page *page) +{ + __free_page(page); +} + +/* + * In our implementation, each pgd entry contains 1 pmd that is never allocated + * or freed. pgd_present is always 1, so this should never be called. -NL + */ +#define pmd_free(mm, pmd) BUG() + +extern inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + free_page((unsigned long) pgd); +} + +extern inline pgd_t *pgd_alloc(struct mm_struct *mm) +{ + pgd_t *new_pgd; + + new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN); + if (!new_pgd) + return NULL; + memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE); + memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT); + return new_pgd; +} + +#define pgd_populate(mm, pmd, pte) BUG() + +#endif /* _MCF_PGALLOC_H */ diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h new file mode 100644 index 000000000000..e649803ee1a2 --- /dev/null +++ b/arch/m68k/include/asm/mcf_pgtable.h @@ -0,0 +1,357 @@ +#ifndef _MCF_PGTABLE_H +#define _MCF_PGTABLE_H + +#include +#include + +#ifndef __ASSEMBLY__ +#include +#include + +/* For virtual address to physical address conversion */ +#define VTOP(addr) __pa(addr) +#define PTOV(addr) __va(addr) + + +#endif /* !__ASSEMBLY__ */ + +/* Page protection values within PTE. */ + +/* MMUDR bits, in proper place. */ +#define CF_PAGE_LOCKED (0x00000002) +#define CF_PAGE_EXEC (0x00000004) +#define CF_PAGE_WRITABLE (0x00000008) +#define CF_PAGE_READABLE (0x00000010) +#define CF_PAGE_SYSTEM (0x00000020) +#define CF_PAGE_COPYBACK (0x00000040) +#define CF_PAGE_NOCACHE (0x00000080) + +#define CF_CACHEMASK (~0x00000040) +#define CF_PAGE_MMUDR_MASK (0x000000fe) + +#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE) + +/* MMUTR bits, need shifting down. */ +#define CF_PAGE_VALID (0x00000400) +#define CF_PAGE_SHARED (0x00000800) + +#define CF_PAGE_MMUTR_MASK (0x00000c00) +#define CF_PAGE_MMUTR_SHIFT (10) +#define CF_ASID_MMU_SHIFT (2) + +/* Fake bits, not implemented in CF, will get masked out before + hitting hardware, and might go away altogether once this port is + complete. */ +#if PAGE_SHIFT < 13 +#error COLDFIRE Error: Pages must be at least 8k in size +#endif +#define CF_PAGE_ACCESSED (0x00001000) +#define CF_PAGE_FILE (0x00000200) +#define CF_PAGE_DIRTY (0x00000001) + +#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */ +#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */ +#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */ +#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */ +#define _DESCTYPE_MASK 0x003 +#define _CACHEMASK040 (~0x060) +#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ + + +/* Externally used page protection values. */ +#define _PAGE_PRESENT (CF_PAGE_VALID) +#define _PAGE_ACCESSED (CF_PAGE_ACCESSED) +#define _PAGE_DIRTY (CF_PAGE_DIRTY) +#define _PAGE_READWRITE (CF_PAGE_WRITABLE \ + | CF_PAGE_READABLE \ + | CF_PAGE_SYSTEM \ + | CF_PAGE_SHARED) + +/* Compound page protection values. */ +#define PAGE_NONE __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED) + +#define PAGE_SHARED __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED) + +#define PAGE_INIT __pgprot(CF_PAGE_VALID \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC \ + | CF_PAGE_SYSTEM \ + | CF_PAGE_SHARED) + +#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC \ + | CF_PAGE_SYSTEM \ + | CF_PAGE_SHARED \ + | CF_PAGE_ACCESSED) + +#define PAGE_COPY __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_DIRTY) +/* + * Page protections for initialising protection_map. See mm/mmap.c + * for use. In general, the bit positions are xwr, and P-items are + * private, the S-items are shared. + */ + +#define __P000 PAGE_NONE +#define __P100 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_EXEC) +#define __P010 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_ACCESSED) +#define __P110 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_EXEC) +#define __P001 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE) +#define __P101 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) +#define __P011 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_READABLE \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_ACCESSED) +#define __P111 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_WRITABLE \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) + +#define __S000 PAGE_NONE +#define __S100 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_EXEC) +#define __S010 PAGE_SHARED +#define __S110 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_EXEC) +#define __S001 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE) +#define __S101 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) +#define __S011 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE) +#define __S111 __pgprot(CF_PAGE_VALID \ + | CF_PAGE_ACCESSED \ + | CF_PAGE_SHARED \ + | CF_PAGE_READABLE \ + | CF_PAGE_EXEC) + +#define PTE_MASK PAGE_MASK +#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY) + +#ifndef __ASSEMBLY__ + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) + +extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot); + return pte; +} + +#define pmd_set(pmdp, ptep) do {} while (0) + +extern inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) +{ + pgd_val(*pgdp) = virt_to_phys(pmdp); +} + +#define __pte_page(pte) \ + ((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET)) +#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd))) + +extern inline int pte_none(pte_t pte) +{ + return !pte_val(pte); +} +extern inline int pte_present(pte_t pte) +{ + return pte_val(pte) & CF_PAGE_VALID; +} +extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, + pte_t *ptep) +{ + pte_val(*ptep) = 0; +} + +#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) +#define pte_page(pte) virt_to_page(__pte_page(pte)) + +extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); } +#define pmd_none(pmd) pmd_none2(&(pmd)) +extern inline int pmd_bad2(pmd_t *pmd) { return 0; } +#define pmd_bad(pmd) pmd_bad2(&(pmd)) +#define pmd_present(pmd) (!pmd_none2(&(pmd))) +extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; } + +extern inline int pgd_none(pgd_t pgd) { return 0; } +extern inline int pgd_bad(pgd_t pgd) { return 0; } +extern inline int pgd_present(pgd_t pgd) { return 1; } +extern inline void pgd_clear(pgd_t *pgdp) {} + + +#define pte_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ + __FILE__, __LINE__, pte_val(e)) +#define pmd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ + __FILE__, __LINE__, pmd_val(e)) +#define pgd_ERROR(e) \ + printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ + __FILE__, __LINE__, pgd_val(e)) + + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not... + * [we have the full set here even if they don't change from m68k] + */ +extern inline int pte_read(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_READABLE; } +extern inline int pte_write(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_WRITABLE; } +extern inline int pte_exec(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_EXEC; } +extern inline int pte_dirty(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_DIRTY; } +extern inline int pte_young(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_ACCESSED; } +extern inline int pte_file(pte_t pte) \ + { return pte_val(pte) & CF_PAGE_FILE; } + +extern inline pte_t pte_wrprotect(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; } +extern inline pte_t pte_rdprotect(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_READABLE; return pte; } +extern inline pte_t pte_exprotect(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_EXEC; return pte; } +extern inline pte_t pte_mkclean(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; } +extern inline pte_t pte_mkold(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; } +extern inline pte_t pte_mkwrite(pte_t pte) \ + { pte_val(pte) |= CF_PAGE_WRITABLE; return pte; } +extern inline pte_t pte_mkread(pte_t pte) \ + { pte_val(pte) |= CF_PAGE_READABLE; return pte; } +extern inline pte_t pte_mkexec(pte_t pte) \ + { pte_val(pte) |= CF_PAGE_EXEC; return pte; } +extern inline pte_t pte_mkdirty(pte_t pte) \ + { pte_val(pte) |= CF_PAGE_DIRTY; return pte; } +extern inline pte_t pte_mkyoung(pte_t pte) \ + { pte_val(pte) |= CF_PAGE_ACCESSED; return pte; } +extern inline pte_t pte_mknocache(pte_t pte) \ + { pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; } +extern inline pte_t pte_mkcache(pte_t pte) \ + { pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; } + +#define swapper_pg_dir kernel_pg_dir +extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; + +/* Find an entry in a pagetable directory. */ +#define pgd_index(address) ((address) >> PGDIR_SHIFT) + +#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) + +/* Find an entry in a kernel pagetable directory. */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* Find an entry in the second-level pagetable. */ +extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address) +{ + return (pmd_t *) pgd; +} + +/* Find an entry in the third-level pagetable. */ +#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \ + __pte_offset(address)) + +/* Disable caching for page at given kernel virtual address. */ +static inline void nocache_page(void *vaddr) +{ + pgd_t *dir; + pmd_t *pmdp; + pte_t *ptep; + unsigned long addr = (unsigned long)vaddr; + + dir = pgd_offset_k(addr); + pmdp = pmd_offset(dir, addr); + ptep = pte_offset_kernel(pmdp, addr); + *ptep = pte_mknocache(*ptep); +} + +/* Enable caching for page at given kernel virtual address. */ +static inline void cache_page(void *vaddr) +{ + pgd_t *dir; + pmd_t *pmdp; + pte_t *ptep; + unsigned long addr = (unsigned long)vaddr; + + dir = pgd_offset_k(addr); + pmdp = pmd_offset(dir, addr); + ptep = pte_offset_kernel(pmdp, addr); + *ptep = pte_mkcache(*ptep); +} + +#define PTE_FILE_MAX_BITS 21 +#define PTE_FILE_SHIFT 11 + +static inline unsigned long pte_to_pgoff(pte_t pte) +{ + return pte_val(pte) >> PTE_FILE_SHIFT; +} + +static inline pte_t pgoff_to_pte(unsigned pgoff) +{ + pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE); + return pte; +} + +/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ +#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ + (offset << PTE_FILE_SHIFT) }) +#define __swp_type(x) ((x).val & 0xFF) +#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) (__pte((x).val)) + +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) + +#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \ + __pte_offset(address)) +#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address) +#define pte_unmap(pte) kunmap(pte) +#define pte_unmap_nested(pte) kunmap(pte) + +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) + + +#endif /* !__ASSEMBLY__ */ +#endif /* !_MCF_PGTABLE_H */ diff --git a/arch/m68k/include/asm/mcf_tlbflush.h b/arch/m68k/include/asm/mcf_tlbflush.h new file mode 100755 index 000000000000..9bf7da2910de --- /dev/null +++ b/arch/m68k/include/asm/mcf_tlbflush.h @@ -0,0 +1,59 @@ +#ifndef _MCF_TLBFLUSH_H +#define _MCF_TLBFLUSH_H + +#include + +/* Flush all userspace mappings. */ +static inline void flush_tlb_all(void) +{ + preempt_disable(); + *MMUOR = MMUOR_CNL; + preempt_enable(); +} + +/* Clear user TLB entries within the context named in mm */ +static inline void flush_tlb_mm(struct mm_struct *mm) +{ + preempt_disable(); + *MMUOR = MMUOR_CNL; + preempt_enable(); +} + +/* Flush a single TLB page. */ +static inline void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr) +{ + preempt_disable(); + *MMUOR = MMUOR_CNL; + preempt_enable(); +} +/* Flush a range of pages from TLB. */ + +static inline void flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ + preempt_disable(); + *MMUOR = MMUOR_CNL; + preempt_enable(); +} + +/* Flush kernel page from TLB. */ +static inline void flush_tlb_kernel_page(void *addr) +{ + preempt_disable(); + *MMUOR = MMUOR_CNL; + preempt_enable(); +} + +static inline void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + flush_tlb_all(); +} + +extern inline void flush_tlb_pgtables(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ +} + +#endif /* M68K_CF_TLBFLUSH_H */ diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h index 6ffd51937f2b..96ac22054f17 100644 --- a/arch/m68k/include/asm/mcfcache.h +++ b/arch/m68k/include/asm/mcfcache.h @@ -110,7 +110,7 @@ .endm #endif /* CONFIG_M532x */ -#if defined(CONFIG_M5407) || defined(CONFIG_M548x) +#if defined(CONFIG_M5407) /* * Version 4 cores have a true harvard style separate instruction * and data cache. Invalidate and enable cache, also enable write diff --git a/arch/m68k/include/asm/mcffec.h b/arch/m68k/include/asm/mcffec.h new file mode 100755 index 000000000000..4581f9e43ee8 --- /dev/null +++ b/arch/m68k/include/asm/mcffec.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All rights reserved. + * Author: Chenghu Wu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef __MCFFEC_H__ +#define __MCFFEC_H +#include +#include +#include +#include +#include +#include +#include + +/* The FEC stores dest/src/type, data, and checksum for receive packets. + */ +#define PKT_MAXBUF_SIZE 1518 + +/* + * The 5270/5271/5280/5282/532x RX control register also contains maximum frame + * size bits. Other FEC hardware does not, so we need to take that into + * account when setting it. + */ +#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ + defined(CONFIG_M537x) || defined(CONFIG_M5301x) || \ + defined(CONFIG_M5445X) +#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) +#else +#define OPT_FRAME_SIZE 0 +#endif +/* + * Some hardware gets it MAC address out of local flash memory. + * if this is non-zero then assume it is the address to get MAC from. + */ +#if defined(CONFIG_NETtel) +#define FEC_FLASHMAC 0xf0006006 +#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) +#define FEC_FLASHMAC 0xf0006000 +#elif defined(CONFIG_CANCam) +#define FEC_FLASHMAC 0xf0020000 +#elif defined(CONFIG_M5272C3) +#define FEC_FLASHMAC (0xffe04000 + 4) +#elif defined(CONFIG_MOD5272) +#define FEC_FLASHMAC 0xffc0406b +#else +#define FEC_FLASHMAC 0 +#endif + +#ifdef CONFIG_FEC_DMA_USE_SRAM +#define TX_RING_SIZE 8 /* Must be power of two */ +#define TX_RING_MOD_MASK 7 /* for this to work */ +#else +#define TX_RING_SIZE 16 /* Must be power of two */ +#define TX_RING_MOD_MASK 15 /* for this to work */ +#endif + +typedef struct fec { + unsigned long fec_reserved0; + unsigned long fec_ievent; /* Interrupt event reg */ + unsigned long fec_imask; /* Interrupt mask reg */ + unsigned long fec_reserved1; + unsigned long fec_r_des_active; /* Receive descriptor reg */ + unsigned long fec_x_des_active; /* Transmit descriptor reg */ + unsigned long fec_reserved2[3]; + unsigned long fec_ecntrl; /* Ethernet control reg */ + unsigned long fec_reserved3[6]; + unsigned long fec_mii_data; /* MII manage frame reg */ + unsigned long fec_mii_speed; /* MII speed control reg */ + unsigned long fec_reserved4[7]; + unsigned long fec_mib_ctrlstat; /* MIB control/status reg */ + unsigned long fec_reserved5[7]; + unsigned long fec_r_cntrl; /* Receive control reg */ + unsigned long fec_reserved6[15]; + unsigned long fec_x_cntrl; /* Transmit Control reg */ + unsigned long fec_reserved7[7]; + unsigned long fec_addr_low; /* Low 32bits MAC address */ + unsigned long fec_addr_high; /* High 16bits MAC address */ + unsigned long fec_opd; /* Opcode + Pause duration */ + unsigned long fec_reserved8[10]; + unsigned long fec_hash_table_high; /* High 32bits hash table */ + unsigned long fec_hash_table_low; /* Low 32bits hash table */ + unsigned long fec_grp_hash_table_high;/* High 32bits hash table */ + unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */ + unsigned long fec_reserved9[7]; + unsigned long fec_x_wmrk; /* FIFO transmit water mark */ + unsigned long fec_reserved10; + unsigned long fec_r_bound; /* FIFO receive bound reg */ + unsigned long fec_r_fstart; /* FIFO receive start reg */ + unsigned long fec_reserved11[11]; + unsigned long fec_r_des_start; /* Receive descriptor ring */ + unsigned long fec_x_des_start; /* Transmit descriptor ring */ + unsigned long fec_r_buff_size; /* Maximum receive buff size */ +} fec_t; + +/* + * Define the buffer descriptor structure. + */ +typedef struct bufdesc { + unsigned short cbd_sc; /* Control and status info */ + unsigned short cbd_datlen; /* Data length */ + unsigned long cbd_bufaddr; /* Buffer address */ +} cbd_t; + +/* Forward declarations of some structures to support different PHYs + */ +typedef struct { + uint mii_data; + void (*funct)(uint mii_reg, struct net_device *dev); +} phy_cmd_t; + +typedef struct { + uint id; + char *name; + + const phy_cmd_t *config; + const phy_cmd_t *startup; + const phy_cmd_t *ack_int; + const phy_cmd_t *shutdown; +} phy_info_t; + +/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and + * tx_bd_base always point to the base of the buffer descriptors. The + * cur_rx and cur_tx point to the currently available buffer. + * The dirty_tx tracks the current buffer that is being sent by the + * controller. The cur_tx and dirty_tx are equal under both completely + * empty and completely full conditions. The empty/ready indicator in + * the buffer descriptor determines the actual condition. + */ +struct fec_enet_private { + /* Hardware registers of the FEC device */ + volatile fec_t *hwp; + + struct net_device *netdev; + struct platform_device *pdev; + /* The saved address of a sent-in-place packet/buffer, for skfree(). */ + unsigned char *tx_bounce[TX_RING_SIZE]; + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + ushort skb_cur; + ushort skb_dirty; + + /* CPM dual port RAM relative addresses. + */ + cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ + cbd_t *tx_bd_base; + cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ + cbd_t *dirty_tx; /* The ring entries to be free()ed. */ + uint tx_full; + /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ + spinlock_t hw_lock; + + /* hold while accessing the mii_list_t() elements */ + spinlock_t mii_lock; + struct mii_bus *mdio_bus; + struct phy_device *phydev; + + uint phy_id; + uint phy_id_done; + uint phy_status; + uint phy_speed; + phy_info_t const *phy; + struct work_struct phy_task; + volatile fec_t *phy_hwp; + + uint sequence_done; + uint mii_phy_task_queued; + + uint phy_addr; + + int index; + int opened; + int link; + int old_link; + int full_duplex; + int duplex; + int speed; + int msg_enable; +}; + +struct fec_platform_private { + struct platform_device *pdev; + + unsigned long quirks; + int num_slots; /* Slots on controller */ + struct fec_enet_private *fep_host[0]; /* Pointers to hosts */ +}; + +#endif diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index e0617b3f9a14..f98ffc2fe7c5 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h @@ -45,8 +45,20 @@ #elif defined(CONFIG_M5407) #include #include -#elif defined(CONFIG_M548x) +#elif defined(CONFIG_M5445X) //with MMU +#include +#include +#include +#include +#include +#include +#include +#include +#include +#elif defined(CONFIG_M547X_8X) //with MMU #include +#include +#include #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index db72e2b889ca..7e10def62465 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -47,13 +47,18 @@ #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#elif defined(CONFIG_M548x) -#define MCFUART_BASE1 0x8600 /* on M548x */ -#define MCFUART_BASE2 0x8700 /* on M548x */ -#define MCFUART_BASE3 0x8800 /* on M548x */ -#define MCFUART_BASE4 0x8900 /* on M548x */ +#elif defined(CONFIG_M5445X) +#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ +#elif defined(CONFIG_M547X_8X) +#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ +#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ +#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ +#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ #endif +#ifndef __ASSEMBLY__ #include #include @@ -65,6 +70,8 @@ struct mcf_platform_uart { unsigned int uartclk; /* UART clock rate */ }; +#endif + /* * Define the ColdFire UART register set addresses. */ @@ -217,7 +224,7 @@ struct mcf_platform_uart { #define MCFUART_URF_RXS 0xc0 /* Receiver status */ #endif -#if defined(CONFIG_M548x) +#if defined(CONFIG_M547X_8X) #define MCFUART_TXFIFOSIZE 512 #elif defined(CONFIG_M5272) #define MCFUART_TXFIFOSIZE 25 diff --git a/arch/m68k/include/asm/mmu_context.h b/arch/m68k/include/asm/mmu_context.h index 7d4341e55a99..3ef8f88c9f89 100644 --- a/arch/m68k/include/asm/mmu_context.h +++ b/arch/m68k/include/asm/mmu_context.h @@ -8,7 +8,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) } #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 +#ifndef CONFIG_SUN3 && !defined(CONFIG_COLDFIRE) #include #include @@ -103,7 +103,7 @@ static inline void activate_mm(struct mm_struct *prev_mm, switch_mm_0460(next_mm); } -#else /* CONFIG_SUN3 */ +#elif defined(CONFIG_SUN3) #include #include @@ -151,7 +151,162 @@ static inline void activate_mm(struct mm_struct *prev_mm, activate_context(next_mm); } -#endif +#else /* CONFIG_COLDFIRE */ + +#include +#include +#include +#include + +#define NO_CONTEXT 256 +#define LAST_CONTEXT 255 +#define FIRST_CONTEXT 1 + +extern void set_context(mm_context_t context, pgd_t *pgd); +extern unsigned long context_map[]; +extern mm_context_t next_mmu_context; + +extern atomic_t nr_free_contexts; +extern struct mm_struct *context_mm[LAST_CONTEXT+1]; +extern void steal_context(void); + +static inline void get_mmu_context(struct mm_struct *mm) +{ + mm_context_t ctx; + + if (mm->context != NO_CONTEXT) + return; + while (atomic_dec_and_test_lt(&nr_free_contexts)) { + atomic_inc(&nr_free_contexts); + steal_context(); + } + ctx = next_mmu_context; + while (test_and_set_bit(ctx, context_map)) { + ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); + if (ctx > LAST_CONTEXT) + ctx = 0; + } + next_mmu_context = (ctx + 1) & LAST_CONTEXT; + mm->context = ctx; + context_mm[ctx] = mm; +} + +/* + * Set up the context for a new address space. + */ +#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0) + +/* + * We're finished using the context for an address space. + */ +static inline void destroy_context(struct mm_struct *mm) +{ + if (mm->context != NO_CONTEXT) { + clear_bit(mm->context, context_map); + mm->context = NO_CONTEXT; + atomic_inc(&nr_free_contexts); + } +} + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + get_mmu_context(tsk->mm); + set_context(tsk->mm->context, next->pgd); +} + +/* + * After we have set current->mm to a new value, this activates + * the context for the new mm so we see the new mappings. + */ +static inline void activate_mm(struct mm_struct *active_mm, + struct mm_struct *mm) +{ + get_mmu_context(mm); + set_context(mm->context, mm->pgd); +} + +#define deactivate_mm(tsk, mm) do { } while (0) + +extern void mmu_context_init(void); +#if defined(CONFIG_M547X_8X) +#define prepare_arch_switch(next) load_ksp_mmu(next) + +//FIXME: Don't use TLB here for kernel stacks + +static inline void load_ksp_mmu(struct task_struct *task) +{ + int flags; + struct mm_struct *mm; + int asid; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + unsigned long mmuar; + + local_irq_save(flags); + mmuar = task->thread.ksp; + + /* Search for a valid TLB entry, if one is found, don't remap */ + *MMUAR = mmuar; + *MMUOR = MMUOR_STLB | MMUOR_ADR; + + //better wait + asm ("nop"); + + if ((*MMUSR) & MMUSR_HIT) + goto end; + + if (mmuar >= PAGE_OFFSET) { + mm = &init_mm; + } else { + printk ("load_ksp_mmu: non-kernel mm found: 0x%08x\n", (unsigned int) task->mm); + mm = task->mm; + } + + if (!mm) + goto bug; + + pgd = pgd_offset(mm, mmuar); + if (pgd_none(*pgd)) + goto bug; + + pmd = pmd_offset(pgd, mmuar); + if (pmd_none(*pmd)) + goto bug; + + pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar) + : pte_offset_map(pmd, mmuar); + if (pte_none(*pte) || !pte_present(*pte)) + goto bug; + + set_pte(pte, pte_mkyoung(*pte)); + asid = mm->context & 0xff; + if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET) + set_pte(pte, pte_wrprotect(*pte)); + + *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT) + | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT) + | MMUTR_V; + + *MMUDR = (pte_val(*pte) & PAGE_MASK) + | ((pte->pte) & CF_PAGE_MMUDR_MASK) + | MMUDR_SZ8K | MMUDR_X; + + *MMUOR = MMUOR_ACC | MMUOR_UAA; + asm ("nop"); + + goto end; + +bug: + printk ("ksp load failed: mm=0x%08x ksp=0x%08x\n", (unsigned int) mm, (unsigned int) mmuar); + +end: + local_irq_restore(flags); +} + +#endif /* CONFIG_M547X_8X */ + #else /* !CONFIG_MMU */ static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h index dfebb7c1e379..e19486e4cffc 100644 --- a/arch/m68k/include/asm/page.h +++ b/arch/m68k/include/asm/page.h @@ -6,7 +6,7 @@ #include /* PAGE_SHIFT determines the page size */ -#ifndef CONFIG_SUN3 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) #define PAGE_SHIFT (12) #else #define PAGE_SHIFT (13) diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h index 87174c904d2b..c0c51463303c 100644 --- a/arch/m68k/include/asm/pgtable_mm.h +++ b/arch/m68k/include/asm/pgtable_mm.h @@ -66,12 +66,15 @@ #ifdef CONFIG_SUN3 #define KMAP_START 0x0DC00000 #define KMAP_END 0x0E000000 +#elif CONFIG_COLDFIRE +#define KMAP_START (VMALLOC_END + 1) +#define KMAP_END 0xe0000000 #else #define KMAP_START 0xd0000000 #define KMAP_END 0xf0000000 #endif -#ifndef CONFIG_SUN3 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) /* Just any arbitrary offset to the start of the vmalloc VM area: the * current 8MB value just means that there will be a 8MB "hole" after the * physical memory until the kernel virtual memory starts. That means that @@ -82,11 +85,14 @@ #define VMALLOC_OFFSET (8*1024*1024) #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_END KMAP_START -#else +#elif defined(CONFIG_SUN3) extern unsigned long m68k_vmalloc_end; #define VMALLOC_START 0x0f800000 #define VMALLOC_END m68k_vmalloc_end -#endif /* CONFIG_SUN3 */ +#else +#define VMALLOC_START 0xC0000000 +#define VMALLOC_END 0xCFFFFFFF +#endif /* CONFIG_COLDFIRE */ /* zero page used for uninitialized stuff */ extern void *empty_zero_page; @@ -130,6 +136,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, #ifdef CONFIG_SUN3 #include +#elif CONFIG_COLDFIRE +#include #else #include #endif @@ -138,11 +146,14 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, /* * Macro to mark a page protection value as "uncacheable". */ -#ifdef SUN3_PAGE_NOCACHE +#ifdef CONFIG_COLDFIRE +# define define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE)) +#elif defined(SUN3_PAGE_NOCACHE) # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE #else # define __SUN3_PAGE_NOCACHE 0 #endif + #define pgprot_noncached(prot) \ (MMU_IS_SUN3 \ ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \ diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h index 7a6a7590cc02..c58938bdf80b 100644 --- a/arch/m68k/include/asm/processor.h +++ b/arch/m68k/include/asm/processor.h @@ -45,9 +45,11 @@ static inline void wrusp(unsigned long usp) * so don't change it unless you know what you are doing. */ #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) #define TASK_SIZE (0xF0000000UL) -#else +#elif defined(CONFIG_COLDFIRE) +#define TASK_SIZE (0xC0000000UL) +#else /* CONFIG_SUN3 */ #define TASK_SIZE (0x0E000000UL) #endif #else @@ -63,9 +65,11 @@ static inline void wrusp(unsigned long usp) * space during mmap's. */ #ifdef CONFIG_MMU -#ifndef CONFIG_SUN3 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) #define TASK_UNMAPPED_BASE 0xC0000000UL -#else +#elif defined(CONFIG_COLDFIRE) +#define TASK_UNMAPPED_BASE 0x60000000UL +#else /* CONFIG_SUN3 */ #define TASK_UNMAPPED_BASE 0x0A000000UL #endif #define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr) @@ -77,7 +81,11 @@ struct thread_struct { unsigned long ksp; /* kernel stack pointer */ unsigned long usp; /* user stack pointer */ unsigned short sr; /* saved status register */ +#ifndef CONFIG_COLDFIRE unsigned short fs; /* saved fs (sfc, dfc) */ +#else + mm_segment_t fs; +#endif unsigned long crp[2]; /* cpu root pointer */ unsigned long esp0; /* points to SR of stack frame */ unsigned long faddr; /* info about last fault */ @@ -99,6 +107,9 @@ struct thread_struct { /* * Do necessary setup to start up a newly executed thread. */ + +#ifndef CONFIG_COLDFIRE + static inline void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long usp) { @@ -110,6 +121,26 @@ static inline void start_thread(struct pt_regs * regs, unsigned long pc, wrusp(usp); } +#else +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + * + * XXX: Why the fuck is this a macro ???? + */ +#define start_thread(_regs, _pc, _usp) \ +do { \ + set_fs(USER_DS); /* reads from user space */ \ + (_regs)->pc = (_pc); \ + if (current->mm) \ + (_regs)->d5 = current->mm->start_data; \ + (_regs)->sr &= ~0x2000; \ + wrusp(_usp); \ +} while (0) +#endif + #else /* diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h index 6e6e3ac1d913..128fee81adf1 100644 --- a/arch/m68k/include/asm/ptrace.h +++ b/arch/m68k/include/asm/ptrace.h @@ -39,8 +39,12 @@ struct pt_regs { long orig_d0; long stkadj; #ifdef CONFIG_COLDFIRE + unsigned long mmuar; + unsigned long mmusr; unsigned format : 4; /* frame format specifier */ + unsigned fs2 : 2; unsigned vector : 12; /* vector offset */ + unsigned fs1 : 2; unsigned short sr; unsigned long pc; #else diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h index ee959219fdfe..722e145618ac 100644 --- a/arch/m68k/include/asm/segment.h +++ b/arch/m68k/include/asm/segment.h @@ -29,6 +29,8 @@ typedef struct { * Get/set the SFC/DFC registers for MOVES instructions */ +#ifndef CONFIG_COLDFIRE + static inline mm_segment_t get_fs(void) { #ifdef CONFIG_MMU @@ -56,6 +58,15 @@ static inline void set_fs(mm_segment_t val) #endif } +#else /* CONFIG_COLDFIRE */ + +#include +#define get_fs() (current->thread.fs) +#define set_fs(val) (current->thread.fs = (val)) +#define get_ds() (KERNEL_DS) + +#endif /* CONFIG_COLDFIRE */ + #define segment_eq(a,b) ((a).seg == (b).seg) #endif /* __ASSEMBLY__ */ diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h index 5bc09c787a11..25275377aee6 100644 --- a/arch/m68k/include/asm/signal.h +++ b/arch/m68k/include/asm/signal.h @@ -150,7 +150,7 @@ typedef struct sigaltstack { #ifdef __KERNEL__ #include -#ifndef __uClinux__ +#if !defined(__uClinux__) #define __HAVE_ARCH_SIG_BITOPS static inline void sigaddset(sigset_t *set, int _sig) diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h index 47b01f4726bc..014fbe1d5f7d 100644 --- a/arch/m68k/include/asm/system_mm.h +++ b/arch/m68k/include/asm/system_mm.h @@ -9,6 +9,20 @@ #ifdef __KERNEL__ +#ifdef CONFIG_COLDFIRE +#define FLUSH_BC (0x00040000) + +#define finish_arch_switch(prev) do { \ + unsigned long tmpreg; \ + asm volatile ( "move.l %2,%0\n" \ + "orl %1,%0\n" \ + "movec %0,%%cacr" \ + : "=&d" (tmpreg) \ + : "id" (FLUSH_BC), "m" (shadow_cacr)); \ + } while(0) + +#endif + /* * switch_to(n) should switch tasks to task ptr, first checking that * ptr isn't the current task, in which case it does nothing. This diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h index 7107f3fbdbb6..20692e3f4fb2 100644 --- a/arch/m68k/include/asm/uaccess_mm.h +++ b/arch/m68k/include/asm/uaccess_mm.h @@ -13,6 +13,11 @@ #define VERIFY_READ 0 #define VERIFY_WRITE 1 +/* Coldifre doesn't have moves instruction; use move. */ +#ifdef CONFIG_COLDFIRE +#define moves move +#endif + /* We let the MMU do all checking */ static inline int access_ok(int type, const void __user *addr, unsigned long size) diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile index 55d5d6b680a2..df95b62c1e77 100644 --- a/arch/m68k/kernel/Makefile +++ b/arch/m68k/kernel/Makefile @@ -2,16 +2,23 @@ # Makefile for the linux kernel. # -ifndef CONFIG_SUN3 - extra-y := head.o +ifdef CONFIG_SUN3 + extra-y := sun3-head.o +else ifdef CONFIG_COLDFIRE + extra-y := cf-head.o else extra-y := sun3-head.o endif + extra-y += vmlinux.lds -obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \ +obj-y := process.o ptrace.o module.o \ sys_m68k.o time.o setup.o m68k_ksyms.o devres.o +ifndef CONFIG_COLDFIRE + obj-y += entry.o signal.o traps.o ints.o +endif + devres-y = ../../../kernel/irq/devres.o obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c index 78e59b82ebc3..eb8c450afb3c 100644 --- a/arch/m68k/kernel/asm-offsets.c +++ b/arch/m68k/kernel/asm-offsets.c @@ -57,8 +57,16 @@ int main(void) DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2)); DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc)); DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr)); +#ifdef CONFIG_COLDFIRE + /* Need to get the context out of struct mm for ASID setting */ + DEFINE(MM_CONTEXT, offsetof(struct mm_struct, context)); + /* Coldfire exception frame has vector *before* pc -.-*/ + DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) - 4); +#else /* bitfields are a bit difficult */ DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); +#endif + /* offsets into the irq_cpustat_t struct */ DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); diff --git a/arch/m68k/kernel/cf-head.S b/arch/m68k/kernel/cf-head.S new file mode 100644 index 000000000000..e1b53214f679 --- /dev/null +++ b/arch/m68k/kernel/cf-head.S @@ -0,0 +1,672 @@ +/* + * head.S is the MMU enabled ColdFire specific initial boot code + * + * Ported to ColdFire by + * Matt Waddel Matt.Waddel@freescale.com + * Kurt Mahan kmahan@freescale.com + * Copyright Freescale Semiconductor, Inc. 2007, 2008 + * Phys kernel mapping Copyright Daniel Krueger, SYSTEC electornic GmbH 2008 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Parts of this code came from arch/m68k/kernel/head.S + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG + +.globl kernel_pg_dir +.globl availmem +.globl set_context +.globl set_fpga +#if defined(CONFIG_UBOOT) +.global uboot_init_sp +#endif + + +#ifdef DEBUG +/* When debugging use readable names for labels */ +#ifdef __STDC__ +#define L(name) .head.S.##name +#else +#define L(name) .head.S./**/name +#endif +#else +#ifdef __STDC__ +#define L(name) .L##name +#else +#define L(name) .L/**/name +#endif +#endif + +/* The __INITDATA stuff is a no-op when ftrace or kgdb are turned on */ +#ifndef __INITDATA +#define __INITDATA .data +#define __FINIT .previous +#endif + +#if CONFIG_SDRAM_BASE != PAGE_OFFSET +/* + * Kernel mapped to virtual ram address. + * + * M5445x: + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs + * Data[1]: 0xA0000000 -> 0xAFFFFFFF PCI + * Code[0]: Not Mapped + * Code[1]: Not Mapped + * + * M547x/M548x + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs + * Data[1]: Not Mapped + * Code[0]: Not Mapped + * Code[1]: Not Mapped + */ +#if defined(CONFIG_M5445X) +#define ACR0_DEFAULT #0xF00FA048 /* System regs */ +#define ACR1_DEFAULT #0xA00FA048 /* PCI */ +#define ACR2_DEFAULT #0x00000000 /* Not Mapped */ +#define ACR3_DEFAULT #0x00000000 /* Not Mapped */ +#elif defined(CONFIG_M547X_8X) +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */ +#define ACR1_DEFAULT #0x00000000 /* Not Mapped */ +#define ACR2_DEFAULT #0x00000000 /* Not Mapped */ +#define ACR3_DEFAULT #0x00000000 /* Not Mapped */ +#endif + +#else /* CONFIG_SDRAM_BASE = PAGE_OFFSET */ +/* + * Kernel mapped to physical ram address. + * + * M5445x: + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs + * Data[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - uncached + * Code[0]: Not Mapped + * Code[1]: 0x40000000 -> 0x4FFFFFFF SDRAM - cached + * + * M547x/M548x + * Data[0]: 0xF0000000 -> 0xFFFFFFFF System regs + * Data[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - uncached + * Code[0]: Not Mapped + * Code[1]: 0x00000000 -> 0x0FFFFFFF SDRAM - cached + */ +#if defined(CONFIG_M5445X) +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */ +#define ACR1_DEFAULT #0x400FA048 /* SDRAM uncached */ +#define ACR2_DEFAULT #0x00000000 /* Not mapped */ +#define ACR3_DEFAULT #0x400FA008 /* SDRAM cached */ +#elif defined(CONFIG_M547X_8X) +#define ACR0_DEFAULT #0xF00FA048 /* System Regs */ +#define ACR1_DEFAULT #0x000FA048 /* SDRAM uncached */ +#define ACR2_DEFAULT #0x00000000 /* Not mapped */ +#define ACR3_DEFAULT #0x000FA008 /* SDRAM cached */ +#endif +#endif + +/* Several macros to make the writing of subroutines easier: + * - func_start marks the beginning of the routine which setups the frame + * register and saves the registers, it also defines another macro + * to automatically restore the registers again. + * - func_return marks the end of the routine and simply calls the prepared + * macro to restore registers and jump back to the caller. + * - func_define generates another macro to automatically put arguments + * onto the stack call the subroutine and cleanup the stack again. + */ + +.macro load_symbol_address symbol,register + movel #\symbol,\register +.endm + +.macro func_start name,saveregs,savesize,stack=0 +L(\name): + linkw %a6,#-\stack + subal #(\savesize),%sp + moveml \saveregs,%sp@ +.set stackstart,-\stack + +.macro func_return_\name + moveml %sp@,\saveregs + addal #(\savesize),%sp + unlk %a6 + rts +.endm +.endm + +.macro func_return name + func_return_\name +.endm + +.macro func_call name + jbsr L(\name) +.endm + +.macro move_stack nr,arg1,arg2,arg3,arg4 +.if \nr + move_stack "(\nr-1)",\arg2,\arg3,\arg4 + movel \arg1,%sp@- +.endif +.endm + +.macro func_define name,nr=0 +.macro \name arg1,arg2,arg3,arg4 + move_stack \nr,\arg1,\arg2,\arg3,\arg4 + func_call \name +.if \nr + lea %sp@(\nr*4),%sp +.endif +.endm +.endm + +func_define serial_putc,1 + +.macro putc ch + pea \ch + func_call serial_putc + addql #4,%sp +.endm + +.macro dputc ch +#ifdef DEBUG + putc \ch +#endif +.endm + +func_define putn,1 + +.macro dputn nr +#ifdef DEBUG + putn \nr +#endif +.endm + +#if CONFIG_SDRAM_BASE != PAGE_OFFSET +/* + mmu_map - creates a new TLB entry + + virt_addr Must be on proper boundary + phys_addr Must be on proper boundary + itlb MMUOR_ITLB if instruction TLB or 0 + asid address space ID + shared_global MMUTR_SG if shared between different ASIDs or 0 + size_code MMUDR_SZ1M 1 MB + MMUDR_SZ4K 4 KB + MMUDR_SZ8K 8 KB + MMUDR_SZ16M 16 MB + cache_mode MMUDR_INC instruction non-cacheable + MMUDR_IC instruction cacheable + MMUDR_DWT data writethrough + MMUDR_DCB data copyback + MMUDR_DNCP data non-cacheable, precise + MMUDR_DNCIP data non-cacheable, imprecise + super_prot MMUDR_SP if user mode generates exception or 0 + readable MMUDR_R if permits read access (data TLB) or 0 + writable MMUDR_W if permits write access (data TLB) or 0 + executable MMUDR_X if permits execute access (instruction TLB) or 0 + locked MMUDR_LK prevents TLB entry from being replaced or 0 + temp_data_reg a data register to use for temporary values +*/ +.macro mmu_map virt_addr,phys_addr,itlb,asid,shared_global,size_code,cache_mode,super_prot,readable,writable,executable,locked,temp_data_reg + /* Set up search of TLB. */ + movel #(\virt_addr+1), \temp_data_reg + movel \temp_data_reg, MMUAR + /* Search. */ + movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg + movew \temp_data_reg, (MMUOR) + /* Set up tag value. */ + movel #(\virt_addr + \asid + \shared_global + MMUTR_V), \temp_data_reg + movel \temp_data_reg, MMUTR + /* Set up data value. */ + movel #(\phys_addr + \size_code + \cache_mode + \super_prot + \readable + \writable + \executable + \locked), \temp_data_reg + movel \temp_data_reg, MMUDR + /* Save it. */ + movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg + movew \temp_data_reg, (MMUOR) +.endm /* mmu_map */ + +.macro mmu_unmap virt_addr,itlb,temp_data_reg + /* Set up search of TLB. */ + movel #(\virt_addr+1), \temp_data_reg + movel \temp_data_reg, MMUAR + /* Search. */ + movel #(MMUOR_STLB + MMUOR_ADR +\itlb), \temp_data_reg + movew \temp_data_reg, (MMUOR) + /* Test for hit. */ + movel MMUSR,\temp_data_reg + btst #MMUSR_HITN,\temp_data_reg + beq 1f + /* Read the TLB. */ + movel #(MMUOR_RW + MMUOR_ACC +\itlb), \temp_data_reg + movew \temp_data_reg, (MMUOR) + movel MMUSR,\temp_data_reg + /* Set up tag value. */ + movel #0, \temp_data_reg + movel \temp_data_reg, MMUTR + /* Set up data value. */ + movel #0, \temp_data_reg + movel \temp_data_reg, MMUDR + /* Save it. */ + movel #(MMUOR_ACC + MMUOR_UAA + \itlb), \temp_data_reg + movew \temp_data_reg, (MMUOR) +1: +.endm /* mmu_unmap */ +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */ + +/* .text */ +.section ".text.head","ax" +ENTRY(_stext) +/* Version numbers of the bootinfo interface -- if we later pass info + * from boot ROM we might want to put something real here. + * + * The area from _stext to _start will later be used as kernel pointer table + */ + bras 1f /* Jump over bootinfo version numbers */ + + .long BOOTINFOV_MAGIC + .long 0 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET +1: jmp __start-(0xc0000000-CONFIG_SDRAM_BASE) +#else +1: jmp __start +#endif + +.equ kernel_pg_dir,_stext +.equ .,_stext+0x1000 + +ENTRY(_start) + jra __start +__INIT +ENTRY(__start) + movew #0x2700,%sr /* no interrupts */ +#if defined(CONFIG_UBOOT) + movel %sp,%a4 /* save initial stack pointer */ + addl #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4 /* high mem offset */ + movel %a4, uboot_init_sp /*this will be used by C code after turning on MMU*/ +#endif + +/* Setup initial stack pointer */ + movel #CONFIG_SDRAM_BASE+0x1000,%sp + +/* Setup usp */ + subl %a0,%a0 + movel %a0,%usp + +#if defined(CONFIG_M5445X) + movel #0x80000000, %d0 + movec %d0, %rambar1 +#elif defined(CONFIG_M547X_8X) + movel #MCF_MBAR, %d0 + movec %d0, %mbar + move.l #(MCF_RAMBAR0 + 0x21), %d0 + movec %d0, %rambar0 + move.l #(MCF_RAMBAR1 + 0x21), %d0 + movec %d0, %rambar1 +#endif + +/* reset cache */ + movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0 + movecl %d0,%cacr + + movel #(MMU_BASE+1),%d0 + movecl %d0,%mmubar + movel #MMUOR_CA,%a0 /* Clear tlb entries */ + movew %a0,(MMUOR) + movel #(MMUOR_CA + MMUOR_ITLB),%a0 /* Use ITLB for searches */ + movew %a0,(MMUOR) + movel #0,%a0 /* Clear Addr Space User ID */ + movecl %a0,%asid + +/* setup ACRs */ + movel ACR0_DEFAULT, %d0 /* ACR0 (DATA) setup */ + movec %d0, %acr0 + nop + movel ACR1_DEFAULT, %d0 /* ACR1 (DATA) setup */ + movec %d0, %acr1 + nop + movel ACR2_DEFAULT, %d0 /* ACR2 (CODE) setup */ + movec %d0, %acr2 + nop + movel ACR3_DEFAULT, %d0 /* ACR3 (CODE) setup */ + movec %d0, %acr3 + nop + + /* If you change the memory size to another value make a matching + change in paging_init(cf-mmu.c) to zones_size[]. */ + +#if CONFIG_SDRAM_BASE != PAGE_OFFSET +#if defined(CONFIG_M5445X) + /* Map 256MB as code */ + mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \ + 0, 0, MMUDR_X, MMUDR_LK, %d0 + + /* Map 256MB as data also */ + mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+1*0x1000000), (PHYS_OFFSET+1*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+2*0x1000000), (PHYS_OFFSET+2*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+3*0x1000000), (PHYS_OFFSET+3*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+4*0x1000000), (PHYS_OFFSET+4*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+5*0x1000000), (PHYS_OFFSET+5*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+6*0x1000000), (PHYS_OFFSET+6*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+7*0x1000000), (PHYS_OFFSET+7*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+8*0x1000000), (PHYS_OFFSET+8*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+9*0x1000000), (PHYS_OFFSET+9*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+10*0x1000000), (PHYS_OFFSET+10*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+11*0x1000000), (PHYS_OFFSET+11*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+12*0x1000000), (PHYS_OFFSET+12*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+13*0x1000000), (PHYS_OFFSET+13*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+14*0x1000000), (PHYS_OFFSET+14*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+15*0x1000000), (PHYS_OFFSET+15*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + + /* Map ATA registers -- sacrifice a data TLB due to the hw design */ + mmu_map (0x90000000), (0x90000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, MMUDR_LK, %d0 + +#elif defined(CONFIG_M547X_8X) + + /* Map first 8 MB as code */ + mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, MMUDR_X, \ + MMUDR_LK, %d0 + + /* Map first 8 MB as data */ + mmu_map (PAGE_OFFSET+0*1024*1024), (0*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+1*1024*1024), (1*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+2*1024*1024), (2*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+3*1024*1024), (3*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+4*1024*1024), (4*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+5*1024*1024), (5*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+6*1024*1024), (6*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 + mmu_map (PAGE_OFFSET+7*1024*1024), (7*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, MMUDR_LK, %d0 +#endif + /* + * Do unity mapping to enable the MMU. Map first chunk of memory + * in place as code/data. The TLBs will be deleted after the MMU is + * enabled and we are executing in high memory. + */ + +#if defined(CONFIG_M5445X) + /* Map first 16 MB as code */ + mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \ + MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \ + 0, MMUDR_X, 0, %d0 + /* Map first 16 MB as data too */ + mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \ + MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \ + 0, 0, %d0 +#elif defined(CONFIG_M547X_8X) + /* Map first 4 MB as code */ + mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ + MMUDR_X, 0, %d0 + mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ + MMUDR_X, 0, %d0 + mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ + MMUDR_X, 0, %d0 + mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_IC, MMUDR_SP, 0, 0, \ + MMUDR_X, 0, %d0 + + /* Map first 4 MB as data too */ + mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, 0, %d0 + mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, 0, %d0 + mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, 0, %d0 + mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \ + MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \ + MMUDR_W, 0, 0, %d0 +#endif +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */ + + /* Turn on MMU */ + movel #(MMUCR_EN),%a0 + movel %a0,MMUCR + nop /* This synchs the pipeline after a write to MMUCR */ + + movel #__running_high,%a0 /* Get around PC-relative addressing. */ + jmp %a0@ + +ENTRY(__running_high) + load_symbol_address _stext,%sp + movel L(memory_start),%a0 + movel %a0,availmem + load_symbol_address L(phys_kernel_start),%a0 + load_symbol_address _stext,%a1 + subl #_stext,%a1 + addl #PAGE_OFFSET,%a1 + movel %a1,%a0@ + +/* zero bss */ + lea _sbss,%a0 + lea _ebss,%a1 + clrl %d0 +_loop_bss: + movel %d0,(%a0)+ + cmpl %a0,%a1 + bne _loop_bss + + /* Unmap unity mappings */ +#if CONFIG_SDRAM_BASE != PAGE_OFFSET +#if defined(CONFIG_M5445X) + mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0 + mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0 +#elif defined(CONFIG_M547X_8X) + mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0 + mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0 + mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0 + mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0 + mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0 + mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0 + mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0 + mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0 +#endif +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */ + + /* + * Load the current task pointer and stack. + */ + lea init_thread_union,%a0 + lea THREAD_SIZE(%a0),%sp + +#ifdef CONFIG_MCF_USER_HALT +/* Setup debug control reg to allow halts from user space */ + lea wdbg_uhe,%a0 + wdebug (%a0) +#endif + + /* Continuing in C code */ + bsr cf_early_init + jmp start_kernel + +.section ".text.head","ax" +set_context: +func_start set_context,%d0,(1*4) + movel 12(%sp),%d0 + movec %d0,%asid +func_return set_context + +#ifdef CONFIG_M5445X +/* + * set_fpga(addr,val) on the M5445X + * + * Map in 0x00000000 -> 0x0fffffff and then do the write. + */ +set_fpga: +#if 0 + movew %sr,%d1 + movew #0x2700,%sr + movel ACR0_FPGA, %d0 + movec %d0, %acr0 + nop + moveal 4(%sp),%a0 + movel 8(%sp),%a0@ + movel ACR0_DEFAULT, %d0 + movec %d0, %acr0 + nop + movew %d1,%sr +#endif + rts +#endif + + .data + .align 4 + +availmem: + .long 0 +L(phys_kernel_start): + .long PAGE_OFFSET +L(kernel_end): + .long 0 +L(memory_start): + .long PAGE_OFFSET_RAW + +#if defined(CONFIG_UBOOT) +L(uboot_init_sp): +.long 0 +#endif + +#ifdef CONFIG_MCF_USER_HALT +/* + * Enable User Halt Enable in the debug control register. + */ +wdbg_uhe: + .word 0x2c80 /* DR0 */ + .word 0x00b0 /* 31:16 */ + .word 0x0400 /* 15:0 -- enable UHE */ + .word 0x0000 /* unused */ +#endif + + diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c index 4bbb3c2a8880..a781816288ed 100644 --- a/arch/m68k/kernel/dma.c +++ b/arch/m68k/kernel/dma.c @@ -15,6 +15,7 @@ #include +#ifndef CONFIG_COLDFIRE void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t flag) { @@ -57,13 +58,33 @@ void *dma_alloc_coherent(struct device *dev, size_t size, return addr; } +#else +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *handle, gfp_t flag) +{ + /* + * On the M5445x platform the memory allocated with GFP_DMA + * is guaranteed to be DMA'able. + */ + void *addr; + + size = PAGE_ALIGN(size); + addr = kmalloc(size, GFP_DMA); + *handle = virt_to_phys(addr); + return addr; +} +#endif EXPORT_SYMBOL(dma_alloc_coherent); void dma_free_coherent(struct device *dev, size_t size, void *addr, dma_addr_t handle) { pr_debug("dma_free_coherent: %p, %x\n", addr, handle); +#ifndef CONFIG_COLDFIRE vfree(addr); +#else + kfree(addr); +#endif } EXPORT_SYMBOL(dma_free_coherent); @@ -89,9 +110,18 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nent enum dma_data_direction dir) { int i; +#ifdef CONFIG_COLDFIRE + struct scatterlist *_sg; //tsk no C99 tsk + + for_each_sg(sg, _sg, nents, i) + dma_sync_single_for_device(dev, _sg->dma_address, _sg->length, dir); + +#else for (i = 0; i < nents; sg++, i++) dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); + +#endif } EXPORT_SYMBOL(dma_sync_sg_for_device); @@ -120,11 +150,20 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir) { int i; +#ifdef CONFIG_COLDFIRE + struct scatterlist *_sg; //tsk no C99 tsk + for_each_sg(sg, _sg, nents, i) { + _sg->dma_address = sg_phys(_sg); + dma_sync_single_for_device(dev, _sg->dma_address, + _sg->length, dir); + } +#else for (i = 0; i < nents; sg++, i++) { sg->dma_address = sg_phys(sg); dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir); } +#endif return nents; } EXPORT_SYMBOL(dma_map_sg); diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c index c2a1fc23dd75..760878870e9a 100644 --- a/arch/m68k/kernel/process.c +++ b/arch/m68k/kernel/process.c @@ -184,13 +184,23 @@ EXPORT_SYMBOL(kernel_thread); void flush_thread(void) { - unsigned long zero = 0; + unsigned long zero = 0; set_fs(USER_DS); + +#ifndef CONFIG_COLDFIRE current->thread.fs = __USER_DS; if (!FPU_IS_EMU) asm volatile (".chip 68k/68881\n\t" "frestore %0@\n\t" ".chip 68k" : : "a" (&zero)); +#else + current->thread.fs = USER_DS; + +#ifdef CONFIG_FPU + if (!FPU_IS_EMU) + asm volatile ("frestore %0@\n\t" : : "a" (&zero)); +#endif +#endif } /* @@ -258,6 +268,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, * Must save the current SFC/DFC value, NOT the value when * the parent was last descheduled - RGH 10-08-96 */ +#ifndef CONFIG_COLDFIRE p->thread.fs = get_fs().seg; if (!FPU_IS_EMU) { @@ -272,7 +283,33 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, /* Restore the state in case the fpu was busy */ asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0])); } +#else + p->thread.fs = get_fs(); +#if defined(CONFIG_FPU) + if (!FPU_IS_EMU) { + /* Copy the current fpu state */ + asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) + : "memory"); + if (p->thread.fpstate[0]) { + asm volatile ("fmovemd %/fp0-%/fp7,%0" + : : "m" (p->thread.fp[0]) + : "memory"); + asm volatile ("fmovel %/fpiar,%0" + : : "m" (p->thread.fpcntl[0]) + : "memory"); + asm volatile ("fmovel %/fpcr,%0" + : : "m" (p->thread.fpcntl[1]) + : "memory"); + asm volatile ("fmovel %/fpsr,%0" + : : "m" (p->thread.fpcntl[2]) + : "memory"); + } + /* Restore the state in case the fpu was busy */ + asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0])); + } +#endif +#endif return 0; } @@ -297,6 +334,7 @@ int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu) } /* First dump the fpu context to avoid protocol violation. */ +#ifndef CONFIG_COLDFIRE asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory"); if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) return 0; @@ -307,6 +345,25 @@ int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu) asm volatile ("fmovemx %/fp0-%/fp7,%0" :: "m" (fpu->fpregs[0]) : "memory"); +#elif CONFIG_FPU + /* COLDFIRE + FPU */ + asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory"); + if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2]) + return 0; + + asm volatile ("fmovel %/fpiar,%0" + : : "m" (fpu->fpcntl[0]) + : "memory"); + asm volatile ("fmovel %/fpcr,%0" + : : "m" (fpu->fpcntl[1]) + : "memory"); + asm volatile ("fmovel %/fpsr,%0" + : : "m" (fpu->fpcntl[2]) + : "memory"); + asm volatile ("fmovemd %/fp0-%/fp7,%0" + : : "m" (fpu->fpregs[0]) + : "memory"); +#endif return 1; } EXPORT_SYMBOL(dump_fpu); diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c index 1e29fac36940..9e1b0e92dcce 100644 --- a/arch/m68k/kernel/setup.c +++ b/arch/m68k/kernel/setup.c @@ -173,8 +173,11 @@ static void __init m68k_parse_bootinfo(const struct bi_record *record) break; case BI_RAMDISK: +//if U-boot then ignore +#ifndef CONFIG_UBOOT m68k_ramdisk.addr = data[0]; m68k_ramdisk.size = data[1]; +#endif break; case BI_COMMAND_LINE: diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c index 3db2e7f902aa..ad75780b3106 100644 --- a/arch/m68k/kernel/sys_m68k.c +++ b/arch/m68k/kernel/sys_m68k.c @@ -30,6 +30,10 @@ #include #include +#ifdef CONFIG_COLDFIRE +#include +#endif + asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address, unsigned long error_code); @@ -46,6 +50,7 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len, } /* Convert virtual (user) address VADDR to physical address PADDR */ +#ifndef CONFIG_COLDFIRE #define virt_to_phys_040(vaddr) \ ({ \ unsigned long _mmusr, _paddr; \ @@ -369,6 +374,8 @@ cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len) return 0; } +#endif /* CONFIG_COLDFIRE */ + /* sys_cacheflush -- flush (part of) the processor cache. */ asmlinkage int sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) @@ -399,6 +406,7 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) goto out; } +#ifndef CONFIG_COLDFIRE if (CPU_IS_020_OR_030) { if (scope == FLUSH_SCOPE_LINE && len < 256) { unsigned long cacr; @@ -443,6 +451,15 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) ret = cache_flush_060 (addr, scope, cache, len); } } +#else /* CONFIG_COLDFIRE */ + if ((cache & FLUSH_CACHE_INSN) && (cache & FLUSH_CACHE_DATA)) + flush_bcache(); + else if (cache & FLUSH_CACHE_INSN) + flush_icache(); + else + flush_dcache(); + + ret = 0; out: return ret; } diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 06438dac08ff..ad342c0a0960 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -41,6 +41,12 @@ static inline int set_rtc_mmss(unsigned long nowtime) */ static irqreturn_t timer_interrupt(int irq, void *dummy) { +#ifdef CONFIG_COLDFIRE + /* kick hardware timer if necessary */ + if (mach_tick) + mach_tick(); +#endif + do_timer(1); update_process_times(user_mode(get_irq_regs())); profile_tick(CPU_PROFILING); diff --git a/arch/m68k/kernel/vmlinux-cf.lds b/arch/m68k/kernel/vmlinux-cf.lds new file mode 100755 index 000000000000..595a3a438f98 --- /dev/null +++ b/arch/m68k/kernel/vmlinux-cf.lds @@ -0,0 +1,136 @@ +/* ld script to make m68k Coldfire Linux kernel + * + * Derived from arch/m68k/kernel/vmlinux-std.lds + * + * Updated 11/26/2007 for new CodeSourcery toolset + * by Kurt Mahan + * + * Copyright Freescale Semiconductor, Inc. 2008-2009 + * Jason Jin Jason.Jin@freescale.com + * Shrek Wu B16972@freescale.com + */ + +#define LOAD_OFFSET 0x00000000 + +#include +#include + +#define START_OFFSET 0x00020000 +#define IMAGE_START PAGE_OFFSET_RAW + START_OFFSET + +OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", "elf32-m68k") +OUTPUT_ARCH(m68k) +ENTRY(_stext) +jiffies = jiffies_64 + 4; +SECTIONS +{ + . = IMAGE_START; + .text.head : AT(ADDR(.text.head) - LOAD_OFFSET) { + _text = .; /* Text and read-only data */ + HEAD_TEXT + } :text = 0x4e75 + + .text : AT(ADDR(.text) - LOAD_OFFSET) { + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.gnu.warning) + } :text = 0x4e75 + + _etext = .; /* End of text section */ + + . = ALIGN(16); + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + + RODATA + + . = ALIGN(8192); + .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */ + DATA_DATA + CONSTRUCTORS + } :data + + + . = ALIGN(16); + .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET ) { + *(.data.cacheline_aligned) + } :data + + _edata = .; /* End of data section */ + + . = ALIGN(8192); /* Initrd */ + .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { + __init_begin = .; + _sinittext = .; + INIT_TEXT + _einittext = .; + } + + .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { + INIT_DATA + } + + . = ALIGN(16); + .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) { + __setup_start = .; + *(.init.setup) + __setup_end = .; + } + + .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) { + __initcall_start = .; + INITCALLS + __initcall_end = .; + } + + .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) { + __con_initcall_start = .; + *(.con_initcall.init) + __con_initcall_end = .; + } + + SECURITY_INIT + +#ifdef CONFIG_BLK_DEV_INITRD + . = ALIGN(8192); + .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } +#endif + NOTES + . = ALIGN(8192); + __init_end = .; + + .data.init_task : AT(ADDR(.data.init_task) - LOAD_OFFSET) { + *(.data.init_task) /* The initial task and kernel stack */ + } + + _sbss = .; + .bss : AT(ADDR(.bss) - LOAD_OFFSET) { /* BSS */ + *(.bss) + } + _ebss = .; + + _end = . ; + + /DISCARD/ : { + EXIT_TEXT + EXIT_DATA + *(.exitcall.exit) + *(.discard) + } + + STABS_DEBUG + .comment 0 : { *(.comment) } + + /* Sections to be discarded */ + /*DISCARDS*/ + +} diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c index 4253f870e54f..9b925221bdc2 100644 --- a/arch/m68k/lib/string.c +++ b/arch/m68k/lib/string.c @@ -21,6 +21,8 @@ char *strcat(char *dest, const char *src) } EXPORT_SYMBOL(strcat); +#ifndef CONFIG_COLDFIRE + void *memset(void *s, int c, size_t count) { void *xs = s; @@ -149,6 +151,69 @@ void *memcpy(void *to, const void *from, size_t n) } EXPORT_SYMBOL(memcpy); +#else /* CONFIG_COLDFIRE */ + +void *memset(void *s, int c, size_t count) +{ + unsigned long x; + void *originalTo = s; + + for (x = 0; x < count; x++) + *(unsigned char *)s++ = (unsigned char)c; + + return originalTo; +} +EXPORT_SYMBOL(memset); + +void *memcpy(void *to, const void *from, size_t n) +{ + void *xto = to; + size_t temp; + + if (!n) + return xto; + if ((long) to & 1) { + char *cto = to; + const char *cfrom = from; + *cto++ = *cfrom++; + to = cto; + from = cfrom; + n--; + } + if (n > 2 && (long) to & 2) { + short *sto = to; + const short *sfrom = from; + *sto++ = *sfrom++; + to = sto; + from = sfrom; + n -= 2; + } + temp = n >> 2; + if (temp) { + long *lto = to; + const long *lfrom = from; + for (; temp; temp--) + *lto++ = *lfrom++; + to = lto; + from = lfrom; + } + if (n & 2) { + short *sto = to; + const short *sfrom = from; + *sto++ = *sfrom++; + to = sto; + from = sfrom; + } + if (n & 1) { + char *cto = to; + const char *cfrom = from; + *cto = *cfrom; + } + return xto; +} +EXPORT_SYMBOL(memcpy); +#endif /* CONFIG_COLDFIRE */ + void *memmove(void *dest, const void *src, size_t n) { void *xdest = dest; diff --git a/arch/m68k/mm/Makefile b/arch/m68k/mm/Makefile index 5eaa43c4cb3c..f0e233a402eb 100644 --- a/arch/m68k/mm/Makefile +++ b/arch/m68k/mm/Makefile @@ -2,7 +2,13 @@ # Makefile for the linux m68k-specific parts of the memory manager. # -obj-y := cache.o init.o fault.o hwtest.o +obj-y := init.o fault.o hwtest.o + +ifndef CONFIG_COLDFIRE + obj-y += cache.o +endif + obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o +obj-$(CONFIG_MMU_CFV4E) += cf-mmu.o kmap.o memory.o diff --git a/arch/m68k/mm/cf-mmu.c b/arch/m68k/mm/cf-mmu.c new file mode 100644 index 000000000000..311f265ae1b3 --- /dev/null +++ b/arch/m68k/mm/cf-mmu.c @@ -0,0 +1,236 @@ +/* + * linux/arch/m68k/mm/cf-mmu.c + * + * Based upon linux/arch/m68k/mm/sun3mmu.c + * Based upon linux/arch/ppc/mm/mmu_context.c + * + * Implementations of mm routines specific to the Coldfire MMU. + * + * Copyright (c) 2008 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_BLK_DEV_RAM +#include +#endif +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define KMAPAREA(x) ((x >= VMALLOC_START) && ( x < KMAP_END)) + +#undef DEBUG + +mm_context_t next_mmu_context; +unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; + +atomic_t nr_free_contexts; +struct mm_struct *context_mm[LAST_CONTEXT+1]; + +const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n"; + +extern unsigned long empty_bad_page_table; +extern unsigned long empty_bad_page; +extern unsigned long num_pages; + +extern char __init_begin, __init_end; + +void free_initmem(void) +{ +#if 0 + unsigned long addr; + unsigned long start = (unsigned long)&__init_begin; + unsigned long end = (unsigned long)&__init_end; + + printk(KERN_INFO "free_initmem: __init_begin = 0x%lx __init_end = 0x%lx\n", start, end); + + addr = (unsigned long)&__init_begin; + for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) { + /* not currently used */ + virt_to_page(addr)->flags &= ~(1 << PG_reserved); + init_page_count(virt_to_page(addr)); + free_page(addr); + totalram_pages++; + } +#endif +} + +/* Coldfire paging_init derived from sun3 */ +void __init paging_init(void) +{ + pgd_t * pg_dir; + pte_t * pg_table; + int i; + unsigned long address; + unsigned long next_pgtable; + unsigned long bootmem_end; + unsigned long zones_size[MAX_NR_ZONES]; + unsigned long size; + enum zone_type zone; + + empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE); + memset((void *)empty_zero_page, 0, PAGE_SIZE); + + pg_dir = swapper_pg_dir; + memset(swapper_pg_dir, 0, sizeof (swapper_pg_dir)); + + size = num_pages * sizeof(pte_t); + size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1); + next_pgtable = (unsigned long)alloc_bootmem_pages(size); + + bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK; + pg_dir += PAGE_OFFSET >> PGDIR_SHIFT; + + address = PAGE_OFFSET; + while (address < (unsigned long)high_memory) + { + pg_table = (pte_t *)next_pgtable; + next_pgtable += PTRS_PER_PTE * sizeof (pte_t); + pgd_val(*pg_dir) = (unsigned long) pg_table; + pg_dir++; + + /* now change pg_table to kernel virtual addresses */ + for (i=0; i= (unsigned long)high_memory) + pte_val (pte) = 0; + + set_pte (pg_table, pte); + address += PAGE_SIZE; + } + } + + current->mm = NULL; + + /* clear zones */ + for (zone = 0; zone < MAX_NR_ZONES; zone++) + zones_size[zone] = 0x0; + + /* allocate the bottom 32M (0x40x 0x41x) to DMA - head.S marks them NO CACHE */ + /* JKM - this should be changed to allocate from the TOP (0x4f,0x4e) but the + * allocator is being a bit challenging */ + zones_size[ZONE_DMA] = (32*1024*1024) >> PAGE_SHIFT; + + /* allocate the rest to NORMAL - head.S marks them CACHE */ + zones_size[ZONE_NORMAL] = (((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT) - zones_size[0]; + + free_area_init(zones_size); +} + + +int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word) +{ + struct mm_struct *mm; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + unsigned long mmuar; + int asid; + int flags; + + local_save_flags(flags); + local_irq_disable(); + + mmuar = ( dtlb ) ? regs->mmuar + : regs->pc + (extension_word * sizeof(long)); + + mm = (!user_mode(regs) && KMAPAREA(mmuar)) ? &init_mm : current->mm; + + if (!mm) { + local_irq_restore(flags); + return (-1); + } + + pgd = pgd_offset(mm, mmuar); + if (pgd_none(*pgd)) { + local_irq_restore(flags); + return (-1); + } + + pmd = pmd_offset(pgd, mmuar); + if (pmd_none(*pmd)) { + local_irq_restore(flags); + return (-1); + } + + pte = (KMAPAREA(mmuar)) ? pte_offset_kernel(pmd, mmuar) + : pte_offset_map(pmd, mmuar); + if (pte_none(*pte) || !pte_present(*pte)) { + local_irq_restore(flags); + return (-1); + } + + if (write) { + if (!pte_write(*pte)) { + local_irq_restore(flags); + return (-1); + } + set_pte(pte, pte_mkdirty(*pte)); + } + + set_pte(pte, pte_mkyoung(*pte)); + asid = mm->context & 0xff; + if (!pte_dirty(*pte) && !KMAPAREA(mmuar)) + set_pte(pte, pte_wrprotect(*pte)); + + *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT) + | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT) + | MMUTR_V; + + *MMUDR = (pte_val(*pte) & PAGE_MASK) + | ((pte->pte) & CF_PAGE_MMUDR_MASK) + | MMUDR_SZ8K | MMUDR_X; + + if ( dtlb ) + *MMUOR = MMUOR_ACC | MMUOR_UAA; + else + *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA; + + asm("nop"); + +#ifdef DEBUG + printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK), + (pte_val(*pte) & PAGE_MASK)); +#endif + local_irq_restore(flags); + return (0); +} + + +/* The following was taken from arch/ppc/mmu_context.c + * + * Initialize the context management stuff. + */ +void __init mmu_context_init(void) +{ + /* + * Some processors have too few contexts to reserve one for + * init_mm, and require using context 0 for a normal task. + * Other processors reserve the use of context zero for the kernel. + * This code assumes FIRST_CONTEXT < 32. + */ + context_map[0] = (1 << FIRST_CONTEXT) - 1; + next_mmu_context = FIRST_CONTEXT; + atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1); +} + + diff --git a/arch/m68k/mm/hwtest.c b/arch/m68k/mm/hwtest.c index 2c7dde3c6430..a7090aaaf5dd 100644 --- a/arch/m68k/mm/hwtest.c +++ b/arch/m68k/mm/hwtest.c @@ -25,6 +25,11 @@ #include +/* On Coldfire if XLB arbiter isn't set up this would kill the kernel. + * So let's not do this. + */ + +#ifndef CONFIG_COLDFIRE int hwreg_present( volatile void *regp ) { int ret = 0; @@ -82,4 +87,5 @@ int hwreg_write( volatile void *regp, unsigned short val ) return( ret ); } EXPORT_SYMBOL(hwreg_write); +#endif diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c index 8bc842554e5b..c85863681d0e 100644 --- a/arch/m68k/mm/init.c +++ b/arch/m68k/mm/init.c @@ -32,6 +32,10 @@ #include #include +#ifdef CONFIG_VDSO +int vdso_init(void); +#endif + DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); pg_data_t pg_data_map[MAX_NUMNODES]; @@ -113,7 +117,7 @@ void __init mem_init(void) } } -#ifndef CONFIG_SUN3 +#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) /* insert pointer tables allocated so far into the tablelist */ init_pointer_table((unsigned long)kernel_pg_dir); for (i = 0; i < PTRS_PER_PGD; i++) { @@ -132,6 +136,11 @@ void __init mem_init(void) codepages << (PAGE_SHIFT-10), datapages << (PAGE_SHIFT-10), initpages << (PAGE_SHIFT-10)); + +#ifdef CONFIG_VDSO + /* init the vdso page */ + vdso_init(); +#endif } #ifdef CONFIG_BLK_DEV_INITRD diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c index 69345849454b..c8399981a097 100644 --- a/arch/m68k/mm/kmap.c +++ b/arch/m68k/mm/kmap.c @@ -24,7 +24,11 @@ #undef DEBUG -#define PTRTREESIZE (256*1024) +#ifndef CONFIG_COLDFIRE + #define PTRTREESIZE (256*1024) +#else +#define PTRTREESIZE PAGE_SIZE +#endif /* * For 040/060 we can use the virtual memory area like other architectures, @@ -35,8 +39,11 @@ #ifdef CPU_M68040_OR_M68060_ONLY -#define IO_SIZE PAGE_SIZE - +#ifdef CONFIG_COLDFIRE +#define IO_SIZE PAGE_SIZE +#else +#define IO_SIZE (256*1024) +#endif static inline struct vm_struct *get_io_area(unsigned long size) { return get_vm_area(size, VM_IOREMAP); @@ -126,8 +133,36 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla } #endif +#ifdef CONFIG_M5445X + if (physaddr >= 0xf0000000) { + /* + * On the M5445x processors an ACR is setup to map + * the 0xF0000000 range into kernel memory as + * non-cacheable. + */ + return (void __iomem *)physaddr; + } +#endif + +#ifdef CONFIG_M547X_8X + if (physaddr >= 0xf0000000) { + /* + * On the M547x/M548x processors an ACR is setup to map + * the 0xF0000000 range into kernel memory as + * non-cacheable. + */ + return (void __iomem *)physaddr; + } + + //FIXME: Check this if PCI is enabled + /*if ((physaddr >= 0xd0000000) && (physaddr + size < 0xd800ffff)) { + printk("ioremap:PCI 0x%lx,0x%lx(%d) - PCI area hit\n", physaddr, size, cacheflag); + return (void *)physaddr; + }*/ +#endif + #ifdef DEBUG - printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag); + printk(KERN_ERR "ioremap: physaddr=0x%lx, size=0x%lx(%d) - ", physaddr, size, cacheflag); #endif /* * Mappings have to be aligned @@ -146,7 +181,7 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla virtaddr = (unsigned long)area->addr; retaddr = virtaddr + offset; #ifdef DEBUG - printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr); + printk("physaddr=0x%lx, virtaddr=0x%lx, retaddr=0x%lx", physaddr, virtaddr, retaddr); #endif /* @@ -171,7 +206,11 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla break; } } else { +#ifndef CONFIG_COLDFIRE physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY); +#else + physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_READWRITE); +#endif switch (cacheflag) { case IOMAP_NOCACHE_SER: case IOMAP_NOCACHE_NONSER: diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index fa9f746cf4ae..dd930aeb102a 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -168,11 +168,6 @@ config M5407 help Motorola ColdFire 5407 processor support. -config M548x - bool "MCF548x" - help - Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. - endchoice config M527x @@ -183,7 +178,7 @@ config M527x config COLDFIRE bool - depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x) + depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 ) select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB default y diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile index 026ef16fa68e..14042574ac21 100644 --- a/arch/m68knommu/Makefile +++ b/arch/m68knommu/Makefile @@ -25,7 +25,6 @@ platform-$(CONFIG_M528x) := 528x platform-$(CONFIG_M5307) := 5307 platform-$(CONFIG_M532x) := 532x platform-$(CONFIG_M5407) := 5407 -platform-$(CONFIG_M548x) := 548x PLATFORM := $(platform-y) board-$(CONFIG_PILOT) := pilot @@ -74,7 +73,6 @@ cpuclass-$(CONFIG_M528x) := coldfire cpuclass-$(CONFIG_M5307) := coldfire cpuclass-$(CONFIG_M532x) := coldfire cpuclass-$(CONFIG_M5407) := coldfire -cpuclass-$(CONFIG_M548x) := coldfire cpuclass-$(CONFIG_M68328) := 68328 cpuclass-$(CONFIG_M68EZ328) := 68328 cpuclass-$(CONFIG_M68VZ328) := 68328 @@ -102,7 +100,6 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307) cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) -cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200) cflags-$(CONFIG_M68328) := -m68000 cflags-$(CONFIG_M68EZ328) := -m68000 cflags-$(CONFIG_M68VZ328) := -m68000 diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 45f501fa4525..788c13f82d9b 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o intc.o obj-$(CONFIG_M532x) += timers.o intc-simr.o obj-$(CONFIG_M5407) += timers.o intc.o -obj-$(CONFIG_M548x) += sltimers.o intc-2.o obj-y += pinmux.o gpio.o extra-y := head.o diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4f1755bddf6b..c7729aaf2b68 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1980,6 +1980,29 @@ config FEC_MPC52xx_MDIO If not sure, enable. If compiled as module, it will be called fec_mpc52xx_phy. +config FEC_DMA + tristate "MCF547x/MCF548x Fast Ethernet Controller support" + depends on M547X_8X + select PHYLIB + help + The MCF547x and MCF548x have a built-in Fast Ethernet Controller. + Saying Y here will include support for this device in the kernel. + + To compile this driver as a module, choose M here: the module + will be called fecm. + +config FEC_DMA_ENABLE_FEC2 + bool "Enable the second FEC" + depends on FEC_DMA + help + This enables the second FEC on the 547x/548x. + +config FEC_DMA_SHARED_PHY + bool "Shared PHY interface(on some ColdFire designs)" + depends on FEC_DMA_ENABLE_FEC2 + help + Say Y here if both PHYs are controlled via a single channel. + config NE_H8300 tristate "NE2000 compatible support for H8/300" depends on H8300 diff --git a/drivers/net/fec_dma.c b/drivers/net/fec_dma.c new file mode 100644 index 000000000000..67d8bdc47088 --- /dev/null +++ b/drivers/net/fec_dma.c @@ -0,0 +1,1554 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Author: Kurt Mahan, kmahan@freescale.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "fec_dma.h" + +#ifdef CONFIG_FEC_548x_ENABLE_FEC2 +#define FEC_MAX_PORTS 2 +#define FEC_2 +#else +#define FEC_MAX_PORTS 1 +#undef FEC_2 +#endif + +#define VERSION "0.20" +MODULE_DESCRIPTION("DMA Fast Ethernet Controller driver ver " VERSION); + +/* fec private */ +struct fec_priv { + struct net_device *netdev; /* owning net device */ + void *fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */ + MCD_bufDescFec *fecpriv_txdesc; /* tx descriptor ptrs */ + volatile unsigned int fecpriv_current_tx; /* current tx desc index */ + volatile unsigned int fecpriv_next_tx; /* next tx desc index */ + unsigned int fecpriv_current_rx; /* current rx desc index */ + MCD_bufDescFec *fecpriv_rxdesc; /* rx descriptor ptrs */ + struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */ + unsigned int fecpriv_initiator_rx; /* rx dma initiator */ + unsigned int fecpriv_initiator_tx; /* tx dma initiator */ + int fecpriv_fec_rx_channel; /* rx dma channel */ + int fecpriv_fec_tx_channel; /* tx dma channel */ + int fecpriv_rx_requestor; /* rx dma requestor */ + int fecpriv_tx_requestor; /* tx dma requestor */ + void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */ + void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */ + unsigned char *fecpriv_mac_addr; /* private fec mac addr */ + struct net_device_stats fecpriv_stat; /* stats ptr */ + spinlock_t fecpriv_lock; + int fecpriv_rxflag; + struct tasklet_struct fecpriv_tasklet_reinit; + int index; /* fec hw number */ + struct phy_device *phydev; + struct mii_bus *mdio_bus; + int duplex; + int link; + int speed; +}; + +struct net_device *fec_dev[FEC_MAX_PORTS]; + +/* FEC functions */ +static int __init fec_init(void); +static struct net_device_stats *fec_get_stat(struct net_device *dev); +static int fec_open(struct net_device *dev); +static int fec_close(struct net_device *nd); +static int fec_tx(struct sk_buff *skb, struct net_device *dev); +static void fec_set_multicast_list(struct net_device *nd); +static int fec_set_mac_address(struct net_device *dev, void *p); +static void fec_tx_timeout(struct net_device *dev); +static void fec_interrupt_fec_tx_handler(struct net_device *dev); +static void fec_interrupt_fec_rx_handler(struct net_device *dev); +static irqreturn_t fec_interrupt_handler(int irq, void *dev_id); +static void fec_interrupt_fec_tx_handler_fec0(void); +static void fec_interrupt_fec_rx_handler_fec0(void); +static void fec_interrupt_fec_reinit(unsigned long data); + +/* default fec0 address */ +unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 }; + +#ifdef FEC_2 +/* default fec1 address */ +unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 }; +#endif + +#ifndef MODULE +int fec_str_to_mac(char *str_mac, unsigned char* addr); +int __init fec_mac_setup0(char *s); +#endif + + +#ifdef FEC_2 +void fec_interrupt_fec_tx_handler_fec1(void); +void fec_interrupt_fec_rx_handler_fec1(void); +#endif + +#ifndef MODULE +int __init fec_mac_setup1(char *s); +#endif + +module_init(fec_init); +/* module_exit(fec_cleanup); */ + +__setup("mac0=", fec_mac_setup0); + +#ifdef FEC_2 +__setup("mac1=", fec_mac_setup1); +#endif + +#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) +#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ + (VAL & 0xffff)) +/* ----------------------------------------------------------- */ +static int coldfire_fec_mdio_read(struct mii_bus *bus, + int phy_id, int reg) +{ + int ret; + struct net_device *dev = bus->priv; +#ifdef CONFIG_FEC_548x_SHARED_PHY + unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; +#else + unsigned long base_addr = (unsigned long) dev->base_addr; +#endif + int tries = 100; + + /* Clear the MII interrupt bit */ + FEC_EIR(base_addr) = FEC_EIR_MII; + + /* Write to the MII management frame register */ + FEC_MMFR(base_addr) = mk_mii_read(reg) | (phy_id << 23); + + /* Wait for the reading */ + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) { + udelay(10); + + if (!tries) { + printk(KERN_ERR "%s timeout\n", __func__); + return -ETIMEDOUT; + } + tries--; + } + + /* Clear the MII interrupt bit */ + FEC_EIR(base_addr) = FEC_EIR_MII; + ret = FEC_MMFR(base_addr) & 0x0000FFFF; + return ret; +} + +static int coldfire_fec_mdio_write(struct mii_bus *bus, + int phy_id, int reg, u16 data) +{ + int ret; + struct net_device *dev = bus->priv; +#ifdef CONFIG_FEC_548x_SHARED_PHY + unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0; +#else + unsigned long base_addr = (unsigned long) dev->base_addr; +#endif + int tries = 100; + + printk(KERN_ERR "%s base_addr %x, phy_id %x, reg %x, data %x\n", + __func__, base_addr, phy_id, reg, data); + /* Clear the MII interrupt bit */ + FEC_EIR(base_addr) = FEC_EIR_MII; + + /* Write to the MII management frame register */ + FEC_MMFR(base_addr) = mk_mii_write(reg, data) | (phy_id << 23); + + /* Wait for the writing */ + while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) { + udelay(10); + if (!tries) { + printk(KERN_ERR "%s timeout\n", __func__); + return -ETIMEDOUT; + } + tries--; + } + /* Clear the MII interrupt bit */ + FEC_EIR(base_addr) = FEC_EIR_MII; + ret = FEC_MMFR(base_addr) & 0x0000FFFF; + + return ret; +} + +static void fec_adjust_link(struct net_device *dev) +{ + struct fec_priv *priv = netdev_priv(dev); + struct phy_device *phydev = priv->phydev; + int new_state = 0; + + if (phydev->link != PHY_DOWN) { + if (phydev->duplex != priv->duplex) { + new_state = 1; + priv->duplex = phydev->duplex; + } + + if (phydev->speed != priv->speed) { + new_state = 1; + priv->speed = phydev->speed; + } + + if (priv->link == PHY_DOWN) { + new_state = 1; + priv->link = phydev->link; + } + } else if (priv->link) { + new_state = 1; + priv->link = PHY_DOWN; + priv->speed = 0; + priv->duplex = -1; + } + + if (new_state) + phy_print_status(phydev); +} + +static int coldfire_fec_init_phy(struct net_device *dev) +{ + struct fec_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int i; + int startnode; + +#ifdef CONFIG_FEC_548x_SHARED_PHY + if (priv->index == 0) + startnode = 0; + else if (priv->index == 1) { + struct fec_priv *priv0 = netdev_priv(fec_dev[0]); + startnode = priv0->phydev->addr + 1; + } else + startnode = 0; +#else + startnode = 0; +#endif +#ifdef FEC_DEBUG + printk(KERN_ERR "%s priv->index %x, startnode %x\n", + __func__, priv->index, startnode); +#endif + /* search for connect PHY device */ + for (i = startnode; i < PHY_MAX_ADDR; i++) { + struct phy_device *const tmp_phydev = + priv->mdio_bus->phy_map[i]; + + if (!tmp_phydev) { +#ifdef FEC_DEBUG + printk(KERN_INFO "%s no PHY here at" + "mii_bus->phy_map[%d]\n", + __func__, i); +#endif + continue; /* no PHY here... */ + } + phydev = tmp_phydev; +#ifdef FEC_DEBUG + printk(KERN_INFO "%s find PHY here at" + "mii_bus->phy_map[%d]\n", + __func__, i); +#endif + break; /* found it */ + } + + /* now we are supposed to have a proper phydev, to attach to... */ + if (!phydev) { + printk(KERN_INFO "%s: Don't found any phy device at all\n", + dev->name); + return -ENODEV; + } + + priv->link = 0; + priv->speed = 0; + priv->duplex = 0; +#ifdef FEC_DEBUG + printk(KERN_INFO "%s phydev_busid %s\n", __func__, dev_name(&phydev->dev)); +#endif + phydev = phy_connect(dev, dev_name(&phydev->dev), + &fec_adjust_link, 0, PHY_INTERFACE_MODE_MII); + if (IS_ERR(phydev)) { + printk(KERN_ERR " %s phy_connect failed\n", __func__); + return PTR_ERR(phydev); + } + + printk(KERN_INFO "attached phy %i to driver %s\n", + phydev->addr, phydev->drv->name); + priv->phydev = phydev; + return 0; +} + +static int fec_mdio_register(struct net_device *dev, + int slot) +{ + int err = 0; + struct fec_priv *fp = netdev_priv(dev); + + fp->mdio_bus = mdiobus_alloc(); + if (!fp->mdio_bus) { + printk(KERN_ERR "ethernet mdiobus_alloc fail\n"); + return -ENOMEM; + } + + if (slot == 0) { + fp->mdio_bus->name = "Coldfire FEC MII 0 Bus"; + strcpy(fp->mdio_bus->id, "0"); + } else if (slot == 1) { + fp->mdio_bus->name = "Coldfire FEC MII 1 Bus"; + strcpy(fp->mdio_bus->id, "1"); + } else { + printk(KERN_ERR "Now coldfire can not" + "support more than 2 mii bus\n"); + } + + fp->mdio_bus->read = &coldfire_fec_mdio_read; + fp->mdio_bus->write = &coldfire_fec_mdio_write; + fp->mdio_bus->priv = dev; + err = mdiobus_register(fp->mdio_bus); + if (err) { + mdiobus_free(fp->mdio_bus); + printk(KERN_ERR "%s: ethernet mdiobus_register fail %d\n", + dev->name, err); + return -EIO; + } + + printk(KERN_INFO "mdiobus_register %s ok\n", + fp->mdio_bus->name); + return err; +} + +static const struct net_device_ops fec_netdev_ops = { + .ndo_open = fec_open, + .ndo_stop = fec_close, + .ndo_start_xmit = fec_tx, + .ndo_set_multicast_list = fec_set_multicast_list, + .ndo_tx_timeout = fec_tx_timeout, + .ndo_get_stats = fec_get_stat, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = fec_set_mac_address, +}; + +/* + * Initialize a FEC device + */ +int fec_enet_init(struct net_device *dev, int slot) +{ + struct fec_priv *fp = netdev_priv(dev); + int i; + + fp->index = slot; + fp->netdev = dev; + fec_dev[slot] = dev; + + if (slot == 0) { + /* disable fec0 */ + FEC_ECR(FEC_BASE_ADDR_FEC0) = FEC_ECR_DISABLE; + + /* setup the interrupt handler */ + dev->irq = 64 + ISC_FEC0; + + if (request_irq(dev->irq, fec_interrupt_handler, + IRQF_DISABLED, "ColdFire FEC 0", dev)) { + dev->irq = 0; + printk(KERN_ERR "Cannot allocate FEC0 IRQ\n"); + } else { + /* interrupt priority and level */ + MCF_ICR(ISC_FEC0) = ILP_FEC0; + } + + /* fec base address */ + dev->base_addr = FEC_BASE_ADDR_FEC0; + + /* requestor numbers */ + fp->fecpriv_rx_requestor = DMA_FEC0_RX; + fp->fecpriv_tx_requestor = DMA_FEC0_TX; + + /* fec0 handlers */ + fp->fecpriv_interrupt_fec_rx_handler = + fec_interrupt_fec_rx_handler_fec0; + fp->fecpriv_interrupt_fec_tx_handler = + fec_interrupt_fec_tx_handler_fec0; + + /* tx descriptors */ + fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC0; + + /* rx descriptors */ + fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC0; + + /* mac addr */ + fec_mac_addr_fec0[0] = + (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF; + fec_mac_addr_fec0[1] = + (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF; + fec_mac_addr_fec0[2] = + (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 8) & 0xFF; + fec_mac_addr_fec0[3] = + (FEC_PALR(FEC_BASE_ADDR_FEC0)) & 0xFF; + fec_mac_addr_fec0[4] = + (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF; + fec_mac_addr_fec0[5] = + (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF; + + fp->fecpriv_mac_addr = fec_mac_addr_fec0; + } else { + /* disable fec1 */ + FEC_ECR(FEC_BASE_ADDR_FEC1) = FEC_ECR_DISABLE; +#ifdef FEC_2 + /* setup the interrupt handler */ + dev->irq = 64 + ISC_FEC1; + + if (request_irq(dev->irq, fec_interrupt_handler, + IRQF_DISABLED, "ColdFire FEC 1", dev)) { + dev->irq = 0; + printk(KERN_ERR "Cannot allocate FEC1 IRQ\n"); + } else { + /* interrupt priority and level */ + MCF_ICR(ISC_FEC1) = ILP_FEC1; + } + + /* fec base address */ + dev->base_addr = FEC_BASE_ADDR_FEC1; + + /* requestor numbers */ + fp->fecpriv_rx_requestor = DMA_FEC1_RX; + fp->fecpriv_tx_requestor = DMA_FEC1_TX; + + /* fec1 handlers */ + fp->fecpriv_interrupt_fec_rx_handler = + fec_interrupt_fec_rx_handler_fec1; + fp->fecpriv_interrupt_fec_tx_handler = + fec_interrupt_fec_tx_handler_fec1; + + /* tx descriptors */ + fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC1; + + /* rx descriptors */ + fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC1; + + /* mac addr + if (uboot_enet1[0] || uboot_enet1[1] || uboot_enet1[2] || + uboot_enet1[3] || uboot_enet1[4] || uboot_enet1[5]) { + use uboot enet 1 addr + memcpy(fec_mac_addr_fec1, uboot_enet1, 6); + }*/ + fec_mac_addr_fec1[0] = + (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF; + fec_mac_addr_fec1[1] = + (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF; + fec_mac_addr_fec1[2] = + (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 8) & 0xFF; + fec_mac_addr_fec1[3] = + (FEC_PALR(FEC_BASE_ADDR_FEC1)) & 0xFF; + fec_mac_addr_fec1[4] = + (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF; + fec_mac_addr_fec1[5] = + (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF; + + fp->fecpriv_mac_addr = fec_mac_addr_fec1; +#endif + } + + /* clear MIB */ + memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN); + + /* clear the statistics structure */ + memset((void *) &(fp->fecpriv_stat), 0, + sizeof(struct net_device_stats)); + + /* grab the FEC initiators */ + dma_set_initiator(fp->fecpriv_tx_requestor); + fp->fecpriv_initiator_tx = dma_get_initiator(fp->fecpriv_tx_requestor); + dma_set_initiator(fp->fecpriv_rx_requestor); + fp->fecpriv_initiator_rx = dma_get_initiator(fp->fecpriv_rx_requestor); + + /* reset the DMA channels */ + fp->fecpriv_fec_rx_channel = -1; + fp->fecpriv_fec_tx_channel = -1; + + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) + fp->askb_rx[i] = NULL; + + /* initialize the pointers to the socket buffers */ + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) + fp->fecpriv_txbuf[i] = NULL; + + ether_setup(dev); + + dev->netdev_ops = &fec_netdev_ops; + dev->watchdog_timeo = FEC_TX_TIMEOUT * HZ; + + memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN); + + spin_lock_init(&fp->fecpriv_lock); + + /* Initialize FEC/I2C/IRQ Pin Assignment Register*/ + FEC_GPIO_PAR_FECI2CIRQ &= 0xF; + FEC_GPIO_PAR_FECI2CIRQ |= FEC_FECI2CIRQ; + + return 0; +} + +/* + * Module Initialization + */ +int __init fec_init(void) +{ + struct net_device *dev; + int i; + int err; + struct fec_priv *fep; + DECLARE_MAC_BUF(mac); + + printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION); + + for (i = 0; i < FEC_MAX_PORTS; i++) { + dev = alloc_etherdev(sizeof(struct fec_priv)); + if (!dev) + return -ENOMEM; + err = fec_enet_init(dev, i); + if (err) { + free_netdev(dev); + continue; + } + + fep = netdev_priv(dev); + FEC_MSCR(dev->base_addr) = FEC_MII_SPEED; +#ifdef CONFIG_FEC_548x_SHARED_PHY + if (i == 0) + err = fec_mdio_register(dev, i); + else { + struct fec_priv *priv0 = netdev_priv(fec_dev[0]); + fep->mdio_bus = priv0->mdio_bus; + printk(KERN_INFO "FEC%d SHARED the %s ok\n", + i, fep->mdio_bus->name); + } +#else + err = fec_mdio_register(dev, i); +#endif + if (err) { + printk(KERN_ERR "%s: ethernet fec_mdio_register\n", + dev->name); + free_netdev(dev); + return -ENOMEM; + } + + if (register_netdev(dev) != 0) { + free_netdev(dev); + return -EIO; + } + + printk(KERN_INFO "%s: ethernet %s\n", + dev->name, print_mac(mac, dev->dev_addr)); + } + return 0; +} + +/* + * Stop a device + */ +void fec_stop(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + + dma_remove_initiator(fp->fecpriv_initiator_tx); + dma_remove_initiator(fp->fecpriv_initiator_rx); + + if (dev->irq) + free_irq(dev->irq, dev); +} + +/************************************************************************ +* NAME: fec_open +* +* DESCRIPTION: This function performs the initialization of +* of FEC and corresponding KS8721 transiver +* +* RETURNS: If no error occurs, this function returns zero. +*************************************************************************/ +int fec_open(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + int fduplex; + int i; + int channel; + int error_code = -EBUSY; + + fp->link = 0; + fp->duplex = 0; + fp->speed = 0; + coldfire_fec_init_phy(dev); + phy_start(fp->phydev); + + /* Receive the DMA channels */ + channel = dma_set_channel_fec(fp->fecpriv_rx_requestor); + + if (channel == -1) { + printk(KERN_ERR "Dma channel cannot be reserved\n"); + goto ERRORS; + } + + fp->fecpriv_fec_rx_channel = channel; + + dma_connect(channel, (int) fp->fecpriv_interrupt_fec_rx_handler); + + channel = dma_set_channel_fec(fp->fecpriv_tx_requestor); + + if (channel == -1) { + printk(KERN_ERR "Dma channel cannot be reserved\n"); + goto ERRORS; + } + + fp->fecpriv_fec_tx_channel = channel; + + dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler); + + /* init tasklet for controller reinitialization */ + tasklet_init(&fp->fecpriv_tasklet_reinit, + fec_interrupt_fec_reinit, (unsigned long) dev); + + /* Reset FIFOs */ + FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL; + FEC_FECFRST(base_addr) &= ~FEC_SW_RST; + + /* Reset and disable FEC */ + FEC_ECR(base_addr) = FEC_ECR_RESET; + + udelay(10); + + /* Clear all events */ + FEC_EIR(base_addr) = FEC_EIR_CLEAR; + + /* Reset FIFO status */ + FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK; + FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK; + + /* Set the default address */ + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | + (fp->fecpriv_mac_addr[1] << 16) | + (fp->fecpriv_mac_addr[2] << 8) | + fp->fecpriv_mac_addr[3]; + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | + (fp->fecpriv_mac_addr[5] << 16) | 0x8808; + + /* Reset the group address descriptor */ + FEC_GALR(base_addr) = 0x00000000; + FEC_GAUR(base_addr) = 0x00000000; + + /* Reset the individual address descriptor */ + FEC_IALR(base_addr) = 0x00000000; + FEC_IAUR(base_addr) = 0x00000000; + + /* Set the receive control register */ + FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII; + + /* Set the receive FIFO control register */ + /*FEC_FECRFCR(base_addr) = + * FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;*/ + FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR + | (FEC_FECRFCR_MSK + /* disable all but ...*/ + & ~FEC_FECRFCR_FAE + /* enable frame accept error*/ + & ~FEC_FECRFCR_RXW + /* enable receive wait condition*/ + /*& ~FEC_FECRFCR_UF*/ + /* enable FIFO underflow*/ + ); + + /* Set the receive FIFO alarm register */ + FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM; + + /* Set the transmit FIFO control register */ + /*FEC_FECTFCR(base_addr) = + FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;*/ + FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR + | (FEC_FECTFCR_MSK + /* disable all but ... */ + & ~FEC_FECTFCR_FAE + /* enable frame accept error */ + /* & ~FEC_FECTFCR_TXW */ + /*enable transmit wait condition*/ + /*& ~FEC_FECTFCR_UF*/ + /*enable FIFO underflow*/ + & ~FEC_FECTFCR_OF); + /* enable FIFO overflow */ + + /* Set the transmit FIFO alarm register */ + FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM; + + /* Set the Tx FIFO watermark */ + FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK; + + /* Enable the transmitter to append the CRC */ + FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC; + + /* Enable the ethernet interrupts */ + /*FEC_EIMR(base_addr) = FEC_EIMR_MASK;*/ + FEC_EIMR(base_addr) = FEC_EIMR_DISABLE + | FEC_EIR_LC + | FEC_EIR_RL + | FEC_EIR_HBERR + | FEC_EIR_XFUN + | FEC_EIR_XFERR + | FEC_EIR_RFERR; + +#if 0 + error_code = init_transceiver(base_addr, &fduplex); + if (error_code != 0) { + printk(KERN_ERR "Initialization of the " + "transceiver is failed\n"); + goto ERRORS; + } +#else + fduplex = 1; +#endif + if (fduplex) + /* Enable the full duplex mode */ + FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC; + else + /* Disable reception of frames while transmitting */ + FEC_RCR(base_addr) |= FEC_RCR_DRT; + + /* Enable MIB */ + FEC_MIBC(base_addr) = FEC_MIBC_ENABLE; + + /* Enable FEC */ + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; + FEC_MSCR(dev->base_addr) = FEC_MII_SPEED; + /* Initialize tx descriptors and start DMA for the transmission */ + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; + + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; + + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; + + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, + MCD_NO_CSUM | MCD_NO_BYTE_SWAP); + + /* Initialize rx descriptors and start DMA for the reception */ + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { + fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA); + if (!fp->askb_rx[i]) { + fp->fecpriv_rxdesc[i].dataPointer = 0; + fp->fecpriv_rxdesc[i].statCtrl = 0; + fp->fecpriv_rxdesc[i].length = 0; + } else { + skb_reserve(fp->askb_rx[i], 16); + fp->askb_rx[i]->dev = dev; + fp->fecpriv_rxdesc[i].dataPointer = + (unsigned int)virt_to_phys(fp->askb_rx[i]->tail); + fp->fecpriv_rxdesc[i].statCtrl = + MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT; + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE; + } + } + + fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP; + fp->fecpriv_current_rx = 0; + + MCD_startDma(fp->fecpriv_fec_rx_channel, (char *) fp->fecpriv_rxdesc, 0, + (unsigned char *) &(FEC_FECRFDR(base_addr)), 0, + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx, + FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT, + MCD_NO_CSUM | MCD_NO_BYTE_SWAP); + + netif_start_queue(dev); + return 0; + +ERRORS: + + /* Remove the channels and return with the error code */ + if (fp->fecpriv_fec_rx_channel != -1) { + dma_disconnect(fp->fecpriv_fec_rx_channel); + dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel); + fp->fecpriv_fec_rx_channel = -1; + } + + if (fp->fecpriv_fec_tx_channel != -1) { + dma_disconnect(fp->fecpriv_fec_tx_channel); + dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel); + fp->fecpriv_fec_tx_channel = -1; + } + + return error_code; +} + +/************************************************************************ +* NAME: fec_close +* +* DESCRIPTION: This function performs the graceful stop of the +* transmission and disables FEC +* +* RETURNS: This function always returns zero. +*************************************************************************/ +int fec_close(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + unsigned long time; + int i; + + netif_stop_queue(dev); + phy_disconnect(fp->phydev); + phy_stop(fp->phydev); + /* Perform the graceful stop */ + FEC_TCR(base_addr) |= FEC_TCR_GTS; + + time = jiffies; + + /* Wait for the graceful stop */ + while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < + (FEC_GR_TIMEOUT * HZ)) + schedule(); + + /* Disable FEC */ + FEC_ECR(base_addr) = FEC_ECR_DISABLE; + + /* Reset the DMA channels */ + spin_lock_irq(&fp->fecpriv_lock); + MCD_killDma(fp->fecpriv_fec_tx_channel); + spin_unlock_irq(&fp->fecpriv_lock); + dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel); + dma_disconnect(fp->fecpriv_fec_tx_channel); + fp->fecpriv_fec_tx_channel = -1; + + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { + if (fp->fecpriv_txbuf[i]) { + kfree(fp->fecpriv_txbuf[i]); + fp->fecpriv_txbuf[i] = NULL; + } + } + + spin_lock_irq(&fp->fecpriv_lock); + MCD_killDma(fp->fecpriv_fec_rx_channel); + spin_unlock_irq(&fp->fecpriv_lock); + + dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel); + dma_disconnect(fp->fecpriv_fec_rx_channel); + fp->fecpriv_fec_rx_channel = -1; + + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { + if (fp->askb_rx[i]) { + kfree_skb(fp->askb_rx[i]); + fp->askb_rx[i] = NULL; + } + } + + return 0; +} + +/************************************************************************ +* +NAME: fec_get_stat +* +* RETURNS: This function returns the statistical information. +*************************************************************************/ +struct net_device_stats *fec_get_stat(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = dev->base_addr; + + /* Receive the statistical information */ + fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr); + fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr); + fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr); + fp->fecpriv_stat.tx_bytes = FECSTAT_RMON_T_OCTETS(base_addr); + + fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr); + fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr); + + fp->fecpriv_stat.rx_length_errors = + FECSTAT_RMON_R_UNDERSIZE(base_addr) + + FECSTAT_RMON_R_OVERSIZE(base_addr) + + FECSTAT_RMON_R_FRAG(base_addr) + + FECSTAT_RMON_R_JAB(base_addr); + fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr); + fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr); + fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr); + + fp->fecpriv_stat.tx_carrier_errors = FECSTAT_IEEE_T_CSERR(base_addr); + fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr); + fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr); + + /* I hope that one frame doesn't have more than one error */ + fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors + + fp->fecpriv_stat.rx_crc_errors + + fp->fecpriv_stat.rx_frame_errors + + fp->fecpriv_stat.rx_over_errors + + fp->fecpriv_stat.rx_dropped; + fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors + + fp->fecpriv_stat.tx_fifo_errors + + fp->fecpriv_stat.tx_window_errors + + fp->fecpriv_stat.tx_aborted_errors + + fp->fecpriv_stat.tx_heartbeat_errors + + fp->fecpriv_stat.tx_dropped; + + return &fp->fecpriv_stat; +} + +/************************************************************************ +* NAME: fec_set_multicast_list +* +* DESCRIPTION: This function sets the frame filtering parameters +*************************************************************************/ +void fec_set_multicast_list(struct net_device *dev) +{ + struct dev_mc_list *dmi; + unsigned int crc, data; + int i, j, k; + unsigned long base_addr = (unsigned long) dev->base_addr; + + if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) { + /* Allow all incoming frames */ + FEC_GALR(base_addr) = 0xFFFFFFFF; + FEC_GAUR(base_addr) = 0xFFFFFFFF; + return; + } + + /* Reset the group address register */ + FEC_GALR(base_addr) = 0x00000000; + FEC_GAUR(base_addr) = 0x00000000; + + /* Process all addresses */ + for (i = 0, dmi = dev->mc_list; i < dev->mc_count; + i++, dmi = dmi->next) { + /* Processing must be only for the group addresses */ + if (!(dmi->dmi_addr[0] & 1)) + continue; + + /* Calculate crc value for the current address */ + crc = 0xFFFFFFFF; + for (j = 0; j < dmi->dmi_addrlen; j++) { + for (k = 0, data = dmi->dmi_addr[j]; + k < 8; k++, data >>= 1) { + if ((crc ^ data) & 1) + crc = (crc >> 1) ^ FEC_CRCPOL; + else + crc >>= 1; + } + } + + /* Add this value */ + crc >>= 26; + crc &= 0x3F; + if (crc > 31) + FEC_GAUR(base_addr) |= 0x1 << (crc - 32); + else + FEC_GALR(base_addr) |= 0x1 << crc; + } +} + +/************************************************************************ +* NAME: fec_set_mac_address +* +* DESCRIPTION: This function sets the MAC address +*************************************************************************/ +int fec_set_mac_address(struct net_device *dev, void *p) +{ + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + struct sockaddr *addr = p; + + if (netif_running(dev)) + return -EBUSY; + + /* Copy a new address to the device structure */ + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + /* Copy a new address to the private structure */ + memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6); + + /* Set the address to the registers */ + FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | + (fp->fecpriv_mac_addr[1] << 16) | + (fp->fecpriv_mac_addr[2] << 8) | + fp->fecpriv_mac_addr[3]; + FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | + (fp->fecpriv_mac_addr[5] << 16) | + 0x8808; + + return 0; +} + +/************************************************************************ +* NAME: fec_tx +* +* DESCRIPTION: This function starts transmission of the frame using DMA +* +* RETURNS: This function always returns zero. +*************************************************************************/ +int fec_tx(struct sk_buff *skb, struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + void *data, *data_aligned; + int offset; + + data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC); + + if (!data) { + fp->fecpriv_stat.tx_dropped++; + dev_kfree_skb(skb); + return 0; + } + + offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) - + (unsigned long)virt_to_phys(data); + data_aligned = (void *)((unsigned long)data + offset); + memcpy(data_aligned, skb->data, skb->len); + + /* flush data cache before initializing + * the descriptor and starting DMA */ + + spin_lock_irq(&fp->fecpriv_lock); + + /* Initialize the descriptor */ + fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data; + fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer + = (unsigned int) virt_to_phys(data_aligned); + fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len; + fp->fecpriv_txdesc[fp->fecpriv_next_tx].statCtrl + |= (MCD_FEC_END_FRAME | MCD_FEC_BUF_READY); + fp->fecpriv_next_tx = (fp->fecpriv_next_tx + 1) & FEC_TX_INDEX_MASK; + + if (fp->fecpriv_txbuf[fp->fecpriv_current_tx] + && fp->fecpriv_current_tx == fp->fecpriv_next_tx) + netif_stop_queue(dev); + + spin_unlock_irq(&fp->fecpriv_lock); + + /* Tell the DMA to continue the transmission */ + MCD_continDma(fp->fecpriv_fec_tx_channel); + + dev_kfree_skb(skb); + + dev->trans_start = jiffies; + + return 0; +} + +/************************************************************************ +* NAME: fec_tx_timeout +* +* DESCRIPTION: If the interrupt processing of received frames was lost +* and DMA stopped the reception, this function clears +* the transmission descriptors and starts DMA +* +*************************************************************************/ +void fec_tx_timeout(struct net_device *dev) +{ + int i; + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + + spin_lock_irq(&fp->fecpriv_lock); + MCD_killDma(fp->fecpriv_fec_tx_channel); + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { + if (fp->fecpriv_txbuf[i]) { + kfree(fp->fecpriv_txbuf[i]); + fp->fecpriv_txbuf[i] = NULL; + } + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; + } + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; + + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; + + /* Reset FIFOs */ + FEC_FECFRST(base_addr) |= FEC_SW_RST; + FEC_FECFRST(base_addr) &= ~FEC_SW_RST; + + /* Reset and disable FEC */ + /* FEC_ECR(base_addr) = FEC_ECR_RESET; */ + + /* Enable FEC */ + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; + + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, + MCD_NO_CSUM | MCD_NO_BYTE_SWAP); + + spin_unlock_irq(&fp->fecpriv_lock); + + netif_wake_queue(dev); + +} + +/************************************************************************ +* NAME: fec_interrupt_tx_handler +* +* DESCRIPTION: This function is called when the data +* transmission from the buffer to the FEC is completed. +* +*************************************************************************/ +void fec_interrupt_fec_tx_handler(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + + /* Release the socket buffer */ + if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]) { + kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]); + fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL; + } + fp->fecpriv_current_tx = + (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK; + + if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) { + for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; + fp->fecpriv_current_tx = + (fp->fecpriv_current_tx + 1) + & FEC_TX_INDEX_MASK) { + if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]) { + kfree(fp->fecpriv_txbuf[ + fp->fecpriv_current_tx]); + fp->fecpriv_txbuf[fp->fecpriv_current_tx] + = NULL; + } + } + } + + if (netif_queue_stopped(dev)) + netif_wake_queue(dev); +} + +/************************************************************************ +* NAME: fec_interrupt_rx_handler +* +* DESCRIPTION: This function is called when the data +* reception from the FEC to the reception buffer is completed. +* +*************************************************************************/ +void fec_interrupt_fec_rx_handler(struct net_device *dev) +{ + struct fec_priv *fp = netdev_priv(dev); + struct sk_buff *skb; + int i; + + fp->fecpriv_rxflag = 1; + /* Some buffers can be missed */ + if (!(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl + & MCD_FEC_END_FRAME)) { + /* Find a valid index */ + for (i = 0; ((i < FEC_RX_BUF_NUMBER) && + !(fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].statCtrl + & MCD_FEC_END_FRAME)); i++, + (fp->fecpriv_current_rx = + (fp->fecpriv_current_rx + 1) + & FEC_RX_INDEX_MASK)) + ; + + if (i == FEC_RX_BUF_NUMBER) { + /* There are no data to process */ + /* Tell the DMA to continue the reception */ + MCD_continDma(fp->fecpriv_fec_rx_channel); + + fp->fecpriv_rxflag = 0; + + return; + } + } + + for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl + & MCD_FEC_END_FRAME; + fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) + & FEC_RX_INDEX_MASK) { + if ((fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length + <= FEC_MAXBUF_SIZE) && + (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length + > 4)) { + /* --tym-- */ + skb = fp->askb_rx[fp->fecpriv_current_rx]; + if (!skb) + fp->fecpriv_stat.rx_dropped++; + else { + /* + * flush data cache before initializing + * the descriptor and starting DMA + */ + skb_put(skb, + (fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].length - 4)); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + } + fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= + ~MCD_FEC_END_FRAME; + /* allocate new skbuff */ + fp->askb_rx[fp->fecpriv_current_rx] = + alloc_skb(FEC_MAXBUF_SIZE + 16, + /*GFP_ATOMIC |*/ GFP_DMA); + if (!fp->askb_rx[fp->fecpriv_current_rx]) { + fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].dataPointer + = 0; + fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].length = 0; + fp->fecpriv_stat.rx_dropped++; + } else { + skb_reserve( + fp->askb_rx[fp->fecpriv_current_rx], 16); + fp->askb_rx[fp->fecpriv_current_rx]->dev = dev; + + /* + * flush data cache before initializing + * the descriptor and starting DMA + */ + + fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].dataPointer = + (unsigned int) virt_to_phys( + fp->askb_rx[ + fp->fecpriv_current_rx]->tail); + fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].length = + FEC_MAXBUF_SIZE; + fp->fecpriv_rxdesc[ + fp->fecpriv_current_rx].statCtrl |= + MCD_FEC_BUF_READY; + + /* + * flush data cache before initializing + * the descriptor and starting DMA + */ + } + } + + } + + /* Tell the DMA to continue the reception */ + MCD_continDma(fp->fecpriv_fec_rx_channel); + + fp->fecpriv_rxflag = 0; +} + +/************************************************************************ +* NAME: fec_interrupt_handler +* +* DESCRIPTION: This function is called when some special errors occur +* +*************************************************************************/ +irqreturn_t fec_interrupt_handler(int irq, void *dev_id) +{ + + struct net_device *dev = (struct net_device *)dev_id; + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + unsigned long events; + + /* Read and clear the events */ + events = FEC_EIR(base_addr) & FEC_EIMR(base_addr); + + if (events & FEC_EIR_HBERR) { + fp->fecpriv_stat.tx_heartbeat_errors++; + FEC_EIR(base_addr) = FEC_EIR_HBERR; + } + + /* receive/transmit FIFO error */ + if (((events & FEC_EIR_RFERR) != 0) + || ((events & FEC_EIR_XFERR) != 0)) { + /* kill DMA receive channel */ + MCD_killDma(fp->fecpriv_fec_rx_channel); + + /* kill running transmission by DMA */ + MCD_killDma(fp->fecpriv_fec_tx_channel); + + /* Reset FIFOs */ + FEC_FECFRST(base_addr) |= FEC_SW_RST; + FEC_FECFRST(base_addr) &= ~FEC_SW_RST; + + /* reset receive FIFO status register */ + FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE | + FEC_FECRFSR_RXW | + FEC_FECRFSR_UF; + + /* reset transmit FIFO status register */ + FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE | + FEC_FECTFSR_TXW | + FEC_FECTFSR_UF | + FEC_FECTFSR_OF; + + /* reset RFERR and XFERR event */ + FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR; + + /* stop queue */ + netif_stop_queue(dev); + + /* execute reinitialization as tasklet */ + tasklet_schedule(&fp->fecpriv_tasklet_reinit); + + fp->fecpriv_stat.rx_dropped++; + } + + /* transmit FIFO underrun */ + if ((events & FEC_EIR_XFUN) != 0) { + /* reset XFUN event */ + FEC_EIR(base_addr) = FEC_EIR_XFUN; + fp->fecpriv_stat.tx_aborted_errors++; + } + + /* late collision */ + if ((events & FEC_EIR_LC) != 0) { + /* reset LC event */ + FEC_EIR(base_addr) = FEC_EIR_LC; + fp->fecpriv_stat.tx_aborted_errors++; + } + + /* collision retry limit */ + if ((events & FEC_EIR_RL) != 0) { + /* reset RL event */ + FEC_EIR(base_addr) = FEC_EIR_RL; + fp->fecpriv_stat.tx_aborted_errors++; + } + return 0; +} + +/************************************************************************ +* NAME: fec_interrupt_reinit +* +* DESCRIPTION: This function is called from interrupt handler +* when controller must be reinitialized. +* +*************************************************************************/ +void fec_interrupt_fec_reinit(unsigned long data) +{ + int i; + struct net_device *dev = (struct net_device *)data; + struct fec_priv *fp = netdev_priv(dev); + unsigned long base_addr = (unsigned long) dev->base_addr; + + /* Initialize reception descriptors and start DMA for the reception */ + for (i = 0; i < FEC_RX_BUF_NUMBER; i++) { + if (!fp->askb_rx[i]) { + fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, + GFP_ATOMIC | GFP_DMA); + if (!fp->askb_rx[i]) { + fp->fecpriv_rxdesc[i].dataPointer = 0; + fp->fecpriv_rxdesc[i].statCtrl = 0; + fp->fecpriv_rxdesc[i].length = 0; + continue; + } + fp->askb_rx[i]->dev = dev; + skb_reserve(fp->askb_rx[i], 16); + } + fp->fecpriv_rxdesc[i].dataPointer = + (unsigned int) virt_to_phys(fp->askb_rx[i]->tail); + fp->fecpriv_rxdesc[i].statCtrl = + MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT; + fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE; + } + + fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP; + fp->fecpriv_current_rx = 0; + + /* restart frame transmission */ + for (i = 0; i < FEC_TX_BUF_NUMBER; i++) { + if (fp->fecpriv_txbuf[i]) { + kfree(fp->fecpriv_txbuf[i]); + fp->fecpriv_txbuf[i] = NULL; + fp->fecpriv_stat.tx_dropped++; + } + fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT; + } + fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP; + fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0; + + /* flush entire data cache before restarting the DMA */ + + /* restart DMA from beginning */ + MCD_startDma(fp->fecpriv_fec_rx_channel, + (char *) fp->fecpriv_rxdesc, 0, + (unsigned char *) &(FEC_FECRFDR(base_addr)), 0, + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx, + FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT, + MCD_NO_CSUM | MCD_NO_BYTE_SWAP); + + MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0, + (unsigned char *) &(FEC_FECTFDR(base_addr)), 0, + FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx, + FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT, + MCD_NO_CSUM | MCD_NO_BYTE_SWAP); + + /* Enable FEC */ + FEC_ECR(base_addr) |= FEC_ECR_ETHEREN; + + netif_wake_queue(dev); +} + +/************************************************************************ +* NAME: fec_interrupt_tx_handler_fec0 +* +* DESCRIPTION: This is the DMA interrupt handler using for FEC0 +* transmission. +* +*************************************************************************/ +void fec_interrupt_fec_tx_handler_fec0(void) +{ + fec_interrupt_fec_tx_handler(fec_dev[0]); +} + +#ifdef FEC_2 +/************************************************************************ +* NAME: fec_interrupt_tx_handler_fec1 +* +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1 +* transmission. +* +*************************************************************************/ +void fec_interrupt_fec_tx_handler_fec1(void) +{ + fec_interrupt_fec_tx_handler(fec_dev[1]); +} +#endif + +/************************************************************************ +* NAME: fec_interrupt_rx_handler_fec0 +* +* DESCRIPTION: This is the DMA interrupt handler using for the FEC0 +* reception. +* +*************************************************************************/ +void fec_interrupt_fec_rx_handler_fec0(void) +{ + fec_interrupt_fec_rx_handler(fec_dev[0]); +} + +#ifdef FEC_2 +/************************************************************************ +* NAME: fec_interrupt_rx_handler_fec1 +* +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1 +* reception. +* +*************************************************************************/ +void fec_interrupt_fec_rx_handler_fec1(void) +{ + fec_interrupt_fec_rx_handler(fec_dev[1]); +} + +#endif + +#ifndef MODULE +/************************************************************************ +* NAME: fec_mac_setup0 +* +* DESCRIPTION: This function sets the MAC address of FEC0 from command line +* +*************************************************************************/ +int __init fec_mac_setup0(char *s) +{ + if (!s || !*s) + return 1; + + if (fec_str_to_mac(s, fec_mac_addr_fec0)) + printk(KERN_ERR "The MAC address of FEC0 " + "cannot be set from command line"); + return 1; +} + +#ifdef FEC_2 + +/************************************************************************ +* NAME: fec_mac_setup1 +* +* DESCRIPTION: This function sets the MAC address of FEC1 from command line +* +*************************************************************************/ +int __init fec_mac_setup1(char *s) +{ + if (!s || !*s) + return 1; + + if (fec_str_to_mac(s, fec_mac_addr_fec1)) + printk(KERN_ERR "The MAC address of FEC1 " + "cannot be set from command line\n"); + return 1; +} +#endif + +/************************************************************************ +* NAME: fec_str_to_mac +* +* DESCRIPTION: This function interprets the character string into MAC addr +* +*************************************************************************/ +int fec_str_to_mac(char *str_mac, unsigned char* addr) +{ + unsigned long val; + char c; + unsigned long octet[6], *octetptr = octet; + int i; + +again: + val = 0; + while ((c = *str_mac) != '\0') { + if ((c >= '0') && (c <= '9')) { + val = (val * 16) + (c - '0'); + str_mac++; + continue; + } else if (((c >= 'a') && (c <= 'f')) + || ((c >= 'A') && (c <= 'F'))) { + val = (val << 4) + + (c + 10 - + (((c >= 'a') && (c <= 'f')) ? 'a' : 'A')); + str_mac++; + continue; + } + break; + } + if (*str_mac == ':') { + *octetptr++ = val, str_mac++; + if (octetptr >= octet + 6) + return 1; + goto again; + } + + /* Check for trailing characters */ + if (*str_mac && !(*str_mac == ' ')) + return 1; + + *octetptr++ = val; + + if ((octetptr - octet) == 6) { + for (i = 0; i <= 6; i++) + addr[i] = octet[i]; + } else + return 1; + + return 0; +} +#endif + diff --git a/drivers/net/fec_dma.h b/drivers/net/fec_dma.h new file mode 100755 index 000000000000..4098ee5ad4c1 --- /dev/null +++ b/drivers/net/fec_dma.h @@ -0,0 +1,246 @@ +#ifndef FEC_DMA_H +#define FEC_DMA_H + +#define FEC_BASE_ADDR_FEC0 ((unsigned int)MCF_MBAR + 0x9000) +#define FEC_BASE_ADDR_FEC1 ((unsigned int)MCF_MBAR + 0x9800) + +/* +#define FEC_INTC_IMRH_INT_MASK38 (0x00000040) +#define FEC_INTC_IMRH_INT_MASK39 (0x00000080) +#define FEC_INTC_ICR_FEC0 (0x30) +#define FEC_INTC_ICR_FEC1 (0x31) +*/ +#define FEC_FECI2CIRQ (0xFFC0) +#define FEC_GPIO_PAR_FECI2CIRQ \ + (*(volatile unsigned short *)((unsigned int)MCF_MBAR + 0xA44)) +/* +#define FEC_INTC_ICRn(x) \ +(*(volatile unsigned char *)(void*) +((unsigned int) MCF_MBAR + 0x000740+((x)*0x001))) +#define FEC_INTC_IMRH \ + *(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708) +*/ +#define FEC_ECR_DISABLE (0x00000000) + +#define FEC_ECR(x) \ + (*(volatile unsigned int *)(x + 0x024)) +#define FEC_EIR(x) \ + (*(volatile unsigned int *)(x + 0x004)) +#define FEC_PALR(x) \ + (*(volatile unsigned int *)(x + 0x0E4)) +#define FEC_PAUR(x) \ + (*(volatile unsigned int *)(x + 0x0E8)) +#define FEC_IALR(x) \ + (*(volatile unsigned int *)(x + 0x11C)) +#define FEC_IAUR(x) \ + (*(volatile unsigned int *)(x + 0x118)) +#define FEC_GALR(x) \ + (*(volatile unsigned int *)(x + 0x124)) +#define FEC_GAUR(x) \ + (*(volatile unsigned int *)(x + 0x120)) +#define FEC_RCR(x) \ + (*(volatile unsigned int *)(x + 0x084)) +#define FEC_FECRFCR(x) \ + (*(volatile unsigned int *)(x + 0x18C)) +#define FEC_FECRFAR(x) \ + (*(volatile unsigned int *)(x + 0x198)) +#define FEC_FECTFCR(x) \ + (*(volatile unsigned int *)(x + 0x1AC)) +#define FEC_FECTFAR(x) \ + (*(volatile unsigned int *)(x + 0x1B8)) +#define FEC_FECTFWR(x) \ + (*(volatile unsigned int *)(x + 0x144)) +#define FEC_CTCWR(x) \ + (*(volatile unsigned int *)(x + 0x1C8)) +#define FEC_EIMR(x) \ + (*(volatile unsigned int *)(x + 0x008)) +#define FEC_TCR(x) \ + (*(volatile unsigned int *)(x + 0x0C4)) +#define FEC_MIBC(x) \ + (*(volatile unsigned int *)(x + 0x064)) +#define FEC_MSCR(x) \ + (*(volatile unsigned int *)(x + 0x044)) +#define FEC_FECTFDR(x) \ + (*(volatile unsigned int *)(x + 0x1A4)) +#define FEC_FECRFDR(x) \ + (*(volatile unsigned int *)(x + 0x184)) +#define FEC_FECTFSR(x) \ + (*(volatile unsigned int *)(x + 0x1A8)) +#define FEC_FECRFSR(x) \ + (*(volatile unsigned int *)(x + 0x188)) +#define FECSTAT_RMON_R_PACKETS(x) \ + (*(volatile unsigned int *)(x + 0x284)) +#define FECSTAT_RMON_T_PACKETS(x) \ + (*(volatile unsigned int *)(x + 0x204)) +#define FECSTAT_RMON_R_OCTETS(x) \ + (*(volatile unsigned int *)(x + 0x2C4)) +#define FECSTAT_RMON_T_OCTETS(x) \ + (*(volatile unsigned int *)(x + 0x244)) +#define FECSTAT_RMON_R_UNDERSIZE(x) \ + (*(volatile unsigned int *)(x + 0x294)) +#define FECSTAT_RMON_R_OVERSIZE(x) \ + (*(volatile unsigned int *)(x + 0x298)) +#define FECSTAT_RMON_R_FRAG(x) \ + (*(volatile unsigned int *)(x + 0x29C)) +#define FECSTAT_RMON_R_JAB(x) \ + (*(volatile unsigned int *)(x + 0x2A0)) +#define FECSTAT_RMON_R_MC_PKT(x) \ + (*(volatile unsigned int *)(x + 0x28C)) +#define FECSTAT_RMON_T_COL(x) \ + (*(volatile unsigned int *)(x + 0x224)) +#define FECSTAT_IEEE_R_ALIGN(x) \ + (*(volatile unsigned int *)(x + 0x2D4)) +#define FECSTAT_IEEE_R_CRC(x) \ + (*(volatile unsigned int *)(x + 0x2D0)) +#define FECSTAT_IEEE_R_MACERR(x) \ + (*(volatile unsigned int *)(x + 0x2D8)) +#define FECSTAT_IEEE_T_CSERR(x) \ + (*(volatile unsigned int *)(x + 0x268)) +#define FECSTAT_IEEE_T_MACERR(x) \ + (*(volatile unsigned int *)(x + 0x264)) +#define FECSTAT_IEEE_T_LCOL(x) \ + (*(volatile unsigned int *)(x + 0x25C)) +#define FECSTAT_IEEE_R_OCTETS_OK(x) \ + (*(volatile unsigned int *)(x + 0x2E0)) +#define FECSTAT_IEEE_T_OCTETS_OK(x) \ + (*(volatile unsigned int *)(x + 0x274)) +#define FECSTAT_IEEE_R_DROP(x) \ + (*(volatile unsigned int *)(x + 0x2C8)) +#define FECSTAT_IEEE_T_DROP(x) \ + (*(volatile unsigned int *)(x + 0x248)) +#define FECSTAT_IEEE_R_FRAME_OK(x) \ + (*(volatile unsigned int *)(x + 0x2CC)) +#define FECSTAT_IEEE_T_FRAME_OK(x) \ + (*(volatile unsigned int *)(x + 0x24C)) +#define FEC_MMFR(x) \ + (*(volatile unsigned int *)(x + 0x040)) +#define FEC_FECFRST(x) \ + (*(volatile unsigned int *)(x + 0x1C4)) + +#define FEC_MAX_FRM_SIZE (1518) +#define FEC_MAXBUF_SIZE (1520) + +/* Register values */ +#define FEC_ECR_RESET (0x00000001) +#define FEC_EIR_CLEAR (0xFFFFFFFF) +#define FEC_EIR_RL (0x00100000) +#define FEC_EIR_HBERR (0x80000000) +#define FEC_EIR_BABR (0x40000000) +/* babbling receive error */ +#define FEC_EIR_BABT (0x20000000) +/* babbling transmit error */ +#define FEC_EIR_TXF (0x08000000) +/* transmit frame interrupt */ +#define FEC_EIR_MII (0x00800000) +/* MII interrupt */ +#define FEC_EIR_LC (0x00200000) +/* late collision */ +#define FEC_EIR_XFUN (0x00080000) +/* transmit FIFO underrun */ +#define FEC_EIR_XFERR (0x00040000) +/* transmit FIFO error */ +#define FEC_EIR_RFERR (0x00020000) +/* receive FIFO error */ +#define FEC_RCR_MAX_FRM_SIZE (FEC_MAX_FRM_SIZE << 16) +#define FEC_RCR_MII (0x00000004) +#define FEC_FECRFCR_FAE (0x00400000) +/* frame accept error */ +#define FEC_FECRFCR_RXW (0x00200000) +/* receive wait condition */ +#define FEC_FECRFCR_UF (0x00100000) +/* receive FIFO underflow */ +#define FEC_FECRFCR_FRM (0x08000000) +#define FEC_FECRFCR_GR (0x7 << 24) + +#define FEC_EIMR_DISABLE (0x00000000) + +#define FEC_FECRFAR_ALARM (0x300) +#define FEC_FECTFCR_FRM (0x08000000) +#define FEC_FECTFCR_GR (0x7 << 24) +#define FEC_FECTFCR_FAE (0x00400000) +/* frame accept error */ +#define FEC_FECTFCR_TXW (0x00040000) +/* transmit wait condition */ +#define FEC_FECTFCR_UF (0x00100000) +/* transmit FIFO underflow */ +#define FEC_FECTFCR_OF (0x00080000) +/* transmit FIFO overflow */ + +#define FEC_FECTFAR_ALARM (0x100) +#define FEC_FECTFWR_XWMRK (0x00000000) + +#define FEC_FECTFSR_MSK (0xC0B00000) +#define FEC_FECTFSR_TXW (0x40000000) +/* transmit wait condition */ +#define FEC_FECTFSR_FAE (0x00800000) +/* frame accept error */ +#define FEC_FECTFSR_UF (0x00200000) +/* transmit FIFO underflow */ +#define FEC_FECTFSR_OF (0x00100000) +/* transmit FIFO overflow */ + +#define FEC_FECRFSR_MSK (0x80F00000) +#define FEC_FECRFSR_FAE (0x00800000) +/* frame accept error */ +#define FEC_FECRFSR_RXW (0x00400000) +/* receive wait condition */ +#define FEC_FECRFSR_UF (0x00200000) +/* receive FIFO underflow */ + +#define FEC_CTCWR_TFCW_CRC (0x03000000) +#define FEC_TCR_FDEN (0x00000004) +#define FEC_TCR_HBC (0x00000002) +#define FEC_RCR_DRT (0x00000002) +#define FEC_EIMR_MASK (FEC_EIR_RL | FEC_EIR_HBERR) +#define FEC_ECR_ETHEREN (0x00000002) +#define FEC_FECTFCR_MSK (0x00FC0000) +#define FEC_FECRFCR_MSK (0x00F80000) +#define FEC_EIR_GRA (0x10000000) +#define FEC_TCR_GTS (0x00000001) +#define FEC_MIBC_ENABLE (0x00000000) +#define FEC_MIB_LEN (228) +#define FEC_PHY_ADDR (0x01) + +#define FEC_RX_DMA_PRI (6) +#define FEC_TX_DMA_PRI (6) + +#define FEC_TX_BUF_NUMBER (8) +#define FEC_RX_BUF_NUMBER (64) + +#define FEC_TX_INDEX_MASK (0x7) +#define FEC_RX_INDEX_MASK (0x3f) + +#define FEC_RX_DESC_FEC0 SYS_SRAM_FEC_START +#define FEC_TX_DESC_FEC0 \ + (FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) + +#define FEC_RX_DESC_FEC1 \ + (SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2) +#define FEC_TX_DESC_FEC1 \ + (FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)) + +#define FEC_EIR_MII (0x00800000) +#define FEC_MMFR_READ (0x60020000) +#define FEC_MMFR_WRITE (0x50020000) + +#define FEC_FLAGS_RX (0x00000001) + +#define FEC_CRCPOL (0xEDB88320) + +#define FEC_MII_TIMEOUT (2) +#define FEC_GR_TIMEOUT (1) +#define FEC_TX_TIMEOUT (1) +#define FEC_RX_TIMEOUT (1) + +#define FEC_SW_RST 0x2000000 +#define FEC_RST_CTL 0x1000000 + +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, + unsigned int *data); +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, + unsigned int data); + +#define FEC_MII_SPEED \ + ((MCF_CLK / 2) / ((2500000 / 2) * 2)) + +#endif /* FEC_DMA_H */ diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 35fda5ac8120..b14739bd76b2 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -56,6 +56,11 @@ config BROADCOM_PHY Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481 and BCM5482 PHYs. +config BROADCOM5222_PHY + tristate "Drivers for Broadcom5222 PHY" + ---help--- + Currently supports the BCM5222 PHYs. + config BCM63XX_PHY tristate "Drivers for Broadcom 63xx SOCs internal PHY" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 13bebab65d02..ea35b9f3b9fa 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_SMSC_PHY) += smsc.o obj-$(CONFIG_VITESSE_PHY) += vitesse.o obj-$(CONFIG_BROADCOM_PHY) += broadcom.o +obj-$(CONFIG_BROADCOM5222_PHY) += broadcom522x.o obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_REALTEK_PHY) += realtek.o diff --git a/drivers/net/phy/broadcom522x.c b/drivers/net/phy/broadcom522x.c new file mode 100755 index 000000000000..f20a519e5d77 --- /dev/null +++ b/drivers/net/phy/broadcom522x.c @@ -0,0 +1,269 @@ +/* + *Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. + * Chenghu Wu + * + * Driver for broadcom PHYs 522x + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include + +/* DP83865 phy identifier values */ +#define BCM5222_PHY_ID 0x00406320 + +/* PHY Register */ +#define BCM5222_TIMEOUT 0x100 + +/* MII Registers */ +#define BCM5222_CTRL 0x00 +#define BCM5222_STATUS 0x01 +#define BCM5222_ID_HIGH 0x02 +#define BCM5222_ID_LOW 0x03 +#define BCM5222_AN_ADV 0x04 +#define BCM5222_AN_LP 0x05 +#define BCM5222_AN_EXP 0x06 +#define BCM5222_AN_NEXTPG 0x07 +#define BCM5222_AN_LP_NPTX 0x08 +#define BCM5222_AUX_CS 0x18 +#define BCM5222_AUX_STATUS 0x19 + +/* CONTROL Bits */ +#define BCM5222_CTRL_RESET 0x8000 +#define BCM5222_CTRL_LOOPBACK 0x4000 +#define BCM5222_CTRL_FORCE 0x2000 +#define BCM5222_CTRL_AUTOEN 0x1000 +#define BCM5222_CTRL_PWRDN 0x0800 +#define BCM5222_CTRL_ISOLATE 0x0400 +#define BCM5222_CTRL_RESTART 0x0200 +#define BCM5222_CTRL_DUPLEX 0x0100 +#define BCM5222_CTRL_COLLEN 0x0080 + +/* STATUS Bits */ +#define BCM5222_STATUS_100T4 0x8000 +#define BCM5222_STATUS_100TXFDX 0x4000 +#define BCM5222_STATUS_100TX 0x2000 +#define BCM5222_STATUS_10FDX 0x1000 +#define BCM5222_STATUS_10 0x0800 +#define BCM5222_STATUS_MF_PREAMBLE 0x0040 +#define BCM5222_STATUS_AN_COMPLETE 0x0020 +#define BCM5222_STATUS_REMOTE_FAULT 0x0010 +#define BCM5222_STATUS_AN_CAPABLE 0x0008 +#define BCM5222_STATUS_LINK 0x0004 +#define BCM5222_STATUS_JABBER 0x0002 +#define BCM5222_STATUS_EXT_CAP 0x0001 + +/* ID Values */ +#define BCM5222_ID_HIGH_VAL 0x0040 +#define BCM5222_ID_LOW_VAL 0x6320 + +/* Advertise Bits */ +#define BCM5222_AN_ADV_NEXTPG 0x8000 +#define BCM5222_AN_ADV_REMOTE_FAULT 0x2000 +#define BCM5222_AN_ADV_PAUSE 0x0400 +#define BCM5222_AN_ADV_100T4 0x0200 +#define BCM5222_AN_ADV_100TXFDX 0x0100 +#define BCM5222_AN_ADV_100TX 0x0080 +#define BCM5222_AN_ADV_10FDX 0x0040 +#define BCM5222_AN_ADV_10 0x0020 +#define BCM5222_AN_ADV_8023 0x0001 +#define BCM5222_AN_ADV_ALL \ + (BCM5222_AN_ADV_100TXFDX | \ + BCM5222_AN_ADV_100TXFDX | \ + BCM5222_AN_ADV_100TX | \ + BCM5222_AN_ADV_10FDX | \ + BCM5222_AN_ADV_10 | \ + BCM5222_AN_ADV_8023) + +/* AUX CTRL/STATUS Bits */ +#define BCM5222_AUX_CS_JABBER_DIS 0x8000 +#define BCM5222_AUX_CS_FORCE_LINK 0x4000 +#define BCM5222_AUX_CS_10M_TX_PWR 0x0100 +#define BCM5222_AUX_CS_HSQ_LSQ_MASK 0x00c0 +#define BCM5222_AUX_CS_EDGE_RATE_MASK 0x0030 +#define BCM5222_AUX_CS_AN_IND 0x0008 +#define BCM5222_AUX_CS_SPEED_FORCE 0x0004 +#define BCM5222_AUX_CS_SPEED 0x0002 +#define BCM5222_AUX_CS_DUPLEX 0x0001 + +/* AUX STATUS Bits */ +#define BCM5222_AUX_STATUS_AN_COMP 0x8000 +#define BCM5222_AUX_STATUS_AN_COMPACK 0x4000 +#define BCM5222_AUX_STATUS_AN_ACKDET 0x2000 +#define BCM5222_AUX_STATUS_AN_ABDET 0x1000 +#define BCM5222_AUX_STATUS_AN_PAUSE 0x0800 +#define BCM5222_AUX_STATUS_AN_HCDMASK 0x0700 +#define BCM5222_AUX_STATUS_AN_PDFAULT 0x0080 +#define BCM5222_AUX_STATUS_LP_RMTFAULT 0x0040 +#define BCM5222_AUX_STATUS_LP_PGRX 0x0020 +#define BCM5222_AUX_STATUS_LP_NEGABLE 0x0010 +#define BCM5222_AUX_STATUS_SPEED 0x0008 +#define BCM5222_AUX_STATUS_LINK 0x0004 +#define BCM5222_AUX_STATUS_AN_EN 0x0002 +#define BCM5222_AUX_STATUS_JABBER 0x0001 + +static int bcm5222_config_intr(struct phy_device *phydev) +{ + int err = 0; + printk(KERN_INFO "%s PHY_INTERRUPT %x\n", + __func__, phydev->interrupts); + + return err; +} + +static int bcm5222_ack_interrupt(struct phy_device *phydev) +{ + return 0; +} + +static int bcm5222_config_init(struct phy_device *phydev) +{ + return bcm5222_ack_interrupt(phydev); +} + +static int bcm5222_config_init_old(struct phy_device *phydev) +{ + int timeout; + int flag = 1; + int ret = phy_read(phydev, BCM5222_AUX_STATUS); + if (ret < 0) { + printk(KERN_INFO "%s MII_BCM5222_ISR %x\n", + __func__, ret); + } + /* + * reset + */ + phy_write(phydev, BCM5222_CTRL, BCM5222_CTRL_RESET); + + /* check that it cleared */ + ret = phy_read(phydev, BCM5222_CTRL); + printk(KERN_INFO "%s BCM5222_CTRL %x\n", + __func__, ret); + /*if reset bit is set, return */ + if (ret & BCM5222_CTRL_RESET) { + printk(KERN_ERR "%s %x = BCM5222_CTRL_RESET(%x)\n", + __func__, ret, BCM5222_CTRL_RESET); + return -ETIME; + } + + /* + * setup auto-negotiation + */ + + /* disable */ + phy_write(phydev, BCM5222_CTRL, 0); + ret = phy_read(phydev, BCM5222_CTRL); + printk(KERN_INFO "%s BCM5222_CTRL %x\n", + __func__, ret); + /* set the auto-negotiation advertisement register */ + phy_write(phydev, BCM5222_AN_ADV, BCM5222_AN_ADV_ALL); + ret = phy_read(phydev, BCM5222_AN_ADV); + printk(KERN_INFO "%s BCM5222_AN_ADV %x, BCM5222_AN_ADV_ALL %x\n", + __func__, ret, BCM5222_AN_ADV_ALL); + /* enable */ + phy_write(phydev, BCM5222_CTRL, BCM5222_CTRL_AUTOEN); + ret = phy_read(phydev, BCM5222_CTRL); + printk(KERN_INFO "%s BCM5222_CTRL %x\n", + __func__, ret); + printk(KERN_INFO "** wait for complete\n"); + + /* read aux status reg */ + ret = phy_read(phydev, BCM5222_AUX_STATUS); + /* Wait for the auto-negotiation completion */ + timeout = BCM5222_TIMEOUT; + while (!(ret & BCM5222_AUX_STATUS_AN_COMP)) { + if (!timeout--) { + flag = 0; + printk(KERN_INFO "BCM5222: TIMEOUT\n"); + break; + } + + mdelay(10); + /* Read PHY status register */ + ret = phy_read(phydev, BCM5222_AUX_STATUS); + } + + ret = phy_read(phydev, BCM5222_AUX_STATUS); + ret = phy_read(phydev, BCM5222_AN_ADV); + return 0; +} + +static int bcm5222_read_status(struct phy_device *phydev) +{ + int ret; + ret = phy_read(phydev, BCM5222_AUX_STATUS); + printk(KERN_INFO "%s ret %x\n", __func__, ret); + + if (ret & BCM5222_AUX_STATUS_LINK) + phydev->link = 1; + else + phydev->link = 0; + + if (ret & BCM5222_AUX_STATUS_SPEED) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + + ret = phy_read(phydev, BCM5222_AUX_CS); + printk(KERN_INFO "%s ret %x\n", __func__, ret); + if (ret & BCM5222_AUX_CS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + return 0; +} + +static int bcm5222_config_aneg(struct phy_device *phydev) +{ + phy_read(phydev, BCM5222_AUX_STATUS); + phy_read(phydev, BCM5222_AN_ADV); + return 0; +} + +static struct phy_driver bcm5222_driver = { + .phy_id = BCM5222_PHY_ID, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5222", + .features = PHY_BASIC_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = bcm5222_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm5222_ack_interrupt, + .config_intr = bcm5222_config_intr, + .driver = {.owner = THIS_MODULE,} +}; + +static int __init bcm5222_init(void) +{ + int ret; + + ret = phy_driver_register(&bcm5222_driver); + if (ret) + goto err1; + + return 0; +err1: + printk(KERN_INFO "register bcm5222 PHY driver fail\n"); + return ret; +} + +static void __exit bcm5222_exit(void) +{ + phy_driver_unregister(&bcm5222_driver); +} + +MODULE_DESCRIPTION("Broadcom PHY driver"); +MODULE_LICENSE("GPL v2"); + +module_init(bcm5222_init); +module_exit(bcm5222_exit); diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 4eb56ed75fbc..3bdb5b6d6d88 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -6,7 +6,7 @@ * * Maintainer: Kumar Gala * - * Copyright 2004 Freescale Semiconductor, Inc + * Copyright 2004-2008 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -18,6 +18,7 @@ #define _FSL_DEVICE_H_ #include +#include /* * Some conventions on how we handle peripherals on Freescale chips @@ -70,6 +71,12 @@ struct fsl_usb2_platform_data { int (*init)(struct platform_device *); void (*exit)(struct platform_device *); + + u32 xcvr_type; /* PORTSCX_PTS_* */ + u32 view; /* ULPI viewport register */ + u32 r_start; /* start of MEM resource */ + u32 r_len; /* length of MEM resource */ + void __iomem *regs; /* ioremap'd register base */ struct clk *clk; unsigned big_endian_mmio:1; @@ -79,6 +86,11 @@ struct fsl_usb2_platform_data { unsigned have_sysif_regs:1; unsigned invert_drvvbus:1; unsigned invert_pwr_fault:1; + unsigned does_otg : 1; /* set IFF it's an OTG port */ + + unsigned power_budget; /* for hcd->power_budget */ + struct fsl_xcvr_ops *xcvr_ops; + int max_ep_nr; /* max # of endpoints */ }; /* Flags in fsl_usb2_mph_platform_data */ @@ -119,4 +131,31 @@ int fsl_deep_sleep(void); static inline int fsl_deep_sleep(void) { return 0; } #endif +struct fsl_ata_platform_data { +#ifdef CONFIG_FSL_PATA_USE_DMA + int udma_mask; /* UDMA modes h/w can handle */ + int fifo_alarm; /* value for fifo_alarm reg */ + int max_sg; /* longest sglist h/w can handle */ +#endif + int (*init)(struct platform_device *pdev); + void (*exit)(void); + int (*get_clk_rate)(void); +}; + +struct coldfire_fec_platform_data { + int hash_table; + unsigned int *fec_hw; + void (*request_intrs)(struct net_device *dev, + irqreturn_t (*)(int, void *), + void *irq_privatedata); + void (*set_mii)(struct net_device *dev); + void (*get_mac)(struct net_device *dev); + void (*enable_phy_intr)(void); + void (*disable_phy_intr)(void); + void (*phy_ack_intr)(void); + void (*localhw_setup)(void); + void (*uncache)(unsigned long addr); + void (*platform_flush_cache)(void); +}; + #endif /* _FSL_DEVICE_H_ */