arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/dma.h>
  28 #include <mach/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285
 286 /*
 287  * omap_mcbsp_get_dma_op_mode just return the current configured
 288  * operating mode for the mcbsp channel
 289  */
 290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 291 {
 292         struct omap_mcbsp *mcbsp;
 293         int dma_op_mode;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         spin_lock_irq(&mcbsp->lock);
 302         dma_op_mode = mcbsp->dma_op_mode;
 303         spin_unlock_irq(&mcbsp->lock);
 304
 305         return dma_op_mode;
 306 }
 307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 308
 309 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 310 {
 311         /*
 312          * Enable wakup behavior, smart idle and all wakeups
 313          * REVISIT: some wakeups may be unnecessary
 314          */
 315         if (cpu_is_omap34xx()) {
 316                 u16 syscon;
 317
 318                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 319                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 320
 321                 spin_lock_irq(&mcbsp->lock);
 322                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 323                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 324                                         CLOCKACTIVITY(0x02));
 325                         OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
 326                                         XRDYEN | RRDYEN);
 327                 } else {
 328                         syscon |= SIDLEMODE(0x01);
 329                 }
 330                 spin_unlock_irq(&mcbsp->lock);
 331
 332                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 333         }
 334 }
 335
 336 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 337 {
 338         /*
 339          * Disable wakup behavior, smart idle and all wakeups
 340          */
 341         if (cpu_is_omap34xx()) {
 342                 u16 syscon;
 343
 344                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 345                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 346                 /*
 347                  * HW bug workaround - If no_idle mode is taken, we need to
 348                  * go to smart_idle before going to always_idle, or the
 349                  * device will not hit retention anymore.
 350                  */
 351                 syscon |= SIDLEMODE(0x02);
 352                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 353
 354                 syscon &= ~(SIDLEMODE(0x03));
 355                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 356
 357                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
 358         }
 359 }
 360 #else
 361 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 362 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 363 #endif
 364
 365 /*
 366  * We can choose between IRQ based or polled IO.
 367  * This needs to be called before omap_mcbsp_request().
 368  */
 369 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 370 {
 371         struct omap_mcbsp *mcbsp;
 372
 373         if (!omap_mcbsp_check_valid_id(id)) {
 374                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 375                 return -ENODEV;
 376         }
 377         mcbsp = id_to_mcbsp_ptr(id);
 378
 379         spin_lock(&mcbsp->lock);
 380
 381         if (!mcbsp->free) {
 382                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 383                         mcbsp->id);
 384                 spin_unlock(&mcbsp->lock);
 385                 return -EINVAL;
 386         }
 387
 388         mcbsp->io_type = io_type;
 389
 390         spin_unlock(&mcbsp->lock);
 391
 392         return 0;
 393 }
 394 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 395
 396 int omap_mcbsp_request(unsigned int id)
 397 {
 398         struct omap_mcbsp *mcbsp;
 399         int err;
 400
 401         if (!omap_mcbsp_check_valid_id(id)) {
 402                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 403                 return -ENODEV;
 404         }
 405         mcbsp = id_to_mcbsp_ptr(id);
 406
 407         spin_lock(&mcbsp->lock);
 408         if (!mcbsp->free) {
 409                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 410                         mcbsp->id);
 411                 spin_unlock(&mcbsp->lock);
 412                 return -EBUSY;
 413         }
 414
 415         mcbsp->free = 0;
 416         spin_unlock(&mcbsp->lock);
 417
 418         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 419                 mcbsp->pdata->ops->request(id);
 420
 421         clk_enable(mcbsp->iclk);
 422         clk_enable(mcbsp->fclk);
 423
 424         /* Do procedure specific to omap34xx arch, if applicable */
 425         omap34xx_mcbsp_request(mcbsp);
 426
 427         /*
 428          * Make sure that transmitter, receiver and sample-rate generator are
 429          * not running before activating IRQs.
 430          */
 431         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 432         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 433
 434         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 435                 /* We need to get IRQs here */
 436                 init_completion(&mcbsp->tx_irq_completion);
 437                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 438                                         0, "McBSP", (void *)mcbsp);
 439                 if (err != 0) {
 440                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 441                                         "for McBSP%d\n", mcbsp->tx_irq,
 442                                         mcbsp->id);
 443                         return err;
 444                 }
 445
 446                 init_completion(&mcbsp->rx_irq_completion);
 447                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 448                                         0, "McBSP", (void *)mcbsp);
 449                 if (err != 0) {
 450                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 451                                         "for McBSP%d\n", mcbsp->rx_irq,
 452                                         mcbsp->id);
 453                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 454                         return err;
 455                 }
 456         }
 457
 458         return 0;
 459 }
 460 EXPORT_SYMBOL(omap_mcbsp_request);
 461
 462 void omap_mcbsp_free(unsigned int id)
 463 {
 464         struct omap_mcbsp *mcbsp;
 465
 466         if (!omap_mcbsp_check_valid_id(id)) {
 467                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 468                 return;
 469         }
 470         mcbsp = id_to_mcbsp_ptr(id);
 471
 472         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 473                 mcbsp->pdata->ops->free(id);
 474
 475         /* Do procedure specific to omap34xx arch, if applicable */
 476         omap34xx_mcbsp_free(mcbsp);
 477
 478         clk_disable(mcbsp->fclk);
 479         clk_disable(mcbsp->iclk);
 480
 481         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 482                 /* Free IRQs */
 483                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 484                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 485         }
 486
 487         spin_lock(&mcbsp->lock);
 488         if (mcbsp->free) {
 489                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 490                         mcbsp->id);
 491                 spin_unlock(&mcbsp->lock);
 492                 return;
 493         }
 494
 495         mcbsp->free = 1;
 496         spin_unlock(&mcbsp->lock);
 497 }
 498 EXPORT_SYMBOL(omap_mcbsp_free);
 499
 500 /*
 501  * Here we start the McBSP, by enabling transmitter, receiver or both.
 502  * If no transmitter or receiver is active prior calling, then sample-rate
 503  * generator and frame sync are started.
 504  */
 505 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 506 {
 507         struct omap_mcbsp *mcbsp;
 508         void __iomem *io_base;
 509         int idle;
 510         u16 w;
 511
 512         if (!omap_mcbsp_check_valid_id(id)) {
 513                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 514                 return;
 515         }
 516         mcbsp = id_to_mcbsp_ptr(id);
 517         io_base = mcbsp->io_base;
 518
 519         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 520         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 521
 522         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 523                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 524
 525         if (idle) {
 526                 /* Start the sample generator */
 527                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 528                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 529         }
 530
 531         /* Enable transmitter and receiver */
 532         w = OMAP_MCBSP_READ(io_base, SPCR2);
 533         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
 534
 535         w = OMAP_MCBSP_READ(io_base, SPCR1);
 536         OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
 537
 538         /*
 539          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 540          * REVISIT: 100us may give enough time for two CLKSRG, however
 541          * due to some unknown PM related, clock gating etc. reason it
 542          * is now at 500us.
 543          */
 544         udelay(500);
 545
 546         if (idle) {
 547                 /* Start frame sync */
 548                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 549                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 550         }
 551
 552         /* Dump McBSP Regs */
 553         omap_mcbsp_dump_reg(id);
 554 }
 555 EXPORT_SYMBOL(omap_mcbsp_start);
 556
 557 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 558 {
 559         struct omap_mcbsp *mcbsp;
 560         void __iomem *io_base;
 561         int idle;
 562         u16 w;
 563
 564         if (!omap_mcbsp_check_valid_id(id)) {
 565                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 566                 return;
 567         }
 568
 569         mcbsp = id_to_mcbsp_ptr(id);
 570         io_base = mcbsp->io_base;
 571
 572         /* Reset transmitter */
 573         w = OMAP_MCBSP_READ(io_base, SPCR2);
 574         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
 575
 576         /* Reset receiver */
 577         w = OMAP_MCBSP_READ(io_base, SPCR1);
 578         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
 579
 580         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 581                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 582
 583         if (idle) {
 584                 /* Reset the sample rate generator */
 585                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 586                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 587         }
 588 }
 589 EXPORT_SYMBOL(omap_mcbsp_stop);
 590
 591 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
 592 {
 593         struct omap_mcbsp *mcbsp;
 594         void __iomem *io_base;
 595         u16 w;
 596
 597         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 598                 return;
 599
 600         if (!omap_mcbsp_check_valid_id(id)) {
 601                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 602                 return;
 603         }
 604
 605         mcbsp = id_to_mcbsp_ptr(id);
 606         io_base = mcbsp->io_base;
 607
 608         w = OMAP_MCBSP_READ(io_base, XCCR);
 609
 610         if (enable)
 611                 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
 612         else
 613                 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
 614 }
 615 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
 616
 617 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
 618 {
 619         struct omap_mcbsp *mcbsp;
 620         void __iomem *io_base;
 621         u16 w;
 622
 623         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 624                 return;
 625
 626         if (!omap_mcbsp_check_valid_id(id)) {
 627                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 628                 return;
 629         }
 630
 631         mcbsp = id_to_mcbsp_ptr(id);
 632         io_base = mcbsp->io_base;
 633
 634         w = OMAP_MCBSP_READ(io_base, RCCR);
 635
 636         if (enable)
 637                 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
 638         else
 639                 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
 640 }
 641 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
 642
 643 /* polled mcbsp i/o operations */
 644 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 645 {
 646         struct omap_mcbsp *mcbsp;
 647         void __iomem *base;
 648
 649         if (!omap_mcbsp_check_valid_id(id)) {
 650                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 651                 return -ENODEV;
 652         }
 653
 654         mcbsp = id_to_mcbsp_ptr(id);
 655         base = mcbsp->io_base;
 656
 657         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 658         /* if frame sync error - clear the error */
 659         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 660                 /* clear error */
 661                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 662                        base + OMAP_MCBSP_REG_SPCR2);
 663                 /* resend */
 664                 return -1;
 665         } else {
 666                 /* wait for transmit confirmation */
 667                 int attemps = 0;
 668                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 669                         if (attemps++ > 1000) {
 670                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 671                                        (~XRST),
 672                                        base + OMAP_MCBSP_REG_SPCR2);
 673                                 udelay(10);
 674                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 675                                        (XRST),
 676                                        base + OMAP_MCBSP_REG_SPCR2);
 677                                 udelay(10);
 678                                 dev_err(mcbsp->dev, "Could not write to"
 679                                         " McBSP%d Register\n", mcbsp->id);
 680                                 return -2;
 681                         }
 682                 }
 683         }
 684
 685         return 0;
 686 }
 687 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 688
 689 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 690 {
 691         struct omap_mcbsp *mcbsp;
 692         void __iomem *base;
 693
 694         if (!omap_mcbsp_check_valid_id(id)) {
 695                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 696                 return -ENODEV;
 697         }
 698         mcbsp = id_to_mcbsp_ptr(id);
 699
 700         base = mcbsp->io_base;
 701         /* if frame sync error - clear the error */
 702         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 703                 /* clear error */
 704                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 705                        base + OMAP_MCBSP_REG_SPCR1);
 706                 /* resend */
 707                 return -1;
 708         } else {
 709                 /* wait for recieve confirmation */
 710                 int attemps = 0;
 711                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 712                         if (attemps++ > 1000) {
 713                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 714                                        (~RRST),
 715                                        base + OMAP_MCBSP_REG_SPCR1);
 716                                 udelay(10);
 717                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 718                                        (RRST),
 719                                        base + OMAP_MCBSP_REG_SPCR1);
 720                                 udelay(10);
 721                                 dev_err(mcbsp->dev, "Could not read from"
 722                                         " McBSP%d Register\n", mcbsp->id);
 723                                 return -2;
 724                         }
 725                 }
 726         }
 727         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 728
 729         return 0;
 730 }
 731 EXPORT_SYMBOL(omap_mcbsp_pollread);
 732
 733 /*
 734  * IRQ based word transmission.
 735  */
 736 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 737 {
 738         struct omap_mcbsp *mcbsp;
 739         void __iomem *io_base;
 740         omap_mcbsp_word_length word_length;
 741
 742         if (!omap_mcbsp_check_valid_id(id)) {
 743                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 744                 return;
 745         }
 746
 747         mcbsp = id_to_mcbsp_ptr(id);
 748         io_base = mcbsp->io_base;
 749         word_length = mcbsp->tx_word_length;
 750
 751         wait_for_completion(&mcbsp->tx_irq_completion);
 752
 753         if (word_length > OMAP_MCBSP_WORD_16)
 754                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 755         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 756 }
 757 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 758
 759 u32 omap_mcbsp_recv_word(unsigned int id)
 760 {
 761         struct omap_mcbsp *mcbsp;
 762         void __iomem *io_base;
 763         u16 word_lsb, word_msb = 0;
 764         omap_mcbsp_word_length word_length;
 765
 766         if (!omap_mcbsp_check_valid_id(id)) {
 767                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 768                 return -ENODEV;
 769         }
 770         mcbsp = id_to_mcbsp_ptr(id);
 771
 772         word_length = mcbsp->rx_word_length;
 773         io_base = mcbsp->io_base;
 774
 775         wait_for_completion(&mcbsp->rx_irq_completion);
 776
 777         if (word_length > OMAP_MCBSP_WORD_16)
 778                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 779         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 780
 781         return (word_lsb | (word_msb << 16));
 782 }
 783 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 784
 785 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 786 {
 787         struct omap_mcbsp *mcbsp;
 788         void __iomem *io_base;
 789         omap_mcbsp_word_length tx_word_length;
 790         omap_mcbsp_word_length rx_word_length;
 791         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 792
 793         if (!omap_mcbsp_check_valid_id(id)) {
 794                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 795                 return -ENODEV;
 796         }
 797         mcbsp = id_to_mcbsp_ptr(id);
 798         io_base = mcbsp->io_base;
 799         tx_word_length = mcbsp->tx_word_length;
 800         rx_word_length = mcbsp->rx_word_length;
 801
 802         if (tx_word_length != rx_word_length)
 803                 return -EINVAL;
 804
 805         /* First we wait for the transmitter to be ready */
 806         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 807         while (!(spcr2 & XRDY)) {
 808                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 809                 if (attempts++ > 1000) {
 810                         /* We must reset the transmitter */
 811                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 812                         udelay(10);
 813                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 814                         udelay(10);
 815                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 816                                 "ready\n", mcbsp->id);
 817                         return -EAGAIN;
 818                 }
 819         }
 820
 821         /* Now we can push the data */
 822         if (tx_word_length > OMAP_MCBSP_WORD_16)
 823                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 824         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 825
 826         /* We wait for the receiver to be ready */
 827         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 828         while (!(spcr1 & RRDY)) {
 829                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 830                 if (attempts++ > 1000) {
 831                         /* We must reset the receiver */
 832                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 833                         udelay(10);
 834                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 835                         udelay(10);
 836                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 837                                 "ready\n", mcbsp->id);
 838                         return -EAGAIN;
 839                 }
 840         }
 841
 842         /* Receiver is ready, let's read the dummy data */
 843         if (rx_word_length > OMAP_MCBSP_WORD_16)
 844                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 845         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 846
 847         return 0;
 848 }
 849 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 850
 851 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 852 {
 853         struct omap_mcbsp *mcbsp;
 854         u32 clock_word = 0;
 855         void __iomem *io_base;
 856         omap_mcbsp_word_length tx_word_length;
 857         omap_mcbsp_word_length rx_word_length;
 858         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 859
 860         if (!omap_mcbsp_check_valid_id(id)) {
 861                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 862                 return -ENODEV;
 863         }
 864
 865         mcbsp = id_to_mcbsp_ptr(id);
 866         io_base = mcbsp->io_base;
 867
 868         tx_word_length = mcbsp->tx_word_length;
 869         rx_word_length = mcbsp->rx_word_length;
 870
 871         if (tx_word_length != rx_word_length)
 872                 return -EINVAL;
 873
 874         /* First we wait for the transmitter to be ready */
 875         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 876         while (!(spcr2 & XRDY)) {
 877                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 878                 if (attempts++ > 1000) {
 879                         /* We must reset the transmitter */
 880                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 881                         udelay(10);
 882                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 883                         udelay(10);
 884                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 885                                 "ready\n", mcbsp->id);
 886                         return -EAGAIN;
 887                 }
 888         }
 889
 890         /* We first need to enable the bus clock */
 891         if (tx_word_length > OMAP_MCBSP_WORD_16)
 892                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 893         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 894
 895         /* We wait for the receiver to be ready */
 896         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 897         while (!(spcr1 & RRDY)) {
 898                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 899                 if (attempts++ > 1000) {
 900                         /* We must reset the receiver */
 901                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 902                         udelay(10);
 903                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 904                         udelay(10);
 905                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 906                                 "ready\n", mcbsp->id);
 907                         return -EAGAIN;
 908                 }
 909         }
 910
 911         /* Receiver is ready, there is something for us */
 912         if (rx_word_length > OMAP_MCBSP_WORD_16)
 913                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 914         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 915
 916         word[0] = (word_lsb | (word_msb << 16));
 917
 918         return 0;
 919 }
 920 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 921
 922 /*
 923  * Simple DMA based buffer rx/tx routines.
 924  * Nothing fancy, just a single buffer tx/rx through DMA.
 925  * The DMA resources are released once the transfer is done.
 926  * For anything fancier, you should use your own customized DMA
 927  * routines and callbacks.
 928  */
 929 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 930                                 unsigned int length)
 931 {
 932         struct omap_mcbsp *mcbsp;
 933         int dma_tx_ch;
 934         int src_port = 0;
 935         int dest_port = 0;
 936         int sync_dev = 0;
 937
 938         if (!omap_mcbsp_check_valid_id(id)) {
 939                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 940                 return -ENODEV;
 941         }
 942         mcbsp = id_to_mcbsp_ptr(id);
 943
 944         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 945                                 omap_mcbsp_tx_dma_callback,
 946                                 mcbsp,
 947                                 &dma_tx_ch)) {
 948                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 949                                 "McBSP%d TX. Trying IRQ based TX\n",
 950                                 mcbsp->id);
 951                 return -EAGAIN;
 952         }
 953         mcbsp->dma_tx_lch = dma_tx_ch;
 954
 955         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 956                 dma_tx_ch);
 957
 958         init_completion(&mcbsp->tx_dma_completion);
 959
 960         if (cpu_class_is_omap1()) {
 961                 src_port = OMAP_DMA_PORT_TIPB;
 962                 dest_port = OMAP_DMA_PORT_EMIFF;
 963         }
 964         if (cpu_class_is_omap2())
 965                 sync_dev = mcbsp->dma_tx_sync;
 966
 967         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 968                                      OMAP_DMA_DATA_TYPE_S16,
 969                                      length >> 1, 1,
 970                                      OMAP_DMA_SYNC_ELEMENT,
 971          sync_dev, 0);
 972
 973         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 974                                  src_port,
 975                                  OMAP_DMA_AMODE_CONSTANT,
 976                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 977                                  0, 0);
 978
 979         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 980                                 dest_port,
 981                                 OMAP_DMA_AMODE_POST_INC,
 982                                 buffer,
 983                                 0, 0);
 984
 985         omap_start_dma(mcbsp->dma_tx_lch);
 986         wait_for_completion(&mcbsp->tx_dma_completion);
 987
 988         return 0;
 989 }
 990 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 991
 992 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 993                                 unsigned int length)
 994 {
 995         struct omap_mcbsp *mcbsp;
 996         int dma_rx_ch;
 997         int src_port = 0;
 998         int dest_port = 0;
 999         int sync_dev = 0;
1000
1001         if (!omap_mcbsp_check_valid_id(id)) {
1002                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1003                 return -ENODEV;
1004         }
1005         mcbsp = id_to_mcbsp_ptr(id);
1006
1007         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1008                                 omap_mcbsp_rx_dma_callback,
1009                                 mcbsp,
1010                                 &dma_rx_ch)) {
1011                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1012                                 "McBSP%d RX. Trying IRQ based RX\n",
1013                                 mcbsp->id);
1014                 return -EAGAIN;
1015         }
1016         mcbsp->dma_rx_lch = dma_rx_ch;
1017
1018         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1019                 dma_rx_ch);
1020
1021         init_completion(&mcbsp->rx_dma_completion);
1022
1023         if (cpu_class_is_omap1()) {
1024                 src_port = OMAP_DMA_PORT_TIPB;
1025                 dest_port = OMAP_DMA_PORT_EMIFF;
1026         }
1027         if (cpu_class_is_omap2())
1028                 sync_dev = mcbsp->dma_rx_sync;
1029
1030         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1031                                         OMAP_DMA_DATA_TYPE_S16,
1032                                         length >> 1, 1,
1033                                         OMAP_DMA_SYNC_ELEMENT,
1034                                         sync_dev, 0);
1035
1036         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1037                                 src_port,
1038                                 OMAP_DMA_AMODE_CONSTANT,
1039                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1040                                 0, 0);
1041
1042         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1043                                         dest_port,
1044                                         OMAP_DMA_AMODE_POST_INC,
1045                                         buffer,
1046                                         0, 0);
1047
1048         omap_start_dma(mcbsp->dma_rx_lch);
1049         wait_for_completion(&mcbsp->rx_dma_completion);
1050
1051         return 0;
1052 }
1053 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1054
1055 /*
1056  * SPI wrapper.
1057  * Since SPI setup is much simpler than the generic McBSP one,
1058  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1059  * Once this is done, you can call omap_mcbsp_start().
1060  */
1061 void omap_mcbsp_set_spi_mode(unsigned int id,
1062                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1063 {
1064         struct omap_mcbsp *mcbsp;
1065         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1066
1067         if (!omap_mcbsp_check_valid_id(id)) {
1068                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1069                 return;
1070         }
1071         mcbsp = id_to_mcbsp_ptr(id);
1072
1073         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1074
1075         /* SPI has only one frame */
1076         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1077         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1078
1079         /* Clock stop mode */
1080         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1081                 mcbsp_cfg.spcr1 |= (1 << 12);
1082         else
1083                 mcbsp_cfg.spcr1 |= (3 << 11);
1084
1085         /* Set clock parities */
1086         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1087                 mcbsp_cfg.pcr0 |= CLKRP;
1088         else
1089                 mcbsp_cfg.pcr0 &= ~CLKRP;
1090
1091         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1092                 mcbsp_cfg.pcr0 &= ~CLKXP;
1093         else
1094                 mcbsp_cfg.pcr0 |= CLKXP;
1095
1096         /* Set SCLKME to 0 and CLKSM to 1 */
1097         mcbsp_cfg.pcr0 &= ~SCLKME;
1098         mcbsp_cfg.srgr2 |= CLKSM;
1099
1100         /* Set FSXP */
1101         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1102                 mcbsp_cfg.pcr0 &= ~FSXP;
1103         else
1104                 mcbsp_cfg.pcr0 |= FSXP;
1105
1106         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1107                 mcbsp_cfg.pcr0 |= CLKXM;
1108                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1109                 mcbsp_cfg.pcr0 |= FSXM;
1110                 mcbsp_cfg.srgr2 &= ~FSGM;
1111                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1112                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1113         } else {
1114                 mcbsp_cfg.pcr0 &= ~CLKXM;
1115                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1116                 mcbsp_cfg.pcr0 &= ~FSXM;
1117                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1118                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1119         }
1120
1121         mcbsp_cfg.xcr2 &= ~XPHASE;
1122         mcbsp_cfg.rcr2 &= ~RPHASE;
1123
1124         omap_mcbsp_config(id, &mcbsp_cfg);
1125 }
1126 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1127
1128 #ifdef CONFIG_ARCH_OMAP34XX
1129 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1130 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1131 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1132 static ssize_t prop##_show(struct device *dev,                          \
1133                         struct device_attribute *attr, char *buf)       \
1134 {                                                                       \
1135         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1136                                                                         \
1137         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1138 }                                                                       \
1139                                                                         \
1140 static ssize_t prop##_store(struct device *dev,                         \
1141                                 struct device_attribute *attr,          \
1142                                 const char *buf, size_t size)           \
1143 {                                                                       \
1144         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1145         unsigned long val;                                              \
1146         int status;                                                     \
1147                                                                         \
1148         status = strict_strtoul(buf, 0, &val);                          \
1149         if (status)                                                     \
1150                 return status;                                          \
1151                                                                         \
1152         if (!valid_threshold(mcbsp, val))                               \
1153                 return -EDOM;                                           \
1154                                                                         \
1155         mcbsp->prop = val;                                              \
1156         return size;                                                    \
1157 }                                                                       \
1158                                                                         \
1159 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1160
1161 THRESHOLD_PROP_BUILDER(max_tx_thres);
1162 THRESHOLD_PROP_BUILDER(max_rx_thres);
1163
1164 static const char *dma_op_modes[] = {
1165         "element", "threshold", "frame",
1166 };
1167
1168 static ssize_t dma_op_mode_show(struct device *dev,
1169                         struct device_attribute *attr, char *buf)
1170 {
1171         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1172         int dma_op_mode, i = 0;
1173         ssize_t len = 0;
1174         const char * const *s;
1175
1176         spin_lock_irq(&mcbsp->lock);
1177         dma_op_mode = mcbsp->dma_op_mode;
1178         spin_unlock_irq(&mcbsp->lock);
1179
1180         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1181                 if (dma_op_mode == i)
1182                         len += sprintf(buf + len, "[%s] ", *s);
1183                 else
1184                         len += sprintf(buf + len, "%s ", *s);
1185         }
1186         len += sprintf(buf + len, "\n");
1187
1188         return len;
1189 }
1190
1191 static ssize_t dma_op_mode_store(struct device *dev,
1192                                 struct device_attribute *attr,
1193                                 const char *buf, size_t size)
1194 {
1195         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1196         const char * const *s;
1197         int i = 0;
1198
1199         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1200                 if (sysfs_streq(buf, *s))
1201                         break;
1202
1203         if (i == ARRAY_SIZE(dma_op_modes))
1204                 return -EINVAL;
1205
1206         spin_lock_irq(&mcbsp->lock);
1207         if (!mcbsp->free) {
1208                 size = -EBUSY;
1209                 goto unlock;
1210         }
1211         mcbsp->dma_op_mode = i;
1212
1213 unlock:
1214         spin_unlock_irq(&mcbsp->lock);
1215
1216         return size;
1217 }
1218
1219 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1220
1221 static const struct attribute *additional_attrs[] = {
1222         &dev_attr_max_tx_thres.attr,
1223         &dev_attr_max_rx_thres.attr,
1224         &dev_attr_dma_op_mode.attr,
1225         NULL,
1226 };
1227
1228 static const struct attribute_group additional_attr_group = {
1229         .attrs = (struct attribute **)additional_attrs,
1230 };
1231
1232 static inline int __devinit omap_additional_add(struct device *dev)
1233 {
1234         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1235 }
1236
1237 static inline void __devexit omap_additional_remove(struct device *dev)
1238 {
1239         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1240 }
1241
1242 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1243 {
1244         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1245         if (cpu_is_omap34xx()) {
1246                 mcbsp->max_tx_thres = max_thres(mcbsp);
1247                 mcbsp->max_rx_thres = max_thres(mcbsp);
1248                 /*
1249                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1250                  * for mcbsp2 instances.
1251                  */
1252                 if (omap_additional_add(mcbsp->dev))
1253                         dev_warn(mcbsp->dev,
1254                                 "Unable to create additional controls\n");
1255         } else {
1256                 mcbsp->max_tx_thres = -EINVAL;
1257                 mcbsp->max_rx_thres = -EINVAL;
1258         }
1259 }
1260
1261 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1262 {
1263         if (cpu_is_omap34xx())
1264                 omap_additional_remove(mcbsp->dev);
1265 }
1266 #else
1267 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1268 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1269 #endif /* CONFIG_ARCH_OMAP34XX */
1270
1271 /*
1272  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1273  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1274  */
1275 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1276 {
1277         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1278         struct omap_mcbsp *mcbsp;
1279         int id = pdev->id - 1;
1280         int ret = 0;
1281
1282         if (!pdata) {
1283                 dev_err(&pdev->dev, "McBSP device initialized without"
1284                                 "platform data\n");
1285                 ret = -EINVAL;
1286                 goto exit;
1287         }
1288
1289         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1290
1291         if (id >= omap_mcbsp_count) {
1292                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1293                 ret = -EINVAL;
1294                 goto exit;
1295         }
1296
1297         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1298         if (!mcbsp) {
1299                 ret = -ENOMEM;
1300                 goto exit;
1301         }
1302
1303         spin_lock_init(&mcbsp->lock);
1304         mcbsp->id = id + 1;
1305         mcbsp->free = 1;
1306         mcbsp->dma_tx_lch = -1;
1307         mcbsp->dma_rx_lch = -1;
1308
1309         mcbsp->phys_base = pdata->phys_base;
1310         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1311         if (!mcbsp->io_base) {
1312                 ret = -ENOMEM;
1313                 goto err_ioremap;
1314         }
1315
1316         /* Default I/O is IRQ based */
1317         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1318         mcbsp->tx_irq = pdata->tx_irq;
1319         mcbsp->rx_irq = pdata->rx_irq;
1320         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1321         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1322
1323         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1324         if (IS_ERR(mcbsp->iclk)) {
1325                 ret = PTR_ERR(mcbsp->iclk);
1326                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1327                 goto err_iclk;
1328         }
1329
1330         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1331         if (IS_ERR(mcbsp->fclk)) {
1332                 ret = PTR_ERR(mcbsp->fclk);
1333                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1334                 goto err_fclk;
1335         }
1336
1337         mcbsp->pdata = pdata;
1338         mcbsp->dev = &pdev->dev;
1339         mcbsp_ptr[id] = mcbsp;
1340         platform_set_drvdata(pdev, mcbsp);
1341
1342         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1343         omap34xx_device_init(mcbsp);
1344
1345         return 0;
1346
1347 err_fclk:
1348         clk_put(mcbsp->iclk);
1349 err_iclk:
1350         iounmap(mcbsp->io_base);
1351 err_ioremap:
1352         kfree(mcbsp);
1353 exit:
1354         return ret;
1355 }
1356
1357 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1358 {
1359         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1360
1361         platform_set_drvdata(pdev, NULL);
1362         if (mcbsp) {
1363
1364                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1365                                 mcbsp->pdata->ops->free)
1366                         mcbsp->pdata->ops->free(mcbsp->id);
1367
1368                 omap34xx_device_exit(mcbsp);
1369
1370                 clk_disable(mcbsp->fclk);
1371                 clk_disable(mcbsp->iclk);
1372                 clk_put(mcbsp->fclk);
1373                 clk_put(mcbsp->iclk);
1374
1375                 iounmap(mcbsp->io_base);
1376
1377                 mcbsp->fclk = NULL;
1378                 mcbsp->iclk = NULL;
1379                 mcbsp->free = 0;
1380                 mcbsp->dev = NULL;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static struct platform_driver omap_mcbsp_driver = {
1387         .probe          = omap_mcbsp_probe,
1388         .remove         = __devexit_p(omap_mcbsp_remove),
1389         .driver         = {
1390                 .name   = "omap-mcbsp",
1391         },
1392 };
1393
1394 int __init omap_mcbsp_init(void)
1395 {
1396         /* Register the McBSP driver */
1397         return platform_driver_register(&omap_mcbsp_driver);
1398 }