arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* enable NPT for AMD64 and X86 with PAE */
  53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  54 static bool npt_enabled = true;
  55 #else
  56 static bool npt_enabled = false;
  57 #endif
  58 static int npt = 1;
  59
  60 module_param(npt, int, S_IRUGO);
  61
  62 static void kvm_reput_irq(struct vcpu_svm *svm);
  63
  64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  65 {
  66         return container_of(vcpu, struct vcpu_svm, vcpu);
  67 }
  68
  69 static unsigned long iopm_base;
  70
  71 struct kvm_ldttss_desc {
  72         u16 limit0;
  73         u16 base0;
  74         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  75         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  76         u32 base3;
  77         u32 zero1;
  78 } __attribute__((packed));
  79
  80 struct svm_cpu_data {
  81         int cpu;
  82
  83         u64 asid_generation;
  84         u32 max_asid;
  85         u32 next_asid;
  86         struct kvm_ldttss_desc *tss_desc;
  87
  88         struct page *save_area;
  89 };
  90
  91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  92 static uint32_t svm_features;
  93
  94 struct svm_init_data {
  95         int cpu;
  96         int r;
  97 };
  98
  99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 100
 101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 102 #define MSRS_RANGE_SIZE 2048
 103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 104
 105 #define MAX_INST_SIZE 15
 106
 107 static inline u32 svm_has(u32 feat)
 108 {
 109         return svm_features & feat;
 110 }
 111
 112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 113 {
 114         int word_index = __ffs(vcpu->arch.irq_summary);
 115         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 116         int irq = word_index * BITS_PER_LONG + bit_index;
 117
 118         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 119         if (!vcpu->arch.irq_pending[word_index])
 120                 clear_bit(word_index, &vcpu->arch.irq_summary);
 121         return irq;
 122 }
 123
 124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 125 {
 126         set_bit(irq, vcpu->arch.irq_pending);
 127         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 128 }
 129
 130 static inline void clgi(void)
 131 {
 132         asm volatile (SVM_CLGI);
 133 }
 134
 135 static inline void stgi(void)
 136 {
 137         asm volatile (SVM_STGI);
 138 }
 139
 140 static inline void invlpga(unsigned long addr, u32 asid)
 141 {
 142         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 143 }
 144
 145 static inline unsigned long kvm_read_cr2(void)
 146 {
 147         unsigned long cr2;
 148
 149         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 150         return cr2;
 151 }
 152
 153 static inline void kvm_write_cr2(unsigned long val)
 154 {
 155         asm volatile ("mov %0, %%cr2" :: "r" (val));
 156 }
 157
 158 static inline unsigned long read_dr6(void)
 159 {
 160         unsigned long dr6;
 161
 162         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 163         return dr6;
 164 }
 165
 166 static inline void write_dr6(unsigned long val)
 167 {
 168         asm volatile ("mov %0, %%dr6" :: "r" (val));
 169 }
 170
 171 static inline unsigned long read_dr7(void)
 172 {
 173         unsigned long dr7;
 174
 175         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 176         return dr7;
 177 }
 178
 179 static inline void write_dr7(unsigned long val)
 180 {
 181         asm volatile ("mov %0, %%dr7" :: "r" (val));
 182 }
 183
 184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 185 {
 186         to_svm(vcpu)->asid_generation--;
 187 }
 188
 189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 190 {
 191         force_new_asid(vcpu);
 192 }
 193
 194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 195 {
 196         if (!npt_enabled && !(efer & EFER_LMA))
 197                 efer &= ~EFER_LME;
 198
 199         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 200         vcpu->arch.shadow_efer = efer;
 201 }
 202
 203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 204                                 bool has_error_code, u32 error_code)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         svm->vmcb->control.event_inj = nr
 209                 | SVM_EVTINJ_VALID
 210                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 211                 | SVM_EVTINJ_TYPE_EXEPT;
 212         svm->vmcb->control.event_inj_err = error_code;
 213 }
 214
 215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 220 }
 221
 222 static int is_external_interrupt(u32 info)
 223 {
 224         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 225         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 226 }
 227
 228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 229 {
 230         struct vcpu_svm *svm = to_svm(vcpu);
 231
 232         if (!svm->next_rip) {
 233                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 238                        __func__,
 239                        svm->vmcb->save.rip,
 240                        svm->next_rip);
 241
 242         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = 1;
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         uint32_t eax, ebx, ecx, edx;
 251
 252         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 253                 printk(KERN_INFO "has_svm: not amd\n");
 254                 return 0;
 255         }
 256
 257         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 258         if (eax < SVM_CPUID_FUNC) {
 259                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 260                 return 0;
 261         }
 262
 263         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 264         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 265                 printk(KERN_DEBUG "has_svm: svm not available\n");
 266                 return 0;
 267         }
 268         return 1;
 269 }
 270
 271 static void svm_hardware_disable(void *garbage)
 272 {
 273         uint64_t efer;
 274
 275         wrmsrl(MSR_VM_HSAVE_PA, 0);
 276         rdmsrl(MSR_EFER, efer);
 277         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 278 }
 279
 280 static void svm_hardware_enable(void *garbage)
 281 {
 282
 283         struct svm_cpu_data *svm_data;
 284         uint64_t efer;
 285         struct desc_ptr gdt_descr;
 286         struct desc_struct *gdt;
 287         int me = raw_smp_processor_id();
 288
 289         if (!has_svm()) {
 290                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 291                 return;
 292         }
 293         svm_data = per_cpu(svm_data, me);
 294
 295         if (!svm_data) {
 296                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 297                        me);
 298                 return;
 299         }
 300
 301         svm_data->asid_generation = 1;
 302         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 303         svm_data->next_asid = svm_data->max_asid + 1;
 304
 305         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 306         gdt = (struct desc_struct *)gdt_descr.address;
 307         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 308
 309         rdmsrl(MSR_EFER, efer);
 310         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 311
 312         wrmsrl(MSR_VM_HSAVE_PA,
 313                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 314 }
 315
 316 static void svm_cpu_uninit(int cpu)
 317 {
 318         struct svm_cpu_data *svm_data
 319                 = per_cpu(svm_data, raw_smp_processor_id());
 320
 321         if (!svm_data)
 322                 return;
 323
 324         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 325         __free_page(svm_data->save_area);
 326         kfree(svm_data);
 327 }
 328
 329 static int svm_cpu_init(int cpu)
 330 {
 331         struct svm_cpu_data *svm_data;
 332         int r;
 333
 334         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 335         if (!svm_data)
 336                 return -ENOMEM;
 337         svm_data->cpu = cpu;
 338         svm_data->save_area = alloc_page(GFP_KERNEL);
 339         r = -ENOMEM;
 340         if (!svm_data->save_area)
 341                 goto err_1;
 342
 343         per_cpu(svm_data, cpu) = svm_data;
 344
 345         return 0;
 346
 347 err_1:
 348         kfree(svm_data);
 349         return r;
 350
 351 }
 352
 353 static void set_msr_interception(u32 *msrpm, unsigned msr,
 354                                  int read, int write)
 355 {
 356         int i;
 357
 358         for (i = 0; i < NUM_MSR_MAPS; i++) {
 359                 if (msr >= msrpm_ranges[i] &&
 360                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 361                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 362                                           msrpm_ranges[i]) * 2;
 363
 364                         u32 *base = msrpm + (msr_offset / 32);
 365                         u32 msr_shift = msr_offset % 32;
 366                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 367                         *base = (*base & ~(0x3 << msr_shift)) |
 368                                 (mask << msr_shift);
 369                         return;
 370                 }
 371         }
 372         BUG();
 373 }
 374
 375 static void svm_vcpu_init_msrpm(u32 *msrpm)
 376 {
 377         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 378
 379 #ifdef CONFIG_X86_64
 380         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 381         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 382         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 383         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 384         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 385         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 386 #endif
 387         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 388         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 389         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 390         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 391 }
 392
 393 static void svm_enable_lbrv(struct vcpu_svm *svm)
 394 {
 395         u32 *msrpm = svm->msrpm;
 396
 397         svm->vmcb->control.lbr_ctl = 1;
 398         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 399         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 400         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 401         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 402 }
 403
 404 static void svm_disable_lbrv(struct vcpu_svm *svm)
 405 {
 406         u32 *msrpm = svm->msrpm;
 407
 408         svm->vmcb->control.lbr_ctl = 0;
 409         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 410         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 411         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 412         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 413 }
 414
 415 static __init int svm_hardware_setup(void)
 416 {
 417         int cpu;
 418         struct page *iopm_pages;
 419         void *iopm_va;
 420         int r;
 421
 422         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 423
 424         if (!iopm_pages)
 425                 return -ENOMEM;
 426
 427         iopm_va = page_address(iopm_pages);
 428         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 429         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 430         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 431
 432         if (boot_cpu_has(X86_FEATURE_NX))
 433                 kvm_enable_efer_bits(EFER_NX);
 434
 435         for_each_online_cpu(cpu) {
 436                 r = svm_cpu_init(cpu);
 437                 if (r)
 438                         goto err;
 439         }
 440
 441         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 442
 443         if (!svm_has(SVM_FEATURE_NPT))
 444                 npt_enabled = false;
 445
 446         if (npt_enabled && !npt) {
 447                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 448                 npt_enabled = false;
 449         }
 450
 451         if (npt_enabled) {
 452                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 453                 kvm_enable_tdp();
 454         }
 455
 456         return 0;
 457
 458 err:
 459         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 460         iopm_base = 0;
 461         return r;
 462 }
 463
 464 static __exit void svm_hardware_unsetup(void)
 465 {
 466         int cpu;
 467
 468         for_each_online_cpu(cpu)
 469                 svm_cpu_uninit(cpu);
 470
 471         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 472         iopm_base = 0;
 473 }
 474
 475 static void init_seg(struct vmcb_seg *seg)
 476 {
 477         seg->selector = 0;
 478         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 479                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 480         seg->limit = 0xffff;
 481         seg->base = 0;
 482 }
 483
 484 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 485 {
 486         seg->selector = 0;
 487         seg->attrib = SVM_SELECTOR_P_MASK | type;
 488         seg->limit = 0xffff;
 489         seg->base = 0;
 490 }
 491
 492 static void init_vmcb(struct vcpu_svm *svm)
 493 {
 494         struct vmcb_control_area *control = &svm->vmcb->control;
 495         struct vmcb_save_area *save = &svm->vmcb->save;
 496
 497         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 498                                         INTERCEPT_CR3_MASK |
 499                                         INTERCEPT_CR4_MASK;
 500
 501         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 502                                         INTERCEPT_CR3_MASK |
 503                                         INTERCEPT_CR4_MASK |
 504                                         INTERCEPT_CR8_MASK;
 505
 506         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 507                                         INTERCEPT_DR1_MASK |
 508                                         INTERCEPT_DR2_MASK |
 509                                         INTERCEPT_DR3_MASK;
 510
 511         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 512                                         INTERCEPT_DR1_MASK |
 513                                         INTERCEPT_DR2_MASK |
 514                                         INTERCEPT_DR3_MASK |
 515                                         INTERCEPT_DR5_MASK |
 516                                         INTERCEPT_DR7_MASK;
 517
 518         control->intercept_exceptions = (1 << PF_VECTOR) |
 519                                         (1 << UD_VECTOR) |
 520                                         (1 << MC_VECTOR);
 521
 522
 523         control->intercept =    (1ULL << INTERCEPT_INTR) |
 524                                 (1ULL << INTERCEPT_NMI) |
 525                                 (1ULL << INTERCEPT_SMI) |
 526                                 (1ULL << INTERCEPT_CPUID) |
 527                                 (1ULL << INTERCEPT_INVD) |
 528                                 (1ULL << INTERCEPT_HLT) |
 529                                 (1ULL << INTERCEPT_INVLPGA) |
 530                                 (1ULL << INTERCEPT_IOIO_PROT) |
 531                                 (1ULL << INTERCEPT_MSR_PROT) |
 532                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 533                                 (1ULL << INTERCEPT_SHUTDOWN) |
 534                                 (1ULL << INTERCEPT_VMRUN) |
 535                                 (1ULL << INTERCEPT_VMMCALL) |
 536                                 (1ULL << INTERCEPT_VMLOAD) |
 537                                 (1ULL << INTERCEPT_VMSAVE) |
 538                                 (1ULL << INTERCEPT_STGI) |
 539                                 (1ULL << INTERCEPT_CLGI) |
 540                                 (1ULL << INTERCEPT_SKINIT) |
 541                                 (1ULL << INTERCEPT_WBINVD) |
 542                                 (1ULL << INTERCEPT_MONITOR) |
 543                                 (1ULL << INTERCEPT_MWAIT);
 544
 545         control->iopm_base_pa = iopm_base;
 546         control->msrpm_base_pa = __pa(svm->msrpm);
 547         control->tsc_offset = 0;
 548         control->int_ctl = V_INTR_MASKING_MASK;
 549
 550         init_seg(&save->es);
 551         init_seg(&save->ss);
 552         init_seg(&save->ds);
 553         init_seg(&save->fs);
 554         init_seg(&save->gs);
 555
 556         save->cs.selector = 0xf000;
 557         /* Executable/Readable Code Segment */
 558         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 559                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 560         save->cs.limit = 0xffff;
 561         /*
 562          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 563          * be consistent with it.
 564          *
 565          * Replace when we have real mode working for vmx.
 566          */
 567         save->cs.base = 0xf0000;
 568
 569         save->gdtr.limit = 0xffff;
 570         save->idtr.limit = 0xffff;
 571
 572         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 573         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 574
 575         save->efer = MSR_EFER_SVME_MASK;
 576         save->dr6 = 0xffff0ff0;
 577         save->dr7 = 0x400;
 578         save->rflags = 2;
 579         save->rip = 0x0000fff0;
 580
 581         /*
 582          * cr0 val on cpu init should be 0x60000010, we enable cpu
 583          * cache by default. the orderly way is to enable cache in bios.
 584          */
 585         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 586         save->cr4 = X86_CR4_PAE;
 587         /* rdx = ?? */
 588
 589         if (npt_enabled) {
 590                 /* Setup VMCB for Nested Paging */
 591                 control->nested_ctl = 1;
 592                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 593                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 594                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 595                                                 INTERCEPT_CR3_MASK);
 596                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 597                                                  INTERCEPT_CR3_MASK);
 598                 save->g_pat = 0x0007040600070406ULL;
 599                 /* enable caching because the QEMU Bios doesn't enable it */
 600                 save->cr0 = X86_CR0_ET;
 601                 save->cr3 = 0;
 602                 save->cr4 = 0;
 603         }
 604         force_new_asid(&svm->vcpu);
 605 }
 606
 607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 608 {
 609         struct vcpu_svm *svm = to_svm(vcpu);
 610
 611         init_vmcb(svm);
 612
 613         if (vcpu->vcpu_id != 0) {
 614                 svm->vmcb->save.rip = 0;
 615                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 616                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 623 {
 624         struct vcpu_svm *svm;
 625         struct page *page;
 626         struct page *msrpm_pages;
 627         int err;
 628
 629         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 630         if (!svm) {
 631                 err = -ENOMEM;
 632                 goto out;
 633         }
 634
 635         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 636         if (err)
 637                 goto free_svm;
 638
 639         page = alloc_page(GFP_KERNEL);
 640         if (!page) {
 641                 err = -ENOMEM;
 642                 goto uninit;
 643         }
 644
 645         err = -ENOMEM;
 646         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 647         if (!msrpm_pages)
 648                 goto uninit;
 649         svm->msrpm = page_address(msrpm_pages);
 650         svm_vcpu_init_msrpm(svm->msrpm);
 651
 652         svm->vmcb = page_address(page);
 653         clear_page(svm->vmcb);
 654         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 655         svm->asid_generation = 0;
 656         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 657         init_vmcb(svm);
 658
 659         fx_init(&svm->vcpu);
 660         svm->vcpu.fpu_active = 1;
 661         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 662         if (svm->vcpu.vcpu_id == 0)
 663                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 664
 665         return &svm->vcpu;
 666
 667 uninit:
 668         kvm_vcpu_uninit(&svm->vcpu);
 669 free_svm:
 670         kmem_cache_free(kvm_vcpu_cache, svm);
 671 out:
 672         return ERR_PTR(err);
 673 }
 674
 675 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 676 {
 677         struct vcpu_svm *svm = to_svm(vcpu);
 678
 679         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 680         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 681         kvm_vcpu_uninit(vcpu);
 682         kmem_cache_free(kvm_vcpu_cache, svm);
 683 }
 684
 685 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 686 {
 687         struct vcpu_svm *svm = to_svm(vcpu);
 688         int i;
 689
 690         if (unlikely(cpu != vcpu->cpu)) {
 691                 u64 tsc_this, delta;
 692
 693                 /*
 694                  * Make sure that the guest sees a monotonically
 695                  * increasing TSC.
 696                  */
 697                 rdtscll(tsc_this);
 698                 delta = vcpu->arch.host_tsc - tsc_this;
 699                 svm->vmcb->control.tsc_offset += delta;
 700                 vcpu->cpu = cpu;
 701                 kvm_migrate_timers(vcpu);
 702         }
 703
 704         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 705                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 706 }
 707
 708 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 709 {
 710         struct vcpu_svm *svm = to_svm(vcpu);
 711         int i;
 712
 713         ++vcpu->stat.host_state_reload;
 714         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 715                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 716
 717         rdtscll(vcpu->arch.host_tsc);
 718 }
 719
 720 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 721 {
 722 }
 723
 724 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 725 {
 726         struct vcpu_svm *svm = to_svm(vcpu);
 727
 728         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 729         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 730         vcpu->arch.rip = svm->vmcb->save.rip;
 731 }
 732
 733 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 734 {
 735         struct vcpu_svm *svm = to_svm(vcpu);
 736         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 737         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 738         svm->vmcb->save.rip = vcpu->arch.rip;
 739 }
 740
 741 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 742 {
 743         return to_svm(vcpu)->vmcb->save.rflags;
 744 }
 745
 746 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 747 {
 748         to_svm(vcpu)->vmcb->save.rflags = rflags;
 749 }
 750
 751 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 752 {
 753         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 754
 755         switch (seg) {
 756         case VCPU_SREG_CS: return &save->cs;
 757         case VCPU_SREG_DS: return &save->ds;
 758         case VCPU_SREG_ES: return &save->es;
 759         case VCPU_SREG_FS: return &save->fs;
 760         case VCPU_SREG_GS: return &save->gs;
 761         case VCPU_SREG_SS: return &save->ss;
 762         case VCPU_SREG_TR: return &save->tr;
 763         case VCPU_SREG_LDTR: return &save->ldtr;
 764         }
 765         BUG();
 766         return NULL;
 767 }
 768
 769 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 770 {
 771         struct vmcb_seg *s = svm_seg(vcpu, seg);
 772
 773         return s->base;
 774 }
 775
 776 static void svm_get_segment(struct kvm_vcpu *vcpu,
 777                             struct kvm_segment *var, int seg)
 778 {
 779         struct vmcb_seg *s = svm_seg(vcpu, seg);
 780
 781         var->base = s->base;
 782         var->limit = s->limit;
 783         var->selector = s->selector;
 784         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 785         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 786         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 787         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 788         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 789         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 790         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 791         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 792         var->unusable = !var->present;
 793 }
 794
 795 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 796 {
 797         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 798
 799         return save->cpl;
 800 }
 801
 802 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 803 {
 804         struct vcpu_svm *svm = to_svm(vcpu);
 805
 806         dt->limit = svm->vmcb->save.idtr.limit;
 807         dt->base = svm->vmcb->save.idtr.base;
 808 }
 809
 810 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 811 {
 812         struct vcpu_svm *svm = to_svm(vcpu);
 813
 814         svm->vmcb->save.idtr.limit = dt->limit;
 815         svm->vmcb->save.idtr.base = dt->base ;
 816 }
 817
 818 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 819 {
 820         struct vcpu_svm *svm = to_svm(vcpu);
 821
 822         dt->limit = svm->vmcb->save.gdtr.limit;
 823         dt->base = svm->vmcb->save.gdtr.base;
 824 }
 825
 826 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 827 {
 828         struct vcpu_svm *svm = to_svm(vcpu);
 829
 830         svm->vmcb->save.gdtr.limit = dt->limit;
 831         svm->vmcb->save.gdtr.base = dt->base ;
 832 }
 833
 834 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 835 {
 836 }
 837
 838 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 839 {
 840         struct vcpu_svm *svm = to_svm(vcpu);
 841
 842 #ifdef CONFIG_X86_64
 843         if (vcpu->arch.shadow_efer & EFER_LME) {
 844                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 845                         vcpu->arch.shadow_efer |= EFER_LMA;
 846                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 847                 }
 848
 849                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 850                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 851                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 852                 }
 853         }
 854 #endif
 855         if (npt_enabled)
 856                 goto set;
 857
 858         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 859                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 860                 vcpu->fpu_active = 1;
 861         }
 862
 863         vcpu->arch.cr0 = cr0;
 864         cr0 |= X86_CR0_PG | X86_CR0_WP;
 865         if (!vcpu->fpu_active) {
 866                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 867                 cr0 |= X86_CR0_TS;
 868         }
 869 set:
 870         /*
 871          * re-enable caching here because the QEMU bios
 872          * does not do it - this results in some delay at
 873          * reboot
 874          */
 875         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 876         svm->vmcb->save.cr0 = cr0;
 877 }
 878
 879 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 880 {
 881         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 882
 883         vcpu->arch.cr4 = cr4;
 884         if (!npt_enabled)
 885                 cr4 |= X86_CR4_PAE;
 886         cr4 |= host_cr4_mce;
 887         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 888 }
 889
 890 static void svm_set_segment(struct kvm_vcpu *vcpu,
 891                             struct kvm_segment *var, int seg)
 892 {
 893         struct vcpu_svm *svm = to_svm(vcpu);
 894         struct vmcb_seg *s = svm_seg(vcpu, seg);
 895
 896         s->base = var->base;
 897         s->limit = var->limit;
 898         s->selector = var->selector;
 899         if (var->unusable)
 900                 s->attrib = 0;
 901         else {
 902                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 903                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 904                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 905                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 906                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 907                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 908                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 909                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 910         }
 911         if (seg == VCPU_SREG_CS)
 912                 svm->vmcb->save.cpl
 913                         = (svm->vmcb->save.cs.attrib
 914                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 915
 916 }
 917
 918 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 919 {
 920         return -EOPNOTSUPP;
 921 }
 922
 923 static int svm_get_irq(struct kvm_vcpu *vcpu)
 924 {
 925         struct vcpu_svm *svm = to_svm(vcpu);
 926         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 927
 928         if (is_external_interrupt(exit_int_info))
 929                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 930         return -1;
 931 }
 932
 933 static void load_host_msrs(struct kvm_vcpu *vcpu)
 934 {
 935 #ifdef CONFIG_X86_64
 936         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 937 #endif
 938 }
 939
 940 static void save_host_msrs(struct kvm_vcpu *vcpu)
 941 {
 942 #ifdef CONFIG_X86_64
 943         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 944 #endif
 945 }
 946
 947 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 948 {
 949         if (svm_data->next_asid > svm_data->max_asid) {
 950                 ++svm_data->asid_generation;
 951                 svm_data->next_asid = 1;
 952                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 953         }
 954
 955         svm->vcpu.cpu = svm_data->cpu;
 956         svm->asid_generation = svm_data->asid_generation;
 957         svm->vmcb->control.asid = svm_data->next_asid++;
 958 }
 959
 960 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 961 {
 962         return to_svm(vcpu)->db_regs[dr];
 963 }
 964
 965 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 966                        int *exception)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969
 970         *exception = 0;
 971
 972         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 973                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 974                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 975                 *exception = DB_VECTOR;
 976                 return;
 977         }
 978
 979         switch (dr) {
 980         case 0 ... 3:
 981                 svm->db_regs[dr] = value;
 982                 return;
 983         case 4 ... 5:
 984                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 985                         *exception = UD_VECTOR;
 986                         return;
 987                 }
 988         case 7: {
 989                 if (value & ~((1ULL << 32) - 1)) {
 990                         *exception = GP_VECTOR;
 991                         return;
 992                 }
 993                 svm->vmcb->save.dr7 = value;
 994                 return;
 995         }
 996         default:
 997                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 998                        __func__, dr);
 999                 *exception = UD_VECTOR;
1000                 return;
1001         }
1002 }
1003
1004 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1005 {
1006         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1007         struct kvm *kvm = svm->vcpu.kvm;
1008         u64 fault_address;
1009         u32 error_code;
1010
1011         if (!irqchip_in_kernel(kvm) &&
1012                 is_external_interrupt(exit_int_info))
1013                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1014
1015         fault_address  = svm->vmcb->control.exit_info_2;
1016         error_code = svm->vmcb->control.exit_info_1;
1017         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1018 }
1019
1020 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1021 {
1022         int er;
1023
1024         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1025         if (er != EMULATE_DONE)
1026                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1027         return 1;
1028 }
1029
1030 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1031 {
1032         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1033         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1034                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1035         svm->vcpu.fpu_active = 1;
1036
1037         return 1;
1038 }
1039
1040 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1041 {
1042         /*
1043          * On an #MC intercept the MCE handler is not called automatically in
1044          * the host. So do it by hand here.
1045          */
1046         asm volatile (
1047                 "int $0x12\n");
1048         /* not sure if we ever come back to this point */
1049
1050         return 1;
1051 }
1052
1053 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1054 {
1055         /*
1056          * VMCB is undefined after a SHUTDOWN intercept
1057          * so reinitialize it.
1058          */
1059         clear_page(svm->vmcb);
1060         init_vmcb(svm);
1061
1062         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1063         return 0;
1064 }
1065
1066 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1067 {
1068         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1069         int size, down, in, string, rep;
1070         unsigned port;
1071
1072         ++svm->vcpu.stat.io_exits;
1073
1074         svm->next_rip = svm->vmcb->control.exit_info_2;
1075
1076         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1077
1078         if (string) {
1079                 if (emulate_instruction(&svm->vcpu,
1080                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1081                         return 0;
1082                 return 1;
1083         }
1084
1085         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1086         port = io_info >> 16;
1087         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1088         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1089         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1090
1091         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1092 }
1093
1094 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1095 {
1096         return 1;
1097 }
1098
1099 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1100 {
1101         svm->next_rip = svm->vmcb->save.rip + 1;
1102         skip_emulated_instruction(&svm->vcpu);
1103         return kvm_emulate_halt(&svm->vcpu);
1104 }
1105
1106 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1107 {
1108         svm->next_rip = svm->vmcb->save.rip + 3;
1109         skip_emulated_instruction(&svm->vcpu);
1110         kvm_emulate_hypercall(&svm->vcpu);
1111         return 1;
1112 }
1113
1114 static int invalid_op_interception(struct vcpu_svm *svm,
1115                                    struct kvm_run *kvm_run)
1116 {
1117         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1118         return 1;
1119 }
1120
1121 static int task_switch_interception(struct vcpu_svm *svm,
1122                                     struct kvm_run *kvm_run)
1123 {
1124         u16 tss_selector;
1125
1126         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1127         if (svm->vmcb->control.exit_info_2 &
1128             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1129                 return kvm_task_switch(&svm->vcpu, tss_selector,
1130                                        TASK_SWITCH_IRET);
1131         if (svm->vmcb->control.exit_info_2 &
1132             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1133                 return kvm_task_switch(&svm->vcpu, tss_selector,
1134                                        TASK_SWITCH_JMP);
1135         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1136 }
1137
1138 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1139 {
1140         svm->next_rip = svm->vmcb->save.rip + 2;
1141         kvm_emulate_cpuid(&svm->vcpu);
1142         return 1;
1143 }
1144
1145 static int emulate_on_interception(struct vcpu_svm *svm,
1146                                    struct kvm_run *kvm_run)
1147 {
1148         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1149                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1150         return 1;
1151 }
1152
1153 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1154 {
1155         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1156         if (irqchip_in_kernel(svm->vcpu.kvm))
1157                 return 1;
1158         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1159         return 0;
1160 }
1161
1162 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1163 {
1164         struct vcpu_svm *svm = to_svm(vcpu);
1165
1166         switch (ecx) {
1167         case MSR_IA32_TIME_STAMP_COUNTER: {
1168                 u64 tsc;
1169
1170                 rdtscll(tsc);
1171                 *data = svm->vmcb->control.tsc_offset + tsc;
1172                 break;
1173         }
1174         case MSR_K6_STAR:
1175                 *data = svm->vmcb->save.star;
1176                 break;
1177 #ifdef CONFIG_X86_64
1178         case MSR_LSTAR:
1179                 *data = svm->vmcb->save.lstar;
1180                 break;
1181         case MSR_CSTAR:
1182                 *data = svm->vmcb->save.cstar;
1183                 break;
1184         case MSR_KERNEL_GS_BASE:
1185                 *data = svm->vmcb->save.kernel_gs_base;
1186                 break;
1187         case MSR_SYSCALL_MASK:
1188                 *data = svm->vmcb->save.sfmask;
1189                 break;
1190 #endif
1191         case MSR_IA32_SYSENTER_CS:
1192                 *data = svm->vmcb->save.sysenter_cs;
1193                 break;
1194         case MSR_IA32_SYSENTER_EIP:
1195                 *data = svm->vmcb->save.sysenter_eip;
1196                 break;
1197         case MSR_IA32_SYSENTER_ESP:
1198                 *data = svm->vmcb->save.sysenter_esp;
1199                 break;
1200         /* Nobody will change the following 5 values in the VMCB so
1201            we can safely return them on rdmsr. They will always be 0
1202            until LBRV is implemented. */
1203         case MSR_IA32_DEBUGCTLMSR:
1204                 *data = svm->vmcb->save.dbgctl;
1205                 break;
1206         case MSR_IA32_LASTBRANCHFROMIP:
1207                 *data = svm->vmcb->save.br_from;
1208                 break;
1209         case MSR_IA32_LASTBRANCHTOIP:
1210                 *data = svm->vmcb->save.br_to;
1211                 break;
1212         case MSR_IA32_LASTINTFROMIP:
1213                 *data = svm->vmcb->save.last_excp_from;
1214                 break;
1215         case MSR_IA32_LASTINTTOIP:
1216                 *data = svm->vmcb->save.last_excp_to;
1217                 break;
1218         default:
1219                 return kvm_get_msr_common(vcpu, ecx, data);
1220         }
1221         return 0;
1222 }
1223
1224 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1225 {
1226         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1227         u64 data;
1228
1229         if (svm_get_msr(&svm->vcpu, ecx, &data))
1230                 kvm_inject_gp(&svm->vcpu, 0);
1231         else {
1232                 svm->vmcb->save.rax = data & 0xffffffff;
1233                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1234                 svm->next_rip = svm->vmcb->save.rip + 2;
1235                 skip_emulated_instruction(&svm->vcpu);
1236         }
1237         return 1;
1238 }
1239
1240 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1241 {
1242         struct vcpu_svm *svm = to_svm(vcpu);
1243
1244         switch (ecx) {
1245         case MSR_IA32_TIME_STAMP_COUNTER: {
1246                 u64 tsc;
1247
1248                 rdtscll(tsc);
1249                 svm->vmcb->control.tsc_offset = data - tsc;
1250                 break;
1251         }
1252         case MSR_K6_STAR:
1253                 svm->vmcb->save.star = data;
1254                 break;
1255 #ifdef CONFIG_X86_64
1256         case MSR_LSTAR:
1257                 svm->vmcb->save.lstar = data;
1258                 break;
1259         case MSR_CSTAR:
1260                 svm->vmcb->save.cstar = data;
1261                 break;
1262         case MSR_KERNEL_GS_BASE:
1263                 svm->vmcb->save.kernel_gs_base = data;
1264                 break;
1265         case MSR_SYSCALL_MASK:
1266                 svm->vmcb->save.sfmask = data;
1267                 break;
1268 #endif
1269         case MSR_IA32_SYSENTER_CS:
1270                 svm->vmcb->save.sysenter_cs = data;
1271                 break;
1272         case MSR_IA32_SYSENTER_EIP:
1273                 svm->vmcb->save.sysenter_eip = data;
1274                 break;
1275         case MSR_IA32_SYSENTER_ESP:
1276                 svm->vmcb->save.sysenter_esp = data;
1277                 break;
1278         case MSR_IA32_DEBUGCTLMSR:
1279                 if (!svm_has(SVM_FEATURE_LBRV)) {
1280                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1281                                         __func__, data);
1282                         break;
1283                 }
1284                 if (data & DEBUGCTL_RESERVED_BITS)
1285                         return 1;
1286
1287                 svm->vmcb->save.dbgctl = data;
1288                 if (data & (1ULL<<0))
1289                         svm_enable_lbrv(svm);
1290                 else
1291                         svm_disable_lbrv(svm);
1292                 break;
1293         case MSR_K7_EVNTSEL0:
1294         case MSR_K7_EVNTSEL1:
1295         case MSR_K7_EVNTSEL2:
1296         case MSR_K7_EVNTSEL3:
1297                 /*
1298                  * only support writing 0 to the performance counters for now
1299                  * to make Windows happy. Should be replaced by a real
1300                  * performance counter emulation later.
1301                  */
1302                 if (data != 0)
1303                         goto unhandled;
1304                 break;
1305         default:
1306         unhandled:
1307                 return kvm_set_msr_common(vcpu, ecx, data);
1308         }
1309         return 0;
1310 }
1311
1312 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1313 {
1314         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1315         u64 data = (svm->vmcb->save.rax & -1u)
1316                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1317         svm->next_rip = svm->vmcb->save.rip + 2;
1318         if (svm_set_msr(&svm->vcpu, ecx, data))
1319                 kvm_inject_gp(&svm->vcpu, 0);
1320         else
1321                 skip_emulated_instruction(&svm->vcpu);
1322         return 1;
1323 }
1324
1325 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1326 {
1327         if (svm->vmcb->control.exit_info_1)
1328                 return wrmsr_interception(svm, kvm_run);
1329         else
1330                 return rdmsr_interception(svm, kvm_run);
1331 }
1332
1333 static int interrupt_window_interception(struct vcpu_svm *svm,
1334                                    struct kvm_run *kvm_run)
1335 {
1336         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1337         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1338         /*
1339          * If the user space waits to inject interrupts, exit as soon as
1340          * possible
1341          */
1342         if (kvm_run->request_interrupt_window &&
1343             !svm->vcpu.arch.irq_summary) {
1344                 ++svm->vcpu.stat.irq_window_exits;
1345                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1346                 return 0;
1347         }
1348
1349         return 1;
1350 }
1351
1352 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1353                                       struct kvm_run *kvm_run) = {
1354         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1355         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1356         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1357         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1358         /* for now: */
1359         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1360         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1361         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1362         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1363         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1364         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1365         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1366         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1367         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1368         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1369         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1370         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1371         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1372         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1373         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1374         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1375         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1376         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1377         [SVM_EXIT_INTR]                         = nop_on_interception,
1378         [SVM_EXIT_NMI]                          = nop_on_interception,
1379         [SVM_EXIT_SMI]                          = nop_on_interception,
1380         [SVM_EXIT_INIT]                         = nop_on_interception,
1381         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1382         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1383         [SVM_EXIT_CPUID]                        = cpuid_interception,
1384         [SVM_EXIT_INVD]                         = emulate_on_interception,
1385         [SVM_EXIT_HLT]                          = halt_interception,
1386         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1387         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1388         [SVM_EXIT_IOIO]                         = io_interception,
1389         [SVM_EXIT_MSR]                          = msr_interception,
1390         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1391         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1392         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1393         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1394         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1395         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1396         [SVM_EXIT_STGI]                         = invalid_op_interception,
1397         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1398         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1399         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1400         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1401         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1402         [SVM_EXIT_NPF]                          = pf_interception,
1403 };
1404
1405 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1406 {
1407         struct vcpu_svm *svm = to_svm(vcpu);
1408         u32 exit_code = svm->vmcb->control.exit_code;
1409
1410         if (npt_enabled) {
1411                 int mmu_reload = 0;
1412                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1413                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1414                         mmu_reload = 1;
1415                 }
1416                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1417                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1418                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1419                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1420                                 kvm_inject_gp(vcpu, 0);
1421                                 return 1;
1422                         }
1423                 }
1424                 if (mmu_reload) {
1425                         kvm_mmu_reset_context(vcpu);
1426                         kvm_mmu_load(vcpu);
1427                 }
1428         }
1429
1430         kvm_reput_irq(svm);
1431
1432         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1433                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1434                 kvm_run->fail_entry.hardware_entry_failure_reason
1435                         = svm->vmcb->control.exit_code;
1436                 return 0;
1437         }
1438
1439         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1440             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1441             exit_code != SVM_EXIT_NPF)
1442                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1443                        "exit_code 0x%x\n",
1444                        __func__, svm->vmcb->control.exit_int_info,
1445                        exit_code);
1446
1447         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1448             || !svm_exit_handlers[exit_code]) {
1449                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1450                 kvm_run->hw.hardware_exit_reason = exit_code;
1451                 return 0;
1452         }
1453
1454         return svm_exit_handlers[exit_code](svm, kvm_run);
1455 }
1456
1457 static void reload_tss(struct kvm_vcpu *vcpu)
1458 {
1459         int cpu = raw_smp_processor_id();
1460
1461         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1462         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1463         load_TR_desc();
1464 }
1465
1466 static void pre_svm_run(struct vcpu_svm *svm)
1467 {
1468         int cpu = raw_smp_processor_id();
1469
1470         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1471
1472         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1473         if (svm->vcpu.cpu != cpu ||
1474             svm->asid_generation != svm_data->asid_generation)
1475                 new_asid(svm, svm_data);
1476 }
1477
1478
1479 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1480 {
1481         struct vmcb_control_area *control;
1482
1483         control = &svm->vmcb->control;
1484         control->int_vector = irq;
1485         control->int_ctl &= ~V_INTR_PRIO_MASK;
1486         control->int_ctl |= V_IRQ_MASK |
1487                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1488 }
1489
1490 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1491 {
1492         struct vcpu_svm *svm = to_svm(vcpu);
1493
1494         svm_inject_irq(svm, irq);
1495 }
1496
1497 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1498 {
1499         struct vcpu_svm *svm = to_svm(vcpu);
1500         struct vmcb *vmcb = svm->vmcb;
1501         int max_irr, tpr;
1502
1503         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1504                 return;
1505
1506         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1507
1508         max_irr = kvm_lapic_find_highest_irr(vcpu);
1509         if (max_irr == -1)
1510                 return;
1511
1512         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1513
1514         if (tpr >= (max_irr & 0xf0))
1515                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1516 }
1517
1518 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1519 {
1520         struct vcpu_svm *svm = to_svm(vcpu);
1521         struct vmcb *vmcb = svm->vmcb;
1522         int intr_vector = -1;
1523
1524         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1525             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1526                 intr_vector = vmcb->control.exit_int_info &
1527                               SVM_EVTINJ_VEC_MASK;
1528                 vmcb->control.exit_int_info = 0;
1529                 svm_inject_irq(svm, intr_vector);
1530                 goto out;
1531         }
1532
1533         if (vmcb->control.int_ctl & V_IRQ_MASK)
1534                 goto out;
1535
1536         if (!kvm_cpu_has_interrupt(vcpu))
1537                 goto out;
1538
1539         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1540             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1541             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1542                 /* unable to deliver irq, set pending irq */
1543                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1544                 svm_inject_irq(svm, 0x0);
1545                 goto out;
1546         }
1547         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1548         intr_vector = kvm_cpu_get_interrupt(vcpu);
1549         svm_inject_irq(svm, intr_vector);
1550         kvm_timer_intr_post(vcpu, intr_vector);
1551 out:
1552         update_cr8_intercept(vcpu);
1553 }
1554
1555 static void kvm_reput_irq(struct vcpu_svm *svm)
1556 {
1557         struct vmcb_control_area *control = &svm->vmcb->control;
1558
1559         if ((control->int_ctl & V_IRQ_MASK)
1560             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1561                 control->int_ctl &= ~V_IRQ_MASK;
1562                 push_irq(&svm->vcpu, control->int_vector);
1563         }
1564
1565         svm->vcpu.arch.interrupt_window_open =
1566                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1567 }
1568
1569 static void svm_do_inject_vector(struct vcpu_svm *svm)
1570 {
1571         struct kvm_vcpu *vcpu = &svm->vcpu;
1572         int word_index = __ffs(vcpu->arch.irq_summary);
1573         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1574         int irq = word_index * BITS_PER_LONG + bit_index;
1575
1576         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1577         if (!vcpu->arch.irq_pending[word_index])
1578                 clear_bit(word_index, &vcpu->arch.irq_summary);
1579         svm_inject_irq(svm, irq);
1580 }
1581
1582 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1583                                        struct kvm_run *kvm_run)
1584 {
1585         struct vcpu_svm *svm = to_svm(vcpu);
1586         struct vmcb_control_area *control = &svm->vmcb->control;
1587
1588         svm->vcpu.arch.interrupt_window_open =
1589                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1590                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1591
1592         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1593                 /*
1594                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1595                  */
1596                 svm_do_inject_vector(svm);
1597
1598         /*
1599          * Interrupts blocked.  Wait for unblock.
1600          */
1601         if (!svm->vcpu.arch.interrupt_window_open &&
1602             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1603                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1604          else
1605                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1606 }
1607
1608 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1609 {
1610         return 0;
1611 }
1612
1613 static void save_db_regs(unsigned long *db_regs)
1614 {
1615         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1616         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1617         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1618         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1619 }
1620
1621 static void load_db_regs(unsigned long *db_regs)
1622 {
1623         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1624         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1625         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1626         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1627 }
1628
1629 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1630 {
1631         force_new_asid(vcpu);
1632 }
1633
1634 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1635 {
1636 }
1637
1638 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1639 {
1640         struct vcpu_svm *svm = to_svm(vcpu);
1641
1642         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1643                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1644                 kvm_lapic_set_tpr(vcpu, cr8);
1645         }
1646 }
1647
1648 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1649 {
1650         struct vcpu_svm *svm = to_svm(vcpu);
1651         u64 cr8;
1652
1653         if (!irqchip_in_kernel(vcpu->kvm))
1654                 return;
1655
1656         cr8 = kvm_get_cr8(vcpu);
1657         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1658         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1659 }
1660
1661 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1662 {
1663         struct vcpu_svm *svm = to_svm(vcpu);
1664         u16 fs_selector;
1665         u16 gs_selector;
1666         u16 ldt_selector;
1667
1668         pre_svm_run(svm);
1669
1670         sync_lapic_to_cr8(vcpu);
1671
1672         save_host_msrs(vcpu);
1673         fs_selector = read_fs();
1674         gs_selector = read_gs();
1675         ldt_selector = read_ldt();
1676         svm->host_cr2 = kvm_read_cr2();
1677         svm->host_dr6 = read_dr6();
1678         svm->host_dr7 = read_dr7();
1679         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1680         /* required for live migration with NPT */
1681         if (npt_enabled)
1682                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1683
1684         if (svm->vmcb->save.dr7 & 0xff) {
1685                 write_dr7(0);
1686                 save_db_regs(svm->host_db_regs);
1687                 load_db_regs(svm->db_regs);
1688         }
1689
1690         clgi();
1691
1692         local_irq_enable();
1693
1694         asm volatile (
1695 #ifdef CONFIG_X86_64
1696                 "push %%rbp; \n\t"
1697 #else
1698                 "push %%ebp; \n\t"
1699 #endif
1700
1701 #ifdef CONFIG_X86_64
1702                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1703                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1704                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1705                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1706                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1707                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1708                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1709                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1710                 "mov %c[r10](%[svm]), %%r10 \n\t"
1711                 "mov %c[r11](%[svm]), %%r11 \n\t"
1712                 "mov %c[r12](%[svm]), %%r12 \n\t"
1713                 "mov %c[r13](%[svm]), %%r13 \n\t"
1714                 "mov %c[r14](%[svm]), %%r14 \n\t"
1715                 "mov %c[r15](%[svm]), %%r15 \n\t"
1716 #else
1717                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1718                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1719                 "mov %c[rdx](%[svm]), %%edx \n\t"
1720                 "mov %c[rsi](%[svm]), %%esi \n\t"
1721                 "mov %c[rdi](%[svm]), %%edi \n\t"
1722                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1723 #endif
1724
1725 #ifdef CONFIG_X86_64
1726                 /* Enter guest mode */
1727                 "push %%rax \n\t"
1728                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1729                 SVM_VMLOAD "\n\t"
1730                 SVM_VMRUN "\n\t"
1731                 SVM_VMSAVE "\n\t"
1732                 "pop %%rax \n\t"
1733 #else
1734                 /* Enter guest mode */
1735                 "push %%eax \n\t"
1736                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1737                 SVM_VMLOAD "\n\t"
1738                 SVM_VMRUN "\n\t"
1739                 SVM_VMSAVE "\n\t"
1740                 "pop %%eax \n\t"
1741 #endif
1742
1743                 /* Save guest registers, load host registers */
1744 #ifdef CONFIG_X86_64
1745                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1746                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1747                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1748                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1749                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1750                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1751                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1752                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1753                 "mov %%r10, %c[r10](%[svm]) \n\t"
1754                 "mov %%r11, %c[r11](%[svm]) \n\t"
1755                 "mov %%r12, %c[r12](%[svm]) \n\t"
1756                 "mov %%r13, %c[r13](%[svm]) \n\t"
1757                 "mov %%r14, %c[r14](%[svm]) \n\t"
1758                 "mov %%r15, %c[r15](%[svm]) \n\t"
1759
1760                 "pop  %%rbp; \n\t"
1761 #else
1762                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1763                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1764                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1765                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1766                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1767                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1768
1769                 "pop  %%ebp; \n\t"
1770 #endif
1771                 :
1772                 : [svm]"a"(svm),
1773                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1774                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1775                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1776                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1777                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1778                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1779                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1780 #ifdef CONFIG_X86_64
1781                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1782                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1783                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1784                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1785                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1786                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1787                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1788                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1789 #endif
1790                 : "cc", "memory"
1791 #ifdef CONFIG_X86_64
1792                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1793                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1794 #else
1795                 , "ebx", "ecx", "edx" , "esi", "edi"
1796 #endif
1797                 );
1798
1799         if ((svm->vmcb->save.dr7 & 0xff))
1800                 load_db_regs(svm->host_db_regs);
1801
1802         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1803
1804         write_dr6(svm->host_dr6);
1805         write_dr7(svm->host_dr7);
1806         kvm_write_cr2(svm->host_cr2);
1807
1808         load_fs(fs_selector);
1809         load_gs(gs_selector);
1810         load_ldt(ldt_selector);
1811         load_host_msrs(vcpu);
1812
1813         reload_tss(vcpu);
1814
1815         local_irq_disable();
1816
1817         stgi();
1818
1819         sync_cr8_to_lapic(vcpu);
1820
1821         svm->next_rip = 0;
1822 }
1823
1824 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1825 {
1826         struct vcpu_svm *svm = to_svm(vcpu);
1827
1828         if (npt_enabled) {
1829                 svm->vmcb->control.nested_cr3 = root;
1830                 force_new_asid(vcpu);
1831                 return;
1832         }
1833
1834         svm->vmcb->save.cr3 = root;
1835         force_new_asid(vcpu);
1836
1837         if (vcpu->fpu_active) {
1838                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1839                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1840                 vcpu->fpu_active = 0;
1841         }
1842 }
1843
1844 static int is_disabled(void)
1845 {
1846         u64 vm_cr;
1847
1848         rdmsrl(MSR_VM_CR, vm_cr);
1849         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1850                 return 1;
1851
1852         return 0;
1853 }
1854
1855 static void
1856 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1857 {
1858         /*
1859          * Patch in the VMMCALL instruction:
1860          */
1861         hypercall[0] = 0x0f;
1862         hypercall[1] = 0x01;
1863         hypercall[2] = 0xd9;
1864 }
1865
1866 static void svm_check_processor_compat(void *rtn)
1867 {
1868         *(int *)rtn = 0;
1869 }
1870
1871 static bool svm_cpu_has_accelerated_tpr(void)
1872 {
1873         return false;
1874 }
1875
1876 static int get_npt_level(void)
1877 {
1878 #ifdef CONFIG_X86_64
1879         return PT64_ROOT_LEVEL;
1880 #else
1881         return PT32E_ROOT_LEVEL;
1882 #endif
1883 }
1884
1885 static struct kvm_x86_ops svm_x86_ops = {
1886         .cpu_has_kvm_support = has_svm,
1887         .disabled_by_bios = is_disabled,
1888         .hardware_setup = svm_hardware_setup,
1889         .hardware_unsetup = svm_hardware_unsetup,
1890         .check_processor_compatibility = svm_check_processor_compat,
1891         .hardware_enable = svm_hardware_enable,
1892         .hardware_disable = svm_hardware_disable,
1893         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1894
1895         .vcpu_create = svm_create_vcpu,
1896         .vcpu_free = svm_free_vcpu,
1897         .vcpu_reset = svm_vcpu_reset,
1898
1899         .prepare_guest_switch = svm_prepare_guest_switch,
1900         .vcpu_load = svm_vcpu_load,
1901         .vcpu_put = svm_vcpu_put,
1902         .vcpu_decache = svm_vcpu_decache,
1903
1904         .set_guest_debug = svm_guest_debug,
1905         .get_msr = svm_get_msr,
1906         .set_msr = svm_set_msr,
1907         .get_segment_base = svm_get_segment_base,
1908         .get_segment = svm_get_segment,
1909         .set_segment = svm_set_segment,
1910         .get_cpl = svm_get_cpl,
1911         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1912         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1913         .set_cr0 = svm_set_cr0,
1914         .set_cr3 = svm_set_cr3,
1915         .set_cr4 = svm_set_cr4,
1916         .set_efer = svm_set_efer,
1917         .get_idt = svm_get_idt,
1918         .set_idt = svm_set_idt,
1919         .get_gdt = svm_get_gdt,
1920         .set_gdt = svm_set_gdt,
1921         .get_dr = svm_get_dr,
1922         .set_dr = svm_set_dr,
1923         .cache_regs = svm_cache_regs,
1924         .decache_regs = svm_decache_regs,
1925         .get_rflags = svm_get_rflags,
1926         .set_rflags = svm_set_rflags,
1927
1928         .tlb_flush = svm_flush_tlb,
1929
1930         .run = svm_vcpu_run,
1931         .handle_exit = handle_exit,
1932         .skip_emulated_instruction = skip_emulated_instruction,
1933         .patch_hypercall = svm_patch_hypercall,
1934         .get_irq = svm_get_irq,
1935         .set_irq = svm_set_irq,
1936         .queue_exception = svm_queue_exception,
1937         .exception_injected = svm_exception_injected,
1938         .inject_pending_irq = svm_intr_assist,
1939         .inject_pending_vectors = do_interrupt_requests,
1940
1941         .set_tss_addr = svm_set_tss_addr,
1942         .get_tdp_level = get_npt_level,
1943 };
1944
1945 static int __init svm_init(void)
1946 {
1947         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1948                               THIS_MODULE);
1949 }
1950
1951 static void __exit svm_exit(void)
1952 {
1953         kvm_exit();
1954 }
1955
1956 module_init(svm_init)
1957 module_exit(svm_exit)