]> rtime.felk.cvut.cz Git - linux-imx.git/blobdiff - drivers/gpu/drm/radeon/btc_dpm.c
drm/radeon/dpm: fix spread spectrum setup (v2)
[linux-imx.git] / drivers / gpu / drm / radeon / btc_dpm.c
index bab01858341746e40b228e8eca385c0353e60ee1..9953e1fbc46d74e53adf50eab2eb05e602287f54 100644 (file)
@@ -2059,6 +2059,19 @@ static void btc_init_stutter_mode(struct radeon_device *rdev)
        }
 }
 
+bool btc_dpm_vblank_too_short(struct radeon_device *rdev)
+{
+       struct rv7xx_power_info *pi = rv770_get_pi(rdev);
+       u32 vblank_time = r600_dpm_get_vblank_time(rdev);
+       u32 switch_limit = pi->mem_gddr5 ? 450 : 100;
+
+       if (vblank_time < switch_limit)
+               return true;
+       else
+               return false;
+
+}
+
 static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
                                         struct radeon_ps *rps)
 {
@@ -2068,7 +2081,8 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
        u32 mclk, sclk;
        u16 vddc, vddci;
 
-       if (rdev->pm.dpm.new_active_crtc_count > 1)
+       if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
+           btc_dpm_vblank_too_short(rdev))
                disable_mclk_switching = true;
        else
                disable_mclk_switching = false;
@@ -2326,14 +2340,11 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
                return ret;
        }
 
-#if 0
-       /* XXX */
-       ret = rv770_unrestrict_performance_levels_after_switch(rdev);
+       ret = rv770_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
        if (ret) {
-               DRM_ERROR("rv770_unrestrict_performance_levels_after_switch failed\n");
+               DRM_ERROR("rv770_dpm_force_performance_level failed\n");
                return ret;
        }
-#endif
 
        return 0;
 }
@@ -2537,9 +2548,6 @@ int btc_dpm_init(struct radeon_device *rdev)
 {
        struct rv7xx_power_info *pi;
        struct evergreen_power_info *eg_pi;
-       int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
-       u16 data_offset, size;
-       u8 frev, crev;
        struct atom_clock_dividers dividers;
        int ret;
 
@@ -2622,16 +2630,7 @@ int btc_dpm_init(struct radeon_device *rdev)
        eg_pi->vddci_control =
                radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
 
-       if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
-                                   &frev, &crev, &data_offset)) {
-               pi->sclk_ss = true;
-               pi->mclk_ss = true;
-               pi->dynamic_ss = true;
-       } else {
-               pi->sclk_ss = false;
-               pi->mclk_ss = false;
-               pi->dynamic_ss = true;
-       }
+       rv770_get_engine_memory_ss(rdev);
 
        pi->asi = RV770_ASI_DFLT;
        pi->pasi = CYPRESS_HASI_DFLT;
@@ -2648,8 +2647,7 @@ int btc_dpm_init(struct radeon_device *rdev)
 
        pi->dynamic_pcie_gen2 = true;
 
-       if (pi->gfx_clock_gating &&
-           (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
+       if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
                pi->thermal_protection = true;
        else
                pi->thermal_protection = false;