drm/radeon: UVD bringup v8

[linux-imx.git] / drivers / gpu / drm / radeon / r600d.h

diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a42ba11a3bed92c1883635d31209dafa00b64719..441bdb809a0b362d2210343f032ae023e27d43b5 100644 (file)
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -691,6 +691,7 @@
 #define SRBM_SOFT_RESET                                   0xe60
 #       define SOFT_RESET_DMA                             (1 << 12)
 #       define SOFT_RESET_RLC                             (1 << 13)
+#       define SOFT_RESET_UVD                             (1 << 18)
 #       define RV770_SOFT_RESET_DMA                       (1 << 20)
 
 #define CP_INT_CNTL                                       0xc124
@@ -1142,6 +1143,66 @@
 #       define AFMT_AZ_FORMAT_WTRIG_ACK      (1 << 29)
 #       define AFMT_AZ_AUDIO_ENABLE_CHG_ACK  (1 << 30)
 
+/*
+ * UVD
+ */
+#define UVD_SEMA_ADDR_LOW                              0xef00
+#define UVD_SEMA_ADDR_HIGH                             0xef04
+#define UVD_SEMA_CMD                                   0xef08
+
+#define UVD_GPCOM_VCPU_CMD                             0xef0c
+#define UVD_GPCOM_VCPU_DATA0                           0xef10
+#define UVD_GPCOM_VCPU_DATA1                           0xef14
+#define UVD_ENGINE_CNTL                                        0xef18
+
+#define UVD_SEMA_CNTL                                  0xf400
+#define UVD_RB_ARB_CTRL                                        0xf480
+
+#define UVD_LMI_EXT40_ADDR                             0xf498
+#define UVD_CGC_GATE                                   0xf4a8
+#define UVD_LMI_CTRL2                                  0xf4f4
+#define UVD_MASTINT_EN                                 0xf500
+#define UVD_LMI_ADDR_EXT                               0xf594
+#define UVD_LMI_CTRL                                   0xf598
+#define UVD_LMI_SWAP_CNTL                              0xf5b4
+#define UVD_MP_SWAP_CNTL                               0xf5bC
+#define UVD_MPC_CNTL                                   0xf5dC
+#define UVD_MPC_SET_MUXA0                              0xf5e4
+#define UVD_MPC_SET_MUXA1                              0xf5e8
+#define UVD_MPC_SET_MUXB0                              0xf5eC
+#define UVD_MPC_SET_MUXB1                              0xf5f0
+#define UVD_MPC_SET_MUX                                        0xf5f4
+#define UVD_MPC_SET_ALU                                        0xf5f8
+
+#define UVD_VCPU_CNTL                                  0xf660
+#define UVD_SOFT_RESET                                 0xf680
+#define                RBC_SOFT_RESET                                  (1<<0)
+#define                LBSI_SOFT_RESET                                 (1<<1)
+#define                LMI_SOFT_RESET                                  (1<<2)
+#define                VCPU_SOFT_RESET                                 (1<<3)
+#define                CSM_SOFT_RESET                                  (1<<5)
+#define                CXW_SOFT_RESET                                  (1<<6)
+#define                TAP_SOFT_RESET                                  (1<<7)
+#define                LMI_UMC_SOFT_RESET                              (1<<13)
+#define UVD_RBC_IB_BASE                                        0xf684
+#define UVD_RBC_IB_SIZE                                        0xf688
+#define UVD_RBC_RB_BASE                                        0xf68c
+#define UVD_RBC_RB_RPTR                                        0xf690
+#define UVD_RBC_RB_WPTR                                        0xf694
+#define UVD_RBC_RB_WPTR_CNTL                           0xf698
+
+#define UVD_STATUS                                     0xf6bc
+
+#define UVD_SEMA_TIMEOUT_STATUS                                0xf6c0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL          0xf6c4
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL               0xf6c8
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                0xf6cc
+
+#define UVD_RBC_RB_CNTL                                        0xf6a4
+#define UVD_RBC_RB_RPTR_ADDR                           0xf6a8
+
+#define UVD_CONTEXT_ID                                 0xf6f4
+
 /*
  * PM4
  */