drm/radeon/dpm: add checks against vblank time

[linux-imx.git] / drivers / gpu / drm / radeon / radeon.h

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 706b018e019ed587eb97bf7a1e2540de5f1c088d..9b7025d02cd0cf42504d08fca87d6daf640c876d 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -200,6 +200,7 @@ struct radeon_clock {
        uint32_t default_mclk;
        uint32_t default_sclk;
        uint32_t default_dispclk;
+       uint32_t current_dispclk;
        uint32_t dp_extclk;
        uint32_t max_pixel_clock;
 };
@@ -978,6 +979,7 @@ struct radeon_cs_parser {
        u32                     cs_flags;
        u32                     ring;
        s32                     priority;
+       struct ww_acquire_ctx   ticket;
 };
 
 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
@@ -1098,6 +1100,7 @@ enum radeon_pm_state_type {
        POWER_STATE_TYPE_INTERNAL_THERMAL,
        POWER_STATE_TYPE_INTERNAL_ACPI,
        POWER_STATE_TYPE_INTERNAL_ULV,
+       POWER_STATE_TYPE_INTERNAL_3DPERF,
 };
 
 enum radeon_pm_profile_type {
@@ -1270,10 +1273,35 @@ struct radeon_cac_leakage_table {
        struct radeon_cac_leakage_entry *entries;
 };
 
+struct radeon_phase_shedding_limits_entry {
+       u16 voltage;
+       u32 sclk;
+       u32 mclk;
+};
+
+struct radeon_phase_shedding_limits_table {
+       u32 count;
+       struct radeon_phase_shedding_limits_entry *entries;
+};
+
+struct radeon_ppm_table {
+       u8 ppm_design;
+       u16 cpu_core_number;
+       u32 platform_tdp;
+       u32 small_ac_platform_tdp;
+       u32 platform_tdc;
+       u32 small_ac_platform_tdc;
+       u32 apu_tdp;
+       u32 dgpu_tdp;
+       u32 dgpu_ulv_power;
+       u32 tj_max;
+};
+
 struct radeon_dpm_dynamic_state {
        struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
        struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
        struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
+       struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
        struct radeon_clock_array valid_sclk_values;
        struct radeon_clock_array valid_mclk_values;
        struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
@@ -1283,6 +1311,8 @@ struct radeon_dpm_dynamic_state {
        u16 vddc_vddci_delta;
        u16 min_vddc_for_pcie_gen2;
        struct radeon_cac_leakage_table cac_leakage_table;
+       struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
+       struct radeon_ppm_table *ppm_table;
 };
 
 struct radeon_dpm_fan {
@@ -1298,6 +1328,19 @@ struct radeon_dpm_fan {
        bool ucode_fan_control;
 };
 
+enum radeon_pcie_gen {
+       RADEON_PCIE_GEN1 = 0,
+       RADEON_PCIE_GEN2 = 1,
+       RADEON_PCIE_GEN3 = 2,
+       RADEON_PCIE_GEN_INVALID = 0xffff
+};
+
+enum radeon_dpm_forced_level {
+       RADEON_DPM_FORCED_LEVEL_AUTO = 0,
+       RADEON_DPM_FORCED_LEVEL_LOW = 1,
+       RADEON_DPM_FORCED_LEVEL_HIGH = 2,
+};
+
 struct radeon_dpm {
        struct radeon_ps        *ps;
        /* number of valid power states */
@@ -1324,6 +1367,7 @@ struct radeon_dpm {
        struct radeon_dpm_fan fan;
        u32 tdp_limit;
        u32 near_tdp_limit;
+       u32 near_tdp_limit_adjusted;
        u32 sq_ramping_threshold;
        u32 cac_leakage;
        u16 tdp_od_limit;
@@ -1336,6 +1380,8 @@ struct radeon_dpm {
        bool                    uvd_active;
        /* thermal handling */
        struct radeon_dpm_thermal thermal;
+       /* forced levels */
+       enum radeon_dpm_forced_level forced_level;
 };
 
 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
@@ -1630,6 +1676,9 @@ struct radeon_asic {
                u32 (*get_sclk)(struct radeon_device *rdev, bool low);
                u32 (*get_mclk)(struct radeon_device *rdev, bool low);
                void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
+               void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
+               int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
+               bool (*vblank_too_short)(struct radeon_device *rdev);
        } dpm;
        /* pageflipping */
        struct {
@@ -2094,6 +2143,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
+#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
+#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
 #define WREG32_P(reg, val, mask)                               \
        do {                                                    \
                uint32_t tmp_ = RREG32(reg);                    \
@@ -2210,6 +2261,21 @@ static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
        WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
 }
 
+static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
+{
+       u32 r;
+
+       WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
+       r = RREG32(R600_UVD_CTX_DATA);
+       return r;
+}
+
+static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+       WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
+       WREG32(R600_UVD_CTX_DATA, (v));
+}
+
 void r100_pll_errata_after_index(struct radeon_device *rdev);
 
 
@@ -2379,6 +2445,9 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
+#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
+#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
+#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
 
 /* Common functions */
 /* AGP */